With Housing Or External Electrode Patents (Class 257/177)
  • Patent number: 11532541
    Abstract: A semiconductor package includes: an insulating substrate having opposing first and second main sides; a power semiconductor die embedded in, and thinner than or a same thickness as, the substrate, and including a first load terminal bond pad at a first side which faces a same direction as the substrate first main side, a second load terminal bond pad at a second side which faces a same direction as the substrate second main side, and a control terminal bond pad; electrically conductive first vias extending through the substrate in a periphery region; a first metallization connecting the first load terminal bond pad to the first vias at the substrate first main side; solderable first contact pads at the substrate second main side and formed by the first vias; and a solderable second contact pad at the substrate second main side and formed by the second load terminal die bond pad.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: December 20, 2022
    Assignee: Infineon Technologies AG
    Inventors: Eung San Cho, Petteri Palm
  • Patent number: 11343925
    Abstract: A housing frame for a control unit for controlling an electrical machine is disclosed. The housing frame has at least one connection pin for electrically contacting a circuit carrier of the control unit. The connection pin has a connection base and is injected into the housing frame such that the connection pin can be electrically connected to the circuit carrier at the connection base by way of laser beam welding. Also disclosed is a control unit having a housing frame, an electrical machine having a control unit, and to a method for electrically connecting a connection pin of the housing frame to a circuit carrier of a control unit.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: May 24, 2022
    Assignee: Robert Bosch GmbH
    Inventors: Reinhold Jocham, Ulrich Trescher, Sascha Bader, Oliver Schilli
  • Patent number: 11201098
    Abstract: A structured metal layer in contact with an electronic component is applied on an upper side of a substrate of electrically insulating material. A metallic contact layer is applied to an underside of the substrate, with the underside configured as planar surface in a state of the substrate that is free of mechanical stress. The contact layer is connected to a metallic base plate via an intermediate layer. The contact layer is connected to the metallic base plate at an elevated temperature. The semiconductor module is then cooled. The side of the metallic base plate facing the substrate and the side of the metallic base plate facing away from the substrate are configured as planar surfaces in a state of the base plate that is free of mechanical stress. Upon cooling of the semiconductor module, the base plate forms a concave curvature on its side facing away from the substrate.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: December 14, 2021
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventor: Bernd Kürten
  • Patent number: 11129300
    Abstract: A module includes a heat dissipating substrate including a first surface and a second surface on an opposite side of the first surface, an element arranged on the first surface of the heat dissipating substrate, a connecting terminal arranged on the first surface of the heat dissipating substrate and provided for electrically connecting the element to a wiring substrate arranged on the module, a module case arranged on the first surface in such a manner that a circumference of the heat dissipating substrate is partially covered, and a sealing member sealing the element and a connecting portion of the connecting terminal with the element, wherein the heat dissipating substrate includes a positioning part for positioning the module with respect to the housing case, and the positioning part protrudes to an outer side of the module case.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: September 21, 2021
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventor: Teiichi Okubo
  • Patent number: 11121055
    Abstract: A semiconductor device module may include a leadframe spacer that provides the functions of both a leadframe and a spacer, while enabling a double-sided cooling configuration. Such a leadframe spacer may include a leadframe surface that provides a die attach pad (DAP) that is shared by at least two semiconductor devices. The leadframe spacer may include at least one downset, where the semiconductor devices may be attached within a recess defined by the at least one downset. A first substrate may be connected to a first side of the leadframe. A second substrate may be connected to downset surfaces of the at least one downset, and positioned for further connection to the semiconductor devices in a double-sided assembly.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: September 14, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Tzu-Hsuan Cheng, Yong Liu, Liangbiao Chen
  • Patent number: 11114349
    Abstract: The present invention concerns a system for allowing the restoration of a first interconnection of a die of a power module connecting the die to an electric circuit. The system comprises: at least one other interconnection of the power module, a periodic current source that is connected to the at least one other interconnection for generating a periodic current flow through the at least one other interconnection in order to reach, in at least a part of the first interconnection, a predetermined temperature during a predetermined time duration. The present invention concerns also the associated method.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: September 7, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Jeffrey Ewanchuk, Julio Brandelero, Stefan Mollov
  • Patent number: 11081422
    Abstract: A power electronics assembly is provided with a self-healing feature. The power electronics assembly may include a semiconductor electronics device and an insulating substrate coupled to the semiconductor electronics device. A base metal structural component may be provided, coupled to the insulating substrate. The assembly may include a frame component cooperating with the base metal structural component and defining an enclosure containing the semiconductor electronics device and the insulating substrate. The assembly further includes a self-healing polymer comprising disulfide bonds. The self-healing polymer is disposed within the enclosure; additional potting material may also be provided as a multi-layered encapsulation. In various aspects, the self-healing polymer may include polydimethylsiloxane based polyurethane (PDMS-PU) modified with disulfide bonds. The frame component may be configured to direct or confine heat to areas of the assembly where ESD may be problematic.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: August 3, 2021
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventor: Ercan Mehmet Dede
  • Patent number: 11011442
    Abstract: A power module will be provided which can suppress insulation performance deterioration caused by heat cycle to ensure insulation performance, by suppressing generation of bubbles and occurrence of detachments between silicone gel and an insulating substrate at a high or low temperature or at a high working voltage.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: May 18, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Masaki Taya
  • Patent number: 11004808
    Abstract: A multi-die package includes a thermally conductive flange, a first semiconductor die made of a first semiconductor material attached to the thermally conductive flange via a first die attach material, a second semiconductor die attached to the same thermally conductive flange as the first semiconductor die via a second die attach material, and leads attached to the thermally conductive flange or to an insulating member secured to the flange. The leads are configured to provide external electrical access to the first and second semiconductor dies. The second semiconductor die is made of a second semiconductor material different than the first semiconductor material. Additional multi-die package embodiments are described.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: May 11, 2021
    Assignee: CREE, INC.
    Inventors: Xikun Zhang, Dejiang Chang, Bill Agar, Michael Lefevre, Alexander Komposch
  • Patent number: 10872830
    Abstract: A power semiconductor device includes a base plate; a Si chip including a Si substrate, the Si chip attached to the base plate; a first metal preform pressed with a first press pin against the Si chip; a wide bandgap material chip comprising a wide bandgap substrate and a semiconductor switch provided in the wide bandgap substrate, the wide bandgap material chip attached to the base plate; and a second metal preform pressed with a second press pin against the wide bandgap material chip; the Si chip and the wide bandgap material chip are connected in parallel via the base plate and via the first press pin and the second press pin; the first metal preform is adapted for forming a conducting path through the Si chip, when heated by an overcurrent; and the second metal preform is adapted for forming an temporary conducting path through the wide bandgap material chip or an open circuit, when heated by an overcurrent.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: December 22, 2020
    Assignee: ABB Schweiz AG
    Inventors: Chunlei Liu, Juergen Schuderer, Franziska Brem, Munaf Rahimo, Peter Karl Steimer, Franc Dugal
  • Patent number: 10768090
    Abstract: An outside opening of each aperture of a plurality of counting chambers for performing particle counting based on the electric resistance method is connected to suction pump through a confluent piping. Liquid supplying part supplies an additional liquid to the counting chamber side after completion of counting of counting chamber, so that the liquid level of sample liquid of counting chamber will not descend to aperture or a predetermined liquid level.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: September 8, 2020
    Assignee: HORIBA, Ltd.
    Inventors: Motoaki Hamada, Kazumasa Takemoto, Yoji Kawanami
  • Patent number: 10743411
    Abstract: A ceramic substrate component suitable for high-power chips includes a ceramic substrate body and at least one raised metal pad. The ceramic substrate body has an upper surface and a lower surface opposite to the upper surface. The raised metal pad includes a base portion and a top layer. The base portion, which is attached to the upper surface of the ceramic substrate body, has a thickness between 10 and 300 micrometers, and a thermal expansion coefficient greater than the ceramic substrate body. The top layer is formed on the base portion and adapted to install a high-power chip thereon. The top layer extends an area less than the base portion but greater than the high-power chip, and has a thermal expansion coefficient greater than the ceramic substrate body. As such, damages due to thermal stress occurring between the base portion and the ceramic substrate body can be mitigated.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: August 11, 2020
    Assignees: ICP Technology Co., Ltd., Industrial Technology Research Institute
    Inventors: Ho-Chieh Yu, Chen-Cheng-Lung Liao, Chun-Yu Lin, Hsiao-Ming Chang, Jing-Yao Chang, Tao-Chih Chang
  • Patent number: 10736238
    Abstract: A semiconductor device may include a stack in which a cooler and a semiconductor module are stacked, the semiconductor module housing a semiconductor element; a contact plate contacting the stack in a stacking direction of the semiconductor module and the cooler; and a spring contacting the contact plate and pressurizing the stack via the contact plate in the stacking direction, wherein the spring may contact a center portion of the contact plate in a direction perpendicular to the stacking direction, and a recess or a cavity may be provided at the center portion of the contact plate, the recess facing the stack.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: August 4, 2020
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Kazunori Uchiyama, Naoki Hakamada, Tomo Sasaki, Masataka Deguchi, Koji Hotta, Tadafumi Yoshida
  • Patent number: 10658268
    Abstract: A lower electrode, a semiconductor chip provided on the lower electrode, a pressure pad provided above or below the semiconductor chip, an upper electrode provided on a structure in which the pressure pad is overlapped with the semiconductor chip, and a connection conductor that provides a new current path between the lower electrode and the upper electrode only when a distance between the lower electrode and the upper electrode becomes larger than a predetermined value are provided. The distance between the lower electrode and the upper electrode is variable, and the pressure pad electrically connects the lower electrode and the upper electrode together via the semiconductor chip regardless of the distance between the lower electrode and the upper electrode.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: May 19, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shigeto Fujita, Tetsuya Matsuda
  • Patent number: 10483244
    Abstract: A power semiconductor module includes a first main electrode, a second main electrode and a control terminal. The power semiconductor module includes controllable power semiconductor components arranged between the first main electrode and the second main electrode. At least some of the controllable power semiconductor components are arranged in a ring arrangement, wherein the controllable power semiconductor components of the ring arrangement are arranged at least approximately along a first circular line of the ring arrangement, and a control conductor track of the ring arrangement is arranged on the first main electrode, wherein the control conductor track runs at least approximately along a second circular line of the ring arrangement, and the second circular line runs concentrically relative to the first circular line.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: November 19, 2019
    Assignee: ABB Schweiz AG
    Inventors: Samuel Hartmann, Franc Dugal, Olle Ekwall, Erik Doré
  • Patent number: 10396008
    Abstract: A semiconductor device includes a first metal plate and a second metal plate which interpose a first semiconductor element therebetween, the first metal plate and the second metal plate being bonded to the first semiconductor element with first soldered portions; and includes a third metal plate and a fourth metal plate which interpose a second semiconductor element therebetween, the third metal plate and the fourth metal plate being bonded to the second semiconductor element with second soldered portions. A first joint provided at an edge of the first metal plate and a second joint provided at an edge of the fourth metal plate are bonded with a third soldered portion. A total sum of thicknesses of the first soldered portions is different from a thickness of the third soldered portion, a solidifying point of the thinner one is higher than a solidifying point of the thicker one.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: August 27, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Satoshi Takahagi, Takuya Kadoguchi, Yuji Hanaki, Syou Funano, Shingo Iwasaki, Takanori Kawashima
  • Patent number: 10297573
    Abstract: A three-dimensional package structure, comprising: a substrate; a first plurality of discrete electronic components disposed over the bottom surface of the substrate, wherein a first insulating layer is disposed over the bottom surface of the substrate to encapsulate the first plurality of discrete electronic components, wherein at least one second insulating layer is disposed over the first insulating layer, wherein a plurality of surface-mount pads are disposed on the bottom surface of the at least one second insulating layer and electrically connected to at least one via disposed in the at least one second insulating layer.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: May 21, 2019
    Assignee: CYNTEC CO., LTD.
    Inventors: Bau-Ru Lu, Ming-Chia Wu, Shao Wei Lu
  • Patent number: 10242969
    Abstract: A semiconductor package includes a first semiconductor module including a plurality of semiconductor transistor chips and a first encapsulation layer disposed above the semiconductor transistor chips, and a second semiconductor module disposed above the first semiconductor module. The second semiconductor module includes a plurality of semiconductor driver channels and a second encapsulation layer disposed above the semiconductor driver channels. The semiconductor driver channels are configured to drive the semiconductor transistor chips.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: March 26, 2019
    Assignee: Infineon Technologies AG
    Inventors: Olaf Hohlfeld, Juergen Hoegerl, Angela Kessler, Magdalena Hoier
  • Patent number: 10211118
    Abstract: A semiconductor module includes a metal substrate having a mounting surface, a first conductive plate on the mounting surface, an insulating substrate on the first conductive plate, a second conductive plate on the insulating substrate, a conductive pad on the insulating substrate, a semiconductor element on the second conductive plate, a circuit board electrically connected to the conductive pad, a resin case connected to the metal substrate and extending along at least a portion thereof, and around the first conductive plate, the insulating substrate, the second conductive plate, the conductive pad, the semiconductor element, and the circuit board, and a silicone gel in a region bounded by the metal substrate and the resin case. The circuit board comprises a plurality of planar surfaces oriented perpendicular to the mounting surface of the metal substrate.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: February 19, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Shuji Kamata
  • Patent number: 10141247
    Abstract: The invention relates to a power semiconductor device with a substrate and an electrically conductive DC voltage bus bar system and a capacitor connected to the bus bar system, wherein the power semiconductor device has, for securing the capacitor, a capacitor securing apparatus comprising a receptacle device for receiving the capacitor, in which at least part of the capacitor is arranged. Electrically conductive bus bar system terminal elements are electrically connected thereto and run in the direction of the substrate. An elastic first deformation element is materially bonded to the capacitor securing apparatus and is formed from an elastomer is arranged on the side of the capacitor securing apparatus facing the DC voltage bus bar system.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: November 27, 2018
    Assignee: SEMIKRON ELEKTRONIK GMBH & CO. KG
    Inventor: Christian Walter
  • Patent number: 10121773
    Abstract: A semiconductor apparatus reduces the effect of inductances and induced magnetic fields, and causes a large current to flow from one device to another device. Provided is a semiconductor apparatus comprising a first device of a first region; a second device of a second region; and a connection conductor that electrically connects the first device to the second device. The connection conductor includes current paths that are adjacent and have opposite directions in at least a portion thereof. The connection conductor causes current to flow from the first device to the second device, and causes current to flow in a direction from the second device toward the first device in at least a portion thereof.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: November 6, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hideo Ami
  • Patent number: 10056355
    Abstract: A common-source type package structure is provided in the present invention. In the package structure, an integrated component body is configured a common-source pin region, a first arrangement region and a second arrangement region. The second and first arrangement regions are spaced apart from each other. A first MOSFET die and a second MOSFET are respectively located at the first and second arrangement region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed to the top surface and spaced apart from each other. A common-source connection element is connected to the source electrode pad and the common-source pin region. A gate connection element is connected to the gate electrode pad and a gate pin region of the integrated component body.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: August 21, 2018
    Assignee: Taiwan Semiconductor Co., Ltd.
    Inventors: Chien-Chung Chen, Sen Mao, Hsin-Liang Lin
  • Patent number: 10043738
    Abstract: In one embodiment, an IC package assembly for a switching regulator, can include: a power switch chip including a control electrode and a first electrode on an obverse side and a second electrode on a reverse side, where the second electrode is configured as a switching terminal of a switching regulator; a control chip including a driving electrode and a plurality of input and output electrodes on the obverse side; and a leadframe including an extension pin, a substrate, and a plurality of discrete pins, where the extension pin is formed integrally with the substrate, and where the reverse side of the power switch chip is arranged on the substrate of the leadframe by a conductive material to electrically connect the second electrode to the substrate.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: August 7, 2018
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Jiaming Ye, Xiaochun Tan
  • Patent number: 9998109
    Abstract: A power module includes a first terminal, a second terminal, and a number of semiconductor die coupled between the first terminal and the second terminal. The semiconductor die are configured to provide a low-resistance path for current flow from the first terminal to the second terminal during a forward conduction mode of operation and a high-resistance path for current flow from the first terminal to the second terminal during a forward blocking configuration. Due to improvements made to the power module, it is able to pass a temperature, humidity, and bias test at 80% of its rated voltage for at least 1000 hours.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: June 12, 2018
    Assignee: Cree, Inc.
    Inventors: Mrinal K. Das, Adam Barkley, Brian Fetzer, Jonathan Young, Van Mieczkowski, Scott Allen
  • Patent number: 9997620
    Abstract: A semiconductor device and an electronic device are improved in performances by supporting a large current. An emitter terminal protrudes from a first side of a sealing body, and signal terminals protrude from a second sides of the sealing body. Namely, the side of the sealing body from which the emitter terminal protrudes and the side of the sealing body from which the signal terminals protrude are different. More particularly, the signal terminals protrude from the side of the sealing body opposite the side thereof from which the emitter terminal protrudes. Further, a second semiconductor chip including a diode formed therein is mounted over a first surface of a chip mounting portion in such a manner as to be situated between the emitter terminal and the a first semiconductor chip including an IGBT formed therein in plan view.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: June 12, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Akira Muto, Nobuya Koike, Masaki Kotsuji, Yukihiro Narita
  • Patent number: 9935577
    Abstract: A method of detecting a fault of a semiconductor device including a power device mounted on a metal base and a drive circuit for driving the power device, the method detecting a fault of the semiconductor device beforehand based on an increase in thermal resistance between the metal base and the power device. A state of the power device is measured immediately before and after the power device is driven by the drive circuit. A temperature difference of the power device before and after driving is calculated according to the result of measurement. An increase in thermal resistance between the metal base and the power device is detected based on the temperature difference and an amount of electricity inputted to the power device in the driving period, and a fault of the semiconductor device is detected beforehand according to the increase.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: April 3, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsutoshi Bito, Daisuke Iijima, Yuji Takehara
  • Patent number: 9922585
    Abstract: A display device includes a display panel with signal wire pads connected to data lines; an integrated circuit (IC) that feeds a data voltage to the data lines; a multiplexer disposed on a substrate of the display panel, between the data lines and the integrated circuit; a flexible circuit board bonded onto the substrate of the display panel and connected to the signal wire pads; and a test circuit on the substrate of the display panel.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: March 20, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Kakyung Kim, Euihyun Chung, Yeseul Han
  • Patent number: 9917031
    Abstract: A semiconductor device includes an insulating substrate; a semiconductor element mounted on the insulating substrate; and a radiation block bonded to the semiconductor element. The radiation block includes a three-dimensional radiation portion and a base portion connected to the radiation portion. The radiation portion of the radiation block has a pin shape, a fin shape, or a porous shape.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: March 13, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shin Soyano
  • Patent number: 9899481
    Abstract: In an embodiment, an electronic component includes a compound semiconductor transistor device having a first current electrode, a second current electrode and a control electrode, a die pad, a first lead, a second lead and a third lead. The first lead, the second lead and the third lead are spaced at a distance from the die pad. The control electrode is coupled to the first lead, the first current electrode is coupled to the die pad and the second current electrode is coupled to the second lead. The third lead is coupled to the compound semiconductor transistor device and provides a source sensing functionality.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: February 20, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Klaus Schiess
  • Patent number: 9852968
    Abstract: The semiconductor device includes an insulating substrate on which is mounted a main circuit part including a semiconductor chip, a printed substrate wherein a conductive connection member connected to the semiconductor chip is disposed on the surface opposing the insulating substrate, a first sealing member that seals so as to enclose the semiconductor chip between the opposing surfaces of the insulating substrate and printed substrate, and a second sealing member that covers the whole excepting a bottom portion of the insulating substrate, the semiconductor device having sealing region regulation rod portions disposed in an outer peripheral portion of a sealing region of the first sealing member and connected between the insulating substrate and printed substrate, wherein the heat resistance temperature of the first sealing member is set to be higher than the heat resistance temperature of the second sealing member.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: December 26, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Norihiro Nashida
  • Patent number: 9848518
    Abstract: An integrated power module packaging structure includes a plastic housing having a cavity; a plurality of step-shaped pins embedded in the plastic housing, a first printed circuit board disposed in the cavity, and a second printed circuit board disposed above the first printed circuit board in the cavity. Each of the step-shaped pins includes a first L-shaped bending portion and a second L-shaped bending portion connected to each other. The first printed circuit board is disposed with at least a power device and is electrically connected to at least a part of the first L-shaped bending portions. Two opposite surfaces of the second printed circuit board are respectively disposed with at least an electronic device, and the second printed circuit board is electrically connected to at least a part of the second L-shaped bending portions.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: December 19, 2017
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Te-Wei Yuan, Hsueh-Kuo Liao, Yi-Kai Chou, Ming-Yuan Tsai, Wei-Hao Chi
  • Patent number: 9806244
    Abstract: Provided is a substrate for a light emitting device having high reflectivity, high heat radiating properties, dielectric strength voltage properties, long-term reliability including heat resistance and light resistance, and excellent mass productivity. A substrate (20) for a light emitting device includes: a first insulating layer (11) having thermal conductivity which is formed on a surface of one side of a metal base (2); a wiring pattern (3) which is formed on the first insulating layer (11); and a second insulating layer (12) having light reflectivity which is formed on the first insulating layer (11) and on some parts of the wiring pattern (3), so that some parts of the wiring pattern (3) are exposed, in which the first insulating layer (11) is a layer of ceramic formed by thermal spraying.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: October 31, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masahiro Konishi, Shin Itoh, Hiroyuki Nokubo, Yoshiaki Itakura
  • Patent number: 9753083
    Abstract: A parallelism adjusting device and a parallelism adjusting method capable of adjusting the parallelism between the surface of a semiconductor and the surface of an electrode by reducing the load on the semiconductor and capable of shortening the cycle time by increasing the operating speed. A probe device of adjusting the parallelism between the surface and the surface of a contact body that is in contact with the surface to press the surface and apply a current is configured to include a pressing body assembly that presses the contact body with a predetermined pressing force until the surface and the surface come into contact with each other to adjust the parallelism and, after that, presses the contact body with a pressing force that is stronger than the predetermined pressing force.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: September 5, 2017
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Shigeto Akahori, Nobuo Kambara
  • Patent number: 9704779
    Abstract: A semiconductor module cooler for reducing a pressure loss of a coolant includes a first plate mounted with a first semiconductor module; a jacket disposed under the first plate and having a distribution portion, and first and second through-holes separated from each other to be disposed at end portions of the depression respectively; an inlet-side header disposed to cover the first through-hole from under the jacket; an outlet-side header disposed to cover the second through-hole from under the jacket and extending in parallel to the inlet-side header; and a plurality of cooling fins disposed in the depression and extending from above a distribution portion of the inlet-side header to above a water collection portion of the outlet-side header.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: July 11, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiromichi Gohara, Nobuhide Arai
  • Patent number: 9659847
    Abstract: A semiconductor die comprising a terminal structure for an active power device. The terminal structure comprises a metallic layer arranged to be electrically coupled between the active power device and an external contact of an integrated circuit package, a conductive sub-structure extending in parallel with the metallic layer, and located such that, when mounted within an integrated circuit device, the conductive sub-structure lies between the metallic layer and a reference voltage plane, and interconnecting elements extending between the metallic layer and the conductive sub-structure and electrically coupling the metallic layer to the conductive sub-structure.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: May 23, 2017
    Assignee: NXP USA, INC.
    Inventor: Igor Ivanovich Blednov
  • Patent number: 9640511
    Abstract: According to a method for producing a circuit carrier arrangement, a carrier which has a surface section formed by an aluminum/silicon carbide metal matrix composite material is provided. A circuit carrier, which has an insulation carrier with a lower side onto which a lower metallization layer is applied, is also provided. A bonding layer, which contains a glass, is generated on the surface section. A material-fit connection between the bonding layer and the circuit carrier is produced by means of a connecting layer.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: May 2, 2017
    Assignee: Infineon Technologies AG
    Inventor: Olaf Hohlfeld
  • Patent number: 9607940
    Abstract: A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin and a first member is fixed to a chip mounting surface side between a peripheral portion of the semiconductor chip and a peripheral portion of the chip mounting part. Also, the first member is sealed by the resin. Also, a length of the first part of the chip mounting part in the first direction is larger than a length of the semiconductor chip in the first direction, in a plan view.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: March 28, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuichi Yato, Hiroi Oka, Noriko Okunishi, Keita Takada
  • Patent number: 9468087
    Abstract: Disclosed examples include power modules and fabrication methods therefor in which one or more power device dies include a switching device and a second device die with a circuit component are mounted to a lead frame or other interconnect structure on a substrate structure, and a body structure is formed around portions of the power module providing a first opening to expose a portion of the substrate structure to provide an externally accessible first exposed surface along the top of the power module, and the body structure includes a second opening exposing a portion of the first device die along the bottom of the power module to provide a thermally conductive path to draw heat away from the power device dies.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: October 11, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Rajeev Dinkar Joshi
  • Patent number: 9324646
    Abstract: According to an exemplary implementation, a power quad flat no-lead (PQFN) leadframe includes U-phase, V-phase, and W-phase power switches situated on the PQFN leadframe. A drain of the U-phase power switch is connected to a U-phase output strip of the PQFN leadframe. A source of the U-phase power switch is connected to a U-phase current sense terminal. The U-phase output strip can substantially traverse across the PQFN leadframe. Another U-phase power switch is situated on the PQFN leadframe with a source of the another U-phase power switch connected to the U-phase output strip of the PQFN leadframe. The PQFN leadframe can include a leadframe island within the U-phase output strip. At least one wirebond may be connected to the U-phase output strip.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: April 26, 2016
    Assignee: Infineon Technologies America Corp.
    Inventors: Dean Fernando, Roel Barbosa, Toshio Takahashi
  • Patent number: 9269699
    Abstract: The present invention discloses a new embedded package comprising: a pre-mold lead frame with a plurality of chips attached thereon, where the molding material fills the voids of the lead frame, so that the lead frame is entirely solid; a plurality of pins arranged around the lead frame; a metal clip attached on and electrically connecting the chips together; first laminate layer which covers the chips, the lead frame, a metal clip and pins; conductive plug and extension formed to connect an electrode of a chip to a corresponding pin or to connect the chips together. The new embedded package of the invention with a three-dimensional stack capacity improves the thickness, thermal and electrical properties and the flexible power and logic hybrid design.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: February 23, 2016
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Zhiqiang Niu, Hua Pan, Ming-Chen Lu, Yueh-Se Ho, Jun Lu
  • Patent number: 9159654
    Abstract: A semiconductor device includes a semiconductor substrate having opposed main and back surfaces; first and second electrodes in a device region of the substrate, and spaced apart from each other; a metal film on the main surface and joined to the second electrode; an air gap between part of the main surface and the metal film, enveloping the first electrode, and having an opening; a cured resin closing the opening; a liquid repellent film increasing contact angle of the resin, relative to contact angles on the substrate and the metal film; a first metal film joined to the metal film, covering the metal film and the cured resin, and joined to an outer peripheral region of the substrate, at a periphery of the device region; and a second metal film on the back surface and connected to the first electrode through a via hole penetrating the substrate.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: October 13, 2015
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Youichi Nogami, Hidetoshi Koyama, Yoshitsugu Yamamoto
  • Patent number: 9029995
    Abstract: To enhance the reliability of connection between a semiconductor chip and a metal plate by ensuring sufficiently the thickness of a conductive material interposed between the semiconductor chip and the metal plate. A lead frame is arranged over a jig and a clip frame is arranged over protruding portions provided on the jig. In this state, a heating process (reflow) is performed. In this case, high melting point solders filling first spaces are melted in a state in which the first space is formed between a High-MOS chip and a High-MOS clip and the first space is formed between a Low-MOS chip and a Low-MOS clip. At this time, even when the high melting point solder is melted in the first space, the size (in particular, the height) of the first space does not change and the first space is maintained.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: May 12, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Funatsu, Tomoaki Uno, Toru Ueguri, Yasushi Takahashi
  • Patent number: 9006784
    Abstract: A semiconductor device includes a link portion that connects a second heat sink to a third heat sink via a solder. The solder is arranged on a connecting surface of a base portion of the link portion, which is orthogonal to a plate thickness direction of the base portion, in a direction perpendicular to first and second surfaces. The link portion has a rib that protrudes from the base portion in a direction orthogonal to the first and second surfaces, and a thickness of a portion where the rib is provided is equal to or less than the thickness of the corresponding heat sink. The rib is provided across an entire length of a first region that is sealed by a sealing resin body and that is between the second and the third heat sinks, in an alignment direction of a first heat sink and the third heat sink.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: April 14, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Tomomi Okumura, Takuya Kadoguchi
  • Patent number: 8994165
    Abstract: A power semiconductor device includes power semiconductor elements joined to wiring patterns of a circuit substrate, cylindrical external terminal communication sections, and wiring means for forming electrical connection between, for example, the power semiconductor elements and the cylindrical external terminal communication sections. The power semiconductor elements, the cylindrical external terminal communication sections, and the wiring means are sealed with transfer molding resin. The cylindrical external terminal communication sections are arranged on the wiring patterns so as to be substantially perpendicular to the wiring patterns, such that external terminals are insertable and connectable to the cylindrical external terminal communication sections, and such that a plurality of cylindrical external terminal communication sections among the cylindrical external terminal communication sections are arranged two-dimensionally on each of wiring patterns that act as main circuits.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: March 31, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takeshi Oi, Seiji Oka, Yoshiko Obiraki, Osamu Usui, Yasushi Nakayama
  • Patent number: 8982561
    Abstract: A lightweight radio/CD player for vehicular application includes a case and frontal interface formed of polymer based material molded to provide details to accept audio devices and radio receivers, as well as the circuit boards required for electrical control and display. The case and frontal interface are of composite structure, including an insert molded electrically conductive wire mesh screen that has been pre-formed to contour with the molding operation. The wire mesh provides shielding and grounding of the circuit boards via exposed wire mesh pads and adjacent ground clips.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: March 17, 2015
    Assignee: Delphi Technologies, Inc.
    Inventors: Chris R. Snider, Vineet Gupta, Joseph K. Huntzinger, Michael G. Coady, Curtis Allen Stapert, Kevin Earl Meyer, Timothy D. Garner, Allen E. Oberlin
  • Patent number: 8981542
    Abstract: A semiconductor power module according to the present invention includes a base member, a semiconductor power device having a surface and a rear surface with the rear surface bonded to the base member, a metal block, having a surface and a rear surface with the rear surface bonded to the surface of the semiconductor power device, uprighted from the surface of the semiconductor power device in a direction separating from the base member and employed as a wiring member for the semiconductor power device, and an external terminal bonded to the surface of the metal block for supplying power to the semiconductor power device through the metal block.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: March 17, 2015
    Assignee: Rohm Co., Ltd.
    Inventor: Toshio Hanada
  • Patent number: 8975537
    Abstract: A circuit substrate includes a resin layer; and an inorganic insulating layer including a groove portion penetrating the inorganic insulating layer in a thickness direction thereof. A part of the resin layer is in the groove portion.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: March 10, 2015
    Assignee: Kyocera Corporation
    Inventor: Katsura Hayashi
  • Patent number: 8975099
    Abstract: An ESD protection device is manufactured such that its ESD characteristics are easily adjusted and stabilized. The ESD protection device includes an insulating substrate, a cavity provided in the insulating substrate, at least one pair of discharge electrodes each including a portion exposed in the cavity, the exposed portions being arranged to face each other, and external electrodes provided on a surface of the insulating substrate and connected to the at least one pair of discharge electrodes. A particulate supporting electrode material having conductivity is dispersed between the exposed portions of the at least one pair of discharge electrodes in the cavity.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: March 10, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Jun Adachi, Jun Urakawa, Issei Yamamoto
  • Patent number: 8933484
    Abstract: A heat transfer member is disposed between a semiconductor element and an electrode plate. The heat transfer member comprises a metal portion extending between a first face at the semiconductor element side and a second face at the plate electrode side, and a ceramic portion surrounding the metal portion. An area of the first face is less than an area of the second face in the metal portion.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: January 13, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Makoto Imai, Atsushi Tanida, Takashi Asada, Masanori Usui, Tomoyuki Shoji
  • Patent number: 8779466
    Abstract: An ESD protection device is manufactured such that its ESD characteristics are easily adjusted and stabilized. The ESD protection device includes an insulating substrate, a cavity provided in the insulating substrate, at least one pair of discharge electrodes each including a portion exposed in the cavity, the exposed portions being arranged to face each other, and external electrodes provided on a surface of the insulating substrate and connected to the at least one pair of discharge electrodes. A particulate supporting electrode material having conductivity is dispersed between the exposed portions of the at least one pair of discharge electrodes in the cavity.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: July 15, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Jun Adachi, Jun Urakawa, Issei Yamamoto