Conductivity Modulation Device (e.g., Unijunction Transistor, Double-base Diode, Conductivity-modulated Transistor) Patents (Class 257/212)
  • Patent number: 10593796
    Abstract: A transistor includes a substrate of a first conductivity type. An epitaxial layer of the first conductivity type is formed at a top surface of the substrate. A first region of the first conductivity type is formed as a well in the epitaxial layer. A second region of a second conductivity type is formed as a well in the epitaxial layer adjacent to the first region and the second conductivity type is opposite of the first conductivity type. A third region of the second conductivity type is formed in the first region and a portion of the first region forms a channel region between the third region and the second region. An emitter region of the first conductivity type is formed in the second region. A gate dielectric is formed over the channel region, and a gate electrode is formed on gate dielectric with the gate electrode overlapping at least a portion of second region and the third region.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: March 17, 2020
    Assignee: NXP USA, INC.
    Inventors: Zihao M. Gao, Christopher Paul Dragon, Walter Sherrard Wright
  • Patent number: 10276667
    Abstract: A vertical conduction junction transistor apparatus includes a multilayered semiconductor unit cell that has a substrate, epitaxial drift layer, epitaxial channel layer, gate region and channel control region. The substrate is silicon carbide (SiC). The epitaxial drift layer comprises SiC and is formed on the top surface of the substrate. The epitaxial channel layer comprises SiC and is formed on a top surface of the epitaxial drift layer, where a sidewall of the epitaxial channel layer is at an angle to the vertical direction. The gate region is formed in the sidewall of the epitaxial channel layer, the gate region having an inner gate region boundary that is parallel to the sidewall. The channel control region is in the epitaxial channel layer and has a width bounded by the inner gate region boundary. The channel control region has a trapezoidal cross-section in a plane taken in the vertical direction.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: April 30, 2019
    Assignee: Silanna Asia Pte Ltd
    Inventor: Petar Atanackovic
  • Patent number: 10134920
    Abstract: A mesa type p-n junction diode silicon carbide semiconductor device that includes a first silicon carbide semiconductor substrate, a first drift layer formed on the silicon carbide semiconductor substrate, a second anode layer formed on the drift layer, a mesa structure having a flat mesa bottom portion formed in an outer periphery thereof and having a mesa side wall obliquely formed with respect to a top face of the anode layer in a cross-section ranging from the anode layer to the drift layer, a second lightly doped region formed from an edge of the anode layer to the mesa bottom portion, and a second highly doped region formed on the side of the mesa side wall in the lightly doped region in contact with the edge of the anode layer and in a portion connected to the mesa bottom portion at a lower part of the mesa side wall.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: November 20, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kotaro Kawahara, Kohei Ebihara
  • Patent number: 10032865
    Abstract: A power semiconductor device is provided. The power semiconductor device includes a substrate having a device region and a surrounding termination region; and at least a power device formed in the device region of the substrate. The power semiconductor substrate also includes a termination structure having a plurality of semiconductor plugs formed in a first surface of the termination region of the substrate. Wherein the plurality of the semiconductor plugs are formed in a plurality of ring trenches formed in the first surface of the substrate in the termination regions, with a semiconductor plug formed in each of the plurality of ring trenches.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: July 24, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Dae Sub Jung, Bo Liu, Roger To-Hoi Szeto
  • Patent number: 9960140
    Abstract: The present invention can give a joining structure using metal nanoparticles to join the same types or different types of metal where when one surface metal is Al based, the parts are joined through a joining layer containing Ni nanoparticles, whereby a good joining strength is obtained. Further, by using two joining layers (6, 8) including metal nanoparticles to sandwich metal foil (7) so as to form a joining layer and joining the same type or different types of surface metals (3-4) through this joining layer, it is possible to ease the thermal stress due to the difference in amounts of thermal expansion of joined members which have two surface metals.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: May 1, 2018
    Assignees: NIPPON STEEL & SUMITOMO METAL CORPORATION, WASEDA UNIVERSITY
    Inventors: Kohei Tatsumi, Shinji Ishikawa, Norie Matsubara, Masamoto Tanaka
  • Patent number: 9865748
    Abstract: A semiconductor structure includes a semiconductor substrate having a first electrical portion, a second electrical portion, and a bridged conductive layer. The first electrical portion includes a first semiconductor well, a second semiconductor well in the first semiconductor well, and a third semiconductor well and a fourth semiconductor well in the second semiconductor well. The second electrical portion includes a fifth semiconductor well, a semiconductor layer in the fifth semiconductor well, and a sixth semiconductor well and a seventh semiconductor well in the fifth semiconductor well. The semiconductor layer has separated first and second portions. The bridged conductive layer connects the fourth semiconductor well and the sixth semiconductor well.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: January 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Chih Chiang, Tung-Yang Lin, Chih-Chang Cheng, Ruey-Hsin Liu
  • Patent number: 9831172
    Abstract: A semiconductor device includes a first device isolation region and a second device isolation region defining a first active region, a second active region, and a third active region in a substrate, a recess region exposing an upper surface of the first active region and upper surfaces of the first and second device isolation regions, and active buffer patterns on the second and third active regions. The first active region is located between the second and third active regions, the first device isolation region is located between the first and second active regions, the second device isolation region is located between the first and third active regions. Upper sidewalls of the second and third active regions are exposed in the recess region.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: November 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Daeik Kim, Jemin Park, Sunghee Han, Yoosang Hwang
  • Patent number: 9595604
    Abstract: Provided is an electronic element that functions as a switch or memory without using metal nanoparticle. The electronic element includes: one electrode 5A and an other electrode 5B arranged to have a nanogap therebetween; and halide ion 6 provided between the electrodes 5A and 5B; and on one of the electrodes.
    Type: Grant
    Filed: March 9, 2014
    Date of Patent: March 14, 2017
    Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Yutaka Majima, Toshiharu Teranishi, Yasuo Azuma, Masanori Sakamoto, Shinya Kano, Daniel Eduardo Hurtado Salinas
  • Patent number: 9520359
    Abstract: A semiconductor device, which may be included in a display driver integrated circuit (IC) and a display device, includes a first interconnection and a second interconnection extending on a substrate and separate from each other, a third interconnection extending at a first level that is higher than a level at which the first interconnection and the second interconnection are disposed, and a fourth interconnection extending at a second level that is higher than the first level. A first contact plug is configured to connect the first interconnection and the third interconnection to each other. A stacked contact plug includes a second contact plug and a third contact plug, wherein the second contact plug is connected to the second interconnection, and the third contact plug is connected to the second contact plug and the fourth interconnection.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: December 13, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Myoung-Soo Kim
  • Patent number: 9455202
    Abstract: A mask set includes a first mask and a second mask. The first mask includes geometric patterns. The second mask includes at least a strip-shaped pattern with a first edge and a second edge opposite to the first edge. The strip-shaped pattern has a centerline along a long axis of the strip-shaped pattern. The first edge includes inwardly displaced segments shifting towards the centerline and each of the inwardly displaced segments overlaps each of the geometric patterns.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: September 27, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Chi Lee, Yu-Lin Wang, Chung-Yuan Lee
  • Patent number: 9385114
    Abstract: A non-linear element, such as a diode, in which an oxide semiconductor is used and a rectification property is favorable is provided. In a thin film transistor including an oxide semiconductor in which the hydrogen concentration is less than or equal to 5×1019/cm3, the work function ?ms of a source electrode in contact with the oxide semiconductor, the work function ?md of a drain electrode in contact with the oxide semiconductor, and electron affinity ? of the oxide semiconductor satisfy ?ms??<?md. By electrically connecting a gate electrode and the drain electrode of the thin film transistor, a non-linear element with a more favorable rectification property can be achieved.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: July 5, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Kawae
  • Patent number: 9331143
    Abstract: A semiconductor structure is provided. The semiconductor structure comprises: a substrate; a first doping region, a first well and a second doping region formed in the substrate; a plurality of first heavily doped regions formed in the first doping region; a plurality of conductors and a plurality of dielectrics formed on the substrate between the first heavily doped regions; a second heavily doped region formed in the first well; a third heavily doped region and a fourth heavily doped region formed in the second doping region; as well as a first gate electrode and a first gate dielectric. The first doping region, the first well, the second heavily doped region and the fourth heavily doped region have a first type of doping. The second doping region, the first heavily doped regions and the third heavily doped region have a second type of doping.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: May 3, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ying-Chieh Tsai, Wing-Chor Chan, Shyi-Yuan Wu, Jeng Gong
  • Patent number: 9312372
    Abstract: A semiconductor device in which an element region including at least an IGBT region is formed on a semiconductor substrate is presented. The IGBT region including: a collector layer; a drift layer; a body layer; a gate electrode placed inside a trench extending from the front surface of the semiconductor substrate to the drift layer; an emitter layer; and a contact layer having a higher impurity concentration than the body layer. In the semiconductor device, assuming that an x direction is a direction in which the trench extends along the front surface of the semiconductor substrate and that a y direction is a direction orthogonal to the x direction along the front surface of the semiconductor substrate, a distance from the contact layer to the emitter layer in the x direction is larger than a distance from the contact layer to the trench in the y direction.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: April 12, 2016
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Keisuke Kimura, Satoru Kameyama
  • Patent number: 9275863
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: March 1, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Patent number: 9093287
    Abstract: A method of manufacturing a diode is provided. An N-type well region is formed in a first upper portion of an N-type epitaxial layer. A P-type drift region is formed in a second upper portion of the N-type epitaxial layer. An N-type doping region is formed in the N-type well region. A P-type doping region is formed in the P-type drift region. An isolation structure is formed in the P-type drift region. The isolation structure is disposed between the P-type doping region and the N-type well region. A first electrode is formed on a portion of the N-type epitaxial layer. The portion of the N-type epitaxial layer is disposed between the N-type well region and the P-type drift region. The first electrode overlaps a portion of the isolation structure. A connection structure is formed to electrically couple the N-type doping region and the first electrode.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: July 28, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hyok Ko, Han-Gu Kim, Min-Chang Ko, Chang-Su Kim, Kyoung-Ki Jeon
  • Patent number: 9070768
    Abstract: A depletion type DMOS transistor comprises a gap in electrode material allowing incorporation of a well dopant species into the underlying semiconductor material. During subsequent dopant diffusion a continuous well region is obtained having an extended lateral extension without having an increased depth. The source dopant species is implanted after masking the gap. Additional channel implantation is performed prior to forming the gate dielectric material.
    Type: Grant
    Filed: February 15, 2010
    Date of Patent: June 30, 2015
    Assignees: X-FAB Semiconductor Foundries AG, Texas Instruments Inc
    Inventors: Ralf Lerner, Phil Hower, Gabriel Kittler, Klaus Schottmann
  • Patent number: 9035189
    Abstract: A circuit board comprising a circuit carrier, a cover layer composed of a nonconductive material, comprising an organic substance, arranged on the circuit carrier, a first metallization layer at least partly arranged on the cover layer, wherein the first metallization layer has a flexible region.
    Type: Grant
    Filed: June 8, 2009
    Date of Patent: May 19, 2015
    Assignee: EPCOS AC
    Inventors: Wolfgang Pahl, Hans Krueger, Peter Demmer
  • Publication number: 20150076565
    Abstract: The disclosure provides an ultrahigh-voltage (UHV) semiconductor structure including a first electrical portion, a second electrical portion and a bridged conductive layer. In which, the first electrical portion and the second electrical portion are isolated, and directly connected to each other through the bridged conductive layer. Thus, there is no current leakage occurring in the UHV semiconductor structure disclosed in this disclosure. And a method for manufacturing the UHV semiconductor structure also provides herein.
    Type: Application
    Filed: September 13, 2013
    Publication date: March 19, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Chih CHIANG, Tung-Yang LIN, Chih-Chang CHENG, Ruey-Hsin LIU
  • Patent number: 8890279
    Abstract: A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: November 18, 2014
    Assignee: PFC Device Corp.
    Inventors: Kou-Liang Chao, Mei-Ling Chen, Tse-Chuan Su, Hung-Hsin Kuo
  • Publication number: 20140285933
    Abstract: The inventive concept shows the embodiment of t-switch which is a MIT 3-terminal device based on a Hole-driven MIT theory and a technology for removing an ESD noise signal which is one of applications of the t-switch. The t-switch includes three terminals of Inlet, Outlet and Control, and a metal-insulator transition (MIT) occurs at an Outlet layer by a current flowing through the Control terminal. In the t-switch, a high resistor is connected to the Control terminal and thereby an ESD noise signal of high voltage flows through the Inlet-Outlet without damaging the device.
    Type: Application
    Filed: October 26, 2012
    Publication date: September 25, 2014
    Applicant: ELectronics and Telecommunications Research Institute
    Inventors: Hyun-Tak Kim, Bongjun Kim, Jeong Yong Choi, Jong Chan Park
  • Patent number: 8816404
    Abstract: A semiconductor device has a first conductive layer formed over a first substrate. A second conductive layer is formed over a second substrate. A first semiconductor die is mounted to the first substrate and electrically connected to the first conductive layer. A second semiconductor die is mounted to the second substrate and electrically connected to the second conductive layer. The first semiconductor die is mounted over the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and the first and second substrates. A conductive interconnect structure is formed through the encapsulant to electrically connect the first and second semiconductor die to the second surface of the semiconductor device. Forming the conductive interconnect structure includes forming a plurality of conductive vias through the encapsulant and the first substrate outside a footprint of the first and second semiconductor die.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: August 26, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: YoungJoon Kim, SangMi Park, YongHyuk Jeong
  • Patent number: 8791456
    Abstract: A non-linear element, such as a diode, in which an oxide semiconductor is used and a rectification property is favorable is provided. In a thin film transistor including an oxide semiconductor in which the hydrogen concentration is less than or equal to 5×1019/cm3, the work function ?ms of a source electrode in contact with the oxide semiconductor, the work function ?md of a drain electrode in contact with the oxide semiconductor, and electron affinity ? of the oxide semiconductor satisfy ?ms??<?md. By electrically connecting a gate electrode and the drain electrode of the thin film transistor, a non-linear element with a more favorable rectification property can be achieved.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 29, 2014
    Assignee: Semiconductor Energy Laboratory Co. Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Kawae
  • Patent number: 8785982
    Abstract: A unit pixel of a depth sensor including a light-intensity output circuit configured to output a pixel signal according to a control signal, the pixel signal corresponding to a first electric charge and a second electric charge, a first light-intensity extraction circuit configured to generate the first electric charge and transmit the first electric charge to the light-intensity output circuit, the first electric charge varying according to an amount of light reflected from a target object and a second light-intensity extraction circuit configured to generate the second electric charge and transmit the second electric charge to the light-intensity output circuit, the second electric charge varying according to the amount of reflected light. The light-intensity output circuit includes a first floating diffusion node. Accordingly, it is possible to minimize waste of a space, thereby manufacturing a small-sized pixel.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: July 22, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo Joo Kim, Hyoung Soo Ko, Yoon Dong Park, Jung Bin Yun
  • Patent number: 8766325
    Abstract: A semiconductor device includes: an n?-type base layer; a p-type base layer formed in a part of a front surface portion of the n?-type base layer; an n+-type source layer formed in a part of a front surface portion of the p-type base layer; a gate insulating film formed on the front surface of the p-type base layer between the n+-type source layer and the n?-type base layer; a gate electrode that faces the p-type base layer through the gate insulating film; a p-type column layer formed continuously from the p-type base layer in the n?-type base layer; a p+-type collector layer formed in a part of a rear surface portion of the n?-type base layer; a source electrode electrically connected to the n+-type source layer; and a drain electrode electrically connected to the n?-type base layer and to the p+-type collector layer.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: July 1, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Toshio Nakajima, Syoji Higashida
  • Patent number: 8766225
    Abstract: According to the embodiment, a storage device includes row lines arranged parallel to one another, column lines arranged parallel to one another to intersect with the row lines, and a memory cell disposed at each of intersections of the row lines and the column lines and including a resistance-change element and a diode connected in series to the resistance-change element. The diode includes a stack of a first semiconductor region containing an impurity of a first conductivity type, a second semiconductor region containing an impurity of the first conductivity type lower in concentration than in the first semiconductor region, and a third semiconductor region containing an impurity of a second conductivity type. An impurity concentration in the second semiconductor region of the diode in a first adjacent portion adjacent to the first semiconductor region is higher than that in a second adjacent portion adjacent to the third semiconductor region.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: July 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Murooka, Hiroshi Kanno
  • Patent number: 8716745
    Abstract: A diode is defined on a die. The diode includes a substrate of P conductivity having an upper surface and a lower surface, the substrate having first and second ends corresponding to first and second edges of the die. An anode contacts the lower surface of the substrate. A layer of N conductivity is provided on the upper surface of the substrate, the layer having an upper surface and a lower surface. A doped region of N conductivity is formed at an upper portion of the layer. A cathode contacts the doped region. A passivation layer is provided on the upper surface of the layer and proximate to the cathode.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: May 6, 2014
    Assignee: IXYS Corporation
    Inventor: Subhas Chandra Bose Jayappa Veeramma
  • Patent number: 8680619
    Abstract: The present disclosure provides a semiconductor device which includes a semiconductor substrate, a first gate structure disposed over the substrate, the first gate structure including a first gate electrode of a first conductivity type, a second gate structure disposed over the substrate and proximate the first gate structure, the second gate structure including a second gate electrode of a second conductivity type different from the first conductivity type, a first doped region of the first conductivity type disposed in the substrate, the first doped region including a first lightly doped region aligned with a side of the first gate structure, and a second doped region of the second conductivity type disposed in the substrate, the second doped region including a second lightly doped region aligned with a side of the second gate structure.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: March 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Compnay, Ltd.
    Inventors: Ming Zhu, Lee-Wee Teo, Harry Hak-Lay Chuang
  • Patent number: 8618626
    Abstract: A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: December 31, 2013
    Assignee: PFC Device Corporation
    Inventors: Kou-Liang Chao, Mei-Ling Chen, Tse-Chuan Su, Hung-Hsin Kuo
  • Patent number: 8541302
    Abstract: An electronic device can include a transistor structure including a semiconductor layer overlying a substrate and a trench extending into the semiconductor layer having a tapered shape. In an embodiment, the tapered shape includes a facet. The transistor structure can include a source region and a drain region wherein different portions of the drain regions are disposed adjacent to the primary surface and within the trench. In another embodiment, different facets may be spaced apart from each other. Processes of forming the tapered etch can be tailored based on the needs or desires of a fabricator.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: September 24, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gary H. Loechelt, Gordon M. Grivna
  • Patent number: 8492806
    Abstract: A non-linear element, such as a diode, in which an oxide semiconductor is used and a rectification property is favorable is provided. In a thin film transistor including an oxide semiconductor in which the hydrogen concentration is less than or equal to 5×1019/cm3, the work function ?ms of a source electrode in contact with the oxide semiconductor, the work function ?md of a drain electrode in contact with the oxide semiconductor, and electron affinity ? of the oxide semiconductor satisfy ?ms??<?md. By electrically connecting a gate electrode and the drain electrode of the thin film transistor, a non-linear element with a more favorable rectification property can be achieved.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: July 23, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Kawae
  • Patent number: 8471308
    Abstract: Process variation-tolerant diodes and diode-connected thin film transistors (TFTs), printed or patterned structures (e.g., circuitry) containing such diodes and TFTs, methods of making the same, and applications of the same for identification tags and sensors are disclosed. A patterned structure comprising a complementary pair of diodes or diode-connected TFTs in series can stabilize the threshold voltage (Vt) of a diode manufactured using printing or laser writing techniques. The present invention advantageously utilizes the separation between the Vt of an NMOS TFT (Vtn) and the Vt of a PMOS TFT (Vtp) to establish and/or improve stability of a forward voltage drop across a printed or laser-written diode. Further applications of the present invention relate to reference voltage generators, voltage clamp circuits, methods of controlling voltages on related or differential signal transmission lines, and RFID and EAS tags and sensors.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: June 25, 2013
    Assignee: Kovio, Inc.
    Inventors: Vivek Subramanian, Patrick Smith
  • Patent number: 8377826
    Abstract: A fin mask for forming saddle type fins in each of active regions formed in an island shape having a certain size with a major axis and a minor axis includes a first fin mask of a line type, and a second fin mask of an island type, wherein the first fin mask and the second fin mask in combination expose saddle type fin regions and cover ends of the neighboring active regions along the major axis.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: February 19, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kwang-Ok Kim
  • Patent number: 8324056
    Abstract: A vertical pillar semiconductor device may include a substrate, a group of channel patterns, a gate insulation layer pattern and a gate electrode. The substrate may be divided into an active region and an isolation layer. A first impurity region may be formed in the substrate corresponding to the active region. The group of channel patterns may protrude from a surface of the active region and may be arranged parallel to each other. A second impurity region may be formed on an upper portion of the group of channel patterns. The gate insulation layer pattern may be formed on the substrate and a sidewall of the group of channel patterns. The gate insulation layer pattern may be spaced apart from an upper face of the group of channel patterns. The gate electrode may contact the gate insulation layer and may enclose a sidewall of the group of channel patterns.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: December 4, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hoon Son, Jong-Wook Lee, Jong-Hyuk Kang
  • Patent number: 8291357
    Abstract: Disclosed are embodiments of on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: October 16, 2012
    Assignee: International Business Machines Corporation
    Inventors: Serafino Bueti, Adam J. Courchesne, Kenneth J. Goodnow, Todd E. Leonard, Peter A. Sandon, Peter A. Twombly, Charles S. Woodruff
  • Patent number: 8101942
    Abstract: The present invention is a two-state switching device based on two electrodes separated by a self-assembled monolayer. At least one of the electrodes may be composed of silver and the other electrode of any electrically conductive material, such as metals, especially gold or platinum. In the high-resistance OFF state, the two electrodes are separated by an organic monolayer having sufficiently low electrical conducting as to be considered non-conductive. Application of a negative threshold bias causes a silver ion filament to grown within the monolayer and bridge the gap between the two electrodes, changing the device into a low-resistance ON state. The device may be turned OFF by application of a positive threshold bias, which causes the ionic filament to retract back into the silver electrode.
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: January 24, 2012
    Assignee: The United States of America as represented by the Secretary of Commerce
    Inventors: Jeremy M. Beebe, James G. Kushmer
  • Patent number: 7977716
    Abstract: A photosensor and an imaging array utilizing the same are disclosed. The photosensor includes a light conversion region that has separate charge storage regions. The light conversion region includes a plurality of separate charge storage regions within a doped region, each charge collection region being doped such that the mobile charges generated by light striking that charge storage region are prevented from moving to an adjacent charge storage region. The photosensor also includes a plurality of transfer gates, having a gate region adjacent to a corresponding one of the charge storage regions and disposed between that charge storage region and a drain region. The charge collection regions and the drain regions are doped such that the mobile charges collected in the charge storage region will flow to the drain region when a first electric field is applied to the gate region.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: July 12, 2011
    Assignee: Fairchild Imaging, Inc.
    Inventor: XinQiao Liu
  • Publication number: 20110095633
    Abstract: Electric generator also can generate from silicon magnetic and quartz material by attract and repulsion polarity of silicon magnetic north and south apply force compress and decompress on quartz material to create electric signal. The other useful of silicon magnetic can keep holes charge at bay to create more free flow of electrons that help silicon switching faster and low heat.
    Type: Application
    Filed: October 27, 2009
    Publication date: April 28, 2011
    Inventor: Chi Hong Le
  • Patent number: 7880201
    Abstract: The present invention is a method and an apparatus for optical modulation, for example for use in optical communications links. In one embodiment, an apparatus for optical modulation includes a first silicon layer having one or more trenches formed therein, a dielectric layer lining the first silicon layer, and a second silicon layer disposed on the dielectric layer and filling the trenches.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: February 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Yurii A. Vlasov, Fengnian Xia
  • Patent number: 7868386
    Abstract: A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrate aligned to the gate structure, sidewall spacers formed on the sidewalls of the gate structure and overlying the lightly doped source/drain regions, deeper source/drain diffusions formed into the substrate aligned to the sidewall spacers and additional pocket implants of source/drain dopants formed at the boundary of the deeper source/drain diffusions and the substrate. In a preferred method, the additional pocket implants are formed using an angled ion implant with the angle being between 4 and 45 degrees from vertical. Additional embodiments include recesses formed in the source/drain regions and methods for forming the recesses.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: January 11, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kong-Beng Thei, Chung Long Cheng, Harry Chuang
  • Patent number: 7859025
    Abstract: A metal ion transistor and related methods are disclosed. In one embodiment, the metal ion transistor includes a cell positioned in at least one isolation layer, the cell including a metal ion doped low dielectric constant (low-k) dielectric material sealed from each adjacent isolation layer; a first electrode contacting the cell on a first side; a second electrode contacting the cell on a second side; and a third electrode contacting the cell on a third side, wherein each electrode is isolated from each other electrode.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: December 28, 2010
    Assignees: International Business Machines Corporation, Infineon Technologies North America Corporation
    Inventors: Fen Chen, Armin Fischer
  • Patent number: 7582895
    Abstract: Methods of producing electrochemical transistor devices are provided, wherein a solidified electrolyte is arranged in direct contact with at least a portion of an organic material having the ability to electrochemically altering its electrical conductivity through change of redox state thereof, such that a current between a source contact and a drain contact of the transistor is controllable by a voltage applied to a gate electrode. A electrochemical transistor device is also provided, wherein an ion isolative material is provided between a solidified electrolyte and an organic material having the ability to electrochemically altering its redox state, such that a transistor channel of said transistor is defined thereby.
    Type: Grant
    Filed: January 9, 2006
    Date of Patent: September 1, 2009
    Assignee: Acreo AB
    Inventors: Marten Armgarth, Miaioxiang M. Chen, David A. Nilsson, Rolf M. Berggren, Thomas Kugler, Tommi M. Remonen, Robert Forchheimer
  • Patent number: 7560757
    Abstract: A semiconductor device which is suitable for miniaturization, capable of improving variations in characteristics of a transistor and enhancing the current driving capability comprises a semiconductor substrate, an isolation protruding from the semiconductor substrate and having a width above the semiconductor substrate narrower than a width in the semiconductor substrate, a semiconductor layer formed on the semiconductor substrate portion between the isolations, and a MOSFET formed on the semiconductor layer.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: July 14, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masato Endo
  • Patent number: 7556990
    Abstract: A CMOS image sensor and a method for manufacturing the same improves signal efficiency by reducing a dark signal, and includes a substrate having a first conductive type comprising an image area and a circuit area, a STI isolation layer in the substrate for electrical isolation within the circuit area, and a field oxide in the substrate for electrical isolation within the image area.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: July 7, 2009
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Bum Sik Kim
  • Publication number: 20090027758
    Abstract: A reversible coloring and deccoloring solid-state device includes a solid-state electrolyte film and a coloring and decoloring film which colors or decolors the coloring and decoloring film reversibly by applying an electric field. A barrier thin film is inserted between the solid-state electrolyte film and the coloring and decoloring film. The barrier thin film comprises at least one layer which is formed by a material having a band gap energy, functions as a barrier for the carrier movement, and has a thickness of 7 nm to 7±2 nm which does not prevent ion conduction. The coloring and decoloring speed is 0.1 seconds to 0.3 seconds by a voltage driving.
    Type: Application
    Filed: March 20, 2006
    Publication date: January 29, 2009
    Applicant: NATIONAL UNIVERSITY CORPORATION TOKYO UNIVERSITY OF AGRICULTURE AND TECHNOLOGY
    Inventors: Nobuyoshi Koshida, Hideo Yoshimura
  • Publication number: 20080315260
    Abstract: An open-base semiconductor diode device has an emitter, base, and collector layers. The layers are configured and doped such that the device has an IV characteristic with: i. a punchthrough region beginning at a voltage Vpt with positive resistance, followed by, and ii. an avalanche region including a positive resistance stage beginning with conductivity modulation at Vcrit and Icrit and having a resistance Rcrit, iii. wherein the values of Vcrit, Icrit and Rcrit are set according to the layer configuration and doping. The device may have a double-base structure, and the width of a lower-doped base region may be minimised such that current density Jcrit at which the conductivity modulation occurs due to avalanche is increased. In one example, the device comprises a N-N+ or a P-P+ double-emitter. Thickness of N? or P? layers may be minimised such that the current-carrying capability is maximised and the doping of this layer does not affect the current-carrying capability of the device.
    Type: Application
    Filed: March 22, 2006
    Publication date: December 25, 2008
    Inventor: Russell Duane
  • Patent number: 7439563
    Abstract: A high-breakdown-voltage semiconductor device comprises a high-resistance semiconductor layer, trenches formed on the surface thereof in a longitudinal plane shape and in parallel, first regions formed on the semiconductor layer to be sandwiched between adjacent ones of the trenches and having an impurity concentration higher than that of the semiconductor layer, a second region having opposite conductivity to the first regions and continuously disposed in a trench sidewall and bottom portion, a sidewall insulating film disposed on the second region of the trench sidewall, a third region disposed on the second region of the trench bottom portion and having the same conductivity as and the higher impurity concentration than the second region, a fourth region disposed on the back surface of the semiconductor layer, a first electrode formed on each first region, a second electrode connected to the third region, and a third electrode formed on the fourth region.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: October 21, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuo Hatakeyama, Takashi Shinohe
  • Publication number: 20080197360
    Abstract: A diode structure having a reduced on-resistance in the forward-biased condition includes semiconductor layers, preferably of silicon carbide. The anode and cathode of the device are located on the same side of the bottom semiconductor layer, providing lateral conduction across the diode body. The anode is positioned on a semiconductor mesa, and the sides of the mesa are covered with a nonconductive spacer extending from the anode to the bottom layer. An ohmic contact, preferably a metal silicide, covers the surface of the bottom layer between the spacer material and the cathode. The conductive path extends from anode to cathode through the body of the mesa and across the bottom semiconductor layer, including the ohmic contact. The method of forming the diode includes reacting layers of silicon and metal on the appropriate regions of the diode to form an ohmic contact of metal silicide.
    Type: Application
    Filed: February 16, 2007
    Publication date: August 21, 2008
    Applicant: Cree, Inc.
    Inventors: Saptharishi Sriram, Thomas J. Smith, Helmut Hagleitner
  • Patent number: 7385231
    Abstract: A method of producing a porous thin-film-deposition substrate, which has the steps of: placing onto a substrate that has an electrostatic charge on its surface, fine particles with a surface electrostatic charge opposite to the electrostatic charge of the substrate surface, depositing a thin film on the fine-particle-placed substrate, and then removing the fine particles to form fine pores in the thin film; further, a method of producing an electron emitting element, which has the steps of: adding a catalyst metal on a substrate, placing fine particles onto the catalyst-added substrate, depositing a thin film on the fine-particle-placed substrate, then removing the fine particles to form fine pores in the film, and growing needle-shaped conductors on the catalyst metal that is exposed on a bottom face of the fine pore.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: June 10, 2008
    Assignee: FujifilmCorporation
    Inventors: Kiyoshi Fujimoto, Masakazu Nakamura
  • Publication number: 20070290234
    Abstract: A power Schottky rectifier device and method of making the same are disclosed. The Schottky rectifier device includes a LOCOS structure grown on the bottom of the trenches by using nitride spacer on the sidewall of the trenches as a thermal oxidation mask. A polycrystalline silicon layer is then filled the first trenches. Under LOCOS structure, a p doped region is optionally formed to minimize the current leakage when the device undergoes a reverse biased. A Schottky barrier silicide layer formed by sputtering and annealing steps is formed on the upper surfaces of the epi-layer and the polycrystalline silicon layer. A top metal layer served as anode is then formed on the Schottky barrier silicide layer and extended to cover a portion of field oxide region of the termination trench. A metal layer served as a cathode electrode is then formed on the backside surface of the substrate opposite to the top metal layer.
    Type: Application
    Filed: June 16, 2006
    Publication date: December 20, 2007
    Inventor: Shye-Lin Wu
  • Patent number: RE41866
    Abstract: There is disclosed a semiconductor device having an MOS gate for reducing variations in threshold voltage (Vth) with time wherein a surface protective film is not formed in a device area including channels but only in a device peripheral area, thereby reducing the amount of hydrogen atoms migrating to a silicon-silicon oxide interface in a cell area and, accordingly, reducing the number of Si—H chemical bonds at the interface.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: October 26, 2010
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Mitsuhiro Yano, Kouichi Mochizuki