Abstract: A power diode includes at least one semiconductor body having an inner zone f a first conductivity type and a given doping level, a cathode zone of the first conductivity type and a doping level higher than the given doping level, and an anode zone of a second conductivity type opposite the first conductivity type and a doping level higher than the given doping level. The inner zone has at least a first region with a first predetermined thickness being dimensioned for a required blocking voltage and a second region with a second thickness being greater than the first predetermined thickness by at least a factor of 1.4. The area and/or the minority carrier life of first and second partial diodes is dimensioned for causing a current flowing through the first partial diode in a conductive phase to be greater than a current flowing through the second partial diode by at least a factor of 2.

Abstract: An integrated CMOS diode with an injection ring which enables construction of an integrated CMOS diode that has the performance characteristics of a high impedance value, when the diode is in the off state, and low impedance, when the diode is in the on state in addition to high breakdown voltages using standard CMOS processing techniques to construct the integrated circuit diode.

Abstract: A diode type read only memory (ROM) includes a diode as a memory cell. The diode is a logic level "on" memory cell and coupled to one of the word lines and one of the bit lines of the ROM. A relative high voltage is given to the bit line coupled to the diode and a relative low voltage is given to the corresponding word line. Therefore, the data saved in the diode can be read out.

Abstract: A PIC structure includes a lightly doped semiconductor layer of the first conductivity type superimposed over a heavily doped semiconductor substrate of a second conductivity type, wherein a Vertical IGBT and a driving and control circuit including at least first conductivity type-channel MOSFETs are integrated. The MOSFETs are provided inside well regions of the second conductivity type which are included in at least one lightly doped region of the first conductivity type completely surrounded and isolated from the lightly doped layer of the first conductivity type by means of a respective isolated region of a second conductivity type.

Abstract: A plurality of minority carriers, which cause a conductivity modulation effect in a semiconductor device, are supplied from a separately disposed minority carrier injection region which is alternately connected to and separated from a drain region. The minority carriers are injected via the minority carrier injection region connected to the drain region during forward biasing. The minority carrier injection is stopped by separating the injection region from the drain region when the turn-off operation begins. This operation reduces the carriers that need to be swept off during a turn-off operation. The turn-off time is shortened in a bipolar semiconductor device, such as an IGBT with a reduced on-voltage, by utilizing the conductivity modulation to reduce switching loss.

Abstract: A MOS-gated power semiconductor device which combines bipolar conduction with MOS-gate control to achieve low on-state voltage drop while having fast-switching characteristics. A floating P injector region located at the upper surface of the device injects holes, and a grounded P collector region, also located at the upper surface of the device, collects the injected holes. A driver DMOSFET integrated in the structure couples the P injector region to the drain potential during the on-state of the device. The P collector region is configured in such that the driver DMOSFET is conductivity modulated by a positive feedback mechanism, thereby drastically reducing the on-resistance of the device at high current levels.

Abstract: A semiconductor device which reduces the turn-off time and the accompanying switching loss in a switching semiconductor device in which conductivity modulation is used to provide a low ON-state voltage. The conductivity modulation is provided by injection of minority carriers. A minority carrier injection-control structure is provided in part of a semiconductor device to change the polarity of a voltage applied to a gate electrode to start or stop the injection of minority carriers. During the ON-state, minority carriers are injected to obtain a low ON-state voltage, while during the OFF-state, the injection of minority carriers are stopped and a channel for majority carriers is formed to eliminate the accumulation of excess carriers and to accelerate discharge, thereby reducing the turn-off time and thus the switching loss.

Abstract: A semiconductor device of the RESURF type with a "low-side" lateral DMOST (LDMOST), comprising a semiconductor body (1) of predominantly a first conductivity type and a surface region (3) adjoining a surface (2) and of a second conductivity type. The LDMOST comprises a back gate region (5) of the first conductivity type provided in the surface region (3) with a source region (6) of the second conductivity type in the back gate region (5) and a channel region (7) defined between the source region (6) and an edge of the back gate region (5). A drain region (8) of the second conductivity type is present at a distance from the back gate region (5). A separation region (15) of the first conductivity type is provided around the LDMOST in the surface region (3), which separation region adjoins the surface (2) and extends towards the semiconductor body (1).

Abstract: A bidirectional semiconductor switch employs two insulated gate semiconductor devices such as insulated gate bipolar transistors (IGBTs) that are connected oppositely in parallel, with the collector of one of the IGBTs being connected to the emitter of the other. The gates of the IGBTs are biased by gate controllers that are potentially independent of each other. The semiconductor switch is capable of controlling a direct current as well as an alternating current at a low ON-state voltage, reducing a conduction loss, and improving efficiency.

Abstract: According to the present invention, a MOSFET is formed of an n source, a p well, an n drain and a MOS gate electrode, a bipolar transistor is formed of an n emitter, a p base and an n collector formed in sequential order adjacent to the n drain. These transistors are formed by being merged with each other by the contact of n drain and the n emitter of the same conductivity type. Holes are injected into the drain of a voltage-driven type transistor comprised of the MOSFET from the bipolar transistor having a very small collector saturation resistance. With this, it is possible to give rise to conductivity modulation in the drain of the MOSFET, while the power dissipation of the voltage-driven type semiconductor device becomes very small.

Abstract: An enhanced mobility MOSFET device (10) comprises a channel layer (12) formed on a monocrystalline silicon layer (11). The channel layer (12) comprises an alloy of silicon and a second material with the second material substitutionally present in silicon lattice sites at an atomic percentage that places the channel layer (12) under a tensile stress.

Abstract: In diodes used with high withstand voltages, the pin-type diode has a low on-resistance, but a large switching loss. Even if a lifetime killer is introduced, the low on-resistance and the switching loss cannot be compatible since both factors are in a trade-off relation. The invention overcomes these problems by providing a semiconductor device that includes p.sup.+ -type anode layers and p.sup.+ -type floating drain layers that are connected to the anode layers by a MOSFET 20 formed on the surface of an n.sup.- -type conductivity-modulating layer. When a forward voltage is applied, holes are injected from the drain layers to create an element with a conductivity-modulated condition and realize a low on-resistance. By the time a reverse voltage is applied, the drain layers have already been separated to reduce the number of excessive carriers. Thus, the reverse recovery current is suppressed.

Abstract: The performance of COMFET-based electrical switches may be improved by connecting a MOSFET substantially in parallel with the COMFET. In a monolithic embodiment, a MOSFET drain region may be added to a surface of a COMFET and shorted to the emitter region of the COMFET. The invention decreases the turn-off time of the COMFET, reduces the discontinuity at current direction reversal and increases the latch-up current of a semiconductor switch.

Abstract: A semiconductor device comprises an insulating region residing adjacent to a first semiconductor region, a control electrode residing via the insulating region, a second semiconductor region and a third semiconductor region, which have an opposite conduction type to that of the first semiconductor region, residing adjacent to and carrying therebetween the first semiconductor region. When the first, second and third semiconductor regions and the control electrode are grounded, the first semiconductor region in contact with the insulating layer is adjusted to be in weak inversion state, and the potential of the control electrode and that of the first semiconductor region are electrically coupled to be operable.

Abstract: A MODFET device has highly doped source and drain regions separated by an undoped semiconductor alloy in which the mole fraction is graded between the source and the drain and with a conduction (and/or valence) band discontinuity at the heterojunction between the source and semiconductor alloy channel region of the device. Due to the graded mole fraction, the bandgap of the undoped semiconductor alloy decreases along the channel from the source to the drain and creates a built-in electric field. The higher bandgap in the source compared to that in the channel permits high energy carrier injection into the channel, with the built-in longitudinal electric field increasing carrier drift velocity and reducing transit time between the source and drain. In a preferred embodiment, the MODFET device has a vertical structure with the source and semiconductor alloy layers stacked on a drain substrate.

Abstract: A latch-up free insulated gate transistor includes an anode region electrically connected to an anode contact, a first base region on the anode region, a second base region on the first base region, connected to a cathode contact, an insulating region on the second base region and a field effect transistor on the insulating region, electrically connected between the cathode contact and the first base region. The field effect transistor provides an electrical connection between the first base region and the cathode contact in response to a turn-on bias signal. The insulating region prevents electrical conduction between the second base region and the field effect transistor and, in particular, suppresses minority carrier injection from the second base region to the source of the field effect transistor which is electrically connected to the cathode contact.

Abstract: An IGBT has an emitter bypass structure. The interval D between N emitter regions is adapted to be larger than two times of a channel length L in order to effectively decrease a channel width to effectively decrease a saturation current. A high concentration region may be provided in a P base region, which is closer to the end portion of the P base region than the emitter regions between the emitter regions, so that the channel width can be effectively decreased even without the relation of D>2L. A channel width per unit area W.sub.U may be in a range of 140 cm.sup.-1 .ltoreq.W.sub.U .ltoreq.280 cm.sup.-1 in an IGBT of a breakdown voltage class of 500-750 V or 70 cm.sup.-1 .ltoreq.W.sub.U .ltoreq.150 cm.sup.-1 in an IGBT of a breakdown voltage class of 1000-1500 V, so that an IGBT having a short-circuit withstandability and a latch-up withstandability suitable for an inverter can be implemented.

Abstract: A general object of the present invention is to make a maximum controllable current large without exerting adverse effect on other characteristics. In a surface of an n.sup.- layer 2 formed on a p.sup.+ substrate 1, p diffusion regions 3a, 3b and 3c are formed separated by n.sup.+ diffusion regions 4a, 4b and an oxidation film 9. Above the p diffusion regions 3b and 3c, gate electrodes 5a and 5b are formed insulated from the surrounding by an oxidation film 6. An Al-Si electrode 7 is in contact with the p diffusion region 3a and the n.sup.+ diffusion region 4a while a metal electrode 8 is in contact with the p.sup.+ substrate 1. By virtue of interposition of the oxidation film 9, a thyristor consisting of the n.sup.+ diffusion region 4a, p diffusion region 3a, n.sup.- layer 2 and p.sup.+ substrate 1 is prevented from being actuated.

Abstract: An improved insulated gate semiconductor device comprises a high-concentration p-type semiconductor region formed widely enough to protrude over n-type emitter regions without reaching an n-type epitaxial layer over a p-type base region only in first regions wherein the n-type emitter regions are wider than second regions as viewed from the top of the device. A gate threshold voltage V.sub.GE (th) has a relatively high level V.sub.GE (th-High) in the first regions, so that a low collector-emitter saturation voltage V.sub.CE (sat) and a low saturation current I.sub.CE (sat) are achieved. This provides for a high short-circuit tolerance as well as a high latch-up tolerance with low losses.

Abstract: An electrically plastic device comprising an amorphous silicon semiconductor layer including movable dopant formed between a pair of electrodes and; at least one gate electrode formed on said amorphous silicon semiconductor layer through an insulation layer or a high resistance layer; whereby the operation of said gate electrode controls the dopant distribution of said amorphous semiconductor layer, thereby varying the electrical conductivity thereof.

Abstract: A semiconductor assembly comprises a semiconductor die which is attached by a carrier material to a lead frame. The carrier material is coated on the die side with one type of adhesive and on the lead frame side with a different adhesive. The lead frame has a small surface area to connect to the carrier material, while the semiconductor die has a large surface area to connect to the carrier material. As used with one inventive embodiment, the adhesive between the die and the carrier softens at a low temperature preventing the die from cracking at elevated temperatures. The adhesive on the lead frame side of the carrier material softens at a higher temperature than the adhesive of the die side of the adhesive, thereby firmly connecting the lead frame having a small surface area to the carrier.

Abstract: A conductivity modulated MOSFET, having a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate and having a high resistance, a base layer of the first conductivity type formed in the semiconductor layer, a source layer of the second conductivity type formed in the base layer, a gate electrode formed on a gate insulating film which is formed on a channel region, the channel region being formed in a surface of the base layer between the semiconductor layer and the source layer, a source electrode ohmic-contacting the source layer and the base layer, and a drain electrode formed on the surface of the semiconductor substrate opposite to the semiconductor layer, characterized in that the conductivity modulated MOSFET has a saturation current smaller than a latch-up current when a predetermined gate voltage is applied to the gate electrode.

Abstract: In a semiconductor equipped with a conductivity modulating MISFET (IGBT) with a high withstand voltage in blocking forward and reverse directions, a withstand power is maintained in lieu of a drain wall disposed to improve the withstand power, and a current-carrying capacity, which is restricted by the drain wall, is increased. A potential at the drain wall disposed between a DMOS section and a collector section is transmitted at a portion between the collector section and an isolation layer by an channel stop electrode (201) that maintains the withstand power, while an increase in the current-carrying capacity is achieved by forming a conductivity modulating layer alone between the above section.

Abstract: A semiconductor rectifying diode includes a first semiconductor region of one conductivity type, a plurality of third semiconductor regions of the other conductivity type provided on one surface of said first semiconductor region to be spaced a distance W, and a main electrode provided on said one main surface to in ohmic contact with said first semiconductor region and in contact with said third semiconductor regions through the Schottky barrier. To reduce reverse leakage current a relation of 2wo<W.ltoreq.3D is satisfied, where D is the depth of said third semiconductor regions and wo is the width of a depletion layer spread to said first semiconductor region by a diffusion potential of the pn junction formed between said first semiconductor region and said third semiconductor region.

Abstract: There is disclosed a single-gate type conductivity-modulation field effect transistor having a semiconductive substrate, a base layer, and a source layer formed in the base layer. A source electrode is provided on a surface of the substrate, for electrically shorting the base layer with the source layer. A drain layer is provided in the substrate surface. A drain electrode is formed on the substrate surface to be in contact with the drain layer. A gate electrode is insulatively provided above the substrate surface, for covering a certain surface portion of the base layer which is positioned between the substrate and the source layer to define a channel region below the gate electrode. A lightly doped semiconductor diffusion layer is formed in the substrate surface so as to overlap said base layer and said drain layer. The diffusion layer having an impurity density which is varied continuously through the thickness of the diffusion layer.

Abstract: A COM switching device includes an n.sup.+ -type layer formed on a p.sup.+ -type layer, p.sup.+ -type regions formed in the surface areas of an n.sup.- -type layer formed on the n.sup.+ -type layer, n.sup.+ -type regions formed in the surface areas of the p.sup.+ -type regions, and a gate electrode formed on an insulating layer over the surface areas of the p.sup.+ -type regions which lie between the n.sup.+ -type regions and the n.sup.- -type layer. The n.sup.+ -type layer is formed such that the amount of impurities per unit area is between 5.times.10.sup.13 cm.sup.-2 and 1.times.10.sup.15 cm.sup.-2, and the p.sup.+ -type layer is formed to have an impurity concentration between 2.times.10.sup.18 and 8.times.10.sup.18 cm.sup.-3.

Abstract: A conductivity modulation type MOSFET including a first region of a first conductivity type having a low impurity concentration, second regions of a second conductivity type selectively formed on the surface region of one side of the first region, third regions of the first conductivity type selectively formed on the surface region of the second regions, gate electrodes each formed above the surface region of the second region located between the first region and the third region, a plurality of gate insulating films interlayered between the gate electrodes and the surface region of the second regions, an emitter electrode in contact with both the second regions and the third regions, a fourth region of the second conductivity type having a high impurity concentration, formed adjoining to another side of the first region, fifth regions of the second conductivity type, selectively formed surrounding the fourth region, having a lower impurity concentration than that of the fourth region, and a collector electro

Abstract: A semiconductive device of the type including a conductivity-modulated field-effect transistor provides all of the three electrodes on the principal surface by use of a buried layer and a variety of means for restricting device current to flow through the buried layer. Some of the arrangements not only overcome some effects of parasitic transistors that are formed, but obtain faster turn-on and turn-off while retaining the desired current capacity of the device. The arrangements include means for stopping the lateral spread of a depletion region, a minority carrier suppression region, and drain wall arrangements, among others.

Abstract: A vertical conducting insulating gate bipolar transistor having an emitter region formed in a base region wherein the base region is not shorted to the emitter is provided. The emitter and base regions are formed in an upper portion of a lightly doped semiconductor drift region and an anode region is formed in a bottom portion of the drift region. During forward conduction, minority carriers are injected from the anode into the base region, biasing the base region sufficiently to inject minority carriers into the upper surface of the drift region. The injected minority carriers improve conductivity in the upper portion of the drift region.

Abstract: An Injector Junction Field Effect Transistor (IJFET) is disclosed which, in addition to having two gates (G1, G2) a drain (D) and a source (S), also has an injector (I). The device may be used as a high impedance charge or current amplifier in, for example, an x-ray fluorescence device. On applying current to the injector carriers are introduced into the channel of the device allowing a small gate leakage current to flow to restore charge to the input. A small restore current is therefore controllable by low impedance injector circuits.