Abstract: A semiconductor device is implementated that includes a source region, multiple elongated drain regions, a channel region, a source electrode, a drain electrode, and a gate electrode. The source region is a flat planar region formed on a compound semiconductor layer. The multiple elongated drain regions are formed so that they are each electrically isolated from each other on the compound semiconductor layer. The channel region is formed so that it contacts one side of the source region and is electrically isolated from the source region and the multiple elongated drain regions. The source electrode is formed at least in a portion on top of the source region. The drain electrode is formed so that it is connected electrically to the multiple elongated drain regions. The gate electrode is formed so that it is connected electrically to the multiple channel regions.

Abstract: Memory arrays having folded architectures and methods of making the same. Specifically, memory arrays having a portion of the transistors in a row that are reciprocated and shifted with respect to other transistors in the same row. Trenches formed between the rows may form a weave pattern throughout the array, in a direction of the row. Trenches formed between legs of the transistors may also form a weave pattern throughout the array in a direction of the row.

Abstract: The present invention is to provide a method for forming a compound epitaxial layer by chemical bonding, which comprises the steps of forming a contact layer on a substrate; chemically reacting atoms on a surface of the contact layer with non-metal atoms, such that the non-metal atoms form non-metal ions for chemically bonding to the atoms on the surface of the contact layer; exciting the non-metal ions by energy excitation, such that unpaired electrons of the non-metal ions not yet bound to the atoms on the surface of the contact layer become dangling bonds; and conducting chemical vapor deposition by introducing an organic metal compound and a reactant gas, wherein metal ions of the organic metal compound are bound to the dangling bonds by electric dipole attraction, and anions of the reactant gas are bound to the metal ions by ionic bonding, such that the compound epitaxial layer is formed.

Abstract: The present invention relates to improved complementary metal-oxide-semiconductor (CMOS) devices with stressed channel regions. Specifically, each improved CMOS device comprises an field effect transistor (FET) having a channel region located in a semiconductor device structure, which has a top surface oriented along one of a first set of equivalent crystal planes and one or more additional surfaces oriented along a second, different set of equivalent crystal planes. Such additional surfaces can be readily formed by crystallographic etching. Further, one or more stressor layers with intrinsic compressive or tensile stress are located over the additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile or compressive stress to the channel region of the FET. Such stressor layers can be formed by pseudomorphic growth of a semiconductor material having a lattice constant different from the semiconductor device structure.

Abstract: This invention relates to a MOS device for making the source/drain region closer to the channel region and a method of manufacturing the same, comprising: providing an initial structure, which includes a substrate, an active region, and a gate stack; performing ion implantation in the active region on both sides of the gate stack, such that part of the substrate material undergoes pre-amorphization to form an amorphous material layer; forming a first spacer; with the first spacer as a mask, performing dry etching, thereby forming a recess, with the amorphous material layer below the first spacer kept; performing wet etching using an etchant solution that is isotropic to the amorphous material layer and whose etch rate to the amorphous material layer is greater than or substantially equal to the etch rate to the {100} and {110} surfaces of the substrate material but is far greater than the etch rate to the {111} surface of the substrate material, thus removing the amorphous material layer below the first space

Abstract: Disclosed is a semiconductor device and a method for fabricating the semiconductor device. The method for fabricating the semiconductor device comprises steps of: forming a side cliff in a substrate in accordance with a gate mask pattern, the side cliff being substantially vertical to a substrate surface; forming a dielectric layer on the substrate that comprises the side cliff; etching the dielectric layer to have the dielectric layer left only on the side cliff, as a dielectric wall; and burying the side cliff by a substrate growth, the burying is performed up to a level higher than the upper end of the dielectric wall.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, at least a first N-type germanium (Ge) structure and at least a first P-type Ge structure. The first N-type Ge structure is formed on the substrate and has two end parts and at least a first central part bonded between the two end parts thereof. The first central part is floated over the substrate, and a side surface of the first central part is a {111} Ge crystallographic surface. The first P-type Ge structure is formed on the substrate and has two end parts and at least a second central part bonded between the two end parts thereof. The side surface of the second central part is a {110} Ge crystallographic surface.

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides a processing for forming improved lightly doped source/drain features and source/drain features in the semiconductor device. Semiconductor device with the improved lightly doped source/drain features and source/drain features may prevent or reduce defects and achieve high strain effect. In at least one embodiment, the lightly doped source/drain features and source/drain features comprises the same semiconductor material formed by epitaxial growth.

Abstract: A silicon carbide semiconductor device includes an insulation film, and a silicon carbide layer having a surface covered with the insulation film. The surface includes a first region. The first region has a first plane orientation at least partially. The first plane orientation is any of a (0-33-8) plane, (30-3-8) plane, (-330-8) plane, (03-3-8) plane, (-303-8) plane, and (3-30-8) plane.

Abstract: A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from bottom to top. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.

Abstract: A housing for radiation-emitting or radiation-receiving optoelectronic components such as LEDs and a method for producing the housing are provided. The housing has a base part and a head part that are joined by a glass layer. The top face of the base part defines an assembly region for an optoelectronic functional element and is also a heat sink for the optoelectronic functional element. The head part extends at least in sections over the peripheral extent of the assembly region, and above the assembly region it forms a passage area for the radiation emitted from or to be received by the optoelectronic functional element.

Abstract: A nonvolatile memory device includes a substrate, an elongate isolation region including a field insulation film disposed in a trench in the substrate, and a word line crossing the insulation region and including a tunneling insulation layer on an active region of the substrate adjacent the isolation region, a charge storage layer on the tunneling insulation layer and a blocking insulation layer on the charge storage layer. A first plane index of a bottom surface of the trench has a first interface trap density and a second plane index of a sidewall of the trench has a second interface trap density equal to or less than the first interface trap density. In some embodiments, the first plane index may be (100) and the second plane index may be (100) or (310).

Abstract: The present invention discloses a semiconductor device, comprising: a substrate, an insulating isolation layer formed on the substrate, a first active region layer and a second active region layer formed in the insulating isolation layer, characterized in that the carrier mobility of the first active region layer and/or second active region layer is higher than that of the substrate. In accordance with the semiconductor device and the manufacturing method thereof in the present invention, an active region formed of a material different from that of the substrate is used, the carrier mobility in the channel region is enhanced, thereby the device response speed is substantially improved and the device performance is enhanced greatly. Furthermore, unlike the existing STI manufacturing process, for the present invention, an STI is formed first, and then filling is performed to form an active region, thus avoiding the problem of generation of holes in STI, and improving the device reliability.

Abstract: Methods and structures for forming a localized silicon-on-insulator (SOI) finFET are disclosed. Fins are formed on a bulk substrate. Nitride spacers protect the fin sidewalls. A shallow trench isolation region is deposited over the fins. An oxidation process causes oxygen to diffuse through the shallow trench isolation region and into the underlying silicon. The oxygen reacts with the silicon to form oxide, which provides electrical isolation for the fins. The shallow trench isolation region is in direct physical contact with the fins and/or the nitride spacers that are disposed on the fins.

Abstract: A transistor in which an electron state at an interface between an oxide semiconductor film and an underlayer film in contact with the oxide semiconductor film is favorable is provided. A value obtained by dividing a difference between nearest neighbor interatomic distance of the underlayer film within the interface and a lattice constant of the semiconductor film by the nearest neighbor interatomic distance of the underlayer film within the interface is less than or equal to 0.15. For example, an oxide semiconductor film is deposited over an underlayer film which contains stabilized zirconia which has a cubic crystal structure and has the (111) plane orientation, whereby the oxide semiconductor film including a crystal region having a high degree of crystallization can be provided directly on the underlayer film.

Abstract: The present invention provides a semiconductor structure, which comprises: a substrate, a semiconductor base, a semiconductor auxiliary base layer, a cavity, a gate stack, a sidewall spacer, and a source/drain region, wherein the gate stack is located on the semiconductor base; the sidewall spacer is located on the sidewalls of the gate stack; the source/drain region is embedded in the semiconductor base and is located on both sides of the gate stack; the cavity is embedded in the substrate; the semiconductor base is suspended above the cavity, the thickness of the middle portion of the semiconductor base is greater than the thickness of the two end portions of the semiconductor base in the direction of the length of the gate, and the two end portions of the semiconductor base are connected to the substrate in the direction of the width of the gate; and the semiconductor auxiliary base layer is located on the sidewall of the semiconductor base and has an opposite doping type to that of the source/drain region

Abstract: An integrated circuit structure includes a semiconductor substrate, and a FinFET over the semiconductor substrate. The FinFET includes a semiconductor fin; a gate dielectric on a top surface and sidewalls of the semiconductor fin; a gate electrode on the gate dielectric; and a source/drain region at an end of the semiconductor fin. A first pair of shallow trench isolation (STI) regions includes portions directly underlying portions of the source/drain regions, wherein the first pair of STI regions is separated by, and adjoining a semiconductor strip. The first pair of STI regions further has first top surfaces. A second pair of STI regions comprises portions directly underlying the gate electrode, wherein the second pair of STI regions is separated from each other by, and adjoining, the semiconductor strip. The second pair of STI regions has second top surfaces higher than the first top surfaces.

Abstract: A semiconductor field-effect device is disclosed that utilizes an octagonal or inverse-octagonal deep trench super-junction in combination with an octagonal or inverse-octagonal gate trench. The field-effect device achieves improved packing density, improved current density, and improved on resistance, while at the same time maintaining compatibility with the multiple-of-45°-angles of native photomask processing and having well characterized (010), (100) and (110) (and their equivalent) silicon sidewall surfaces for selective epitaxial refill and gate oxidation, resulting in improved scalability. By varying the relative length of each sidewall surface, devices with differing threshold voltages can be achieved without additional processing steps. Mixing trenches with varying sidewall lengths also allows for stress balancing during selective epitaxial refill.

Abstract: The present invention includes a method for manufacturing a silicon epitaxial wafer having a silicon homoepitaxial layer formed on a surface of a silicon single crystal wafer, including the steps of: preparing the silicon single crystal wafer such that a plane orientation of the silicon single crystal wafer is tilted at an angle in the range from 0.1° to 8° in a <112> direction from a {110} plane; and growing the silicon homoepitaxial layer on the prepared silicon single crystal wafer. According to the present invention, a silicon epitaxial wafer using the {110} substrate with improved surface quality, such as Haze and surface roughness and a method for manufacturing the silicon epitaxial wafer are provided.

Abstract: An integrated circuit includes at least one single-crystal fin having a first crystal orientation. The integrated circuit also includes at least one single-crystal fin having a second crystal orientation. The single-crystal fin having the first crystal orientation and the single-crystal fin having the second crystal orientation are substantially parallel.

Abstract: In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction.

Abstract: In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction.

Abstract: A semiconductor device includes a base insulating film including silicon, an oxide semiconductor film over the base insulating film, a gate insulating film over the oxide semiconductor film, a gate electrode which is in contact with the gate insulating film and overlaps with at least the oxide semiconductor film, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. The oxide semiconductor film includes a region in which a concentration of silicon distributed from the interface with the base insulating film toward an inside of the oxide semiconductor film is lower than or equal to 1.0 at. %. A crystal portion is included at least in the region.

Abstract: A semiconductor device includes an isolation layer formed on a semiconductor substrate; an active region defined by the isolation layer; at least one gate line formed to overlap with the active region; at least one first active tab formed on a first interface of the active region which overlaps with the gate line; and a first gate tab formed on a second interface facing away from the first interface in such a way as to project from the gate line.

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device (e.g., FinFET device) having a gate structure formed on a planar surface thereof. Specifically, a uniform, oxide-fin (OF) surface is formed. Then, a “dummy” gate structure and a set of spacers are formed thereon. Once the gate structure and set of spacers have been formed, the OF surface may be recessed. In one embodiment, the OF surface is uniformly recessed. In another embodiment, the OF surface is selectively recessed to yield a set of fins. In any event, after the recessing, an epitaxial layer is grown and an oxide fill is performed. Then, the “dummy” gate structure is removed (from between the set of spacers) and an oxide recess is performed to yield a set of channel fins between the spacers.

Abstract: An integrated circuit device and a process for making the integrated circuit device. The integrated circuit device including a substrate having a trench formed therein, a first layer of isolation material occupying the trench, a second layer of isolation material formed over the first layer of isolation material, an epitaxially-grown silicon layer on the substrate and horizontally adjacent the second layer of isolation material, and a gate structure formed on the epitaxially-grown silicon, the gate structure defining a channel.

Abstract: A CMOS chip comprising a high performance device region and a high density device region includes a plurality of high performance devices comprising n-type field effect transistors (NFETs) and p-type field effect transistors (PFETs) in the high performance device region, wherein the high performance devices have a high performance pitch; and a plurality of high density devices comprising NFETs and PFETs in the high density device region, wherein the high density devices have a high density pitch, and wherein the high performance pitch is about 2 to 3 times the high density pitch; wherein the high performance device region comprises doped source and drain regions, NFET gate regions having an elevated stress induced using stress memorization technique (SMT), gate silicide and source/drain silicide regions, and a dual stressed liner, and wherein the high density device region comprises doped source and drain regions, gate silicide regions, and a neutral stressed liner.

Abstract: A semiconductor device includes a gate pattern disposed on a semiconductor substrate, a bulk epitaxial pattern disposed in a recess region formed in the semiconductor substrate at a side of the gate pattern, an insert epitaxial pattern disposed on the bulk epitaxial pattern, and a capping epitaxial pattern disposed on the insert epitaxial pattern. The bulk epitaxial pattern has an upper inclined surface that is a {111} crystal plane, and the insert epitaxial pattern includes a specific element that promotes the growth rate of the insert epitaxial pattern on the upper inclined surface.

Abstract: A semiconductor structure and a method of fabricating the same comprising the steps of providing a substrate, forming at least one fin structure on said substrate, forming a gate covering said fin structure, forming a plurality of epitaxial structures covering said fin structures, performing a gate pullback process to reduce the critical dimension (CD) of said gate and separate said gate and said epitaxial structures, forming lightly doped drains (LDD) in said fin structures, and forming a spacer on said gate and said fin structures.

Abstract: An integrated circuit device and a process for making the integrated circuit device. The integrated circuit device including a substrate having a trench formed therein, a first layer of isolation material occupying the trench, a second layer of isolation material formed over the first layer of isolation material, an epitaxially-grown silicon layer on the substrate and horizontally adjacent the second layer of isolation material, and a gate structure formed on the epitaxially-grown silicon, the gate structure defining a channel.

Abstract: Manufacturing a semiconductor device with higher operating characteristics and achieve low power consumption of a semiconductor integrated circuit. A single crystal semiconductor layer is formed so that crystal plane directions of single crystal semiconductor layers which are used for channel regions of an n-channel and a p-channel TFT and which are formed over the same plane of the substrate are the most appropriate crystal plane directions for each TFT. In accordance with such a structure, mobility of carrier flowing through a channel is increased and the semiconductor device with higher operating characteristics can be provided. Low voltage driving can be performed, and low power consumption can be achieved.

Abstract: An accumulation mode transistor has an impurity concentration of a semiconductor layer in a channel region at a value higher than 2×1017 cm?3 to achieve a large gate voltage swing.

Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

Abstract: An integrated circuit includes at least one single-crystal fin having a first crystal orientation. The integrated circuit also includes at least one single-crystal fin having a second crystal orientation. The single-crystal fin having the first crystal orientation and the single-crystal fin having the second crystal orientation are substantially parallel.

Abstract: A biosensor array, system and method for affinity based assays that are able to simultaneously obtain high quality measurements of the binding characteristics of multiple analytes, and that are able to determine the amounts of those analytes in solution. The invention also provides a fully integrated bioarray for detecting real-time characteristics of affinity based assays.

Abstract: A memory cell is provided with a transistor which includes source and drain electrodes formed in a semiconductor film by respectively N-doped and P-doped areas. The transistor includes first and second devices for generating a potential barrier in the semiconductor film. The two potential barriers are shifted laterally and are opposed to the passage of the charge carriers emitted by the nearest source/drain electrode. One of the devices for generating the potential barrier is electrically connected to the gate. The other of the devices for generating the potential barrier is electrically connected to the counter-electrode. The writing of a high state is carried out by imposing on the P-doped electrode a potential higher than that of the N-doped electrode and charging the capacitor formed between the gate and the semiconductor film. The resetting of the memory cell is obtained by discharging the capacitor.

Abstract: A semiconductor device includes field regions formed in a substrate, and n-type impurity regions disposed between the field regions. At least one of the side surfaces of the field regions has a {100}, {310}, or {311} plane.

Abstract: A semiconductor device may include, but is not limited to, a semiconductor substrate, a word line, and an isolation region. The semiconductor substrate has an active region and first and second grooves. Each of the first and second grooves extends across the active region. The first groove is wider in width than the second groove. The word line is disposed in the first groove. The isolation region is disposed in the second groove. The isolation region is narrower in width than the word line.

Abstract: A structure includes a substrate containing at least first and second adjacent gate structures on a silicon surface of the substrate and a silicided source/drain region formed in a V-shaped groove between the first and second adjacent gate structures. The silicided source/drain region formed in the V-shaped groove extend substantially from an edge of the first gate structure to an opposing edge of the second gate structure.

Abstract: The present invention facilitates semiconductor device fabrication and performance by providing a semiconductor device that can improve channel mobility for both N type and P type transistor devices. The semiconductor device of the present invention is fabricated on a semiconductor substrate 802 that has a first and second crystallographic orientation axes (e.g., <110>, <100>) 804 and 806. Source to drain channel regions for P type devices are formed 904 and aligned along the first crystallographic orientation axis. Source to drain channel regions for N type devices are formed 906 rotated from the channel regions of the P type devices by an offset angle so that the source to drain channel regions for the N type devices are aligned with the second crystallographic orientation axis.

Abstract: The transistor comprises first and second source/drain electrodes formed in a semiconductor film by N-doped and P-doped areas, respectively. A polarization voltage is applied between the two source/drain electrodes in order to impose to the P-doped electrode a potential higher than that of the N-doped electrode. The transistor comprises first and second devices for generating a potential barrier in the semiconductor film. The two potential barriers are opposed to the passage of the charge carriers emitted by the first and second source/drain electrodes, respectively. The two potential barriers are shifted with respect to an axis connecting the two source/drain electrodes. The two devices for generating a potential barrier are configured to generate a potential barrier having a variable amplitude and it are electrically connected to the gate and to the counter electrode.

Abstract: An object is to realize high performance and low power consumption in a semiconductor device having an SOI structure. In addition, another object is to provide a semiconductor device having a high performance semiconductor element which is more highly integrated. A semiconductor device is such that a plurality of n-channel field-effect transistors and p-channel field-effect transistors are stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. By controlling a distortion caused to a semiconductor layer due to an insulating film having a stress, a plane orientation of the semiconductor layer, and a crystal axis in a channel length direction, difference in mobility between the n-channel field-effect transistor and the p-channel field-effect transistor can be reduced, whereby current driving capabilities and response speeds of the n-channel field-effect transistor and the p-channel field-effect can be comparable.

Abstract: A method and structure of an embedded stressor in a semiconductor transistor device having a sigma-shaped channel sidewall and a vertical isolation sidewall. The embedded stressor structure is made by a first etch to form a recess in a substrate having a gate and first and second spacers. The second spacers are removed and a second etch creates a step in the recess on a channel sidewall. An anisotropic etch creates facets in the channel sidewall of the recess. Where the facets meet, a vertex is formed. The depth of the vertex is determined by the second etch depth (step depth). The lateral position of the vertex is determined by the thickness of the first spacers. A semiconductor material having a different lattice spacing than the substrate is formed in the recess to achieve the embedded stressor structure.

Abstract: A three-dimensional CMOS circuit having at least a first N-conductivity field-effect transistor and a second P-conductivity field-effect transistor respectively formed on first and second crystalline substrates. The first field-effect transistor is oriented, in the first substrate, with a first secondary crystallographic orientation. The second field-effect transistor is oriented, in the second substrate, with a second secondary crystallographic orientation. The orientations of the first and second transistors form a different angle from the angle formed, in one of the substrates, by the first and second secondary crystallographic directions. The first and second substrates are assembled vertically.

Abstract: A semiconductor structure and a method for fabricating the semiconductor structure include a hybrid orientation substrate having a first active region having a first crystallographic orientation that is vertically separated from a second active region having a second crystallographic orientation different than the first crystallographic orientation. A first field effect device having a first gate electrode is located and formed within and upon the first active region and a second field effect device having a second gate electrode is located and formed within and upon the second active region. Upper surfaces of the first gate electrode and the second gate electrode are coplanar. The structure and method allow for avoidance of epitaxial defects generally encountered when using hybrid orientation technology substrates that include coplanar active regions.

Abstract: A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.

Abstract: A transistor includes a gate electrode disposed over a substrate. At least one composite strain structure is disposed adjacent to a channel below the gate electrode. The at least one composite strain structure includes a first strain region within the substrate. A second strain region is disposed over the first strain region. At least a portion of the second strain region is disposed within the substrate.

Abstract: Memory cell structures, including PSOIs, NANDs, NORs, FinFETs, etc., and methods of fabrication have been described that include a method of epitaxial silicon growth. The method includes providing a silicon layer on a substrate. A dielectric layer is provided on the silicon layer. A trench is formed in the dielectric layer to expose the silicon layer, the trench having trench walls in the <100> direction. The method includes epitaxially growing silicon between trench walls formed in the dielectric layer.

Abstract: A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.

Abstract: A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.