Field Effect Device Patents (Class 257/213)
  • Patent number: 11393824
    Abstract: A semiconductor device includes: a gate trench formed into a semiconductor substrate; a gate dielectric layer formed in the gate trench to cover an inside surface of the gate trench; and a gate electrode disposed over the gate dielectric layer to fill the gate trench, wherein the gate electrode includes: second crystal grains formed in the gate trench; and first crystal grains disposed between the second crystal grains and the gate dielectric layer and having a smaller crystal grain size than the second crystal grains.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: July 19, 2022
    Assignee: SK hynix Inc.
    Inventor: Dong-Soo Kim
  • Patent number: 11374171
    Abstract: Provided are memristors and neuromorphic devices including the memristors. A memristor includes a lower electrode and an upper electrode that are apart from each other and first and second two-dimensional material layers that are arranged between the lower electrode and the upper electrode and stacked without a chemical bond therebetween.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: June 28, 2022
    Assignees: Samsung Electronics Co., Ltd., President and Fellows of Harvard College
    Inventors: Minhyun Lee, Dovran Amanov, Renjing Xu, Houk Jang, Haeryong Kim, Hyeonjin Shin, Yeonchoo Cho, Donhee Ham
  • Patent number: 11325343
    Abstract: Ion-doped two-dimensional nanomaterials are made by inducing electronic carriers (electrons and holes) in a two-dimensional material using a captured ion layer at the surface of the material. The captured ion layer is stabilized using a capping layer. The induction of electronic carriers works in atomically-thin two-dimensional materials, where it induces high carrier density of at least 1014 carriers/cm2. A variety of novel ion-doped nanomaterials and p-n junction-based nanoelectronic devices are made possible by the method.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: May 10, 2022
    Assignee: Northeastern University
    Inventors: Swastik Kar, Ji Hao, Daniel Rubin, Yung Joon Jung
  • Patent number: 11309385
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Patent number: 11239107
    Abstract: A multilayer semiconductor on insulator structure is provided in which the handle substrate and an epitaxial layer in interfacial contact with the handle substrate comprise electrically active dopants of opposite type. The epitaxial layer is depleted by the handle substrate free carriers, thereby resulting in a high apparent resistivity, which improves the function of the structure in RF devices.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: February 1, 2022
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Gang Wang, Jeffrey L. Libbert, Shawn George Thomas, Qingmin Liu
  • Patent number: 11233127
    Abstract: A silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. A gate pad faces the first main surface. A drain electrode is in contact with the second main surface. The silicon carbide substrate includes a first impurity region constituting the second main surface and having a first conductivity type, a second impurity region provided on the first impurity region and having a second conductivity type different from the first conductivity type, a third impurity region provided on the second impurity region and having the first conductivity type, and a fourth impurity region provided on the third impurity region, constituting the first main surface, and having the second conductivity type. Each of the first impurity region, the second impurity region, the third impurity region, and the fourth impurity region is located between the gate pad and the drain electrode.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: January 25, 2022
    Inventors: Kosuke Uchida, Toru Hiyoshi
  • Patent number: 11222913
    Abstract: An image sensor device is provided. The image sensor device includes a substrate. The image sensor device includes a light-sensing region in the substrate. The image sensor device includes an isolation structure in the substrate. The isolation structure surrounds the light-sensing region. The image sensor device includes a grid layer over the substrate. The grid layer is over the isolation structure. The image sensor device includes a first lens over the light-sensing region and surrounded by the grid layer. The image sensor device includes a color filter layer over and in direct contact with the first lens. The image sensor device includes a second lens over the color filter layer.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: January 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shih-Hsun Hsu
  • Patent number: 11217695
    Abstract: Semiconductor devices are provided. A semiconductor device includes a fin structure having a plurality of first semiconductor patterns and a plurality of second semiconductor patterns alternately stacked on a substrate, and extending in a first direction. The semiconductor device includes a semiconductor cap layer on an upper surface of the fin structure, and extending along opposite side surfaces of the fin structure in a second direction crossing the first direction. The semiconductor device includes a gate electrode on the semiconductor cap layer, and extending in the second direction. The semiconductor device includes a gate insulating film between the semiconductor cap layer and the gate electrode. Moreover, the semiconductor device includes a source/drain region connected to the fin structure. The plurality of first semiconductor patterns include silicon germanium (SiGe) having a germanium (Ge) content in a range of 25% to 35%, and the plurality of second semiconductor patterns include silicon (Si).
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: January 4, 2022
    Inventors: Sanghoon Lee, Krishna Bhuwalka, Myunggil Kang, Kyoungmin Choi
  • Patent number: 11205657
    Abstract: Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: December 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: D. V. Nirmal Ramaswamy, Gurtej S. Sandhu
  • Patent number: 11201213
    Abstract: A channel all-around semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a plurality of gate structures and a multi-connected channel layer. The gate structures have the same extension direction, and each of the gate structures has opposite first end and second end. The gate structures are all surrounded by the multi-connected channel layer, and the plane direction of the multi-connected channel layer is perpendicular to the above extension direction, so that the channels of the gate structures are connected to each other.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: December 14, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Chun-Sheng Chen
  • Patent number: 11195912
    Abstract: A sacrificial gate stack for forming a nanosheet transistor includes a substrate. first, second and third silicon channel nanosheets formed over the substrate, and a first sandwich of germanium (Ge) containing layers disposed between the substrate and first silicon channel nanosheet. The stack also includes a second sandwich of Ge containing layers disposed between the first silicon channel nanosheet and the second silicon channel nanosheet; and a third sandwich of Ge containing layers disposed between the second silicon channel nanosheet and the third silicon channel nanosheet. Each sandwich includes first and second low Ge containing layers surrounding a silicon germanium (SiGe) sacrificial nanosheet that has a higher Ge concentration than the first and second low Ge containing layers.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: December 7, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Choonghyun Lee, Juntao Li, Peng Xu
  • Patent number: 11177176
    Abstract: A semiconductor device that can have favorable electrical characteristics and can be highly integrated is provided. The semiconductor device includes a first insulator; a second insulator over the first insulator; an oxide over the second insulator; a first conductor and a second conductor over the oxide; a third insulator over the oxide; a third conductor positioned over the third insulator and overlapping with the oxide; a fourth insulator in contact with the second insulator, a side surface of the oxide, a side surface of the first conductor, a top surface of the first conductor, a side surface of the second conductor, a top surface of the second conductor, and a side surface of the third insulator; and a fifth insulator in contact with a top surface of the third insulator and a top surface of the third conductor, and a top surface of the fourth insulator is in contact with the fifth insulator.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: November 16, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toshihiko Takeuchi, Hiromi Sawai, Ryota Hodo, Katsuaki Tochibayashi
  • Patent number: 11177384
    Abstract: A method of making a semiconductor device includes depositing an isolation region between adjacent fins of a plurality of fins over a substrate, wherein a top-most surface of the isolation region is a first distance from a bottom of the substrate. The method further includes doping each of the plurality of fins with a first dopant having a first dopant type to define a first doped region in each of the plurality of fins, wherein a bottom-most surface of the first doped region is a second distance from the bottom of the substrate, and the second distance is greater than the first distance. The method further includes doping each of the plurality of fins with a second dopant having a second dopant type to define a second doped region in each of the plurality of fins, wherein the second doped region contacts the isolation region.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: November 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chewn-Pu Jou, Tzu-Jin Yeh, Chia-Chung Chen
  • Patent number: 11145647
    Abstract: An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: October 12, 2021
    Assignee: United Semiconductor Japan Co., Ltd.
    Inventor: David A. Kidd
  • Patent number: 11133190
    Abstract: According to one embodiment, a method includes performing a plasma etching process on a masked III-V semiconductor, and forming a passivation layer on etched portions of the III-V semiconductor. The passivation layer includes at least one of a group III element and/or a metal from the following: Ni, Cr, W, Mo, Pt, Pd, Mg, Ti, Zr, Hf, Y, Ta, and Sc.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: September 28, 2021
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: Sara E. Harrison, Clint Frye, Rebecca J. Nikolic, Qinghui Shao, Lars F. Voss
  • Patent number: 11128830
    Abstract: A sensing module is provided, including a sensing unit. The sensing unit is formed by a plurality of sensing pixels arranged in an array. Each of the plurality of sensing pixels includes a body and a sensing element. The sensing element is disposed on a bottom surface of the body. During sensing, a light may enter and pass through the bodies and be transmitted to the sensing elements. The sensing pixels are divided into at least a first group and a second group from a center of the array to a periphery of the array, and photon collection efficiency of sensing pixels in the first group is less than photon collection efficiency of sensing pixels in the second group. Meanwhile, a design method of a sensing module is also provided.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: September 21, 2021
    Assignee: Egis Technology Inc.
    Inventor: Chia-Yu Liu
  • Patent number: 11114336
    Abstract: In a method of manufacturing a semiconductor device, a first source/drain structure is formed over a substrate, one or more first insulating layers are formed over the first source/drain structure, a first opening is formed in the one or more first insulating layers, the first opening is filled with a first conductive material to form a first lower contact in contact with the first source/drain structure, one or more second insulating layers are formed over the first lower contact, a second opening is formed in the one or more second insulating layers to at least partially expose the first lower contact, a first liner layer is formed on at least a part of an inner side face of the second opening, and the second opening is filled with a second conductive material to form a first upper contact in contact with the first lower contact without the first liner layer.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: September 7, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Huang-Kui Chen
  • Patent number: 11107721
    Abstract: A 3D semiconductor device, the device including: a first level including a single crystal layer and a plurality of first transistors; a first metal layer including interconnects between the plurality of first transistors, where the interconnects between the plurality of first transistors includes forming a plurality of logic gates; a plurality of second transistors atop at least a portion of the first metal layer, where at least six of the plurality of first transistors are connected in series forming at least a portion of a NAND logic structure, where the plurality of second transistors are vertically oriented transistors, and where the plurality of second transistors are at least partially directly atop of the NAND logic structure; and a second metal layer atop at least a portion of the plurality of second transistors, where the second metal layer is aligned to the first metal layer with less than 150 nm misalignment, and where at least one of the second transistors is a junction-less transistor.
    Type: Grant
    Filed: January 10, 2021
    Date of Patent: August 31, 2021
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Patent number: 11101180
    Abstract: A nano-crystalline high-k film and methods of forming the same in a semiconductor device are disclosed herein. The nano-crystalline high-k film may be initially deposited as an amorphous matrix layer of dielectric material and self-contained nano-crystallite regions may be formed within and suspended in the amorphous matrix layer. As such, the amorphous matrix layer material separates the self-contained nano-crystallite regions from one another preventing grain boundaries from forming as leakage and/or oxidant paths within the dielectric layer. Dopants may be implanted in the dielectric material and crystal phase of the self-contained nano-crystallite regions maybe modified to change one or more of the permittivity of the high-k dielectric material and/or a ferroelectric property of the dielectric material.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yen Peng, Te-Yang Lai, Sai-Hooi Yeong, Chi On Chui
  • Patent number: 11049880
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical stack of single crystalline ferroelectric dielectric layers and a respective vertical semiconductor channel.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: June 29, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Adarsh Rajashekhar, Fei Zhou, Rahul Sharangpani, Raghuveer S. Makala
  • Patent number: 10978299
    Abstract: A semiconductor device according to an example embodiment includes a substrate extending in first and second directions intersecting with each other; nanowires on the substrate and spaced apart from each other in the second direction; gate electrodes extending in the first direction and spaced apart from each other in the second direction, and surrounding the nanowires to be superimposed vertically with the nanowires; external spacers on the substrate and covering sidewalls of the gate electrodes on the nanowires; and an isolation layer between the gate electrodes and extending in the first direction, wherein an upper surface of the isolation layer is flush with upper surfaces of the gate electrodes.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: April 13, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-woo Noh, Myung-gil Kang, Ho-jun Kim, Geum-jong Bae, Dong-il Bae
  • Patent number: 10976281
    Abstract: Embodiments of the present disclosure relate to the field of electronic sensing technologies, and provide a chemical sensing unit, a chemical sensor, and a chemical sensing device. The chemical sensing unit includes a thin film transistor arranged on a substrate, and a light emitting diode coupled to the thin film transistor. The thin film transistor includes a semiconductor active layer, a source, and a drain, and the semiconductor active layer is mainly composed of a chemically sensitive semiconductor material. The chemical sensing unit is provided with a via hole in a region between the source and the drain, such that the semiconductor active layer is exposed at a position corresponding to the via hole. The light emitting diode includes a first electrode, a light-emitting functional layer, and a second electrode which are stacked in sequence, wherein the first electrode is coupled to the drain.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: April 13, 2021
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Qinghe Wang, Liangchen Yan, Dongfang Wang, Tongshang Su, Leilei Cheng, Yongchao Huang, Yang Zhang, Guangyao Li, Guangcai Yuan
  • Patent number: 10978513
    Abstract: Provided are a complementary carbon nanotube field effect transistor (CNT-FET) and a manufacturing method thereof. In particular, provided is carbon nanotube-based type conversion technology (p-type?n-type) using a photosensitive polyvinyl alcohol polymer which can be selectively cross-linked at a desired position based on a semiconductor standard process, i.e., photolithography.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: April 13, 2021
    Assignee: INCHEON UNIVERSITY INDUSTRY ACADEMIC COOPERATION FOUNDATION
    Inventor: Sung Hun Jin
  • Patent number: 10971629
    Abstract: Structures and methods of forming self-aligned unsymmetric gate (SAUG) FinFET are provided. The SAUG FinFET structure has two different gate structures on opposite sides of each fin: a programming gate structure and a switching gate structure. The SAUG FinFET may be used as non-volatile memory (NVM) storage element that may be electrically programmed by trapping charges in the charge trapping dielectric (e.g., Si3N4) with appropriate bias on the control gate of the programming gate structure. The stored data may be sensed by sensing the channel current through the SAUG FinFET in response to a bias on the switching gate of the switching gate structure.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: April 6, 2021
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Chiao Tung University
    Inventors: Chao-Hsin Chien, Yu-Che Chou, Chien-Wei Tsai, Chin-Ya Yi
  • Patent number: 10964601
    Abstract: A method of fabricating a vertical fin field effect transistor with a merged top source/drain, including, forming a source/drain layer at the surface of a substrate, forming a plurality of vertical fins on the source/drain layer; forming protective spacers on each of the plurality of vertical fins, forming a sacrificial plug between two protective spacers, forming a filler layer on the protective spacers not in contact with the sacrificial plug, and selectively removing the sacrificial plug to form an isolation region trench between the two protective spacers.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: March 30, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10937908
    Abstract: Various methods for fabricating non-planar integrated circuit devices, such as FinFET devices, are disclosed herein. An exemplary method includes forming a rib structure extending from a substrate; forming a two-dimensional material layer (including, for example, transition metal dichalcogenide or graphene) on the rib structure and the substrate; patterning the two-dimensional material layer, such that the two-dimensional material layer is disposed on at least one surface of the rib structure; and forming a gate on the two-dimensional material layer. In some implementations, a channel region, a source region, and a drain region are defined in the two-dimensional material layer. The channel region is disposed between the source region and the drain region, where the gate is disposed over the channel region. In some implementations, the patterning includes removing the two-dimensional material layer disposed on a top surface of the substrate and/or disposed on a top surface of the rib structure.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mark van Dal, Martin Christopher Holland, Matthias Passlack
  • Patent number: 10923388
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gap fill void and connection structures and methods of manufacture. The structure includes: a gate structure comprising source and drain regions; a gate contact in direct contact and overlapping the gate structure; and source and drain contacts directly connecting to the source and drain regions, respectively.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: February 16, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Haigou Huang, Yuping Ren, Paul Ackmann, Guoxiang Ning
  • Patent number: 10910368
    Abstract: A circuit structure including a first gate structure, a first multi-connected channel layer and a second transistor is provided. The first gate structure has a first extension direction, and the first gate structure has a first end and a second end opposite to each other. The first gate structure is fully surrounded by the first multi-connected channel layer, and a plane direction of the multi-connected channel layer is perpendicular to the first extension direction. The first gate structure and the first multi-connected channel layer form a first transistor. The second transistor is disposed in the first multi-connected channel layer. A second gate structure or a channel of the second transistor is electrical connected to the first multi-connected channel layer.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: February 2, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Chun-Sheng Chen
  • Patent number: 10886227
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including gate structures on a substrate; source/drain layers on portions of the substrate that are adjacent the gate structures, respectively; first contact plugs contacting upper surfaces of the source/drain layers, respectively; a second contact plug contacting one of the gate structures, a sidewall of the second contact plug being covered by an insulating spacer; and a third contact plug commonly contacting an upper surface of at least one of the gate structures and at least one of the first contact plugs, at least a portion of a sidewall of the third contact plug not being covered by an insulating spacer.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: January 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyo-Jin Kim, Chang-Hwa Kim, Hwi-Chan Jun, Chui-Hong Park, Jae-Seok Yang, Kwan-Young Chun
  • Patent number: 10872957
    Abstract: A semiconductor device includes a semiconductor substrate, a transistor cell region formed in the semiconductor substrate and an inner termination region formed in the semiconductor substrate and devoid of transistor cells. The transistor cell region includes a plurality of transistor cells and a gate structure that forms a grid separating transistor sections of the transistor cells from each other, each of the transistor sections including a needle-shaped first field plate structure extending from a first surface into the semiconductor substrate. The inner termination region surrounds the transistor cell region and includes needle-shaped second field plate structures extending from the first surface into the semiconductor substrate. The first field plate structures form a first portion of a regular pattern and the second field plate structures form a second portion of the same regular pattern.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: December 22, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Oliver Blank, Franz Hirler, Michael Hutzler, David Laforet, Cedric Ouvrard, Li Juin Yip
  • Patent number: 10847513
    Abstract: Various examples of a buried interconnect line are disclosed herein. In an example, a device includes a fin disposed on a substrate. The fin includes an active device. A plurality of isolation features are disposed on the substrate and below the active device. An interconnect is disposed on the substrate and between the plurality of isolation features such that the interconnect is below a topmost surface of the plurality of isolation features. The interconnect is electrically coupled to the active device. In some such examples, a gate stack of the active device is disposed over a channel region of the active device and is electrically coupled to the interconnect. In some such examples, a source/drain contact is electrically coupled to a source/drain region of the active device, and the source/drain contact is electrically coupled to the interconnect.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Kuan-Ting Pan, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10847653
    Abstract: Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Martin D. Giles, Annalisa Cappellani, Sanaz Gardner, Rafael Rios, Cory E. Weber, Aaron A. Budrevich
  • Patent number: 10847631
    Abstract: Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Abhijit Jayant Pethe, Tahir Ghani, Harry Gomez
  • Patent number: 10847431
    Abstract: A method for fabricating a semiconductor device using a high-temperature ion implantation process includes providing a substrate including a plurality of fins. In some examples, a mask material is deposited and patterned to expose a group of fins of the plurality of fins and a test structure. By way of example, a first ion implantation may be performed, at a first temperature, through the group of fins and the test structure. Additionally, a second ion implantation may be performed, at a second temperature greater than the first temperature, through the group of fins and the test structure. In various examples, an interstitial cluster is formed within the group of fins and within the test structure. In some embodiments, an anneal process is performed, where the anneal process serves to remove the interstitial cluster from the group of fins and form at least one dislocation loop within the test structure.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsan-Chun Wang, Chun Hsiung Tsai, Ziwei Fang
  • Patent number: 10818776
    Abstract: A substrate structure having a set of nanosheet layers and a set of sacrificial layers stacked upon a substrate is received and a dummy gate is formed upon the nanosheet layers and the sacrificial layers. A portion of a subset of the set of sacrificial layers and a subset of the set of nanosheet layers is etched. A portion of a subset of the subset of sacrificial layers is etched to create divots within the sacrificial layers. A divot fill layer is deposited. The divot fill layer is etched to form an inner spacer between the nanosheet layers. A source/drain region is formed adjacent to the nanosheet layers and the divots. A remaining portion of the subset of the sacrificial layers is removed. The subset of the nanosheet layers is etched to a desired channel thickness producing faceted surfaces between the subset of nanosheet layers and the inner spacer.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: October 27, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Nicolas Loubet, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 10811317
    Abstract: Methods for manufacturing semiconductor structures are provided. The method includes alternately stacking first epitaxy layers and second epitaxy layers to form a semiconductor stack and forming a first mask structure and a second mask structure over the semiconductor stack. The method further includes forming spacers on sidewalls of the second mask and patterning the semiconductor stack to form a first fin structure covered by the first mask structure and a second fin structure covered by the second mask structure and the spacers. The method further includes removing the first epitaxy layers of the first fin structure to form first nanostructures and removing the first epitaxy layers of the second fin structure to form second nanostructures. In addition, the second nanostructures are wider than the first nanostructures.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Shi-Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10796964
    Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region in a plane view. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping with the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping with the gate region.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: October 6, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Yin Hsiao, Ching-Chung Yang, Kuan-Liang Liu
  • Patent number: 10734166
    Abstract: A composite structure for an electric energy storage device is envisioned. The structure is made of a metal substrate and a metal oxide layer disposed over a majority of the metal substrate with the metal oxide layer being comprised of a first and second metals. Carbon nanotubes are disposed on the metal oxide layer. In an embodiment the first metal and the second metal are each selected from a group consisting of: iron, nickel, aluminum, cobalt, copper, chromium, and gold.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: August 4, 2020
    Assignee: ZapGo Ltd
    Inventors: Cattien Nguyen, You Li, Hoang Nguyen Ly, Darrell Niemann, Bevan Vo, Phillip Kraus
  • Patent number: 10727298
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Patent number: 10720503
    Abstract: A semiconductor device includes a semiconductor substrate, a first fin structure and a second fin structure. The first fin structure includes a first fin and at least two first nano wires disposed above the first fin, and the first fin protrudes from the semiconductor substrate. The second fin structure includes a second fin and at least two second nano wires disposed above the second fin, and the second fin protrudes from the semiconductor substrate. Each first nano wire has a first width different from a second width of each second nano wire.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: July 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Shi-Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10680075
    Abstract: A semiconductor device includes a fin structure disposed over a substrate, wherein the fin structure including a channel layer and extending in a first direction, a gate structure including a gate electrode layer and a gate dielectric layer, sidewall spacers disposed on opposite side faces of the gate structure, and a source/drain structure including an epitaxial layer having at least seven facets in a cross section along the first direction.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chao-Wei Hsu
  • Patent number: 10651178
    Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Kuan Lin, Chang-Ta Yang, Ping-Wei Wang, Kuo-Yi Chao, Mei-Yun Wang
  • Patent number: 10629501
    Abstract: A semiconductor device includes first and second nanowire structures disposed on semiconductor substrate extending in first direction on substrate. First nanowire structure includes plurality of first nanowires including first nanowire material extending along first direction and arranged in second direction, second direction substantially perpendicular to first direction. Second nanowire structure includes plurality of second nanowires including second nanowire material extending along first direction arranged in second direction. Second nanowire material is not same as first nanowire material. Each nanowire is spaced-apart from immediately adjacent nanowire. First and second gate structures wrap around first and second nanowires at first region of respective first and second nanowire structures. First and second gate structures include gate electrodes.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: April 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Gerben Doornbos, Mark Van Dal, Chung-Te Lin
  • Patent number: 10622479
    Abstract: Aspects disclosed herein include circuits employing a double diffusion break (DDB) and a single diffusion break (SDB) in different type diffusion regions, and related fabrication methods are disclosed. In exemplary aspects disclosed herein, either a DDB or a SDB is formed in the N-type diffusion region(s) and the opposing type diffusion, either a SDB or DDB, is formed in the P-type diffusion region(s). Forming different diffusion breaks between a DDB and a SDB in different diffusion regions of the circuit can be employed to induce channel strain that will increase carrier mobility of either P-type or N-type semiconductor devices formed in respective P-type or N-type diffusion region(s), while avoiding or reducing such induced channel strain in either P-type or N-type semiconductor devices formed in respective P- or N-type diffusion region(s) that may degrade carrier mobility.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: April 14, 2020
    Assignee: QUALCOMM Incorporated
    Inventor: Haining Yang
  • Patent number: 10602252
    Abstract: A membrane (112) for an acoustic device including an electrical conductor (120) integrally formed within the membrane (112). The integrally formed electrical conductor (120) may be net-shaped and may be formed between two or more layers of membrane material. The integrally formed electrical conductor (120) may be electrically connected to the voice coil in an acoustic device, wherein the integrally formed electrical conductor (120) is adapted to provide an electrical signal to the voice coil during operation of the acoustic device. Additionally or alternatively, the integrally formed electrical conductor (120) may be electrically connected to one or more electrical and/or electronic components (240) affixed to the membrane (112).
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: March 24, 2020
    Assignee: Sound Solutions International Co., Ltd.
    Inventors: Helmut Wasinger, Corinna Schwarz
  • Patent number: 10573759
    Abstract: A transistor device comprising an inorganic oxide semiconductor channel having a channel length L and a channel width W between source and drain conductors and capacitively coupled to a gate conductor via an organic polymer dielectric in contact with the inorganic oxide semiconductor channel. The gate voltage required to maintain a constant current of at least X nA between the source and drain conductors over a period of 14 hours while the gate and drain conductors are maintained at the same electric potential, varies by less than 1V, preferably less than about 0.2V; wherein X equals the W/L ratio multiplied by 50.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: February 25, 2020
    Assignee: CAMBRIDGE ENTERPRISE LIMITED
    Inventors: Henning Sirringhaus, Kal Banger, Vincenzo Pecunia
  • Patent number: 10573748
    Abstract: Aspects disclosed herein include circuits employing a double diffusion break (DDB) and a single diffusion break (SDB) in different type diffusion regions, and related fabrication methods are disclosed. In exemplary aspects disclosed herein, either a DDB or a SDB is formed in the N-type diffusion region(s) and the opposing type diffusion, either a SDB or DDB, is formed in the P-type diffusion region(s). Forming different diffusion breaks between a DDB and a SDB in different diffusion regions of the circuit can be employed to induce channel strain that will increase carrier mobility of either P-type or N-type semiconductor devices formed in respective P-type or N-type diffusion region(s), while avoiding or reducing such induced channel strain in either P-type or N-type semiconductor devices formed in respective P- or N-type diffusion region(s) that may degrade carrier mobility.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: February 25, 2020
    Assignee: QUALCOMM Incorporated
    Inventor: Haining Yang
  • Patent number: 10566443
    Abstract: A substrate structure having a set of nanosheet layers and a set of sacrificial layers stacked upon a substrate is received and a dummy gate is formed upon the nanosheet layers and the sacrificial layers. A portion of a subset of the set of sacrificial layers and a subset of the set of nanosheet layers is etched. A portion of a subset of the subset of sacrificial layers is etched to create divots within the sacrificial layers. A divot fill layer is deposited. The divot fill layer is etched to form an inner spacer between the nanosheet layers. A source/drain region is formed adjacent to the nanosheet layers and the divots. A remaining portion of the subset of the sacrificial layers is removed. The subset of the nanosheet layers is etched to a desired channel thickness producing faceted surfaces between the subset of nanosheet layers and the inner spacer.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: February 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Nicolas Loubet, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 10559755
    Abstract: A method of making a carbon nanotube structure includes depositing a first oxide layer on a substrate and a second oxide layer on the first oxide layer; etching a trench through the second oxide layer; removing end portions of the first oxide layer and portions of the substrate beneath the end portions to form cavities in the substrate; depositing a metal in the cavities to form first body metal pads; disposing a carbon nanotube on the first body metal pads and the first oxide layer such that ends of the carbon nanotube contact each of the first body metal layers; depositing a metal to form second body metal pads on the first body metal pads at the ends of the carbon nanotube; and etching to release the carbon nanotube, first body metal pads, and second body metal pads from the substrate, first oxide layer, and second oxide layer.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: February 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin M. Frank, Shu-Jen Han, George S. Tulevski
  • Patent number: 10553590
    Abstract: A semiconductor device includes: a gate trench formed into a semiconductor substrate; a gate dielectric layer formed in the gate trench to cover an inside surface of the gate trench; and a gate electrode disposed over the gate dielectric layer to fill the gate trench, wherein the gate electrode includes: second crystal grains formed in the gate trench; and first crystal grains disposed between the second crystal grains and the gate dielectric layer and having a smaller crystal grain size than the second crystal grains.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: February 4, 2020
    Assignee: SK hynix Inc.
    Inventor: Dong-Soo Kim