Field Effect Device Patents (Class 257/213)
  • Patent number: 10978513
    Abstract: Provided are a complementary carbon nanotube field effect transistor (CNT-FET) and a manufacturing method thereof. In particular, provided is carbon nanotube-based type conversion technology (p-type?n-type) using a photosensitive polyvinyl alcohol polymer which can be selectively cross-linked at a desired position based on a semiconductor standard process, i.e., photolithography.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: April 13, 2021
    Assignee: INCHEON UNIVERSITY INDUSTRY ACADEMIC COOPERATION FOUNDATION
    Inventor: Sung Hun Jin
  • Patent number: 10978299
    Abstract: A semiconductor device according to an example embodiment includes a substrate extending in first and second directions intersecting with each other; nanowires on the substrate and spaced apart from each other in the second direction; gate electrodes extending in the first direction and spaced apart from each other in the second direction, and surrounding the nanowires to be superimposed vertically with the nanowires; external spacers on the substrate and covering sidewalls of the gate electrodes on the nanowires; and an isolation layer between the gate electrodes and extending in the first direction, wherein an upper surface of the isolation layer is flush with upper surfaces of the gate electrodes.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: April 13, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-woo Noh, Myung-gil Kang, Ho-jun Kim, Geum-jong Bae, Dong-il Bae
  • Patent number: 10976281
    Abstract: Embodiments of the present disclosure relate to the field of electronic sensing technologies, and provide a chemical sensing unit, a chemical sensor, and a chemical sensing device. The chemical sensing unit includes a thin film transistor arranged on a substrate, and a light emitting diode coupled to the thin film transistor. The thin film transistor includes a semiconductor active layer, a source, and a drain, and the semiconductor active layer is mainly composed of a chemically sensitive semiconductor material. The chemical sensing unit is provided with a via hole in a region between the source and the drain, such that the semiconductor active layer is exposed at a position corresponding to the via hole. The light emitting diode includes a first electrode, a light-emitting functional layer, and a second electrode which are stacked in sequence, wherein the first electrode is coupled to the drain.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: April 13, 2021
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Qinghe Wang, Liangchen Yan, Dongfang Wang, Tongshang Su, Leilei Cheng, Yongchao Huang, Yang Zhang, Guangyao Li, Guangcai Yuan
  • Patent number: 10971629
    Abstract: Structures and methods of forming self-aligned unsymmetric gate (SAUG) FinFET are provided. The SAUG FinFET structure has two different gate structures on opposite sides of each fin: a programming gate structure and a switching gate structure. The SAUG FinFET may be used as non-volatile memory (NVM) storage element that may be electrically programmed by trapping charges in the charge trapping dielectric (e.g., Si3N4) with appropriate bias on the control gate of the programming gate structure. The stored data may be sensed by sensing the channel current through the SAUG FinFET in response to a bias on the switching gate of the switching gate structure.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: April 6, 2021
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Chiao Tung University
    Inventors: Chao-Hsin Chien, Yu-Che Chou, Chien-Wei Tsai, Chin-Ya Yi
  • Patent number: 10964601
    Abstract: A method of fabricating a vertical fin field effect transistor with a merged top source/drain, including, forming a source/drain layer at the surface of a substrate, forming a plurality of vertical fins on the source/drain layer; forming protective spacers on each of the plurality of vertical fins, forming a sacrificial plug between two protective spacers, forming a filler layer on the protective spacers not in contact with the sacrificial plug, and selectively removing the sacrificial plug to form an isolation region trench between the two protective spacers.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: March 30, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10937908
    Abstract: Various methods for fabricating non-planar integrated circuit devices, such as FinFET devices, are disclosed herein. An exemplary method includes forming a rib structure extending from a substrate; forming a two-dimensional material layer (including, for example, transition metal dichalcogenide or graphene) on the rib structure and the substrate; patterning the two-dimensional material layer, such that the two-dimensional material layer is disposed on at least one surface of the rib structure; and forming a gate on the two-dimensional material layer. In some implementations, a channel region, a source region, and a drain region are defined in the two-dimensional material layer. The channel region is disposed between the source region and the drain region, where the gate is disposed over the channel region. In some implementations, the patterning includes removing the two-dimensional material layer disposed on a top surface of the substrate and/or disposed on a top surface of the rib structure.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mark van Dal, Martin Christopher Holland, Matthias Passlack
  • Patent number: 10923388
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gap fill void and connection structures and methods of manufacture. The structure includes: a gate structure comprising source and drain regions; a gate contact in direct contact and overlapping the gate structure; and source and drain contacts directly connecting to the source and drain regions, respectively.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: February 16, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Haigou Huang, Yuping Ren, Paul Ackmann, Guoxiang Ning
  • Patent number: 10910368
    Abstract: A circuit structure including a first gate structure, a first multi-connected channel layer and a second transistor is provided. The first gate structure has a first extension direction, and the first gate structure has a first end and a second end opposite to each other. The first gate structure is fully surrounded by the first multi-connected channel layer, and a plane direction of the multi-connected channel layer is perpendicular to the first extension direction. The first gate structure and the first multi-connected channel layer form a first transistor. The second transistor is disposed in the first multi-connected channel layer. A second gate structure or a channel of the second transistor is electrical connected to the first multi-connected channel layer.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: February 2, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Chun-Sheng Chen
  • Patent number: 10886227
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including gate structures on a substrate; source/drain layers on portions of the substrate that are adjacent the gate structures, respectively; first contact plugs contacting upper surfaces of the source/drain layers, respectively; a second contact plug contacting one of the gate structures, a sidewall of the second contact plug being covered by an insulating spacer; and a third contact plug commonly contacting an upper surface of at least one of the gate structures and at least one of the first contact plugs, at least a portion of a sidewall of the third contact plug not being covered by an insulating spacer.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: January 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyo-Jin Kim, Chang-Hwa Kim, Hwi-Chan Jun, Chui-Hong Park, Jae-Seok Yang, Kwan-Young Chun
  • Patent number: 10872957
    Abstract: A semiconductor device includes a semiconductor substrate, a transistor cell region formed in the semiconductor substrate and an inner termination region formed in the semiconductor substrate and devoid of transistor cells. The transistor cell region includes a plurality of transistor cells and a gate structure that forms a grid separating transistor sections of the transistor cells from each other, each of the transistor sections including a needle-shaped first field plate structure extending from a first surface into the semiconductor substrate. The inner termination region surrounds the transistor cell region and includes needle-shaped second field plate structures extending from the first surface into the semiconductor substrate. The first field plate structures form a first portion of a regular pattern and the second field plate structures form a second portion of the same regular pattern.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: December 22, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Oliver Blank, Franz Hirler, Michael Hutzler, David Laforet, Cedric Ouvrard, Li Juin Yip
  • Patent number: 10847431
    Abstract: A method for fabricating a semiconductor device using a high-temperature ion implantation process includes providing a substrate including a plurality of fins. In some examples, a mask material is deposited and patterned to expose a group of fins of the plurality of fins and a test structure. By way of example, a first ion implantation may be performed, at a first temperature, through the group of fins and the test structure. Additionally, a second ion implantation may be performed, at a second temperature greater than the first temperature, through the group of fins and the test structure. In various examples, an interstitial cluster is formed within the group of fins and within the test structure. In some embodiments, an anneal process is performed, where the anneal process serves to remove the interstitial cluster from the group of fins and form at least one dislocation loop within the test structure.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsan-Chun Wang, Chun Hsiung Tsai, Ziwei Fang
  • Patent number: 10847513
    Abstract: Various examples of a buried interconnect line are disclosed herein. In an example, a device includes a fin disposed on a substrate. The fin includes an active device. A plurality of isolation features are disposed on the substrate and below the active device. An interconnect is disposed on the substrate and between the plurality of isolation features such that the interconnect is below a topmost surface of the plurality of isolation features. The interconnect is electrically coupled to the active device. In some such examples, a gate stack of the active device is disposed over a channel region of the active device and is electrically coupled to the interconnect. In some such examples, a source/drain contact is electrically coupled to a source/drain region of the active device, and the source/drain contact is electrically coupled to the interconnect.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Kuan-Ting Pan, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10847631
    Abstract: Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Abhijit Jayant Pethe, Tahir Ghani, Harry Gomez
  • Patent number: 10847653
    Abstract: Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Martin D. Giles, Annalisa Cappellani, Sanaz Gardner, Rafael Rios, Cory E. Weber, Aaron A. Budrevich
  • Patent number: 10818776
    Abstract: A substrate structure having a set of nanosheet layers and a set of sacrificial layers stacked upon a substrate is received and a dummy gate is formed upon the nanosheet layers and the sacrificial layers. A portion of a subset of the set of sacrificial layers and a subset of the set of nanosheet layers is etched. A portion of a subset of the subset of sacrificial layers is etched to create divots within the sacrificial layers. A divot fill layer is deposited. The divot fill layer is etched to form an inner spacer between the nanosheet layers. A source/drain region is formed adjacent to the nanosheet layers and the divots. A remaining portion of the subset of the sacrificial layers is removed. The subset of the nanosheet layers is etched to a desired channel thickness producing faceted surfaces between the subset of nanosheet layers and the inner spacer.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: October 27, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Nicolas Loubet, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 10811317
    Abstract: Methods for manufacturing semiconductor structures are provided. The method includes alternately stacking first epitaxy layers and second epitaxy layers to form a semiconductor stack and forming a first mask structure and a second mask structure over the semiconductor stack. The method further includes forming spacers on sidewalls of the second mask and patterning the semiconductor stack to form a first fin structure covered by the first mask structure and a second fin structure covered by the second mask structure and the spacers. The method further includes removing the first epitaxy layers of the first fin structure to form first nanostructures and removing the first epitaxy layers of the second fin structure to form second nanostructures. In addition, the second nanostructures are wider than the first nanostructures.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Shi-Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10796964
    Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region in a plane view. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping with the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping with the gate region.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: October 6, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Yin Hsiao, Ching-Chung Yang, Kuan-Liang Liu
  • Patent number: 10734166
    Abstract: A composite structure for an electric energy storage device is envisioned. The structure is made of a metal substrate and a metal oxide layer disposed over a majority of the metal substrate with the metal oxide layer being comprised of a first and second metals. Carbon nanotubes are disposed on the metal oxide layer. In an embodiment the first metal and the second metal are each selected from a group consisting of: iron, nickel, aluminum, cobalt, copper, chromium, and gold.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: August 4, 2020
    Assignee: ZapGo Ltd
    Inventors: Cattien Nguyen, You Li, Hoang Nguyen Ly, Darrell Niemann, Bevan Vo, Phillip Kraus
  • Patent number: 10727298
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Patent number: 10720503
    Abstract: A semiconductor device includes a semiconductor substrate, a first fin structure and a second fin structure. The first fin structure includes a first fin and at least two first nano wires disposed above the first fin, and the first fin protrudes from the semiconductor substrate. The second fin structure includes a second fin and at least two second nano wires disposed above the second fin, and the second fin protrudes from the semiconductor substrate. Each first nano wire has a first width different from a second width of each second nano wire.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: July 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Shi-Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10680075
    Abstract: A semiconductor device includes a fin structure disposed over a substrate, wherein the fin structure including a channel layer and extending in a first direction, a gate structure including a gate electrode layer and a gate dielectric layer, sidewall spacers disposed on opposite side faces of the gate structure, and a source/drain structure including an epitaxial layer having at least seven facets in a cross section along the first direction.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chao-Wei Hsu
  • Patent number: 10651178
    Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Kuan Lin, Chang-Ta Yang, Ping-Wei Wang, Kuo-Yi Chao, Mei-Yun Wang
  • Patent number: 10629501
    Abstract: A semiconductor device includes first and second nanowire structures disposed on semiconductor substrate extending in first direction on substrate. First nanowire structure includes plurality of first nanowires including first nanowire material extending along first direction and arranged in second direction, second direction substantially perpendicular to first direction. Second nanowire structure includes plurality of second nanowires including second nanowire material extending along first direction arranged in second direction. Second nanowire material is not same as first nanowire material. Each nanowire is spaced-apart from immediately adjacent nanowire. First and second gate structures wrap around first and second nanowires at first region of respective first and second nanowire structures. First and second gate structures include gate electrodes.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: April 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Gerben Doornbos, Mark Van Dal, Chung-Te Lin
  • Patent number: 10622479
    Abstract: Aspects disclosed herein include circuits employing a double diffusion break (DDB) and a single diffusion break (SDB) in different type diffusion regions, and related fabrication methods are disclosed. In exemplary aspects disclosed herein, either a DDB or a SDB is formed in the N-type diffusion region(s) and the opposing type diffusion, either a SDB or DDB, is formed in the P-type diffusion region(s). Forming different diffusion breaks between a DDB and a SDB in different diffusion regions of the circuit can be employed to induce channel strain that will increase carrier mobility of either P-type or N-type semiconductor devices formed in respective P-type or N-type diffusion region(s), while avoiding or reducing such induced channel strain in either P-type or N-type semiconductor devices formed in respective P- or N-type diffusion region(s) that may degrade carrier mobility.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: April 14, 2020
    Assignee: QUALCOMM Incorporated
    Inventor: Haining Yang
  • Patent number: 10602252
    Abstract: A membrane (112) for an acoustic device including an electrical conductor (120) integrally formed within the membrane (112). The integrally formed electrical conductor (120) may be net-shaped and may be formed between two or more layers of membrane material. The integrally formed electrical conductor (120) may be electrically connected to the voice coil in an acoustic device, wherein the integrally formed electrical conductor (120) is adapted to provide an electrical signal to the voice coil during operation of the acoustic device. Additionally or alternatively, the integrally formed electrical conductor (120) may be electrically connected to one or more electrical and/or electronic components (240) affixed to the membrane (112).
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: March 24, 2020
    Assignee: Sound Solutions International Co., Ltd.
    Inventors: Helmut Wasinger, Corinna Schwarz
  • Patent number: 10573759
    Abstract: A transistor device comprising an inorganic oxide semiconductor channel having a channel length L and a channel width W between source and drain conductors and capacitively coupled to a gate conductor via an organic polymer dielectric in contact with the inorganic oxide semiconductor channel. The gate voltage required to maintain a constant current of at least X nA between the source and drain conductors over a period of 14 hours while the gate and drain conductors are maintained at the same electric potential, varies by less than 1V, preferably less than about 0.2V; wherein X equals the W/L ratio multiplied by 50.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: February 25, 2020
    Assignee: CAMBRIDGE ENTERPRISE LIMITED
    Inventors: Henning Sirringhaus, Kal Banger, Vincenzo Pecunia
  • Patent number: 10573748
    Abstract: Aspects disclosed herein include circuits employing a double diffusion break (DDB) and a single diffusion break (SDB) in different type diffusion regions, and related fabrication methods are disclosed. In exemplary aspects disclosed herein, either a DDB or a SDB is formed in the N-type diffusion region(s) and the opposing type diffusion, either a SDB or DDB, is formed in the P-type diffusion region(s). Forming different diffusion breaks between a DDB and a SDB in different diffusion regions of the circuit can be employed to induce channel strain that will increase carrier mobility of either P-type or N-type semiconductor devices formed in respective P-type or N-type diffusion region(s), while avoiding or reducing such induced channel strain in either P-type or N-type semiconductor devices formed in respective P- or N-type diffusion region(s) that may degrade carrier mobility.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: February 25, 2020
    Assignee: QUALCOMM Incorporated
    Inventor: Haining Yang
  • Patent number: 10566443
    Abstract: A substrate structure having a set of nanosheet layers and a set of sacrificial layers stacked upon a substrate is received and a dummy gate is formed upon the nanosheet layers and the sacrificial layers. A portion of a subset of the set of sacrificial layers and a subset of the set of nanosheet layers is etched. A portion of a subset of the subset of sacrificial layers is etched to create divots within the sacrificial layers. A divot fill layer is deposited. The divot fill layer is etched to form an inner spacer between the nanosheet layers. A source/drain region is formed adjacent to the nanosheet layers and the divots. A remaining portion of the subset of the sacrificial layers is removed. The subset of the nanosheet layers is etched to a desired channel thickness producing faceted surfaces between the subset of nanosheet layers and the inner spacer.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: February 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Nicolas Loubet, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 10559755
    Abstract: A method of making a carbon nanotube structure includes depositing a first oxide layer on a substrate and a second oxide layer on the first oxide layer; etching a trench through the second oxide layer; removing end portions of the first oxide layer and portions of the substrate beneath the end portions to form cavities in the substrate; depositing a metal in the cavities to form first body metal pads; disposing a carbon nanotube on the first body metal pads and the first oxide layer such that ends of the carbon nanotube contact each of the first body metal layers; depositing a metal to form second body metal pads on the first body metal pads at the ends of the carbon nanotube; and etching to release the carbon nanotube, first body metal pads, and second body metal pads from the substrate, first oxide layer, and second oxide layer.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: February 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin M. Frank, Shu-Jen Han, George S. Tulevski
  • Patent number: 10553590
    Abstract: A semiconductor device includes: a gate trench formed into a semiconductor substrate; a gate dielectric layer formed in the gate trench to cover an inside surface of the gate trench; and a gate electrode disposed over the gate dielectric layer to fill the gate trench, wherein the gate electrode includes: second crystal grains formed in the gate trench; and first crystal grains disposed between the second crystal grains and the gate dielectric layer and having a smaller crystal grain size than the second crystal grains.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: February 4, 2020
    Assignee: SK hynix Inc.
    Inventor: Dong-Soo Kim
  • Patent number: 10546942
    Abstract: A substrate structure having a set of nanosheet layers and a set of sacrificial layers stacked upon a substrate is received and a dummy gate is formed upon the nanosheet layers and the sacrificial layers. A portion of a subset of the set of sacrificial layers and a subset of the set of nanosheet layers is etched. A portion of a subset of the subset of sacrificial layers is etched to create divots within the sacrificial layers. A divot fill layer is deposited. The divot fill layer is etched to form an inner spacer between the nanosheet layers. A source/drain region is formed adjacent to the nanosheet layers and the divots. A remaining portion of the subset of the sacrificial layers is removed. The subset of the nanosheet layers is etched to a desired channel thickness producing faceted surfaces between the subset of nanosheet layers and the inner spacer.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Nicolas Loubet, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 10546771
    Abstract: A multilayer semiconductor on insulator structure is provided in which the handle substrate and an epitaxial layer in interfacial contact with the handle substrate comprise electrically active dopants of opposite type. The epitaxial layer is depleted by the handle substrate free carriers, thereby resulting in a high apparent resistivity, which improves the function of the structure in RF devices.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: January 28, 2020
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Gang Wang, Jeffrey L. Libbert, Shawn George Thomas, Qingmin Liu
  • Patent number: 10535732
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Patent number: 10529830
    Abstract: A method of forming a semiconductor device having a channel and a source-drain coupled to the channel. The method includes etching a channel region such that an end of the channel region forms a recess within a gate structure surrounding the channel region. An extension region is formed in contact with the channel region and at least partially filling the recess. Extension material of the extension region has a different composition from channel material of the channel region such that a strain is caused in the channel region. A source-drain region is in contact with the extension region and adjacent to the gate structure.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: January 7, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kandabara Tapily, Jeffrey Smith, Nihar Mohanty, Anton J. Devilliers
  • Patent number: 10522564
    Abstract: In an embodiment, a ferroelectric memory device includes a substrate having a source region and a drain region, a ferroelectric structure disposed on the substrate, and a gate electrode layer disposed on the ferroelectric structure. The ferroelectric structure includes a ferroelectric material layer having a concentration gradient of a dopant.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: December 31, 2019
    Assignee: SK hynix Inc.
    Inventor: Hyangkeun Yoo
  • Patent number: 10505111
    Abstract: A method is presented for reducing heat loss to adjacent semiconductor structures. The method includes forming a plurality of conductive lines within an interlayer dielectric, forming a barrier layer over at least one conductive line of the plurality of conductive lines, forming a via extending to a top surface of the barrier layer, and defining dual air gaps within the via and over the barrier layer.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: December 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Wei Wang
  • Patent number: 10468505
    Abstract: A semiconductor device includes a substrate, a cavity in the substrate, and a germanium (Ge) nanowire suspending in the cavity.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 5, 2019
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Deyuan Xiao
  • Patent number: 10469174
    Abstract: Provided is an anti-interference semiconductor device for an optical transceiver. The semiconductor device includes: a back metallization layer, a p++ bearing wafer layer, a P-type epitaxial layer, an isolation layer and a metal layer arranged from bottom to top. The back metallization layer serves as a substrate, on which the p++ bearing wafer layer is formed. The P-type epitaxial layer is formed on the p++ bearing wafer layer. The metal layer is formed on the isolation layer. The semiconductor device includes at least two N-type heavily doped grooves, two P-type heavily doped grooves and a plurality of deep through-silicon vias, which are formed in the P-type epitaxial layer and the isolation layer. The deep through-silicon vias are distributed and divided into at least two rows. The N-type heavily doped grooves and the P-type heavily doped grooves are alternately arranged at two sides of the deep through-silicon vias.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: November 5, 2019
    Assignee: WINGCOMM CO. LTD.
    Inventor: Yun Bai
  • Patent number: 10446664
    Abstract: Embodiments of the invention are directed to a method of fabricating a semiconductor device. A non-limiting example of the method includes performing fabrication operations to form a nanosheet field effect transistor device, wherein the fabrication operations include forming a stack over a substrate. The stack includes alternating layers of sacrificial nanosheets and channel nanosheets over a substrate. The stack further includes lateral sidewalls having a length (L) and end sidewalls having a width (W), wherein L is greater than W. Source or drain (S/D) regions are formed along the length (L) of the lateral sidewalls.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: October 15, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Choonghyun Lee, Juntao Li, Peng Xu
  • Patent number: 10439049
    Abstract: A nanosheet transistor device having reduced access resistance is fabricated by recessing channel nanosheets and replacing the channel material with epitaxially grown doped extension regions. Sacrificial semiconductor layers between the channel nanosheets are selectively removed without damaging source/drain regions epitaxially grown on the extension regions. The sacrificial semiconductor layers are replaced by gate dielectric and gate metal layers.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: October 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10403711
    Abstract: In one embodiment, a method of manufacturing a silicon-carbide (SiC) device includes receiving a selection of a specific terrestrial cosmic ray (TCR) rating at a specific applied voltage, determining a breakdown voltage for the SiC device based at least on the specific TCR rating at the specific applied voltage, determining drift layer design parameters based at least on the breakdown voltage. The drift layer design parameters include doping concentration and thickness of the drift layer. The method also includes fabricating the SiC device having a drift layer with the determined drift layer design parameters. The SiC device has the specific TCR rating at the specific applied voltage.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: September 3, 2019
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Alexander Viktorovich Bolotnikov, Ljubisa Dragoljub Stevanovic, Peter Almern Losee
  • Patent number: 10388649
    Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, wherein the semiconductor substrate includes a first region and a second region. The semiconductor device also includes a buried layer disposed in the first region of the semiconductor substrate and having the first conductivity type, wherein the buried layer has a dopant concentration that is greater than that of the semiconductor substrate. The semiconductor device further includes an epitaxial layer disposed on the semiconductor substrate, and a first element disposed on the first region of the semiconductor substrate, wherein the first element includes a bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) (BCD) transistor. In addition, the semiconductor device includes a second element disposed on the second region of the semiconductor substrate, wherein the second element includes an ultra-high voltage (UHV) transistor.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: August 20, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chien-Wei Chiu, Shin-Cheng Lin, Yu-Hao Ho
  • Patent number: 10381482
    Abstract: A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: August 13, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Yu Chen, Chi-Yuan Shih, Chi-Wen Liu
  • Patent number: 10366993
    Abstract: A semiconductor structure includes a semiconductor substrate having a trench isolation region formed therein. A conductive gate electrode is buried in the trench isolation region. An air gap is disposed between the conductive gate electrode and the semiconductor substrate.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: July 30, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee
  • Patent number: 10354941
    Abstract: A heat sink capable of dissipating heat concentrating on a chip portion of a power semiconductor device module efficiently is provided. A heat sink (20) includes a heat sink body (21) in which a power semiconductor device module (10) having a plurality of power semiconductor devices (11) is placed on a cooling surface F1 and which radiates heat generated by the power semiconductor device (11); and a heat dissipation structure portion (25) having a higher heat conductivity than the heat sink body (21) and capable of dissipating heat generated by the power semiconductor device (11), wherein the heat dissipation structure portion (25) is provided at a position overlapping the power semiconductor device (11) disposed in the power semiconductor device module (10) in a direction (Z) orthogonal to the cooling surface (F1) of the heat sink body (21).
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: July 16, 2019
    Assignee: FANUC CORPORATION
    Inventors: Masato Watanabe, Taku Sasaki
  • Patent number: 10347671
    Abstract: An image sensor includes a plurality of unit pixels formed as a semiconductor chip, each of which has a photoelectric converting unit, a charge holding unit that holds charges stored in the photoelectric converting unit, a charge-voltage converting unit that converts a charge transferred from the charge holding unit to a voltage, and light shielding films between which an opening is formed above the photoelectric converting unit. The plurality of unit pixels are placed in a matrix in a pixel array. The shapes of the light shielding films are varied depending on the position of the unit pixel in the pixel array.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: July 9, 2019
    Assignee: Sony Semiconductor Solution Corporation
    Inventor: Tomohiro Ohkubo
  • Patent number: 10325913
    Abstract: Generally, in one embodiment, the present disclosure is directed to a method for forming a transistor. The method includes: implanting a substrate to form at least one of an n and p doped region; depositing an epitaxial semiconductor layer over the substrate; forming trenches through the epitaxial layer and partially through at least one of an n and p doped region; forming dielectric isolation regions in the trenches; forming a fin in an upper portion of the epitaxial semiconductor layer by partially recessing the dielectric isolation regions; forming a gate dielectric adjacent at least two surfaces of the fin; and diffusing dopant from at least one of the n and p doped regions at least partially into the epitaxial semiconductor layer to form a diffusion doped transition region adjacent a bottom portion of the fin.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: June 18, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: David Paul Brunco, Jeffrey Bowman Johnson
  • Patent number: 10312345
    Abstract: The present disclosure provides a method for manufacturing a transistor having a gate with a variable work function, comprising: providing a semiconductor substrate; forming a dummy gate stack on the semiconductor substrate and performing ion implantation on an exposed area of the semiconductor substrate at both sides of the dummy gate stack to form source/drain regions; removing the dummy gate and annealing the source/drain regions; providing an atomic layer deposition reaction device; introducing a precursor source reactant into the atomic layer deposition reaction device; and controlling an environmental factor for the atomic layer deposition device to grow a work function metal layer. The present disclosure also provides a transistor having a gate with a variable work function. The present disclosure may adjust a variable work function, and may use the same material system to obtain an adjustable threshold voltage within an adjustable range.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: June 4, 2019
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Jinjuan Xiang, Xiaolei Wang, Hong Yang, Shi Liu, Junfeng Li, Wenwu Wang, Chao Zhao
  • Patent number: 10312332
    Abstract: A semiconductor device is provided, which includes a substrate, a gate and a gate contact. The substrate has a well region, which has a source, a drain and a channel region extending between the source and the drain. The gate is on the well region and extends across the channel region. The gate contact is directly on the gate and vertically overlaps with the channel region. The gate contact has a strip shape of which a ratio of a length to a width is at least 2. The gate contact includes a gate conductive plug and a gate contact dielectric. The gate conductive plug directly contacts the gate. The gate contact dielectric surrounds side surfaces of the gate conductive plug and has a frame shape. A dielectric constant of the gate contact dielectric is substantially greater than 4.9.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10276580
    Abstract: Systems and methods are provided for forming an intra-connection structure. A first gate structure and a first source/drain region adjacent to the first gate structure is formed on a substrate. A first dielectric material is disposed on the first source/drain region. A spacer material is formed on the first gate structure. The first dielectric material is removed to expose at least part of the first source/drain region. At least part of the spacer material is removed to expose at least part of the first gate structure. A first conductive material is formed between the first gate structure and the first source/drain region to electrically connect the first source/drain region and the first gate structure.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Feng-Ming Chang, Kuo-Hsiu Hsu