Field Effect Device Patents (Class 257/213)
  • Patent number: 10680075
    Abstract: A semiconductor device includes a fin structure disposed over a substrate, wherein the fin structure including a channel layer and extending in a first direction, a gate structure including a gate electrode layer and a gate dielectric layer, sidewall spacers disposed on opposite side faces of the gate structure, and a source/drain structure including an epitaxial layer having at least seven facets in a cross section along the first direction.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chao-Wei Hsu
  • Patent number: 10651178
    Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Kuan Lin, Chang-Ta Yang, Ping-Wei Wang, Kuo-Yi Chao, Mei-Yun Wang
  • Patent number: 10629501
    Abstract: A semiconductor device includes first and second nanowire structures disposed on semiconductor substrate extending in first direction on substrate. First nanowire structure includes plurality of first nanowires including first nanowire material extending along first direction and arranged in second direction, second direction substantially perpendicular to first direction. Second nanowire structure includes plurality of second nanowires including second nanowire material extending along first direction arranged in second direction. Second nanowire material is not same as first nanowire material. Each nanowire is spaced-apart from immediately adjacent nanowire. First and second gate structures wrap around first and second nanowires at first region of respective first and second nanowire structures. First and second gate structures include gate electrodes.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: April 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Gerben Doornbos, Mark Van Dal, Chung-Te Lin
  • Patent number: 10622479
    Abstract: Aspects disclosed herein include circuits employing a double diffusion break (DDB) and a single diffusion break (SDB) in different type diffusion regions, and related fabrication methods are disclosed. In exemplary aspects disclosed herein, either a DDB or a SDB is formed in the N-type diffusion region(s) and the opposing type diffusion, either a SDB or DDB, is formed in the P-type diffusion region(s). Forming different diffusion breaks between a DDB and a SDB in different diffusion regions of the circuit can be employed to induce channel strain that will increase carrier mobility of either P-type or N-type semiconductor devices formed in respective P-type or N-type diffusion region(s), while avoiding or reducing such induced channel strain in either P-type or N-type semiconductor devices formed in respective P- or N-type diffusion region(s) that may degrade carrier mobility.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: April 14, 2020
    Assignee: QUALCOMM Incorporated
    Inventor: Haining Yang
  • Patent number: 10602252
    Abstract: A membrane (112) for an acoustic device including an electrical conductor (120) integrally formed within the membrane (112). The integrally formed electrical conductor (120) may be net-shaped and may be formed between two or more layers of membrane material. The integrally formed electrical conductor (120) may be electrically connected to the voice coil in an acoustic device, wherein the integrally formed electrical conductor (120) is adapted to provide an electrical signal to the voice coil during operation of the acoustic device. Additionally or alternatively, the integrally formed electrical conductor (120) may be electrically connected to one or more electrical and/or electronic components (240) affixed to the membrane (112).
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: March 24, 2020
    Assignee: Sound Solutions International Co., Ltd.
    Inventors: Helmut Wasinger, Corinna Schwarz
  • Patent number: 10573759
    Abstract: A transistor device comprising an inorganic oxide semiconductor channel having a channel length L and a channel width W between source and drain conductors and capacitively coupled to a gate conductor via an organic polymer dielectric in contact with the inorganic oxide semiconductor channel. The gate voltage required to maintain a constant current of at least X nA between the source and drain conductors over a period of 14 hours while the gate and drain conductors are maintained at the same electric potential, varies by less than 1V, preferably less than about 0.2V; wherein X equals the W/L ratio multiplied by 50.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: February 25, 2020
    Assignee: CAMBRIDGE ENTERPRISE LIMITED
    Inventors: Henning Sirringhaus, Kal Banger, Vincenzo Pecunia
  • Patent number: 10573748
    Abstract: Aspects disclosed herein include circuits employing a double diffusion break (DDB) and a single diffusion break (SDB) in different type diffusion regions, and related fabrication methods are disclosed. In exemplary aspects disclosed herein, either a DDB or a SDB is formed in the N-type diffusion region(s) and the opposing type diffusion, either a SDB or DDB, is formed in the P-type diffusion region(s). Forming different diffusion breaks between a DDB and a SDB in different diffusion regions of the circuit can be employed to induce channel strain that will increase carrier mobility of either P-type or N-type semiconductor devices formed in respective P-type or N-type diffusion region(s), while avoiding or reducing such induced channel strain in either P-type or N-type semiconductor devices formed in respective P- or N-type diffusion region(s) that may degrade carrier mobility.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: February 25, 2020
    Assignee: QUALCOMM Incorporated
    Inventor: Haining Yang
  • Patent number: 10566443
    Abstract: A substrate structure having a set of nanosheet layers and a set of sacrificial layers stacked upon a substrate is received and a dummy gate is formed upon the nanosheet layers and the sacrificial layers. A portion of a subset of the set of sacrificial layers and a subset of the set of nanosheet layers is etched. A portion of a subset of the subset of sacrificial layers is etched to create divots within the sacrificial layers. A divot fill layer is deposited. The divot fill layer is etched to form an inner spacer between the nanosheet layers. A source/drain region is formed adjacent to the nanosheet layers and the divots. A remaining portion of the subset of the sacrificial layers is removed. The subset of the nanosheet layers is etched to a desired channel thickness producing faceted surfaces between the subset of nanosheet layers and the inner spacer.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: February 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Nicolas Loubet, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 10559755
    Abstract: A method of making a carbon nanotube structure includes depositing a first oxide layer on a substrate and a second oxide layer on the first oxide layer; etching a trench through the second oxide layer; removing end portions of the first oxide layer and portions of the substrate beneath the end portions to form cavities in the substrate; depositing a metal in the cavities to form first body metal pads; disposing a carbon nanotube on the first body metal pads and the first oxide layer such that ends of the carbon nanotube contact each of the first body metal layers; depositing a metal to form second body metal pads on the first body metal pads at the ends of the carbon nanotube; and etching to release the carbon nanotube, first body metal pads, and second body metal pads from the substrate, first oxide layer, and second oxide layer.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: February 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin M. Frank, Shu-Jen Han, George S. Tulevski
  • Patent number: 10553590
    Abstract: A semiconductor device includes: a gate trench formed into a semiconductor substrate; a gate dielectric layer formed in the gate trench to cover an inside surface of the gate trench; and a gate electrode disposed over the gate dielectric layer to fill the gate trench, wherein the gate electrode includes: second crystal grains formed in the gate trench; and first crystal grains disposed between the second crystal grains and the gate dielectric layer and having a smaller crystal grain size than the second crystal grains.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: February 4, 2020
    Assignee: SK hynix Inc.
    Inventor: Dong-Soo Kim
  • Patent number: 10546942
    Abstract: A substrate structure having a set of nanosheet layers and a set of sacrificial layers stacked upon a substrate is received and a dummy gate is formed upon the nanosheet layers and the sacrificial layers. A portion of a subset of the set of sacrificial layers and a subset of the set of nanosheet layers is etched. A portion of a subset of the subset of sacrificial layers is etched to create divots within the sacrificial layers. A divot fill layer is deposited. The divot fill layer is etched to form an inner spacer between the nanosheet layers. A source/drain region is formed adjacent to the nanosheet layers and the divots. A remaining portion of the subset of the sacrificial layers is removed. The subset of the nanosheet layers is etched to a desired channel thickness producing faceted surfaces between the subset of nanosheet layers and the inner spacer.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Nicolas Loubet, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 10546771
    Abstract: A multilayer semiconductor on insulator structure is provided in which the handle substrate and an epitaxial layer in interfacial contact with the handle substrate comprise electrically active dopants of opposite type. The epitaxial layer is depleted by the handle substrate free carriers, thereby resulting in a high apparent resistivity, which improves the function of the structure in RF devices.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: January 28, 2020
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Gang Wang, Jeffrey L. Libbert, Shawn George Thomas, Qingmin Liu
  • Patent number: 10535732
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Patent number: 10529830
    Abstract: A method of forming a semiconductor device having a channel and a source-drain coupled to the channel. The method includes etching a channel region such that an end of the channel region forms a recess within a gate structure surrounding the channel region. An extension region is formed in contact with the channel region and at least partially filling the recess. Extension material of the extension region has a different composition from channel material of the channel region such that a strain is caused in the channel region. A source-drain region is in contact with the extension region and adjacent to the gate structure.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: January 7, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kandabara Tapily, Jeffrey Smith, Nihar Mohanty, Anton J. Devilliers
  • Patent number: 10522564
    Abstract: In an embodiment, a ferroelectric memory device includes a substrate having a source region and a drain region, a ferroelectric structure disposed on the substrate, and a gate electrode layer disposed on the ferroelectric structure. The ferroelectric structure includes a ferroelectric material layer having a concentration gradient of a dopant.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: December 31, 2019
    Assignee: SK hynix Inc.
    Inventor: Hyangkeun Yoo
  • Patent number: 10505111
    Abstract: A method is presented for reducing heat loss to adjacent semiconductor structures. The method includes forming a plurality of conductive lines within an interlayer dielectric, forming a barrier layer over at least one conductive line of the plurality of conductive lines, forming a via extending to a top surface of the barrier layer, and defining dual air gaps within the via and over the barrier layer.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: December 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Wei Wang
  • Patent number: 10468505
    Abstract: A semiconductor device includes a substrate, a cavity in the substrate, and a germanium (Ge) nanowire suspending in the cavity.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 5, 2019
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Deyuan Xiao
  • Patent number: 10469174
    Abstract: Provided is an anti-interference semiconductor device for an optical transceiver. The semiconductor device includes: a back metallization layer, a p++ bearing wafer layer, a P-type epitaxial layer, an isolation layer and a metal layer arranged from bottom to top. The back metallization layer serves as a substrate, on which the p++ bearing wafer layer is formed. The P-type epitaxial layer is formed on the p++ bearing wafer layer. The metal layer is formed on the isolation layer. The semiconductor device includes at least two N-type heavily doped grooves, two P-type heavily doped grooves and a plurality of deep through-silicon vias, which are formed in the P-type epitaxial layer and the isolation layer. The deep through-silicon vias are distributed and divided into at least two rows. The N-type heavily doped grooves and the P-type heavily doped grooves are alternately arranged at two sides of the deep through-silicon vias.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: November 5, 2019
    Assignee: WINGCOMM CO. LTD.
    Inventor: Yun Bai
  • Patent number: 10446664
    Abstract: Embodiments of the invention are directed to a method of fabricating a semiconductor device. A non-limiting example of the method includes performing fabrication operations to form a nanosheet field effect transistor device, wherein the fabrication operations include forming a stack over a substrate. The stack includes alternating layers of sacrificial nanosheets and channel nanosheets over a substrate. The stack further includes lateral sidewalls having a length (L) and end sidewalls having a width (W), wherein L is greater than W. Source or drain (S/D) regions are formed along the length (L) of the lateral sidewalls.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: October 15, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Choonghyun Lee, Juntao Li, Peng Xu
  • Patent number: 10439049
    Abstract: A nanosheet transistor device having reduced access resistance is fabricated by recessing channel nanosheets and replacing the channel material with epitaxially grown doped extension regions. Sacrificial semiconductor layers between the channel nanosheets are selectively removed without damaging source/drain regions epitaxially grown on the extension regions. The sacrificial semiconductor layers are replaced by gate dielectric and gate metal layers.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: October 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10403711
    Abstract: In one embodiment, a method of manufacturing a silicon-carbide (SiC) device includes receiving a selection of a specific terrestrial cosmic ray (TCR) rating at a specific applied voltage, determining a breakdown voltage for the SiC device based at least on the specific TCR rating at the specific applied voltage, determining drift layer design parameters based at least on the breakdown voltage. The drift layer design parameters include doping concentration and thickness of the drift layer. The method also includes fabricating the SiC device having a drift layer with the determined drift layer design parameters. The SiC device has the specific TCR rating at the specific applied voltage.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: September 3, 2019
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Alexander Viktorovich Bolotnikov, Ljubisa Dragoljub Stevanovic, Peter Almern Losee
  • Patent number: 10388649
    Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, wherein the semiconductor substrate includes a first region and a second region. The semiconductor device also includes a buried layer disposed in the first region of the semiconductor substrate and having the first conductivity type, wherein the buried layer has a dopant concentration that is greater than that of the semiconductor substrate. The semiconductor device further includes an epitaxial layer disposed on the semiconductor substrate, and a first element disposed on the first region of the semiconductor substrate, wherein the first element includes a bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) (BCD) transistor. In addition, the semiconductor device includes a second element disposed on the second region of the semiconductor substrate, wherein the second element includes an ultra-high voltage (UHV) transistor.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: August 20, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chien-Wei Chiu, Shin-Cheng Lin, Yu-Hao Ho
  • Patent number: 10381482
    Abstract: A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: August 13, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Yu Chen, Chi-Yuan Shih, Chi-Wen Liu
  • Patent number: 10366993
    Abstract: A semiconductor structure includes a semiconductor substrate having a trench isolation region formed therein. A conductive gate electrode is buried in the trench isolation region. An air gap is disposed between the conductive gate electrode and the semiconductor substrate.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: July 30, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee
  • Patent number: 10354941
    Abstract: A heat sink capable of dissipating heat concentrating on a chip portion of a power semiconductor device module efficiently is provided. A heat sink (20) includes a heat sink body (21) in which a power semiconductor device module (10) having a plurality of power semiconductor devices (11) is placed on a cooling surface F1 and which radiates heat generated by the power semiconductor device (11); and a heat dissipation structure portion (25) having a higher heat conductivity than the heat sink body (21) and capable of dissipating heat generated by the power semiconductor device (11), wherein the heat dissipation structure portion (25) is provided at a position overlapping the power semiconductor device (11) disposed in the power semiconductor device module (10) in a direction (Z) orthogonal to the cooling surface (F1) of the heat sink body (21).
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: July 16, 2019
    Assignee: FANUC CORPORATION
    Inventors: Masato Watanabe, Taku Sasaki
  • Patent number: 10347671
    Abstract: An image sensor includes a plurality of unit pixels formed as a semiconductor chip, each of which has a photoelectric converting unit, a charge holding unit that holds charges stored in the photoelectric converting unit, a charge-voltage converting unit that converts a charge transferred from the charge holding unit to a voltage, and light shielding films between which an opening is formed above the photoelectric converting unit. The plurality of unit pixels are placed in a matrix in a pixel array. The shapes of the light shielding films are varied depending on the position of the unit pixel in the pixel array.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: July 9, 2019
    Assignee: Sony Semiconductor Solution Corporation
    Inventor: Tomohiro Ohkubo
  • Patent number: 10325913
    Abstract: Generally, in one embodiment, the present disclosure is directed to a method for forming a transistor. The method includes: implanting a substrate to form at least one of an n and p doped region; depositing an epitaxial semiconductor layer over the substrate; forming trenches through the epitaxial layer and partially through at least one of an n and p doped region; forming dielectric isolation regions in the trenches; forming a fin in an upper portion of the epitaxial semiconductor layer by partially recessing the dielectric isolation regions; forming a gate dielectric adjacent at least two surfaces of the fin; and diffusing dopant from at least one of the n and p doped regions at least partially into the epitaxial semiconductor layer to form a diffusion doped transition region adjacent a bottom portion of the fin.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: June 18, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: David Paul Brunco, Jeffrey Bowman Johnson
  • Patent number: 10312345
    Abstract: The present disclosure provides a method for manufacturing a transistor having a gate with a variable work function, comprising: providing a semiconductor substrate; forming a dummy gate stack on the semiconductor substrate and performing ion implantation on an exposed area of the semiconductor substrate at both sides of the dummy gate stack to form source/drain regions; removing the dummy gate and annealing the source/drain regions; providing an atomic layer deposition reaction device; introducing a precursor source reactant into the atomic layer deposition reaction device; and controlling an environmental factor for the atomic layer deposition device to grow a work function metal layer. The present disclosure also provides a transistor having a gate with a variable work function. The present disclosure may adjust a variable work function, and may use the same material system to obtain an adjustable threshold voltage within an adjustable range.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: June 4, 2019
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Jinjuan Xiang, Xiaolei Wang, Hong Yang, Shi Liu, Junfeng Li, Wenwu Wang, Chao Zhao
  • Patent number: 10312332
    Abstract: A semiconductor device is provided, which includes a substrate, a gate and a gate contact. The substrate has a well region, which has a source, a drain and a channel region extending between the source and the drain. The gate is on the well region and extends across the channel region. The gate contact is directly on the gate and vertically overlaps with the channel region. The gate contact has a strip shape of which a ratio of a length to a width is at least 2. The gate contact includes a gate conductive plug and a gate contact dielectric. The gate conductive plug directly contacts the gate. The gate contact dielectric surrounds side surfaces of the gate conductive plug and has a frame shape. A dielectric constant of the gate contact dielectric is substantially greater than 4.9.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10276580
    Abstract: Systems and methods are provided for forming an intra-connection structure. A first gate structure and a first source/drain region adjacent to the first gate structure is formed on a substrate. A first dielectric material is disposed on the first source/drain region. A spacer material is formed on the first gate structure. The first dielectric material is removed to expose at least part of the first source/drain region. At least part of the spacer material is removed to expose at least part of the first gate structure. A first conductive material is formed between the first gate structure and the first source/drain region to electrically connect the first source/drain region and the first gate structure.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Feng-Ming Chang, Kuo-Hsiu Hsu
  • Patent number: 10269982
    Abstract: In a method for manufacturing a metallic-channel device, a metallic layer is formed on a substrate. The metallic layer is formed by an atomic layer deposition technique and has a first thickness. An insulating layer is formed over the metallic layer. A gate contact layer is formed over the insulating layer. The formed layers are processed to remove the gate contact layer, the insulating layer, and a portion of the metallic layer from a source-drain region. A remaining portion of the metallic layer on the source-drain region has a second thickness that is smaller than the first thickness. Source and drain metal contacts are formed over the remaining portion of the metallic layer.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: April 23, 2019
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Miin-Jang Chen, Chi-Wen Liu, Po-Hsien Cheng
  • Patent number: 10269428
    Abstract: Provided are a method for fabricating nano structures which includes: preparing a substrate; preparing a polymer including a plurality of metal atoms; applying the polymer to the substrate to attach the metal atoms onto the substrate; and making one or more metallic nano particles from the metal atoms.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: April 23, 2019
    Assignee: SK INNOVATION CO., LTD.
    Inventor: Jun-Hyung Kim
  • Patent number: 10267763
    Abstract: An improved sensing method is provided for rapid analyte detection. The method includes: applying an AC excitation signal to the channel region of the transistor; applying an AC drive signal to the transistor; delivering an analyte of interest to a channel region of a transistor; and monitoring a mixing current of the excitation signal and the drive signal through the transistor, where a change in the mixing current is indicative of the concentration of the analyte of interest.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: April 23, 2019
    Assignee: The Regents of The University of Michigan
    Inventors: Zhaohui Zhong, Girish Kulkarni, Karthik Reddy, Xudong Fan
  • Patent number: 10263112
    Abstract: Vertical non-planar semiconductor devices for system-on-chip (SoC) applications and methods of fabricating vertical non-planar semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate, the semiconductor fin having a recessed portion and an uppermost portion. A source region is disposed in the recessed portion of the semiconductor fin. A drain region is disposed in the uppermost portion of the semiconductor fin. A gate electrode is disposed over the uppermost portion of the semiconductor fin, between the source and drain regions.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: April 16, 2019
    Assignee: Intel Corporation
    Inventors: Chia-Hong Jan, Walid M. Hafez, Curtis Tsai, Jeng-Ya D. Yeh, Joodong Park
  • Patent number: 10249633
    Abstract: An integrated circuit product includes a silicon-on-insulator (SOI) substrate and a flash memory device positioned in a first area of the SOI substrate. The SOI substrate includes a semiconductor bulk substrate, a buried insulating layer positioned above the semiconductor bulk substrate, and a semiconductor layer positioned above the buried insulating layer, and the flash memory device includes a flash transistor device and a read transistor device. The flash transistor device includes a floating gate, an insulating layer positioned above the floating gate, and a control gate positioned above the insulating layer, wherein the floating gate includes a portion of the semiconductor layer. The read transistor device includes a gate dielectric layer positioned above the semiconductor bulk substrate and a read gate electrode positioned above the gate dielectric layer.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: April 2, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ralf Richter, Sven Beyer, Jan Paul
  • Patent number: 10243143
    Abstract: A method of making a carbon nanotube structure includes depositing a first oxide layer on a substrate and a second oxide layer on the first oxide layer; etching a trench through the second oxide layer; removing end portions of the first oxide layer and portions of the substrate beneath the end portions to form cavities in the substrate; depositing a metal in the cavities to form first body metal pads; disposing a carbon nanotube on the first body metal pads and the first oxide layer such that ends of the carbon nanotube contact each of the first body metal layers; depositing a metal to form second body metal pads on the first body metal pads at the ends of the carbon nanotube; and etching to release the carbon nanotube, first body metal pads, and second body metal pads from the substrate, first oxide layer, and second oxide layer.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin M. Frank, Shu-Jen Han, George S. Tulevski
  • Patent number: 10242933
    Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Griselda Bonilla, Elbert Huang, Son Nguyen, Takeshi Nogami, Christopher J. Penny, Deepika Priyadarshini
  • Patent number: 10205026
    Abstract: A thin film transistor includes a substrate, and, a source electrode, a drain electrode, a gate, a gate insulation layer and an active layer disposed on the substrate; the gate insulation layer is located between the gate and the active layer, and the source electrode and the drain electrode are connected to the active layer, respectively; and the gate is a composite metal layer including at least one first metal layer which contains doped ions therein and which is close to the gate insulation layer, and at least one second metal layer which is apart from the gate insulation layer and is not doped with ions.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: February 12, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Hui Tian
  • Patent number: 10199382
    Abstract: A method for fabricating a semiconductor device includes forming a gate dielectric layer on a base substrate including an N-type logic region, a P-type logic region, a first pull down transistor (PDT) region, a second PDT region, and a pass gate transistor (PGT) region, forming a first work function layer (WFL) in the first N-type threshold-voltage (TV) region, the P-type logic region, the second PDT region, and the PGT region, forming a second WFL on the first WFL in the first P-type TV region, and forming a third WFL on the second WFL in the first P-type TV region, the first WFL in the second P-type TV region, and the gate dielectric layer in the second N-type TV region and the first PDT region. The thickness of the third WFL is smaller than the thickness of the first WFL. The method further includes forming a fourth WFL on the substrate.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: February 5, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Yong Li
  • Patent number: 10186601
    Abstract: A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer; and a second step following the first step and including forming a second insulating film around the fin-shaped semiconductor layer, depositing a first polysilicon on the second insulating film to conduct planarization, forming a second resist for forming a gate line and a pillar-shaped semiconductor layer so that the second resist extends in a direction perpendicular to a direction in which the fin-shaped semiconductor layer extends, and etching the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form a pillar-shaped semiconductor layer and a first dummy gate formed of the first polysilicon.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: January 22, 2019
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 10177076
    Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: January 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Griselda Bonilla, Elbert Huang, Son Nguyen, Takeshi Nogami, Christopher J. Penny, Deepika Priyadarshini
  • Patent number: 10170498
    Abstract: A method for constructing an advanced FinFET structure is described. A first long silicon fin for n-type FinFET devices and a first long silicon germanium fin for p-type FinFET devices are provided on a strain relaxation buffer (SRB) substrate. The first long silicon fin is cut forming a first and a second cut silicon fin so that the first and second cut silicon fin have a vertical face at a fin end. The first long silicon germanium fin is cut forming a first and a second cut silicon germanium fin, the first and the second cut silicon germanium cut fin have a vertical face at a fin end. A tensile dielectric structure is formed which contacts the vertical faces of the first and second cut silicon fins to maintain tensile strain in the first and second cut silicon fins. A compressive dielectric structure is formed which contacts the vertical faces of the silicon germanium fins to maintain compressive strain in the first and second cut silicon germanium fins.
    Type: Grant
    Filed: October 22, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Balasubramanian Pranatharthiharan, Juntao Li
  • Patent number: 10163947
    Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method is performed by forming a gate dielectric layer over a substrate, and selectively forming a gate material over the gate dielectric layer. A gate dielectric protection layer is formed over the gate dielectric layer, and a first sidewall spacer is formed over the gate dielectric protection layer and flanking a side of the gate material. The gate dielectric protection layer continuously extends from between the first sidewall spacer and the gate dielectric layer to outside of the first sidewall spacer.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hsien Chou, Wen-I Hsu, Tsun-Kai Tsao, Chih-Yu Lai, Jiech-Fun Lu, Yeur-Luen Tu
  • Patent number: 10141338
    Abstract: A FinFET device includes a strain relaxation buffer (SRB) substrate. A set of cut silicon fins is on the SRB substrate. Each fin in the set of cut silicon fins has a pair of long vertical faces and a pair of short vertical faces. Pairs of the cut silicon fins are oriented so that respective short vertical faces of the pair are oriented opposite to each other. A set of cut silicon germanium fins is on the SRB substrate. Each fin in the set of silicon germanium fins has a pair of long vertical faces and a pair of short vertical faces. Pairs of the cut silicon germanium fins are oriented so that respective short vertical faces of the pair are oriented opposite to each other. A set of tensile dielectric structures bridge between the short vertical faces of respective pairs of the cut silicon fins to maintain tensile strain at the fin ends of the pair of cut silicon fins.
    Type: Grant
    Filed: October 22, 2017
    Date of Patent: November 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Balasubramanian Pranatharthiharan, Juntao Li
  • Patent number: 10134865
    Abstract: A method and structure for providing a GAA device. In some embodiments, a substrate including an insulating layer disposed thereon is provided. By way of example, a first metal portion is formed within the insulating layer. In various embodiments, a first lateral surface of the first metal portion is exposed. After exposure of the first lateral surface of the first metal portion, a first graphene layer is formed on the exposed first lateral surface. In some embodiments, the first graphene layer defines a first vertical plane parallel to the exposed first lateral surface. Thereafter, in some embodiments, a first nanobar is formed on the first graphene layer, where the first nanobar extends in a first direction normal to the first vertical plane defined by the first graphene layer.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Wei Yang, Chi-Wen Liu, Hao-Hsiung Lin, Ling-Yen Yeh
  • Patent number: 10115596
    Abstract: A method of fabricating a metal gate structure in a semiconductor device is disclosed. The method comprises removing a dummy poly gate, removing IL oxide and STI using a dry etch process and a wet lateral etch process to form a T-shape void in the semiconductor device, and depositing metal gate material in the T-shape void to form a T-shape structure in a metal gate line-end. A semiconductor device fabricated from a process that included the removal of a dummy poly gate is disclosed. The semiconductor device comprises an OD fin and a metal gate fabricated above a section of the OD fin and adjacent to a side section of the OD fin. The metal gate has a T-shape structure in a metal gate line-end. The T-shape structure was formed by removing IL oxide and STI using a dry and a wet lateral etch process to form a T-shape void.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Chih Lin, Chien-Hung Yeh, Guan-Jie Shen, Chia-Der Chang
  • Patent number: 10074607
    Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and an interconnect structure formed over the substrate. The interconnect structure includes a first dielectric layer formed over the substrate, and a first graphene layer formed in and on the first dielectric layer. The first graphene layer includes a first portion in the first dielectric layer and a second portion on the first dielectric layer and a first insulating layer formed over the first portion of the first graphene layer.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: September 11, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-I Yang, Tien-I Bao, Tien-Lu Lin, Wei-Chen Chu
  • Patent number: 10056459
    Abstract: A semiconductor arrangement comprising a substrate having a first trench formed therein, a field plate layer arranged to extend within the first trench and coat the first trench, the field plate layer having a thickness such that it defines a second trench within the first trench, a barrier layer arranged to coat an internal surface of the second trench; and a trench fill material configured to substantially planarize the first and second trenches.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: August 21, 2018
    Assignee: Nexperia B.V.
    Inventors: Thomas Igel-Holtzendorff, Reza Behtash, Tim Boettcher
  • Patent number: 10049885
    Abstract: A method for patterning fins for FinFET devices are disclosed. The method includes forming elongated protrusions on a semiconductor substrate and forming a mask covering a first portion of the elongated protrusions. The method further includes forming a spacer surrounding the mask. The mask and the spacer together cover a second portion of the elongated protrusions. The method further includes removing a portion of the elongated protrusions not covered by the mask and the spacer. In an embodiment, an outer boundary of the spacer and the mask corresponds to an outer boundary of a non-rectangular pattern.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: August 14, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hoi-Tou Ng, Kuei-Liang Lu, Ming-Feng Shieh, Ru-Gun Liu
  • Patent number: 10050025
    Abstract: A power converter (100) comprising a semiconductor chip (101) with a first (101a) and a parallel second (101b) surface, and through-silicon vias (TSVs, 110). The chip embedding a high-side (HS) field-effect transistor (FET) interconnected with a low side (LS) FET. Surface (101a) includes first metallic pads (111) as inlets of the TSVs, and an attachment site for an integrated circuit (IC) chip (150). Surface (101b) includes second metallic pads (115) as outlets of the TSVs, and third metallic pads as terminals of the converter: Pad (123a) as HS FET inlet, pad (122a) as HS FET gate, pad (131a) as LS FET outlet, pad (132a) as LS FET gate, and gate (140a) as common HS FET and LS FET switch-node. Driver-and-controller IC chip 150) has the IC terminals connected to respective first pads.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: August 14, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jonathan Almeria Noquil, Osvaldo Jorge Lopez, Haian Lin