Abstract: Disclosed herein are tunneling field effect transistors (TFETs), and related methods and computing devices. In some embodiments, a TFET may include: a first source/drain material having a p-type conductivity; a second source/drain material having an n-type conductivity; a channel material at least partially between the first source/drain material and the second source/drain material, wherein the channel material has a first side face and a second side face opposite the first side face; and a gate above the channel material, on the first side face, and on the second side face.

Abstract: A semiconductor body is disclosed. In an embodiment a semiconductor body includes an n-doped region comprising a first layer sequence comprising pairs of alternating layers, wherein a first layer and a second layer of each pair differ in their doping concentration, and wherein the first and second layers of each pair have the same material composition except for their doping and a second layer sequence comprising pairs of alternating layers, wherein a first layer and a second layer of each pair differ in their material composition, an active region, wherein the second layer sequence is disposed between the first layer sequence and the active region and a p-doped region, wherein the active region is disposed between the n-doped region and the p-doped region.

Abstract: A photo detector includes a superlattice with an undoped first semiconductor layer including undoped intrinsic semiconductor material, a doped second semiconductor layer having a first conductivity type on the first semiconductor layer, an undoped third semiconductor layer including undoped intrinsic semiconductor material on the second semiconductor layer, and a fourth semiconductor layer having a second opposite conductivity type on the third semiconductor layer, along with a first contact having the first conductivity type in the first, second, third, and fourth semiconductor layers, and a second contact having the second conductivity type and spaced apart from the first contact in the first, second, third, and fourth semiconductor layers. An optical shield on a second shielded portion of a top surface of the fourth semiconductor layer establishes electron and hole lakes.

Abstract: A laser diode having a surface region configured on either a non-polar or semi-polar orientation. The laser diode also has N waveguide structures each overlying a different portion of the surface region. Each of the N waveguide structures is coupled to at least one immediately adjacent one of the N waveguide structures and extends in a different direction than immediately adjacent ones of the N waveguide structures.

Abstract: A plasmonic light source includes a substrate and a square nano-cavity formed on the substrate. The nano-cavity includes a quantum well structure. The quantum well structure includes III-V materials. A plasmonic metal is formed as an electrode on the square nano-cavity and is configured to excite surface plasmons with the quantum well structure to generate light. Complementary metal oxide semiconductor (CMOS) devices are formed on the substrate.

Abstract: In some embodiments, a first product is provided. The first product may include a substrate, a device having a device footprint disposed over the substrate, and a barrier film disposed over the substrate and substantially along a side of the device footprint. The barrier film may comprise a mixture of a polymeric material and non-polymeric material. The barrier film may have a perpendicular length that is less than or equal to 3.0 mm from the side of the device footprint.

Abstract: According to one embodiment, a semiconductor device is disclosed. The device includes a graphene layer containing impurities, and including a first region and a second region. The second region has a resistance higher than a resistance of the first region. The second region includes a side surface of an end of the graphene layer. The device further includes a first plug being in contact with the first region.

Abstract: A displaying apparatus includes a flexible substrate, at least one composite layer disposed on the flexible substrate, and an electronic device disposed on the composite layer. The composite layer includes a stack of an organic layer and an inorganic layer, and at least one of the inorganic layer and the organic layer includes at least one anti-static material, such as anti-static particles, an anti-static agent or an anti-static layer (e.g., transparent conductive layer/transparent conductive oxide layer, or polymeric conductive layer). The displaying apparatus of the embodiment enables the electronic device, such as the flexible electronic device, to achieve the product requirements, such as the flexibility, good resistance to water and vapor, and the ability of releasing the electrostatic charges and making the overall structure to release stresses.

Abstract: A plasmonic light source includes a substrate and a square nano-cavity formed on the substrate. The nano-cavity includes a quantum well structure. The quantum well structure includes III-V materials. A plasmonic metal is formed as an electrode on the square nano-cavity and is configured to excite surface plasmons with the quantum well structure to generate light. Complementary metal oxide semiconductor (CMOS) devices are formed on the substrate.

Abstract: A tunnel effect transistor includes a channel made of an intrinsic semiconductor material; source and drain extension regions on either side of the channel, the source extension region being made of a semiconductor material doped according to a first type of doping P or N and the drain extension region being made of a semiconductor material doped according to a second type of doping opposite to said first type of doping; source and drain conductive regions respectively in contact with the source and drain extension regions; a gate structure including a gate dielectric layer in contact with the channel and a gate area arranged such that the gate dielectric layer is arranged between the gate area and the channel; and an area doped according to the first type of doping inserted between the channel and the drain extension region.

Abstract: A field effect transistor includes a substrate, a first graphene (Gr) layer on the substrate, a second graphene (Gr) layer on the substrate, a fluorographene (GrF) layer on the substrate and between the first and second graphene layers, a first ohmic contact on the first graphene layer, a second ohmic contact on the second graphene layer, a gate aligned over the fluorographene layer, and a gate dielectric between the gate and the fluorographene layer and between the gate and the first and second ohmic contacts.

Abstract: Transistors, and methods of manufacturing the transistors, include graphene and a material converted from graphene. The transistor may include a channel layer including graphene and a gate insulating layer including a material converted from graphene. The material converted from the graphene may be fluorinated graphene. The channel layer may include a patterned graphene region. The patterned graphene region may be defined by a region converted from graphene. A gate of the transistor may include graphene.

Abstract: Solid-state transducers (“SSTs”) and vertical high voltage SSTs having buried contacts are disclosed herein. An SST die in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the transducer structure, and a second semiconductor material at a second side of the transducer structure. The SST can further include a plurality of first contacts at the first side and electrically coupled to the first semiconductor material, and a plurality of second contacts extending from the first side to the second semiconductor material and electrically coupled to the second semiconductor material. An interconnect can be formed between at least one first contact and one second contact. The interconnects can be covered with a plurality of package materials.

Abstract: A technique is provided for performing sequencing with a nanodevice. Alternating graphene layers and dielectric layers are provided one on top of another to form a multilayer stack of heterojunctions. The dielectric layers include boron nitride, molybdenum disulfide, and/or hafnium disulfide layers. A nanopore is formed through the graphene layers and the dielectric layers. The graphene layers are individually addressed by applying individual voltages to each of the graphene layers on a one to one basis when a particular base of a molecule is in the nanopore. Each of the graphene layers is an electrode. Individual electrical currents are measured for each of the graphene layers as the particular base moves from a first graphene layer through a last graphene layer in the nanopore. The base is identified according to the individual electrical currents repeatedly measured for the base moving from the first through last graphene layer in the nanopore.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate including semiconductor elements formed thereon, a graphene wiring structure stuck on the substrate with a connection insulating film disposed therebetween and including graphene wires, and through vias each formed through the graphene wiring structure and connection insulating film to connect part of the semiconductor elements to the graphene wires.

Abstract: The invention relates inter alia to an arrangement comprising a carrier (10), a layer and a material (20) enclosed between the carrier and the layer. According to the invention, it is provided that the layer is formed by a single two-dimensionally crosslinked layer (40) or by a plurality of two-dimensionally crosslinked layers which are indirectly or directly connected to one another.

Abstract: The application discloses a technique for fabricating gallium-arsenide-phosphorous (GaAsP) nanostructures using gallium-assisted (Ga-assisted) Vapour-Liquid-Solid (VLS) growth, i.e. without requiring gold catalyst particles. The resulting Ga-assisted GaAsP nanostructures are free of gold particles, which renders them useful for optoelectronic applications, e.g. as a junction in a solar cell. The Ga-assisted GaAsP nanostructures can be fabricated with a band gap in the range 1.6 to 1.8 eV (e.g. at and around 1.7 eV).

Abstract: A simple method that makes it possible to manufacture a highly-workable organic solar cell module having a plurality of connected organic solar cells is provided. The method includes: a first electrode substrate forming step of forming a plurality of first electrode layers on a first substrate to form a first electrode substrate; preparing a single piece of second electrode substrate-forming base material having at least a second electrode layer and capable of being cut into a plurality of second electrode substrates; a functional layer forming step; a cutting step to form a plurality of second electrode substrates; a bonding step so that the first and second electrode substrates are bonded together; and a connecting step of electrically connecting the first electrode layer of one of the organic solar cells to the second electrode layer of another organic solar cell which is adjacent to the one organic solar cell.

Abstract: A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.

Abstract: A semiconductor device includes a channel region; a gate dielectric over the channel region; a gate electrode over the gate dielectric; and a first source/drain region adjacent the gate dielectric. The first source/drain region is of a first conductivity type. At least one of the channel region and the first source/drain region includes a superlattice structure. The semiconductor device further includes a second source/drain region on an opposite side of the channel region than the first source/drain region. The second source/drain region is of a second conductivity type opposite the first conductivity type. At most, one of the first source/drain region and the second source/drain region comprises an additional superlattice structure.

Abstract: A light emitting diode and a method of fabricating a light emitting diode, the diode has a first set of multiple quantum wells (MQWs), each of the MQWs of the first set comprising a wetting layer providing nucleation sites for quantum dots (QDs) or QD-like structures in a well layer of said each MQW; and a second set of MQWs, each of the MQWs of the second set formed so as to exhibit a photoluminescence (PL) peak wavelength shifted compared to the MQWs of the first set.

Abstract: A method for manufacturing a plurality of holders each being for an LED package structure includes steps: providing a base, pluralities of through holes being defined in the base to divide the base into a plurality of basic units; etching the base to form a dam at an upper surface of each of the basic units of the base; forming a first electrical portion and a second electrical portion on each basic unit of the base, the first electrical portion and the second electrical portion being separated and insulated from each other by the dam; providing a plurality of reflective cups each on a corresponding basic unit of the base, each of the reflective cups surrounding the corresponding dam; and cutting the base into the plurality of basic units along the through holes to form the plurality of holders.

Abstract: Solid-state transducers (“SSTs”) and SST arrays having backside contacts are disclosed herein. An SST in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the transducer structure, and a second semiconductor material at a second side of the transducer structure. The SST can further include a first contact at the first side and electrically coupled to the first semiconductor material, and a second contact extending from the first side to the second semiconductor material and electrically coupled to the second semiconductor material. A carrier substrate having conductive material can be bonded to the first and second contacts.

Abstract: Non-planar semiconductor devices are provided that include at least one semiconductor nanowire suspended above a semiconductor oxide layer that is present on a first portion of a bulk semiconductor substrate. An end segment of the at least one semiconductor nanowire is attached to a first semiconductor pad region and another end segment of the at least one semiconductor nanowire is attached to a second semiconductor pad region. The first and second pad regions are located above and are in direct contact with a second portion of the bulk semiconductor substrate which is vertically offsets from the first portion. The structure further includes a gate surrounding a central portion of the at least one semiconductor nanowire, a source region located on a first side of the gate, and a drain region located on a second side of the gate which is opposite the first side of the gate.

Abstract: The invention relates to a micromechanical device comprising a semiconductor element capable of deflecting or resonating and comprising at least two regions having different material properties and drive or sense means functionally coupled to said semiconductor element. According to the invention, at least one of said regions comprises one or more n-type doping agents, and the relative volumes, doping concentrations, doping agents and/or crystal orientations of the regions being configured so that the temperature sensitivities of the generalized stiffness are opposite in sign at least at one temperature for the regions, and the overall temperature drift of the generalized stiffness of the semiconductor element is 50 ppm or less on a temperature range of 100° C. The device can be a resonator. Also a method of designing the device is disclosed.

Abstract: A non-planar semiconductor device is provided including at least one semiconductor nanowire suspended above a semiconductor oxide layer present within a portion of a bulk semiconductor substrate. The semiconductor oxide layer has a topmost surface that is coplanar with a topmost surface of the bulk semiconductor substrate. A gate surrounds a portion of the at least one suspended semiconductor nanowire, a source region located on a first side of the gate, and a drain region located on a second side of the gate. The source region is in direct contact with an exposed end portion of the at least one suspended semiconductor nanowire, and the drain region is in direct contact with another exposed end portion of the at least one suspended semiconductor nanowire. The source and drain regions have an epitaxial relationship with the exposed end portions of the suspended semiconductor nanowire.

Abstract: Structure including nano-ribbons and method thereof. The structure include multiple nano-ribbons. Each of the multiple nano-ribbons corresponds to a first end and a second end, and the first end and the second end are separated by a first distance of at least 100 ?m. Each of the multiple nano-ribbons corresponds to a cross-sectional area associated with a ribbon thickness, and the ribbon thickness ranges from 5 nm to 500 nm. Each of the multiple nano-ribbons is separated from at least another nano-ribbon selected from the multiple nano-ribbons by a second distance ranging from 5 nm to 500 nm.

Abstract: An electrical device comprising (A) a substrate having a surface and (B) a nanohole superlattice superimposed on a portion of the surface is provided. The nanohole superlattice comprises a plurality of sheets having an array of holes defined therein. The array of holes is characterized by a band gap or band gap range. The plurality of sheets forms a first edge and a second edge. A first lead comprising a first electrically conductive material forms a first junction with the first edge. A second lead comprising a second electrically conductive material forms a second junction with the second edge. The first junction is a Schottky barrier with respect to a carrier. In some instances a metal protective coating covers all or a portion of a surface of the first lead. In some instances, the first lead comprises titanium, the second lead comprises palladium, and the metal protective coating comprises gold.

Abstract: A light emitting diode structure and a method of forming a light emitting diode structure are provided. The structure includes a superlattice comprising, a first barrier layer; a first quantum well layer comprising a first metal-nitride based material formed on the first barrier layer; a second barrier layer formed on the first quantum well layer; and a second quantum well layer including the first metal-nitride based material formed on the second barrier layer; and wherein a difference between conduction band energy of the first quantum well layer and conduction band energy of the second quantum well layer is matched to a single or multiple longitudinal optical phonon energy for reducing electron kinetic energy in the superlattice.

Abstract: The present disclosure provides a semiconductor structure including a nanoribbon-containing layer of alternating graphene nanoribbons separated by alternating insulating ribbons. The alternating graphene nanoribbons are parallel to a surface of an underlying substrate and, in some embodiments, might be oriented along crystallographic directions of the substrate. The alternating insulating ribbons may comprise hydrogenated graphene, i.e., graphane, fluorinated graphene, or fluorographene. The semiconductor structure mentioned above can be formed by selectively converting portions of an initial graphene layer into alternating insulating ribbons, while the non-converted portions of the initial graphene form the alternating graphene nanoribbons. Semiconductor devices such as, for example, field effect transistors, can be formed atop the semiconductor structure provided in the present disclosure.

Abstract: A structure and method for producing same provides a solid-state light emitting device with suppressed lattice defects in epitaxially formed nitride layers over a non-c-plane oriented (e.g., semi-polar) template or substrate. A dielectric layer with “window” openings or trenches provides significant suppression of all diagonally running defects during growth. Posts of appropriate height and spacing may further provide suppression of vertically running defects. A layer including gallium nitride is formed over the dielectric layer, and polished to provide a planar growth surface with desired roughness. A tri-layer indium gallium nitride active region is employed. For laser diode embodiments, a relatively thick aluminum gallium nitride cladding layer is provided over the gallium nitride layer.

Abstract: A SiC semiconductor substrate is disclosed which includes a SiC single crystal substrate, a nitrogen (N)-doped n-type SiC epitaxial layer in which nitrogen (N) is doped and a phosphorus (P)-doped n-type SiC epitaxial layer in which phosphorus (P) is doped. The nitrogen (N)-doped n-type SiC epitaxial layer and the phosphorus (P)-doped n-type SiC epitaxial layer are laminated on the silicon carbide single crystal substrate sequentially. The nitrogen (N)-doped n-type SiC epitaxial layer and the phosphorus (P)-doped n-type SiC epitaxial layer are formed by using two or more different dopants, for example, nitrogen and phosphorus, at the time of epitaxial growth. Basal plane dislocations in a SiC device can be reduced.

Abstract: A semiconductor chip includes a semiconductor body with a semiconductor layer sequence. An active region intended for generating radiation is arranged between an n-conductive multilayer structure and a p-conductive semiconductor layer. A doping profile is formed in the n-conductive multilayer structure which includes at least one doping peak.

Abstract: A structure and method for producing same provides a solid-state light emitting device with suppressed lattice defects in epitaxially formed nitride layers over a non-c-plane oriented (e.g., semi-polar) template or substrate. A dielectric layer with “window” openings or trenches provides significant suppression of all diagonally running defects during growth. Posts of appropriate height and spacing may further provide suppression of vertically running defects. A layer including gallium nitride is formed over the dielectric layer, and polished to provide a planar growth surface with desired roughness. A tri-layer indium gallium nitride active region is employed. For laser diode embodiments, a relatively thick aluminum gallium nitride cladding layer is provided over the gallium nitride layer.

Abstract: A functional device and functional system are provided. A functional device is formed by coupling a first structure formed by local interaction and a second structure formed according to a predetermined global rule via a third structure having an anisotropic configuration.

Abstract: A light emitting chip includes a substrate, a reflective layer, a light emitting structure and a first electrode having a base formed between the reflective layer and the substrate. The light emitting structure includes a first semiconductor layer, an active layer and a second semiconductor layer. The first electrode further includes a connecting section extending upwardly from the base. An electrically insulating ion region is defined in the light emitting structure and extends from an upper surface of the base to the first semiconductor layer. A receiving groove is defined in the ion region and extends upwardly from the upper surface of the base to the first semiconductor layer. The connecting section is positioned in the receiving groove and electrically connects with the first semiconductor layer.

Abstract: A structure and method for producing same provides a solid-state light emitting device with suppressed lattice defects in epitaxially formed nitride layers over a non-c-plane oriented (e.g., semi-polar) template or substrate. A dielectric layer with “window” openings or trenches provides significant suppression of all diagonally running defects during growth. Posts of appropriate height and spacing may further provide suppression of vertically running defects. A layer including gallium nitride is formed over the dielectric layer, and polished to provide a planar growth surface with desired roughness. A tri-layer indium gallium nitride active region is employed. For laser diode embodiments, a relatively thick aluminum gallium nitride cladding layer is provided over the gallium nitride layer.

Abstract: Silicon, silicon-germanium alloy, and germanium nanowire optoelectronic devices and methods for fabricating the same are provided. According to one embodiment, a P-I-N device is provided that includes a parallel array of intrinsic silicon, silicon-germanium or germanium nanowires located between a p+ contact and an n+ contact. In certain embodiments, the intrinsic silicon and germanium nanowires can be fabricated with diameters of less than 4.9 nm and 19 nm, respectively. In a further embodiment, vertically stacked silicon, silicon-germanium and germanium nanowires can be formed.

Abstract: A thin film transistor includes a first insulating layer covering the gate electrode layer; source and drain regions which at least partly overlaps with the gate electrode layer; a pair of second insulating layers which is provided apart from each other in a channel length direction over the first insulating layer and which at least partly overlaps with the gate electrode layer and the pair of impurity semiconductor layers; a pair of microcrystalline semiconductor layers provided apart from each other on and in contact with the second insulating layers; and an amorphous semiconductor layer covering the first insulating layer, the pair of second insulating layers, and the pair of microcrystalline semiconductor layers and which extends to exist between the pair of microcrystalline semiconductor layers. The first insulating layer is a silicon nitride layer and each of the pair of the second insulating layers is a silicon oxynitride layer.

Abstract: A superlattice-based infrared absorber and the matching electron-blocking and hole-blocking unipolar barriers, absorbers and barriers with graded band gaps, high-performance infrared detectors, and methods of manufacturing such devices are provided herein. The infrared absorber material is made from a superlattice (periodic structure) where each period consists of two or more layers of InAs, InSb, InSbAs, or InGaAs. The layer widths and alloy compositions are chosen to yield the desired energy band gap, absorption strength, and strain balance for the particular application. Furthermore, the periodicity of the superlattice can be “chirped” (varied) to create a material with a graded or varying energy band gap.

Abstract: The present disclosure provides a semiconductor structure including a nanoribbon-containing layer of alternating graphene nanoribbons separated by alternating insulating ribbons. The alternating graphene nanoribbons are parallel to a surface of an underlying substrate and, in some embodiments, might be oriented along crystallographic directions of the substrate. The alternating insulating ribbons may comprise hydrogenated graphene, i.e., graphane, fluorinated graphene, or fluorographene. The semiconductor structure mentioned above can be formed by selectively converting portions of an initial graphene layer into alternating insulating ribbons, while the non-converted portions of the initial graphene form the alternating graphene nanoribbons. Semiconductor devices such as, for example, field effect transistors, can be formed atop the semiconductor structure provided in the present disclosure.

Abstract: A homo-material heterophased quantum well includes a first structural layer, a second structural layer and a third structural layer. The second structural layer is sandwiched between the first and third structural layers. The first structural layer, second structural layer and third structural layer are formed by growing atoms of a single material in a single growth direction. The energy gap of the second structural layer is smaller than that of the first and third structural layers.

Abstract: According to embodiments of the present invention, a light emitting device is provided. The light emitting device includes: an active region comprising at least one p-i-n junction, the at least one p-i-n junction comprising a p-doped region, an intrinsic region and an n-doped region; a first contact; and a second contact, wherein the active region is disposed between the first contact and the second contact; and wherein a voltage applied to the first contact and the second contact produces a current configured to flow between the first contact and the second contact in a direction substantially parallel to a surface of the intrinsic region of the active region configured to emit a light. According to embodiments of the present invention, the intrinsic region includes a multiple quantum well (MQW) such that a current injected flows laterally in a direction substantially parallel to the surface of the wells of the MQW.

Abstract: Isolation of III-nitride devices may be performed with a dopant selective etch that provides a smooth profile with little crystal damage in comparison to previously used isolation techniques. The dopant selective etch may be an electro-chemical or photo-electro-chemical etch. The desired isolation area may be identified by changing the conductivity type of the semiconductor material to be etched. The etch process can remove a conductive layer to isolate a device atop the conductive layer. The etch process can be self stopping, where the process automatically terminates when the selectively doped semiconductor material is removed.

Abstract: Disclosed herein is a nitride-based semiconductor device. The nitride-based semiconductor device includes a base substrate having a PN junction structure, an epi-growth layer disposed on the base substrate, and an electrode unit disposed on the epi-growth layer.

Abstract: A structure and method for producing same provides a solid-state light emitting device with suppressed lattice defects in epitaxially formed nitride layers over a non-c-plane oriented (e.g., semi-polar) template or substrate. A dielectric layer with “window” openings or trenches provides significant suppression of all diagonally running defects during growth. Posts of appropriate height and spacing may further provide suppression of vertically running defects. A layer including gallium nitride is formed over the dielectric layer, and polished to provide a planar growth surface with desired roughness. A tri-layer indium gallium nitride active region is employed. For laser diode embodiments, a relatively thick aluminum gallium nitride cladding layer is provided over the gallium nitride layer.

Abstract: A method of producing silicon nanowires includes providing a substrate in the form of a doped material; formulating an etching solution; and applying an appropriate current density for an appropriate length of time. Related structures and devices composed at least in part from silicon nanowires are also described.

Abstract: A gallium nitride device substrate comprises a layer of gallium nitride containing an additional lattice parameter altering element located over a substitute substrate.

Abstract: A nanocrystalline superlattice solar cell utilizing a superlattice constructed from alternating amorphous and nanocrystalline layers is provided. The amorphous layers of the superlattice include Germanium. In one embodiment the Germanium content is homogeneous across the amorphous layer. Alternatively, the Germanium content is graded across the amorphous layer from a lower content to a greater content as the amorphous layer is grown. The grading of Germanium content can vary from 0% or greater at a boundary with the preceding layer to 100% or less at a boundary with a subsequent layer. The grading may be continuous or may occur in discreet step increases in Germanium content.

Abstract: A semiconductor device may include a substrate and at least one MOSFET adjacent the substrate. The MOSFET may include a superlattice channel including a plurality of stacked groups of layers, a source and a drain adjacent the superlattice channel, and a gate adjacent the superlattice channel. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A first dopant may be in at least one region adjacent at least one of the source and drain, and a second dopant may also be in the at least one region. The second dopant may be different than the first dopant and reduce diffusion thereof.