Thin Active Physical Layer Which Is (1) An Active Potential Well Layer Thin Enough To Establish Discrete Quantum Energy Levels Or (2) An Active Barrier Layer Thin Enough To Permit Quantum Mechanical Tunneling Or (3) An Active Layer Thin Enough To Permit Carrier Transmission With Substantially No Scattering (e.g., Superlattice Quantum Well, Or Ballistic Transport Device) Patents (Class 257/9)
  • Patent number: 11329055
    Abstract: Semiconductor cell and its forming method and operating method are provided. The semiconductor device includes: a substrate with a first region; a first nanopillar, formed on a substrate surface of the first region and perpendicular to the substrate surface; a first source/drain region, formed at a bottom of the first nanopillar and in a portion of the substrate in the first region; a first gate structure, surrounding the first nanopillar and formed on the first source/drain region; and a second source/drain region, formed at a top of the first nanopillar and on the first gate structure.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: May 10, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang
  • Patent number: 11329183
    Abstract: A photo detection element includes: a substrate; a light-receiving layer formed over the substrate, the light-receiving layer including graphene layers and spacer layers that are alternately stacked, light passing through each of the spacer layers, the spacer layers being made of insulating material; a first electrode that is in contact with the light-receiving layer; and a second electrode that is in contact with the light-receiving layer, a material of the second electrode being different from a material of the first electrode.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: May 10, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Shintaro Sato, Hironori Nishino, Daiyu Kondo, Kenjiro Hayashi
  • Patent number: 11316064
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and/or PIN diode structures and methods of manufacture. The structure includes: at least one fin including substrate material, the at least one fin including sidewalls and a top surface; a trench on opposing sides of the at least one fin; a first semiconductor material lining the sidewalls and the top surface of the at least one fin, and a bottom surface of the trench; a photosensitive semiconductor material on the first semiconductor material and at least partially filling the trench; and a third semiconductor material on the photosensitive semiconductor material.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: April 26, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Siva P. Adusumilli, John J. Ellis-Monaghan, Mark D. Levy, Vibhor Jain, Andre Sturm
  • Patent number: 11309432
    Abstract: There are provided a nanometer semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. According to an embodiment, the semiconductor device may include: a substrate; at least one nanowire spaced apart from the substrate; at least one semiconductor layer, each formed around a periphery of respective one of the at least one nanowire to at least partially surround the corresponding nanowire, wherein the semiconductor layer(s) formed around the respective nanowire(s) are separated from each other; an isolation layer formed on the substrate, exposing the at least one semiconductor layer; and a gate stack formed on the isolation layer and intersecting the at least one semiconductor layer, wherein the gate stack includes a gate dielectric layer at least partially surrounding a periphery of respective one of the at least one semiconductor layer and a gate conductor layer.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: April 19, 2022
    Assignee: Institute of Microelectronics, Chinese /Academy of Sciences
    Inventor: Huilong Zhu
  • Patent number: 11302810
    Abstract: A ferroelectric field effect transistor (FeFET) is provided. The FeFET includes a buried oxide (BOX) layer; a nanowire layer including pads formed on the BOX layer at source and drain regions of the FeFET, and a nanowire core extending between the pads and over a recess formed in the BOX layer; a metal electrode coating the nanowire core; a ferroelectric layer coating the metal electrode; an interfacial layer coating the ferroelectric layer; and a polysilicon layer formed over a channel region of the FeFET, the polysilicon layer coating the interfacial layer.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: April 12, 2022
    Assignee: International Business Machines Corporation
    Inventors: Nanbo Gong, Takashi Ando, Guy M. Cohen
  • Patent number: 11296291
    Abstract: A photovoltaic solar cell apparatus is described herein combining the advantages of several discoveries that address the previously unsolved problem of creating high conversion efficiency solar cells at a low cost. The solar cell designs and underlying principals disclosed herein may be applied in any type of photovoltaic solar power application, such as large scale photovoltaic solar plants, rooftop panels, solar powered electronic devices, and many others.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: April 5, 2022
    Assignee: Dimerond Technologies, LLC
    Inventor: Dieter M. Gruen
  • Patent number: 11287536
    Abstract: A radiation field is detected or imaged using one or more junction devices in which a two-dimensional conductor layer is capacitively coupled to a semiconductor absorber layer. In the junction devices, pixel-level amplification and read-out are accomplished through the photogating of the devices by absorption within the absorber layer while it is in a state of deep depletion. When the two-dimensional conductor is graphene, we refer to a device operating in that manner as a deeply depleted graphene-oxide-semiconductor (D2GOS) detector.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: March 29, 2022
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Stephen W. Howell, David W. Peters, Thomas Edwin Beechem, III, Isaac Ruiz, Richard Karl Harrison, Jeffrey B. Martin
  • Patent number: 11289417
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Yu Chou, Jr-Hung Li, Liang-Yin Chen, Su-Hao Liu, Tze-Liang Lee, Meng-Han Chou, Kuo-Ju Chen, Huicheng Chang, Tsai-Jung Ho, Tzu-Yang Ho
  • Patent number: 11275408
    Abstract: A display device includes a lower substrate that includes a first substrate, and a plurality of second substrates on the first substrate. The plurality of second substrates have higher rigidity than a rigidity of the first substrate. The plurality of second substrates may be spaced apart from each other. The lower substrate also includes one or more light emitting elements disposed on each of the plurality of second substrates.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: March 15, 2022
    Assignee: LG Display Co., Ltd.
    Inventors: JiYoung Ahn, Seulki Kim
  • Patent number: 11251280
    Abstract: Forming a fin, where the fin includes a nanowire stack on a semiconductor substrate, where the nanowire stack includes a plurality of silicon layers and a plurality of silicon germanium layers stacked one on top of the other in an alternating fashion, removing a portion of the fin to form an opening and expose vertical sidewalls of the plurality of silicon layers and the plurality of silicon germanium layer, and epitaxially growing a source drain region/structure in the opening from the exposed vertical sidewalls of the plurality of silicon layers and the plurality of silicon germanium layers, where the source drain region/structure substantially fills the opening.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: February 15, 2022
    Assignee: International Business Machines Corporation
    Inventors: Heng Wu, Chen Zhang, Kangguo Cheng, Xin Miao, Lan Yu
  • Patent number: 11233137
    Abstract: Devices and methods of fabricating vertical nanowires on semiconductor devices. A doped silicon substrate, a first insulator over the doped silicon substrate, a gate conductor over the first insulator, and a second insulator over the gate conductor. Silicon nanowires extend from the top surface of the substrate through the first insulator, the gate conductor, and the second insulator. A first contact extends from the gate conductor through the second insulator, a second contact extends from the substrate through the first insulator, the gate conductor, and the second insulator layer, and an insulating spacer material is positioned between the second contact and the gate conductor.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: January 25, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Dominic J. Schepis, Alexander Reznicek
  • Patent number: 11220756
    Abstract: A variety of homogeneous or layered hybrid nanostructures are fabricated by electric field-directed assembly of nanoelements. The nanoelements and the fabricated nanostructures can be conducting, semi-conducting, or insulating, or any combination thereof. Factors for enhancing the assembly process are identified, including optimization of the electric field and combined dielectrophoretic and electrophoretic forces to drive assembly. The fabrication methods are rapid and scalable. The resulting nanostructures have electrical and optical properties that render them highly useful in nanoscale electronics, optics, and biosensors.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: January 11, 2022
    Assignee: Northeastern University
    Inventors: Ahmed Busnaina, Cihan Yilmaz, TaeHoon Kim, Sivasubramanian Somu
  • Patent number: 11222149
    Abstract: Methods, systems, and apparatus for designing an artificial quantum thermal bath. In one aspect, an apparatus includes a primary quantum system; an auxiliary quantum system comprising a plurality of modes and that interacts with the primary quantum system, wherein: the auxiliary system interacts with the primary quantum system through one or more couplings, wherein the one or more couplings are controllable; a steady state of the auxiliary system, a response function of the auxiliary quantum system, an auxiliary system operator, and a spectrum of the auxiliary quantum system are determined to meet a respective condition; and the auxiliary system is controllable to relax the primary quantum system to an equilibrium state using a controllable function of the auxiliary system operator.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: January 11, 2022
    Assignee: Google LLC
    Inventors: Alireza Shabani Barzegar, Hartmut Neven
  • Patent number: 11217738
    Abstract: Various methods and devices for ultrasensitive infrared photodetection, infrared imaging, and other optoelectronic applications using the plasmon assisted thermoelectric effect in graphene are described. Infrared detection by the photo-thermoelectric uses the generation of a temperature gradient (?T) for the efficient collection of the generated hot-carriers. An asymmetric plasmon-induced hot-carrier Seebeck photodetection scheme at room temperature exhibits a remarkable responsivity along with an ultrafast response in the technologically relevant 8-12 ?m band. This is achieved by engineering the asymmetric electronic environment of the generated hot carriers on chemical vapor deposition (CVD) grown large area nanopatterned monolayer graphene, which leads to a record ?T across the device terminals thereby enhancing the photo-thermoelectric voltage beyond the theoretical limit for graphene. The results provide a strategy for uncooled, tunable, multispectral infrared detection.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: January 4, 2022
    Assignee: UNIVERSITY OF CENTRAL FLORIDA RESEARCH FOUNDATION, INC.
    Inventors: Debashis Chanda, Michael Leuenberger, Alireza Safaei, Sayan Chandra
  • Patent number: 11211773
    Abstract: A photonic integrated circuit device includes a passive waveguide section formed over a substrate, a quantum cascade laser (QCL) gain section formed over the substrate and adjacent to the passive waveguide section, and a taper section disposed between and in contact with each of the passive waveguide section and the QCL gain section. In some embodiments, the passive waveguide section includes a passive waveguide core layer disposed between a first cladding layer and a second cladding layer. In some examples, the QCL gain section includes a QCL active region disposed between a first confinement layer and a second confinement layer, where the QCL active region has a lower index of refraction than each of the first and second confinement layers. In some embodiments, the taper section is configured to optically couple the QCL gain section to the passive waveguide section.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: December 28, 2021
    Assignee: TRANSWAVE PHOTONICS, LLC.
    Inventors: Seungyong Jung, Mikhail A. Belkin
  • Patent number: 11205650
    Abstract: A semiconductor device according to an embodiment includes a first gate-all-around (GAA) transistor and a second GAA transistor. The first GAA transistor includes a first plurality of channel members, a first interfacial layer over the first plurality of channel members, a first hafnium-containing dielectric layer over the first interfacial layer, and a metal gate electrode layer over the first hafnium-containing dielectric layer. The second GAA transistor includes a second plurality of channel members, a second interfacial layer over the second plurality of channel members, a second hafnium-containing dielectric layer over the second interfacial layer, and the metal gate electrode layer over the second hafnium-containing dielectric layer. A first thickness of the first interfacial layer is greater than a second thickness of the second interfacial layer. A third thickness of the first hafnium-containing dielectric layer is smaller than a fourth thickness of the second hafnium-containing dielectric layer.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: December 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang
  • Patent number: 11201243
    Abstract: The current disclosure describes techniques for forming a gate-all-around device where semiconductor layers are released by etching out the buffer layers that are vertically stacked between semiconductor layers in an alternating manner. The buffer layers stacked at different vertical levels include different material compositions, which bring about different etch rates with respect to an etchant that is used to remove at least partially the buffer layers to release the semiconductor layers.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: December 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chansyun David Yang, Han-Yu Lin, Chun-Yu Chen, Chih-Ching Wang, Fang-Wei Lee, Tze-Chung Lin, Li-Te Lin, Gwan-Sin Chang, Pinyen Lin
  • Patent number: 11195982
    Abstract: In an embodiment, a method includes forming a first chip having a first substrate and one or more qubits disposed on the first substrate, each of the one or more qubits having an associated resonance frequency. In an embodiment, the method includes forming a second chip having a second substrate and at least one conductive surface disposed on the second substrate opposite the one or more qubits, the at least one conductive surface having at least one dimension configured to adjust the resonance frequency associated with at least one of the one or more qubits to a determined frequency adjustment value.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: December 7, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dongbing Shao, Markus Brink, Firat Solgun, Jared Barney Hertzberg
  • Patent number: 11195878
    Abstract: An optoelectronic device including a first optoelectronic circuit bonded to a second electronic circuit. The second electronic circuit includes conductive pads. The first optoelectronic circuit includes, for each pixel: at least first and second three-dimensional semiconductor elements extending over a first conductive layer and having the same height; first active areas resting on the first semiconductor elements and capable of emitting or receiving a first electromagnetic radiation; second active areas resting on the second semiconductor elements and capable of emitting or receiving a second electromagnetic radiation; and second, third, and fourth conductive layers electrically coupled to the conductive pads, the second, third, and fourth conductive layers being respectively coupled to the first active areas, to the second active areas, and to the first conductive layer.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: December 7, 2021
    Assignee: Aledia
    Inventor: Eric Pourquier
  • Patent number: 11188044
    Abstract: An optimization device includes a plurality of calculation circuits; a selection circuit; an identification information calculation circuit, and an updating circuit. Each of the plurality of calculation circuits calculates, for a plurality of bits corresponding to a plurality of spins included in an Ising model obtained by converting a problem to be calculated, a first energy change of the Ising model due to a value of a first bit having the value of 1 being changed from 1 to 0 and a value of a second bit having the value of 0 being changed from 0 to 1. The selection circuit outputs first bit identification information identifying one second bit having a value permitted to be updated from 0 to 1, based on a magnitude relationship between thermal excitation energy and the first energy change output by each of the plurality of calculation circuits.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: November 30, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Kouichi Kanda, Hirotaka Tamura, Hidetoshi Matsumura
  • Patent number: 11189692
    Abstract: A cell architecture for vertical field-effect transistors (VFETs) is provided. The cell architecture includes: top source/drain (S/D) contact structure having a square shape in a plan view; and horizontal metal patterns formed on the top S/D contact structures and extended in an X-direction to be connected to a vertical pattern through with an output signal of a logic circuit formed by the VFETs. The cell architecture further includes a gate contact structure formed on a gate connection pattern connecting gates of the VFETs, wherein a super via is formed on the gate contact structure to receive an input signal of the logic circuit.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: November 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Ho Do, Rwik Sengupta
  • Patent number: 11177316
    Abstract: A method of manufacturing a light source device includes the steps of providing a mask layer to a substrate, providing the mask layer with a plurality of first openings and at least one second opening, and growing columnar parts having a light emitting section from the plurality of first openings, and growing a structure from the second opening.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: November 16, 2021
    Inventors: Tetsuji Fujita, Yasutaka Imai, Koichiro Akasaka, Hideki Hahiro, Michifumi Nagawa
  • Patent number: 11177182
    Abstract: One illustrative vertical transistor device disclosed herein includes a channel region comprising at least one layer of a two-dimensional (2D) material, a bottom source/drain region, a top source/drain region and a gate structure positioned all around at least the at least one layer of a two-dimensional (2D) material.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: November 16, 2021
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Heng Yang, David Pritchard, Kai Sun, Hongru Ren, Neha Nayyar, Manjunatha Prabhu, Elizabeth Strehlow, Salvatore Cimino
  • Patent number: 11164941
    Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having a first region and a second region; forming first nanowires over the first region of the semiconductor substrate; forming second nanowires with a diameter smaller than a diameter of the first nanowires over the second region of the semiconductor substrate; forming a first gate layer around the first nanowires; and forming a second gate layer around the second nanowires.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: November 2, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Huan Yun Zhang, Jian Wu
  • Patent number: 11151470
    Abstract: A method to evaluate a semiconductor-superconductor heterojunction for use in a qubit register of a topological quantum computer includes measuring a radio-frequency (RF) junction admittance of the semiconductor-superconductor heterojunction to obtain mapping data; finding by analysis of the mapping data one or more regions of a parameter space consistent with an unbroken topological phase of the semiconductor-superconductor heterojunction; measuring a sub-RF conductance including a non-local conductance of the semiconductor-superconductor heterojunction in each of the one or more regions of the parameter space, to obtain refinement data; and finding by analysis of the refinement data a boundary of the unbroken topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: October 19, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Dmitry Pikulin, Mason L Thomas, Chetan Vasudeo Nayak, Roman Mykolayovych Lutchyn, Georg Wolfgang Winkler, Sebastian Heedt, Gijsbertus De Lange, Bernard Van Heck, Esteban Adrian Martinez, Lucas Casparis, Torsten Karzig
  • Patent number: 11152500
    Abstract: The application discloses a tunneling field-effect transistor, including: a substrate layer; a rectangular semiconductor strip formed on an upper surface of the substrate layer, where the rectangular semiconductor strip includes a first source region, a first channel region, a drain region, a second channel region, and a second source region that are disposed in sequence along a first direction; a first gate dielectric layer covering an outer surface of a first part of the first source region and a second gate dielectric layer covering an outer surface of a third part of the second source region.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: October 19, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jing Zhao, Chen-Xiong Zhang
  • Patent number: 11152495
    Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: October 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alan B. Botula, Max L. Lifson, James A. Slinkman, Theodore G. Van Kessel, Randy L. Wolf
  • Patent number: 11139405
    Abstract: A method of manufacturing a semiconductor device includes providing a substrate structure. The substrate structure includes a conductive layer and a plurality of nanopillars spaced apart from each other overlying the conductive layer. Each nanopillar includes a first semiconductor layer and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer have different conductivity types. The method also includes forming a graphene layer overlying the plurality of nanopillars. The graphene layer is connected to each of the plurality of nanopillars.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: October 5, 2021
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Ming Zhou
  • Patent number: 11133279
    Abstract: A method for manufacturing connection structure, the method includes arranging conductive particles and a first composite on a first electrode located on a first surface of a first member, arranging a second composite on the first electrode and a region other than the first electrode of the first surface, arranging the first surface and a second surface of a second member where a second electrode is located, so that the first electrode and the second electrode are opposed to each other, pressing the first member and the second member, and curing the first composite and the second composite.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: September 28, 2021
    Assignee: MIKUNI ELECTRON CORPORATION
    Inventor: Sakae Tanaka
  • Patent number: 11121232
    Abstract: Semiconductor devices include vertically stacked channel layers formed from a semiconductor material. A metallic interface layer is formed between metal source/drain regions and the vertically stacked channel layers. The metallic interface layer includes the semiconductor material and a metal. A gate stack is formed between and around the channel layers.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: September 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Choonghyun Lee, Kangguo Cheng, Juntao Li
  • Patent number: 11099084
    Abstract: Provided is a pressure sensor including a first optical waveguide inside a lower substrate, a graphene layer above the lower substrate, an upper substrate above the graphene layer, and spacers between the lower substrate and the upper substrate.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: August 24, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventor: Jin Tae Kim
  • Patent number: 11094831
    Abstract: Semiconductor nanowire devices having cavity spacers and methods of fabricating cavity spacers for semiconductor nanowire devices are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires including a discrete channel region. A common gate electrode stack surrounds each of the discrete channel regions of the plurality of vertically stacked nanowires. A pair of dielectric spacers is on either side of the common gate electrode stack, each of the pair of dielectric spacers including a continuous material disposed along a sidewall of the common gate electrode and surrounding a discrete portion of each of the vertically stacked nanowires. A pair of source and drain regions is on either side of the pair of dielectric spacers.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: August 17, 2021
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Szuya S. Liao, Stephen M. Cea
  • Patent number: 11087233
    Abstract: Methods, systems, and apparatus for operating a system of qubits. In one aspect, a method includes operating a first qubit from a first plurality of qubits at a first qubit frequency from a first qubit frequency region, and operating a second qubit from the first plurality of qubits at a second qubit frequency from a second first qubit frequency region, the second qubit frequency and the second first qubit frequency region being different to the first qubit frequency and the first qubit frequency region, respectively, wherein the second qubit is diagonal to the first qubit in a two-dimensional grid of qubits.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: August 10, 2021
    Assignee: Google LLC
    Inventors: John Martinis, Rami Barends, Austin Greig Fowler
  • Patent number: 11087832
    Abstract: Described herein are IC devices that include semiconductor nanoribbons stacked over one another to realize high-density 3D SRAM. An example device includes an SRAM cell built based on a first nanoribbon, suitable for forming NMOS transistors, and a second nanoribbon, suitable for forming PMOS transistors. Both nanoribbons may extend substantially in the same plane above a support structure over which the memory device is provided. The SRAM cell includes transistors M1-M4, arranged to form two inverter structures. The first inverter structure includes transistor M1 in the first nanoribbon and transistor M2 in the second nanoribbon, while the second inverter structure includes transistor M3 in the first nanoribbon and transistor M4 in the second nanoribbon. The IC device may include multiple layers of nanoribbons, with one or more such SRAM cells in each layer, stacked upon one another above the support structure, thus realizing 3D SRAM.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: August 10, 2021
    Assignee: Intel Corporation
    Inventors: Wilfred Gomes, Kinyip Phoa, Mauro J. Kobrinsky, Tahir Ghani
  • Patent number: 11081484
    Abstract: There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: August 3, 2021
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Zhengyong Zhu
  • Patent number: 11069793
    Abstract: A semiconductor device includes a plurality of nanostructures. The nanostructures each contain a semiconductive material. A plurality of first spacers circumferentially wrap around the nanostructures. A plurality of second spacers circumferentially wrap around the first spacers. A plurality of third spacers is disposed between the second spacers vertically. A gate structure surrounds the second spacers and the third spacers.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: July 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Shi Ning Ju, Kuan-Lun Cheng
  • Patent number: 11056602
    Abstract: A graphene device for filtering color, involving a graphene structure responsive to continuous in-situ electrical gate-tuning of a Fermi level thereof and a plurality of nanoparticles disposed in relation to the graphene structure, each portion of the plurality of nanoparticles having a distinct energy bandgap in relation to another portion of the plurality of nanoparticles, and each portion of the plurality of nanoparticles configured to one of activate and deactivate in relation to the distinct energy bandgap and in response to the in-situ electrical gate-tuning of the Fermi level of the graphene structure.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: July 6, 2021
    Assignee: United States of America as represented by the Secretary of the Navy
    Inventors: Richard C. Ordonez, Carlos M. Torres, Jr., Cody K. Hayashi, David Garmire
  • Patent number: 11056400
    Abstract: Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: July 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Ching Cheng, Tzu-Chiang Chen, Chen-Feng Hsu, Yu-Lin Yang, Tung Ying Lee, Chih Chieh Yeh
  • Patent number: 11050034
    Abstract: A quantum dot (QD) light emitting diode comprising first and second electrodes facing each other; a QD emitting material layer between the first and second electrodes; and a semiconducting member acting as a hole transporting path in the QD emitting material layer is provided.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: June 29, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Tae-Yang Lee, Kyu-Nam Kim, Sung-Il Woo
  • Patent number: 11049937
    Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: June 29, 2021
    Inventors: Chung-Liang Cheng, Chun-I Wu, Huang-Lin Chao
  • Patent number: 11049036
    Abstract: Methods, systems, and apparatus for operating a system of qubits. In one aspect, a method includes operating a first qubit from a first plurality of qubits at a first qubit frequency from a first qubit frequency region, and operating a second qubit from the first plurality of qubits at a second qubit frequency from a second first qubit frequency region, the second qubit frequency and the second first qubit frequency region being different to the first qubit frequency and the first qubit frequency region, respectively, wherein the second qubit is diagonal to the first qubit in a two-dimensional grid of qubits.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: June 29, 2021
    Assignee: Google LLC
    Inventors: John Martinis, Rami Barends, Austin Greig Fowler
  • Patent number: 11049857
    Abstract: This invention provides a semiconductor device and a manufacturing method thereof.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: June 29, 2021
    Assignee: SiEn (QingDao) Integrated Circuits Co., Ltd.
    Inventors: Deyuan Xiao, Richard R. Chang
  • Patent number: 11038042
    Abstract: Techniques for forming gate last VFET devices are provided. In one aspect, a method of forming a VFET device includes: forming a stack on a wafer including: i) a doped bottom source/drain, ii) sacrificial layers having layers of a first sacrificial material with a layer of a second sacrificial material therebetween, and iii) a doped top source/drain; patterning trenches in the stack to form individual gate regions; filling the trenches with a channel material to form vertical fin channels; selectively removing the layers of the first sacrificial material forming first cavities in the gate regions; forming gate spacers in the first cavities; selectively removing the layer of the second sacrificial material forming second cavities in the gate regions; and forming replacement metal gates in the second cavities. A VFET device is also provided.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: June 15, 2021
    Assignee: International Business Machines Corporation
    Inventor: Nicolas Loubet
  • Patent number: 11031292
    Abstract: A method of fabricating a device includes providing a first fin in a first device type region and a second fin in a second device type region. Each of the first and second fins include a plurality of semiconductor channel layers. A two-step recess of an STI region on opposing sides of each of the first and second fins is performed to expose a first number of semiconductor channel layers of the first fin and a second number of semiconductor channel layers of the second fin. A first gate structure is formed in the first device type region and a second gate structure is formed in the second device type region. The first gate structure is formed over the first fin having the first number of exposed semiconductor channel layers, and the second gate structure is formed over the second fin having the second number of exposed semiconductor channel layers.
    Type: Grant
    Filed: September 29, 2019
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shi Ning Ju, Kuo-Cheng Chiang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11031243
    Abstract: A nanowire structure includes a substrate, a patterned mask layer on the substrate, and a nanowire. The patterned mask layer is on the substrate and includes an opening through which the substrate is exposed. The nanowire is on the substrate in the opening of the patterned mask layer. The nanowire includes a buffer layer on the substrate, a defect filtering layer on the buffer layer, and an active layer on the defect filtering layer. The defect filtering layer is a strained layer. By providing the defect filtering layer between the buffer layer and the active layer of the nanowire, defects present in the buffer layer can be prevented from propagating into the active layer. Accordingly, defects in the active layer of the nanowire are reduced, thereby improving the performance of the nanowire structure.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: June 8, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Geoffrey C. Gardner, Sergei V. Gronin, Raymond L. Kallaher
  • Patent number: 11011646
    Abstract: A TFT structure based on a flexible multi-layer graphene quantum carbon substrate material and a method for manufacturing the same. The TFT structure includes a multi-layer graphene quantum carbon substrate, a first source, a first drain, a first gate insulating layer, and a first gate. The multi-layer graphene quantum carbon substrate includes a first channel area, and a first drain area and a first source area that are located at corresponding recessed positions on the multi-layer graphene quantum carbon substrate that are separated from each other. The first channel area is located between the first drain area and the first source area, the first source is filled in the first source area, the first drain is filled in the first drain area, the first gate insulating layer is disposed on the first channel area, and the first gate is disposed on the first gate insulating layer.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: May 18, 2021
    Assignee: Guang Dong Dongbond Technology Co., Ltd.
    Inventor: Ping Liu
  • Patent number: 11004847
    Abstract: An integrated circuit (IC) device comprises a substrate having a metal-oxide-semiconductor (MOS) region; a gate region disposed over the substrate and in the MOS region; and source/drain features in the MOS region and separated by the gate region. The gate region includes a fin structure and a nanowire over the fin structure. The nanowire extends from the source feature to the drain feature.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: May 11, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ting-Hung Hsu
  • Patent number: 10991799
    Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: April 27, 2021
    Assignee: Sony Corporation
    Inventors: Kelin J. Kuhn, Seiyon Kim, Rafael Rios, Stephen M. Cea, Martin D. Giles, Annalisa Cappellani, Titash Rakshit, Peter Chang, Willy Rachmady
  • Patent number: 10984335
    Abstract: A system for transmission of quantum information for quantum error correction includes an ancilla qubit chip including a plurality of ancilla qubits, and a data qubit chip spaced apart from the ancilla qubit chip, the data qubit chip including a plurality of data qubits. The system includes an interposer coupled to the ancilla qubit chip and the data qubit chip, the interposer including a dielectric material and a plurality of superconducting structures formed in the dielectric material. The superconducting structures enable transmission of quantum information between the plurality of data qubits on the data qubit chip and the plurality of ancilla qubits on the ancilla qubit chip via virtual photons for quantum error correction.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: April 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicholas T. Bronn, Daniela F. Bogorin, Patryk Gumann, Sean Hart, Salvatore B. Olivadese
  • Patent number: 10971609
    Abstract: An integrated circuit (IC) structure with a nanowire power switch device and a method of forming the IC structure are disclosed. The method includes forming a first layer of metal lines of a first back end of line (BEOL) interconnect structure and forming a semiconductor nanowire structure on a first metal line of the first layer of metal lines. The BEOL interconnect structure is formed on a front end of line (FEOL) device layer having multiple active devices. The method further includes forming a first dielectric layer wrapped around the semiconductor nanowire structure, forming a metal layer on the dielectric layer and on a second metal line of the first layer of metal lines, and forming a second layer of metal lines of a second BEOL interconnect structure on the semiconductor nanowire structure. The first and second metal lines are electrically isolated from each other.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Yang Chuang, Ching-Wei Tsai, Wang-Chun Huang, Kuan-Lun Cheng