Thin Active Physical Layer Which Is (1) An Active Potential Well Layer Thin Enough To Establish Discrete Quantum Energy Levels Or (2) An Active Barrier Layer Thin Enough To Permit Quantum Mechanical Tunneling Or (3) An Active Layer Thin Enough To Permit Carrier Transmission With Substantially No Scattering (e.g., Superlattice Quantum Well, Or Ballistic Transport Device) Patents (Class 257/9)
  • Patent number: 10446719
    Abstract: The disclosed technology provides micro-assembled micro-LED displays and lighting elements using arrays of micro-LEDs that are too small (e.g., micro-LEDs with a width or diameter of 10 ?m to 50 ?m), numerous, or fragile to assemble by conventional means. The disclosed technology provides for micro-LED displays and lighting elements assembled using micro-transfer printing technology. The micro-LEDs can be prepared on a native substrate and printed to a display substrate (e.g., plastic, metal, glass, or other materials), thereby obviating the manufacture of the micro-LEDs on the display substrate. In certain embodiments, the display substrate is transparent and/or flexible.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: October 15, 2019
    Assignee: X-Celeprint Limited
    Inventors: Christopher Bower, Matthew Meitl, David Gomez, Salvatore Bonafede, David Kneeburg, Alin Fecioru, Carl Prevatte
  • Patent number: 10431663
    Abstract: Disclosed are methods for forming an integrated circuit with a nanowire-type field effect transistor and the resulting structure. A sacrificial gate is formed on a multi-layer fin. A sidewall spacer is formed with a gate section on the sacrificial gate and fin sections on exposed portions of the fin. Before or after removal of the exposed portions of the fin, the fins sections of the sidewall spacer are removed or reduced in size without exposing the sacrificial gate. Thus, the areas within which epitaxial source/drain regions are to be formed will not be bound by sidewall spacers. Furthermore, isolation material, which is deposited into these areas prior to epitaxial source/drain region formation and which is used to form isolation elements between the transistor gate and source/drain regions, can be removed without removing the isolation elements. Techniques are also disclosed for simultaneous formation of a nanosheet-type and/or fin-type field effect transistors.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: October 1, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Balasubramanian Pranatharthiharan, Pietro Montanini, Julien Frougier
  • Patent number: 10430493
    Abstract: Disclosed are systems and methods for performing efficient vector-matrix multiplication using a sparsely-connected conductance matrix and analog mixed signal (AMS) techniques. Metal electrodes are sparsely connected using coaxial nanowires. Each electrode can be used as an input/output node or neuron in a neural network layer. Neural network synapses are created by random connections provided by coaxial nanowires. A subset of the metal electrodes can be used to receive a vector of input voltages and the complementary subset of the metal electrodes can be used to read output currents. The output currents are the result of vector-matrix multiplication of the vector of input voltages with the sparsely-connected matrix of conductances.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: October 1, 2019
    Assignee: Rain Neuromorphics Inc.
    Inventor: Jack Kendall
  • Patent number: 10424696
    Abstract: Provided are a wavelength converting particle, a method for manufacturing a wavelength converting particle, and a light-emitting diode containing a wavelength converting particle. The wavelength converting particle comprises an organic/inorganic/hybrid perovskite nanocrystal that converts a wavelength of light generated by an excitation light source into a specified wavelength. Accordingly, it is possible to optically stabilize and improve color purity and light-emission performance without changes in a light-emitting wavelength range.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: September 24, 2019
    Assignees: POSTECH ACADEMY-INDUSTRY FOUNDATION
    Inventors: Taewoo Lee, Younghoon Kim, Himchan Cho
  • Patent number: 10411090
    Abstract: Hybrid trigate and nanowire CMOS device architecture, and methods of fabricating hybrid trigate and nanowire CMOS device architecture, are described. For example, a semiconductor structure includes a semiconductor device of a first conductivity type having a plurality of vertically stacked nanowires disposed above a substrate. The semiconductor structure also includes a semiconductor device of a second conductivity type opposite the first conductivity type, the second semiconductor device having a semiconductor fin disposed above the substrate.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: Cory E. Weber, Rishabh Mehandru, Stephen M. Cea
  • Patent number: 10403754
    Abstract: Semiconductor devices are provided. A semiconductor device includes a channel. The semiconductor device includes a gate structure having first and second portions. The channel is between the first and second portions of the gate structure. A contact structure is adjacent a portion of a side surface of the channel. Related methods of forming semiconductor devices are also provided.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Dae Suk, Sunhom Steve Paak, Yeon-Ho Park, Dong-Ho Cha
  • Patent number: 10396214
    Abstract: Non-planar semiconductor devices including semiconductor fins or stacked semiconductor nanowires that are electrostatically enhanced are provided. The electrostatic enhancement is achieved in the present application by epitaxially growing a semiconductor material protruding portion on exposed sidewalls of alternating semiconductor material portions of at least one hard mask capped semiconductor-containing fin structure that is formed on a substrate.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 10374035
    Abstract: Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Junli Wang
  • Patent number: 10367033
    Abstract: A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Ombretta Donghi, Marcello Ravasio, Samuele Sciarrillo, Roberto Somaschini
  • Patent number: 10347719
    Abstract: A semiconductor structure. The structure includes first source/drain located in a first source/drain region. The structure includes a second source/drain located in a second source/drain region. The structure includes a plurality of semiconductor nanosheets located between the first source/drain and the second source/drain in a gate region. The structure includes an insulating layer separating the first source drain from a bulk substrate. The bulk substrate may have a first horizontal surface in the gate region, a second horizontal surface in the first source/drain region, and a connecting surface forming an at least partially vertical connection between the first horizontal surface and the second horizontal surface. The insulating layer may be directly on the second horizontal surface and the connecting surface.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 10347760
    Abstract: A reconfigurable field effect transistor (RFET) includes a nanowire, wherein the nanowire comprises two Schottky contacts, as well as two gate contacts partially enclosing the nanowire in cross section. An integrated circuit can be produced therefrom. The aim of producing CMOS circuits with enhanced functionality and a more compact design is achieved in that the nanowire is divided along the cross section thereof into two nanowire parts, wherein each nanowire part comprises a respective Schottky contact and a respective gate contact, and the two nanowire parts are connected electrically to one another via a common substrate and stand vertically on the substrate. In a nanowire-parts-array, between the nanowire parts, a respective top-gate contact and/or back-gate contact can be formed in a substrate defining a substrate plane.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: July 9, 2019
    Assignees: Technische Universität Dresden, NaMLab gGmbH
    Inventors: Tim Baldauf, André Heinzig, Walter Michael Weber
  • Patent number: 10332961
    Abstract: Embodiments are directed to a method of fabricating inner spacers of a nanosheet FET. The method includes forming sacrificial and channel nanosheets over a substrate, removing sidewall portions of the sacrificial nanosheet, and forming a dielectric that extends over the channel nanosheet and within a space that was occupied by the removed sidewall portions of the sacrificial nanosheet. The method further includes forming a top protective spacer over the channel nanosheet and the dielectric, as well as applying a directional etch to the top protective spacer, the channel nanosheet, and the dielectric, wherein the directional etch is configured to be selective to the channel nanosheet and the dielectric, wherein the directional etch is configured to not be selective to the top protective spacer, and wherein applying the directional etch etches portions of the channel nanosheet and portions of the flowable dielectric that are not under the top dielectric.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: June 25, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-chen Yeh
  • Patent number: 10333027
    Abstract: Disclosed in one embodiment is a light-emitting device comprising: a first semiconductor layer; an active layer arranged on the first semiconductor layer and including a plurality of first uneven portions; an electron blocking layer including a plurality of second uneven portions arranged on the plurality of first uneven portions; and a second semiconductor layer formed on the electron blocking layer, wherein the electron blocking layer has at least two doping concentration peak sections of a p-type dopant in the thickness direction.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: June 25, 2019
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Chong Cook Kim
  • Patent number: 10325996
    Abstract: A semiconductor device is produced by providing a semiconductor substrate, forming an epitaxial layer on the semiconductor substrate, and introducing dopant atoms of a first doping type and dopant atoms of a second doping type into the epitaxial layer.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: June 18, 2019
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Franz Hirler, Anton Mauder, Helmut Strack, Frank Kahlmann, Gerhard Miller
  • Patent number: 10325993
    Abstract: A device includes a nanowire, a gate dielectric layer and a gate electrode. The nanowire has a sidewall. The gate dielectric layer surrounds the nanowire. The gate electrode surrounds the gate dielectric layer and separated from the nanowire. The gate electrode comprises a sloped sidewall inclined with respect to the sidewall of the nanowire.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: June 18, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yung-Chih Wang, Yu-Chieh Liao, Tai-I Yang, Hsin-Ping Chen
  • Patent number: 10325820
    Abstract: Techniques for source/drain isolation in nanosheet devices are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of sacrificial/active channel nanosheets as a stack on a substrate; forming gates on the stack; forming spacers alongside opposite sidewalls of the gates; patterning the stack, in between the spacers, into individual PFET/NFET stacks and pockets in the substrate; laterally recessing the sacrificial nanosheets in the PFET/NFET stacks to expose tips of the active channel nanosheets in the PFET/NFET stacks; forming inner spacers alongside the PFET/NFET stacks covering the tips of the active channel nanosheets; forming a protective layer lining the pockets; and selectively etching back the inner spacers to expose tips of the active channel nanosheets and epitaxially growing source and drains from the exposed tips of the active channel nanosheets sequentially in the PFET/NFET stacks. A nanosheet device is also provided.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Soon-Cheon Seo, Choonghyun Lee, Injo Ok
  • Patent number: 10319846
    Abstract: A semiconductor structure includes a substrate, an isolation layer disposed over the substrate, a plurality of nanosheet channels, interfacial layers surrounding each of the nanosheet channels, and dielectric layers surrounding each of the interfacial layers. The plurality of nanosheet channels includes first and second sets of two or more nanosheet channels for first and second NFETs and third and fourth sets of two or more nanosheet channels for first and second PFETs. The interfacial layers surrounding the first and third sets of nanosheet channels for the first NFET and the first PFET have a first thickness, and interfacial layers surrounding the second and fourth sets of nanosheets channels for the second NFET and the second PFET have a second thickness smaller than the first thickness. The first NFET has a higher threshold voltage than the second NFET, and the first PFET has a lower threshold voltage than the second PFET.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, ChoongHyun Lee, Jingyun Zhang, Pouya Hashemi
  • Patent number: 10319676
    Abstract: Embodiments are directed to a method and resulting structures for forming a semiconductor device having a vertically integrated nanosheet fuse. A nanosheet stack is formed on a substrate. The nanosheet stack includes a semiconductor layer formed between an upper nanosheet and a lower nanosheet. The semiconductor layer is modified such that an etch rate of the modified semiconductor layer is greater than an etch rate of the upper and lower nanosheets when exposed to an etchant. Portions of the modified semiconductor layer are removed to form a cavity between the upper and lower nanosheets and a silicide region is formed in the upper nanosheet.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robin H. Chao, James J. Demarest, Nicolas J. Loubet
  • Patent number: 10312323
    Abstract: Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Junli Wang
  • Patent number: 10312329
    Abstract: The present disclosure relates to the technical field of semiconductor processes, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method includes: providing a substrate structure including a substrate and a first material layer on the substrate, wherein a recess is formed in the substrate and the first material layer includes a nanowire; forming a base layer on the substrate structure; selectively growing a graphene layer on the base layer; forming a second dielectric layer on the graphene layer; forming an electrode material layer on the substrate structure to cover the second dielectric layer; defining an active region; and forming a gate by etching at least a portion of a stack layer to at least the second dielectric layer so as to form a gate structure surrounding an intermediate portion of the nanowire, where the gate structure includes a portion of the electrode material layer and the second dielectric layer.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: June 4, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Ming Zhou
  • Patent number: 10296352
    Abstract: Systems and methods of processing using a quantum processor are described. A method includes obtaining a problem Hamiltonian and defining a nested Hamiltonian with a plurality of logical qubits by embedding a logical KN representing the problem Hamiltonian into a larger KC×N, where N represents a number of the logical qubits and C represents a nesting level defining the amount of hardware resources for the nest Hamiltonian. The method also includes encoding the nested Hamiltonian into the plurality of physical qubits of the quantum processor; and performing a quantum annealing process with the quantum processor after the encoding.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: May 21, 2019
    Assignee: University of Southern California
    Inventors: Daniel Lidar, Tameem Albash, Walter Vinci
  • Patent number: 10297671
    Abstract: A method is presented for forming a nanosheet structure having a uniform threshold voltage (Vt). The method includes forming a conductive barrier surrounding a nanosheet, forming a first work function conducting layer over the conductive barrier layer, and forming a conducting layer adjacent the first work function conducting layer, the conducting layer defining a first region and a second region. The method further includes forming a second work function conducting layer over the second region of the conducting layer to compensate for threshold voltage offset between the first and second regions of the conducting layer.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Hemanth Jagannathan, Paul C. Jamison, ChoongHyun Lee, Vijay Narayanan, Koji Watanabe
  • Patent number: 10290738
    Abstract: One illustrative method disclosed includes, among other things, forming a gate structure around a fin and above a layer of insulating material, forming a gate spacer adjacent the gate structure and a fin spacer positioned adjacent the fin above the insulating material, the fin spacer leaving an upper surface of the fin exposed, and performing at least one etching process to remove at least a portion of the fin positioned between the fin spacer, the fin having a recessed upper surface that at least partially defines a fin recess positioned between the fin spacer. In this example, the method further includes forming an epi semiconductor material on the fin recess and removing the fin spacer from adjacent the epi semiconductor material while leaving a portion of the gate spacer in position adjacent the gate structure.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: May 14, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Christopher M. Prindle, Kwan-Yong Lim
  • Patent number: 10283607
    Abstract: A semiconductor structure includes a first GAA transistor and a second GAA transistor. The first GAA transistor includes: a first diffusion region, a second diffusion region, and a first nanowire. The second GAA transistor includes: a third diffusion region, a fourth diffusion region, and a second nanowire. The first diffusion region, the second diffusion region, and the first nanowire are symmetrical with the third diffusion region, the fourth diffusion region, and the second nanowire respectively, the first GAA transistor is arranged to provide a first current to flow through the first nanowire, and the second GAA transistor is arranged to provide a second current to flow through the second nanowire.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chung-Hui Chen
  • Patent number: 10283649
    Abstract: A Schottky barrier diode includes a graphene nanoribbon, a first electrode connected to one end of the graphene nanoribbon, and a second electrode connected to the other end of the graphene nanoribbon. The graphene nanoribbon includes a first part and a second part which are connected in the length direction of the graphene nanoribbon and which differ in electronic state. For example, edges of the first part in a length direction of the graphene nanoribbon are terminated with a first modifying group and edges of the second part in the length direction of the graphene nanoribbon are terminated with a second modifying group.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: May 7, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Shintaro Sato, Hideyuki Jippo
  • Patent number: 10272647
    Abstract: Described herein are methods for improved transfer of graphene from formation substrates to target substrates. In particular, the methods described herein are useful in the transfer of high-quality chemical vapor deposition-grown monolayers of graphene from metal, e.g., copper, formation substrates via non-polymeric methods. The improved processes provide graphene materials with less defects in the structure.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: April 30, 2019
    Assignee: Corning Incorporated
    Inventors: Benedict Yorke Johnson, Prantik Mazumder, Kamal Kishore Soni
  • Patent number: 10274645
    Abstract: A manufacturing method of micro-nano structure antireflective coating layer and a display apparatus thereof are described. The method includes providing a substrate, forming a silicon oxide layer on the substrate, forming a graphene layer with a hexagonal honeycomb lattice on the silicon oxide layer, and forming a bottom surface of the antireflective coating layer in the nucleation points by serving the graphene layer as a growing base layer, wherein a diffusion length and an atomic mass of diffusion atoms of the antireflective coating layer are decreased with time by a gradient growing manner to form a upper surface of the antireflective coating layer.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: April 30, 2019
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventor: Guowei Zha
  • Patent number: 10252914
    Abstract: Methods of producing layers of patterned graphene with smooth edges are provided. The methods comprise the steps of fabricating a layer of crystalline graphene on a surface, wherein the layer of crystalline graphene has a crystallographically disordered edge, and decreasing the crystallographic disorder of the edge of the layer of crystalline graphene by heating the layer of crystalline graphene on the surface at an elevated temperature in a catalytic environment comprising carbon-containing molecules.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: April 9, 2019
    Assignee: WISCONSIN ALUMNI RESEARCH FOUNDATION
    Inventors: Michael Scott Arnold, Padma Gopalan, Nathaniel S. Safron, Myungwoong Kim
  • Patent number: 10211359
    Abstract: An integrated circuit includes a substrate material that includes an epitaxial layer, wherein the substrate material and the epitaxial layer form a first semiconductor material with the epitaxial layer having a first conductivity type. At least one nanowire comprising a second semiconductor material having a second conductivity type doped differently than the first conductivity type of the first semiconductor material forms a junction crossing region with the first semiconductor material. The nanowire and the first semiconductor material form an avalanche photodiode (APD) in the junction crossing region to enable single photon detection. In an alternative configuration, the APD is formed as a p-i-n crossing region where n represents an n-type material, i represents an intrinsic layer, and p represents a p-type material.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: February 19, 2019
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Narsingh B. Singh, John V. Veliadis, Bettina Nechay, Andre Berghmans, David J. Knuteson, David Kahler, Brian Wagner, Marc Sherwin
  • Patent number: 10186351
    Abstract: A system for providing electrical and optical interconnection using a 3D non-carbon-based topological insulator (TI) is disclosed. The system includes a length of the TI having a tube shape having wall thickness of about 10 nm to about 200 nm and a hollow interior portion surrounded by an interior surface of the TI. The length includes a first end and a second end, wherein the first end is configured to receive an optical signal, an electrical signal, or both. The optical signal propagates in the hollow interior portion along the length to the second end by total internal reflection due to a refractive index of the interior surface of the TI. The electrical signal propagates along an external surface of the TI to the second end.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: January 22, 2019
    Assignee: THE BOEING COMPANY
    Inventors: Jeffrey H. Hunt, Wayne R. Howe, Angela W. Li
  • Patent number: 10181495
    Abstract: A process for producing a light emitting diode device, the process including: forming a plurality of quantum dots on a surface of a layer including a first area and a second area, the forming including: exposing the first area of the surface to light having a first wavelength while exposing the first area to a quantum dot forming environment that causes the quantum dots in the first area to form at a first growth rate while the quantum dots have a dimension less than a first threshold dimension; exposing the second area of the surface to light having a second wavelength while exposing the second area to the quantum dot forming environment that causes the quantum dots in the second area to form at a third growth rate while the quantum dots have a dimension less than a second threshold dimension; and processing the layer to form the LED device.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: January 15, 2019
    Assignee: X Development LLC
    Inventors: Martin Friedrich Schubert, Michael Jason Grundmann
  • Patent number: 10170374
    Abstract: A semiconductor device includes at least one n-channel, at least one p-channel, at least one first high-k dielectric sheath, at least one second high-k dielectric sheath, a first metal gate electrode and a second metal gate electrode. The first high-k dielectric sheath surrounds the n-channel. The second high-k dielectric sheath surrounds the p-channel. The first high-k dielectric sheath and the second high-k dielectric sheath comprise different high-k dielectric materials. The first metal gate electrode surrounds the first high-k dielectric sheath. The second metal gate electrode surrounds the second high-k dielectric sheath.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Sheng Chen, Tzu-Chiang Chen, Cheng-Hsien Wu, Chih-Chieh Yeh, Chih-Sheng Chang
  • Patent number: 10139655
    Abstract: The spin-Hall effect can be used to modulate the linear polarization of light via the magneto-optical Kerr effect. A material is illuminated while simultaneously passing a modulated electric current through the material, so that reflected light has a new linear polarization that differs from the initial linear polarization to a degree depending on the amplitude of the modulated electric current.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: November 27, 2018
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Olaf M. J. van't Erve, Connie H. Li, Berend T. Jonker, Aubrey T. Hanbicki, Kathleen M. McCreary
  • Patent number: 10141424
    Abstract: Method of manufacturing a structure with semiconducting bars suitable for forming one at least one transistor channel, including the following steps: a) make a semiconducting structure, composed of an alternation of first bars based on a first material and second bars based on a second material, the second material being a semiconducting material, then b) remove exposed portions of the structure based on the first material through an opening in a mask formed on the structure, the removal being made by selective etching in the opening of the first material relative to the second material, so as to expose a space around the second bars, then c) grow a given semiconducting material (25) around the second bars (6c) in the opening, the given semiconducting material having a mesh parameter different from the mesh parameter of the second material (7) so as to induce a strain on the sheaths based on the given semiconducting material.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: November 27, 2018
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, IBM CORPORATION
    Inventors: Remi Coquand, Emmanuel Augendre, Nicolas Loubet, Shay Reboh
  • Patent number: 10121877
    Abstract: A method for fabricating a semiconductor device includes forming a semiconductor fin over a substrate. A first doped region is formed on a first end of the semiconductor fin. A second doped region is formed on a second end of the semiconductor fin. An extended contact is formed on the second doped region. A portion of the extended contact extends past an end of the semiconductor fin in a direction orthogonal to a channel of the semiconductor fin. A contact extension is formed on the portion of the extended contact extending past the end of the semiconductor fin. A contact is formed on the first doped region.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: November 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Terence B. Hook, Joshua M. Rubin, Tenko Yamashita
  • Patent number: 10121854
    Abstract: Provided are electronic devices and methods of manufacturing same. An electronic device includes an energy barrier forming layer on a substrate, an upper channel material layer on the substrate, and a gate electrode that covers the upper channel material layer and the energy barrier forming layer. The gate electrode includes a side gate electrode portion that faces a side surface of the energy barrier forming layer. The side gate electrode may be configured to cause an electric field to be applied directly on the energy barrier forming layer via the side surface of the energy barrier forming layer, thereby enabling adjustment of the energy barrier between the energy barrier forming layer and the upper channel material layer. The electronic device may further include a lower channel material layer that is provided on the substrate and does not contact the upper channel material layer.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: November 6, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinseong Heo, Kiyoung Lee, Jaeho Lee, Seongjun Park
  • Patent number: 10103266
    Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a lower fin that protrudes from a substrate and extends in a first direction, an oxide film the lower fin, an upper fin that protrudes from the oxide film and that is spaced apart from the lower fin at a position corresponding to the lower fin, and a gate structure the upper fin that extends in a second direction to intersect the upper fin, wherein germanium (Ge) is included in a portion of the oxide film located between the lower fin and the upper fin.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: October 16, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Kim, Kyung-Seok Oh, Cheol Kim, Heon-Jong Shin, Jong-Ryeol Yoo, Hyun-Jung Lee, Seong-Hoon Jeong
  • Patent number: 10084128
    Abstract: Provided is a method for increasing a driving current of a junctionless transistor that includes: a substrate; a source region and a drain region which are formed on the substrate and are doped with the same type of dopant; a nanowire channel region which connects the source region and the drain source and is doped with the same type dopant as that of the source region and the drain region; a gate insulation layer which is formed to surround the nanowire channel region; and a gate electrode which is formed on the gate insulation layer and is formed to surround the nanowire channel region. An amount of current flowing through the nanowire channel region is increased by joule heat generated by applying a voltage to the source region and the drain region.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: September 25, 2018
    Assignees: Korea Advanced Institute of Science and Technology, Center for Integrated Smart Sensors Foundation
    Inventors: Yang-Kyu Choi, Jun-Young Park, Chang-Hoon Jeon
  • Patent number: 10084102
    Abstract: A plasmon-enhanced terahertz graphene-based photodetector exhibits an increased absorption efficiency attained by utilizing a tunable plasmonic resonance in sub-wavelengths graphene micro-ribbons formed on SiC substrate in contact with an array of bi-metallic electrode lines. The orientation of the graphene micro-ribbons is tailored with respect to the array of sub-wavelengths bi-metallic electrode lines. The graphene micro-ribbons extend at the angle of approximately 45 degrees with respect to the electrode lines in the bi-metal electrodes array. The plasmonic mode is efficiently excited by an incident wave polarized perpendicular to the electrode lines, and/or to the graphene micro-ribbons. The absorption of radiation by graphene is enhanced through tunable geometric parameters (such as, for example, the width of the graphene micro-ribbons) and control of a carrier density in graphene achieved through tuning the gate voltage applied to the photodetector.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: September 25, 2018
    Assignees: University of Maryland, College Park, The United States of America, as represented by the Secretary of the Navy, Monash University
    Inventors: Xinghan Cai, Andrei B. Sushkov, Mohammad M. Jadidi, David Kurt Gaskill, Thomas E. Murphy, Michael Fuhrer, Howard Dennis Drew
  • Patent number: 10084055
    Abstract: A method is presented for forming a nanosheet structure having a uniform threshold voltage (Vt). The method includes forming a conductive barrier surrounding a nanosheet, forming a first work function conducting layer over the conductive barrier layer, and forming a conducting layer adjacent the first work function conducting layer, the conducting layer defining a first region and a second region. The method further includes forming a second work function conducting layer over the second region of the conducting layer to compensate for threshold voltage offset between the first and second regions of the conducting layer.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: September 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Hemanth Jagannathan, Paul C. Jamison, ChoongHyun Lee, Vijay Narayanan, Koji Watanabe
  • Patent number: 10083879
    Abstract: A method for fabricating a semiconductor nanowire device includes forming a base including a plurality of PMOS regions, forming a plurality of first openings in the base of the PMOS regions, forming a plurality of first epitaxial wires by filling the first openings with a germanium-containing material, and forming a plurality of second openings in the base by etching a portion of the base under each first epitaxial wire. Each first epitaxial wire is connected to both sidewalls of a corresponding second opening and is hung above a bottom surface of the corresponding second opening. The method also includes performing a thermal oxidation treatment process on the plurality of first epitaxial wires to form an oxide layer on each first epitaxial wire, forming a plurality of first nanowires by removing the oxide layer from each first epitaxial wire, and forming a first wrap-gate structure to surround each first nanowire.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: September 25, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Deyuan Xiao
  • Patent number: 10083869
    Abstract: Stacked devices and circuits formed by stacked devices are described. In accordance with some embodiments, a semiconductor post extends vertically from a substrate. A first source/drain region is in the semiconductor post. A first gate electrode layer laterally surrounds the semiconductor post and is vertically above the first source/drain region. A first gate dielectric layer is interposed between the first gate electrode layer and the semiconductor post. A second source/drain region is in the semiconductor post and is vertically above the first gate electrode layer. The second source/drain region is connected to a power supply node. A second gate electrode layer laterally surrounds the semiconductor post and is vertically above the second source/drain region. A second gate dielectric layer is interposed between the second gate electrode layer and the semiconductor post. A third source/drain region is in the semiconductor post and is vertically above the second gate electrode layer.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: September 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ta-Pen Guo, Carlos H. Diaz, Chih-Hao Wang, Jean-Pierre Colinge
  • Patent number: 10056523
    Abstract: A method of making a device comprises forming a layer comprising quantum dots over a substrate including a first electrode, fixing the layer comprising quantum dots formed over the substrate, and exposing at least a portion of, and preferably all, exposed surfaces of the fixed layer comprising quantum dots to small molecules. The layer comprising quantum dots can be preferably fixed in the absence or substantial absence of oxygen. Also disclosed is a method of making a device comprises forming a layer comprising quantum dots over a substrate including a first electrode, exposing the layer comprising quantum dots to small molecules and light flux.
    Type: Grant
    Filed: November 13, 2016
    Date of Patent: August 21, 2018
    Assignee: SAMSUNG RESEARCH AMERICA, INC.
    Inventors: Peter T. Kazlas, John Spencer Morris, Robert J. Nick, Zoran Popovic, Matthew Stevenson, Jonathan S. Steckel
  • Patent number: 10038060
    Abstract: An n-type metal-oxide-semiconductor (NMOS) transistor comprises a graphene channel with a chemically adsorbed nitrogen dioxide (NO2) layer formed thereon. The NMOS transistor may comprise a substrate having a graphene layer formed thereon and a gate stack formed on a portion of the graphene layer disposed in a channel region that further includes a spacer region. The gate stack may comprise the chemically adsorbed NO2 layer formed on the graphene channel, a high-k dielectric formed over the adsorbed NO2 layer, a gate metal formed over the high-k dielectric, and spacer structures formed in the spacer region. The adsorbed NO2 layer formed under the gate and the spacer structures may therefore attract electrons from the graphene channel to turn the graphene-based NMOS transistor off at a gate voltage (Vg) equal to zero, making the graphene-based NMOS transistor suitable for digital logic applications.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: July 31, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Yong Ju Lee, Yang Du
  • Patent number: 10036101
    Abstract: The present invention provides a method and a system for forming wires (1) that enables a large scale process combined with a high structural complexity and material quality comparable to wires formed using substrate-based synthesis. The wires (1) are grown from catalytic seed particles (2) suspended in a gas within a reactor. Due to a modular approach wires (1) of different configuration can be formed in a continuous process. In-situ analysis to monitor and/or to sort particles and/or wires formed enables efficient process control.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: July 31, 2018
    Assignee: QUNANO AB
    Inventors: Lars Samuelson, Martin Magnusson, Knut Deppert, Magnus Heurlin
  • Patent number: 10032678
    Abstract: Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices are disclosed. In one aspect, an exemplary CMOS device includes a nanowire channel structure that includes a plurality of continuously stacked nanowires. Vertically adjacent nanowires are connected at narrow top and bottom end portions of each nanowire. Thus, the nanowire channel structure comprises a plurality of narrow portions that are narrower than a corresponding plurality of central portions. A wrap-around gate material is disposed around the nanowire channel structure, including the plurality of narrow portions, without entirely wrapping around any nanowire therein. The exemplary CMOS device provides, for example, a larger effective channel width and better gate control than a conventional fin field-effect transistor (FET) (FinFET) of a similar footprint. The exemplary CMOS device further provides, for example, a shorter nanowire channel structure than a conventional nanowire FET.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: July 24, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Jeffrey Junhao Xu, Stanley Seungchul Song, Da Yang, Vladimir Machkaoutsan, Mustafa Badaroglu, Choh Fei Yeap
  • Patent number: 10034382
    Abstract: A method of manufacturing a flexible electronic device is provided. The method includes a) filtering a mixture including an electrically conducting nanostructured material through a membrane such that the electrically conducting nanostructured material is deposited on the membrane; b) depositing an elastomeric polymerizable material on the electrically conducting nanostructured material and curing the elastomeric polymerizable material thereby embedding the electrically conducting nanostructured material in an elastomeric polymer thus formed; and c) separating the elastomeric polymer with the embedded electrically conducting nanostructured material from the membrane to obtain the flexible electronic device. Flexible electronic device manufactured by the method, and use of the flexible electronic device are also provided.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: July 24, 2018
    Assignee: Nanyang Technology University
    Inventors: Chaoyi Yan, Pooi See Lee
  • Patent number: 9997598
    Abstract: A semiconductor device including a substrate and a gate region of a field effect transistor formed on the substrate. The gate region includes vertically stacked nanowires having longitudinal axes that extend parallel with a working surface of the substrate. A given stack of vertically stacked nanowires includes at least two nanowires vertically aligned in which a p-type nanowire and an n-type nanowire are spatially separated from each other vertically. The semiconductor device further includes a step-shaped connecting structure formed within the gate region that electrically connects each nanowire to positions above the gate region. A first gate electrode has a step-shaped profile and connects to a first-level nanowire.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: June 12, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Jeffrey Smith, Anton deVilliers, Nihar Mohanty, Subhadeep Kal, Kandabara Tapily
  • Patent number: 9997421
    Abstract: A test device includes a diode junction layer having a first dopant conductivity region and a second dopant conductivity region formed within the diode junction layer on opposite sides of a diode junction. A first portion of vertical transistors is formed over the first dopant conductivity region as a device under test, and a second portion of vertical transistors is formed over the second dopant conductivity region. A common source/drain region is formed over the first and second portions of vertical transistors. Current through the first portion of vertical transistors permits measurement of a resistance at a probe contact connected to the common source/drain region.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Zuoguang Liu, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 9978678
    Abstract: Embodiments are directed to a method and resulting structures for forming a semiconductor device having a vertically integrated nanosheet fuse. A nanosheet stack is formed on a substrate. The nanosheet stack includes a semiconductor layer formed between an upper nanosheet and a lower nanosheet. The semiconductor layer is modified such that an etch rate of the modified semiconductor layer is greater than an etch rate of the upper and lower nanosheets when exposed to an etchant. Portions of the modified semiconductor layer are removed to form a cavity between the upper and lower nanosheets and a silicide region is formed in the upper nanosheet.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: May 22, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robin H. Chao, James J. Demarest, Nicolas J. Loubet