Thin Active Physical Layer Which Is (1) An Active Potential Well Layer Thin Enough To Establish Discrete Quantum Energy Levels Or (2) An Active Barrier Layer Thin Enough To Permit Quantum Mechanical Tunneling Or (3) An Active Layer Thin Enough To Permit Carrier Transmission With Substantially No Scattering (e.g., Superlattice Quantum Well, Or Ballistic Transport Device) Patents (Class 257/9)
  • Patent number: 10845506
    Abstract: Provided is a coated optical element that includes: an optical element; and a coating disposed on the optical element. The coating includes at least one layer of a topological insulator.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: November 24, 2020
    Assignee: THE BOEING COMPANY
    Inventors: Jeffrey H. Hunt, Angela W. Li, Wayne R. Howe
  • Patent number: 10826009
    Abstract: A quantum dot light-emitting diode and a display apparatus comprising the quantum dot light-emitting diode are provided. The quantum dot light-emitting diode comprises an anode, a hole injecting layer, a hole transporting layer, a quantum dot light-emitting layer, an electron transporting layer and a cathode from bottom to top, wherein the materials of the quantum dot light-emitting layer contain quantum dots and CuSCN nano-particles. By blending quantum dots and CuSCN nano-particles into a membrane to prepare a quantum dot light-emitting layer, a hole trap state on the surface of the quantum dots is passivated, and the transporting effect of a hole is improved, so that the injection of holes in the quantum dot light-emitting diode and that of electrons achieve balance, and thus the light-emitting efficiency and stability are improved.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: November 3, 2020
    Assignee: TCL TECHNOLOGY GROUP CORPORATION
    Inventors: Zhurong Liang, Weiran Cao
  • Patent number: 10804235
    Abstract: A method for manufacturing connection structure, the method includes arranging conductive particles and a first composite on a first electrode located on a first surface of a first member, arranging a second composite on the first electrode and a region other than the first electrode of the first surface, arranging the first surface and a second surface of a second member where a second electrode is located, so that the first electrode and the second electrode are opposed to each other, pressing the first member and the second member, and curing the first composite and the second composite.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: October 13, 2020
    Assignee: MIKUNI ELECTRON CORPORATION
    Inventor: Sakae Tanaka
  • Patent number: 10804416
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to graphene detectors integrated with optical waveguide structures and methods of manufacture. The structure includes a plurality of non-planar fin structures composed of substrate material, and a non-planar sheet of graphene material extending entirely over each of the plurality of non-planar fin structures.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: October 13, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Ajey P. Jacob
  • Patent number: 10777727
    Abstract: An efficiency-enhanced, three-terminal, bi-junction thermoelectric device driven by independently-adjustable parameters of temperature and voltage.
    Type: Grant
    Filed: September 9, 2012
    Date of Patent: September 15, 2020
    Assignees: YEDA RESEARCH AND DEVELOPMENT CO. LTD., BEN GURION UNIVERSITY OF THE NEGEV RESEARCH AND DEVELOPMENT AUTHORITY
    Inventors: Yoseph Imry, Ora Entin-Wohlman, JianHua Jiang
  • Patent number: 10770989
    Abstract: Example embodiments relate to an electrode structure, a triboelectric generator including the electrode structure, and a method of manufacturing the electrode structure. The electrode structure includes a flexible layer configured to be bendable by an external force and an electrode, at least some regions thereof being embedded in the flexible layer.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: September 8, 2020
    Assignees: Samsung Electronics Co., Ltd., Research & Business Foundation Sungkyunkwan University
    Inventors: Hyeonjin Shin, Jeongho Cho, Hyungseok Kang, Han Kim, Sangwoo Kim, Seongsu Kim, Siuk Cheon
  • Patent number: 10748908
    Abstract: A method of fabricating a semiconductor device includes forming a device isolation layer in a substrate to define active regions, forming a conductive layer on the active regions, forming first mask patterns intersecting the active regions on the conductive layer, etching the conductive layer using the first mask patterns as etch masks to form bit lines, growing second mask patterns from top surfaces of the first mask patterns, and performing a patterning process using the second mask patterns as etch masks to form contact holes exposing the active regions between the bit lines.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: August 18, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Heon Lee, Munjun Kim, ByeongJu Bae
  • Patent number: 10741677
    Abstract: Embodiments of the present invention are directed to a method that incorporates a germanium pull-out process to form semiconductor structures having stacked silicon nanotubes. In a non-limiting embodiment of the invention, a sacrificial layer is formed over a substrate. The sacrificial layer includes a first type of semiconductor material. A pull-out layer is formed on the sacrificial layer. The first type of semiconductor material from the sacrificial layer is removed to form a silicon-rich layer on a surface of the sacrificial layer. The sacrificial layer can be removed such that the silicon-rich layer defines a silicon nanotube.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juntao Li, Kangguo Cheng, Choonghyun Lee, Peng Xu
  • Patent number: 10734500
    Abstract: Various transistors, such as horizontal gate-all-around transistors, and methods of fabricating such are disclosed herein. An exemplary transistor includes a first nanowire and a second nanowire that include a first semiconductor material, a gate that wraps a channel region of the first nanowire and the second nanowire, and source/drain feature that wraps source/drain regions of the first nanowire and the second nanowire. The source/drain feature includes a second semiconductor material that is configured differently than the first semiconductor material. In some implementations, the transistor further includes a fin-like semiconductor layer disposed over a substrate. The first nanowire and the second nanowire are disposed over the fin-like semiconductor layer, such that the first nanowire, the second nanowire, and the fin-like semiconductor layer extend substantially parallel to one another along the same length-wise direction.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hsiung Lin, Chung-Cheng Wu, Carlos H. Diaz, Chih-Hao Wang, Wen-Hsing Hsieh, Yi-Ming Sheu
  • Patent number: 10732441
    Abstract: Compact electro-optic modulator with integrated voltage-switched transparent conductive oxide capacitor with one-dimensional silicon photonic crystal nano-cavity.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: August 4, 2020
    Assignee: OREGON STATE UNIVERSITY
    Inventors: Alan Wang, Erwen Li
  • Patent number: 10714569
    Abstract: Strained nanosheet field effect transistors (FETs) using a phase change material are described herein. In some embodiments, a semiconductor device can comprise alternating layers of a channel material and a phase change material to produce strained nanosheet field effect transistors, wherein the layers of the phase change material cause a strain in the layers of the channel material. The phase change material comprises germanium antimony telluride. The germanium antimony telluride crystallizes into a crystalline germanium antimony telluride based on annealing above 300 degrees Celsius and a volume of the crystalline germanium antimony telluride is reduced up to six percent relative to an initial volume the germanium antimony telluride to cause the strain in the layers of the channel material. The semiconductor device can also comprise source and drain epitaxial growths on both ends of the layers of the channel material that lock the strain in the layers of the channel material.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: July 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dexin Kong, Kangguo Cheng, Juntao Li, Zhenxing Bi
  • Patent number: 10700066
    Abstract: A semiconductor device comprises a substrate having an N-type field effect transistor (NFET) region and a P-type field effect transistor (PFET) region, a plurality of first nanowires in the PFET region and arranged in a first direction substantially perpendicular to the substrate and a plurality of second nanowires in the NFET region and arranged in the first direction. A composition of the first nanowires is different from a composition of the second nanowires, and one of the first nanowires is substantially aligned with one of the second nanowires in a second direction substantially perpendicular to the first direction.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Winnie Victoria Wei-Ning Chen, Meng-Hsuan Hsiao, Tung-Ying Lee, Pang-Yen Tsai, Yasutoshi Okuno
  • Patent number: 10663773
    Abstract: The spin-Hall effect can be used to modulate the linear polarization of light via the magneto-optical Kerr effect. A central area of an outer surface of an added layer atop a spin Hall material is illuminated while simultaneously passing a modulated electric current through the material, so that reflected light has a new linear polarization that differs from the initial linear polarization to a degree depending on the amplitude of the modulated electric current.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: May 26, 2020
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Olaf M. J. van 't Erve, Connie H. Li, Berend T. Jonker, Aubrey T. Hanbicki, Kathleen M. Mccreary
  • Patent number: 10665671
    Abstract: Disclosed is a method of manufacturing a junctionless transistor based on vertically integrated gate-all-around multiple nanowire channels including forming vertically integrated multiple nanowire channels in which a plurality of nanowires is vertically integrated, forming an interlayer dielectric layer (ILD) on the vertically integrated multiple nanowire channels, forming a hole in the interlayer dielectric layer such that at least some of the vertically integrated multiple nanowire channels is exposed, and forming a gate dielectric layer on the interlayer dielectric layer to fill the hole, wherein the forming of the gate dielectric layer on the interlayer dielectric layer to fill the hole includes depositing the gate dielectric layer on the interlayer dielectric layer to surround at least some of the vertically integrated multiple nanowire channels which is exposed though the hole.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: May 26, 2020
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Yang-Kyu Choi, Byung-Hyun Lee, Min-Ho Kang
  • Patent number: 10657456
    Abstract: An apparatus for performing quantum computing includes multiple qubits, each of at least a subset of the qubits comprising a loop formed of a Dirac or Weyl semimetal and having at least two stable quantum states. The apparatus further includes at least one terahertz cavity coupled with the qubits, the terahertz cavity being configured to detect the quantum states of the qubits. Each of at least the subset of qubits is configured to receive a circularly polarized radiation source. The radiation source is adapted to excite a chiral current in each of at least the subset of qubits, the quantum states of the plurality of qubits being a function of the chiral current.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: May 19, 2020
    Assignees: BROOKHAVEN SCIENCE ASSOCIATES, LLC, THE RESEARCH FOUNDATION FOR THE STATE UNIVERSITY OF NEW YORK
    Inventors: Dmitri Kharzeev, Qiang Li
  • Patent number: 10658542
    Abstract: A quantum dot light-emitting device includes: a first electrode; a second electrode opposite to the first electrode; an emission layer between the first electrode and the second electrode, the emission layer including quantum dots; and an inorganic layer between the emission layer and the second electrode, the inorganic layer including a metal halide.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: May 19, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yisu Kim, Dongchan Kim, Eungseok Park, Wonmin Yun, Byoungduk Lee, Yongchan Ju
  • Patent number: 10643905
    Abstract: There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: May 5, 2020
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Zhengyong Zhu
  • Patent number: 10636585
    Abstract: Provided are a novel method for manufacturing a stack of carbon nanotube and graphene that can improve a capacitor characteristic, an electrode material including the stack of carbon nanotube and graphene, and an electric double-layer capacitor using the same. A method for manufacturing a stack of graphene and carbon nanotube includes a step of dispersing the graphene in an aqueous MOH solution (M represents an element selected from a group consisting of Li, Na, and K) to adsorb MOH on the graphene, a step of heating the graphene with MOH adsorbed thereon that is obtained in the adsorption step in vacuum or in an inert atmosphere in a temperature range of 400° C. or more and 900° C. or less to form pores in the graphene, and a step of dispersing the carbon nanotube and the graphene with the pores that are obtained in the step of forming the pores in a dispersion medium to stack the carbon nanotube and the graphene with the pores.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: April 28, 2020
    Assignee: NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Jie Tang, Kun Zhang, Jing Li, Jinshi Yuan, Luchang Qin, Norio Shinya
  • Patent number: 10629498
    Abstract: There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: April 21, 2020
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Zhengyong Zhu
  • Patent number: 10622466
    Abstract: A semiconductor structure includes a substrate, an isolation layer disposed over the substrate, a plurality of nanosheet channels, interfacial layers surrounding each of the nanosheet channels, and dielectric layers surrounding each of the interfacial layers. The plurality of nanosheet channels includes first and second sets of two or more nanosheet channels for first and second NFETs and third and fourth sets of two or more nanosheet channels for first and second PFETs. The interfacial layers surrounding the first and third sets of nanosheet channels for the first NFET and the first PFET have a first thickness, and interfacial layers surrounding the second and fourth sets of nanosheets channels for the second NFET and the second PFET have a second thickness smaller than the first thickness. The first NFET has a higher threshold voltage than the second NFET, and the first PFET has a lower threshold voltage than the second PFET.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: April 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, ChoongHyun Lee, Jingyun Zhang, Pouya Hashemi
  • Patent number: 10621140
    Abstract: Techniques for improving the performance of a quantum processor are described. The techniques include reading out a fraction of the qubits in a quantum processor and utilizing one or more post-processing operations to reconstruct qubits of the quantum processor that are not read. The reconstructed qubits may be determined using a perfect sampler to provide results that are strictly better than reading all of the qubits directly from the quantum processor. The composite sample that includes read qubits and reconstructed qubits may be obtained faster than if all qubits of the quantum processor are read directly.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: April 14, 2020
    Assignee: D-WAVE SYSTEMS INC.
    Inventor: Jack Raymond
  • Patent number: 10607993
    Abstract: A quantum device with spin qubits, comprising: a first semiconducting layer comprising a first matrix of data qubits and measurement qubits connected to each other through tunnel barriers; means of addressing qubits configured for controlling conduction of each tunnel barrier by the field effect and comprising: first and second conducting portions arranged in first and second superposed metallisation levels respectively; first and second conducting vias each comprising a first end connected to one of the first and second conducting portions respectively, and a second end located facing one of the tunnel barriers; a first dielectric layer interposed between the tunnel barriers and the second ends of the first and second conducting vias.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: March 31, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Louis Hutin, Silvano De Franceschi, Tristan Meunier, Maud Vinet
  • Patent number: 10600638
    Abstract: A method of forming a semiconductor device and resulting structures having nanosheet transistors with sharp junctions by forming a nanosheet stack over a substrate, the nanosheet stack having a plurality of nanosheets alternating with a plurality of sacrificial layers, such that a topmost and a bottommost layer of the nanosheet stack is a sacrificial layer; forming an oxide recess on a first and a second end of each sacrificial layer; and forming a doped extension region on a first and a second end of each nanosheet.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: March 24, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Lawrence A. Clevenger, Balasubramanian S. Pranatharthi Haran, John Zhang
  • Patent number: 10600696
    Abstract: There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: March 24, 2020
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Zhengyong Zhu
  • Patent number: 10600881
    Abstract: The present disclosure relates to a tunneling field-effect transistor and a fabrication method. One example transistor includes a semiconductor substrate, a semiconductor nanosheet, a source region and a drain region, a dielectric layer, and a gate metal layer. The semiconductor nanosheet is vertically disposed on the semiconductor substrate. The source region and the drain region are connected using a channel. The drain region, the channel, and the source region are disposed on the semiconductor nanosheet in turn. The drain region is in contact with the semiconductor substrate. The source region is located at an end, of the semiconductor nanosheet, far away from the semiconductor substrate. The dielectric layer comprises at least a gate dielectric layer, is disposed on a surface of the semiconductor nanosheet, and surrounds the channel. The gate metal layer is disposed on a surface of the gate dielectric layer and surrounds the gate dielectric layer.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: March 24, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Xichao Yang, Chen-Xiong Zhang
  • Patent number: 10583452
    Abstract: A method for coating a thin film in a rolling manner and a thin film coating apparatus are provided. The method includes: floating a thin film material on a liquefied material; rolling a cylindrical substrate after contacting the cylindrical substrate with the thin film material; and coating the thin film material on a surface of the cylindrical substrate by using an attraction force between the surface of the cylindrical substrate and the thin film material.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: March 10, 2020
    Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Taek-Soo Kim, Sumin Kang
  • Patent number: 10578891
    Abstract: Embodiments are directed to a microwave-to-optical transducer device. The device includes an anchorage structure that includes a bar extending in a plane and laterally delimiting two voids on each longitudinal side of the bar. That is, the two voids are arranged side-by-side in said plane. The device further includes a piezoelectric beam structured as an optical cavity (e.g., as a 1D photonic crystal cavity), where the beam extends transversally to the bar, parallel to said plane, and is anchored on a resting point on the bar. The beam extends outwardly, beyond the resting point and on each side thereof, so as to overhang each of the two voids. Embodiments are further directed to related microwave circuits, including a microwave-to-optical transducer such as described above and, in particular, to superconducting microwave circuits configured as quantum information processing devices.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: March 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Katharina Schmeing, Paul F. Seidler
  • Patent number: 10559675
    Abstract: Embodiments of the present invention are directed to a method that incorporates a germanium pull-out process to form semiconductor structures having stacked silicon nanotubes. In a non-limiting embodiment of the invention, a sacrificial layer is formed over a substrate. The sacrificial layer includes a first type of semiconductor material. A pull-out layer is formed on the sacrificial layer. The first type of semiconductor material from the sacrificial layer is removed to form a silicon-rich layer on a surface of the sacrificial layer. The sacrificial layer can be removed such that the silicon-rich layer defines a silicon nanotube.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: February 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juntao Li, Kangguo Cheng, Choonghyun Lee, Peng Xu
  • Patent number: 10553496
    Abstract: A complementary metal-oxide-semiconductor field-effect transistor comprises a semiconductor substrate, N-type and P-type field-effect transistors positioned in the semiconductor substrate. Each of the field-effect transistors includes a germanium nanowire, a III-V compound layer surrounding the germanium nanowire, a potential barrier layer mounted on the III-V compound layer, a gate dielectric layer, a gate, a source region and a drain region mounted on two sides of the gate. The field-effect transistor can produce two-dimensional electron gases and two-dimensional electron hole gases, and enhance the carrier mobility of the complementary metal-oxide-semiconductor field-effect transistor.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: February 4, 2020
    Assignee: Zing Semiconductor Corporation
    Inventor: Deyuan Xiao
  • Patent number: 10546994
    Abstract: A technique relates a superconducting microwave cavity. An array of posts has different heights in the cavity, and the array supports a localized microwave mode. The array of posts includes lower resonant frequency posts and higher resonant frequency posts. The higher resonant frequency posts are arranged around the lower resonant frequency posts. A first plate is opposite a second plate in the cavity. One end of the lower resonant frequency posts is positioned on the second plate so as to be electrically connected to the second plate. Another end of the lower resonant frequency posts in the array is open so as not to form an electrical connection to the first plate. Qubits are connected to the lower resonant frequency posts in the array of posts, such that each of the qubits is physically connected to one or two of the lower resonant frequency posts in the array of posts.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oliver Dial, Jay M. Gambetta, Douglas T. McClure, III, Matthias Steffen
  • Patent number: 10546957
    Abstract: A semiconductor device includes a semiconductor wafer having one or more suspended nanosheet extending between first and second source/drain regions. A gate structure wraps around the nanosheet stack to define a channel region located between the source/drain regions. The semiconductor device further includes a first all-around source/drain contact formed in the first source/drain region and a second all-around source/drain contact formed in the second source/drain region. The first and second all-around source/drain contacts each include a source/drain epitaxy structure and an electrically conductive external portion that encapsulates the source/drain epitaxy structure.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peng Xu, Chun Wing Yeung, Chen Zhang
  • Patent number: 10535737
    Abstract: A semiconductor device includes a substrate, a channel structure, and a gate structure. The channel structure is over the substrate and extends along a first direction, in which the channel structure has plurality of first portions and plurality of second portions alternately stacked, and a width of the first portions is smaller than that of the second portions in a second direction different from the first direction. The gate structure is disposed over the substrate and crossing the channel structure along the second direction, in which the gate structure is in contact with the first portions and the second portions.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: January 14, 2020
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Fang-Liang Lu, Chia-Che Chung, Yu-Jiun Peng, Chee-Wee Liu
  • Patent number: 10522622
    Abstract: A multi-gate semiconductor structure includes a plurality of nanowires, a gate structure disposed over the plurality of nanowires, and source/drain structures at two ends of each of the plurality of nanowires. The source/drain structures include a conductor, and a bottom surface of the conductor is lower than the plurality of nanowires.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, I-Sheng Chen, Tzu-Chiang Chen, Shih-Syuan Huang, Hung-Li Chiang
  • Patent number: 10522694
    Abstract: A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a core region, and one or more shell regions. The core region has an approximately square-shape cross section and a first shell of the one or more shells forms a first shell region of an approximately rhombus-shape cross section around the core region and is connected to an adjacent first shell region corresponding to a neighboring semiconductor wire.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Sheng Chen, Szu-Wei Huang, Hung-Li Chiang, Cheng-Hsien Wu, Chih Chieh Yeh
  • Patent number: 10489477
    Abstract: Systems, devices, articles, methods, and techniques for advancing quantum computing by removing unwanted interactions in one or more quantum processor. One approach includes creating an updated plurality of programmable parameters based at least in part on a received value for the characteristic magnetic susceptibility of the qubit in the at least one quantum processor, and returning the updated plurality of programmable parameters. Examples programmable parameters include local biases, and coupling values characterizing the problem Hamilton.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: November 26, 2019
    Assignee: D-WAVE SYSTEMS INC.
    Inventor: Trevor Michael Lanting
  • Patent number: 10483105
    Abstract: Provided is a method for growing a nanowire, including: providing a substrate with a base portion having a first surface and at least one support structure extending above or below the first surface; forming a dielectric coating on the at least one support structure; forming a photoresist coating over the substrate; forming a metal coating over at least a portion of the dielectric coating; removing a portion of the dielectric coating to expose a surface of the at least one support structure; removing a portion of the at least one support structure to form a nanowire growth surface; growing at least one nanowire on the nanowire growth surface of a corresponding one of the at least one support structure, wherein the nanowire comprises a root end attached to the growth surface and an opposing, free end extending from the root end; and elastically bending the at least one nanowire.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: November 19, 2019
    Assignee: STC.UNM
    Inventors: Seung-Chang Lee, Steven R. J. Brueck
  • Patent number: 10468312
    Abstract: There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: November 5, 2019
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Zhengyong Zhu
  • Patent number: 10446719
    Abstract: The disclosed technology provides micro-assembled micro-LED displays and lighting elements using arrays of micro-LEDs that are too small (e.g., micro-LEDs with a width or diameter of 10 ?m to 50 ?m), numerous, or fragile to assemble by conventional means. The disclosed technology provides for micro-LED displays and lighting elements assembled using micro-transfer printing technology. The micro-LEDs can be prepared on a native substrate and printed to a display substrate (e.g., plastic, metal, glass, or other materials), thereby obviating the manufacture of the micro-LEDs on the display substrate. In certain embodiments, the display substrate is transparent and/or flexible.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: October 15, 2019
    Assignee: X-Celeprint Limited
    Inventors: Christopher Bower, Matthew Meitl, David Gomez, Salvatore Bonafede, David Kneeburg, Alin Fecioru, Carl Prevatte
  • Patent number: 10431663
    Abstract: Disclosed are methods for forming an integrated circuit with a nanowire-type field effect transistor and the resulting structure. A sacrificial gate is formed on a multi-layer fin. A sidewall spacer is formed with a gate section on the sacrificial gate and fin sections on exposed portions of the fin. Before or after removal of the exposed portions of the fin, the fins sections of the sidewall spacer are removed or reduced in size without exposing the sacrificial gate. Thus, the areas within which epitaxial source/drain regions are to be formed will not be bound by sidewall spacers. Furthermore, isolation material, which is deposited into these areas prior to epitaxial source/drain region formation and which is used to form isolation elements between the transistor gate and source/drain regions, can be removed without removing the isolation elements. Techniques are also disclosed for simultaneous formation of a nanosheet-type and/or fin-type field effect transistors.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: October 1, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Balasubramanian Pranatharthiharan, Pietro Montanini, Julien Frougier
  • Patent number: 10430493
    Abstract: Disclosed are systems and methods for performing efficient vector-matrix multiplication using a sparsely-connected conductance matrix and analog mixed signal (AMS) techniques. Metal electrodes are sparsely connected using coaxial nanowires. Each electrode can be used as an input/output node or neuron in a neural network layer. Neural network synapses are created by random connections provided by coaxial nanowires. A subset of the metal electrodes can be used to receive a vector of input voltages and the complementary subset of the metal electrodes can be used to read output currents. The output currents are the result of vector-matrix multiplication of the vector of input voltages with the sparsely-connected matrix of conductances.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: October 1, 2019
    Assignee: Rain Neuromorphics Inc.
    Inventor: Jack Kendall
  • Patent number: 10424696
    Abstract: Provided are a wavelength converting particle, a method for manufacturing a wavelength converting particle, and a light-emitting diode containing a wavelength converting particle. The wavelength converting particle comprises an organic/inorganic/hybrid perovskite nanocrystal that converts a wavelength of light generated by an excitation light source into a specified wavelength. Accordingly, it is possible to optically stabilize and improve color purity and light-emission performance without changes in a light-emitting wavelength range.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: September 24, 2019
    Assignees: POSTECH ACADEMY-INDUSTRY FOUNDATION
    Inventors: Taewoo Lee, Younghoon Kim, Himchan Cho
  • Patent number: 10411090
    Abstract: Hybrid trigate and nanowire CMOS device architecture, and methods of fabricating hybrid trigate and nanowire CMOS device architecture, are described. For example, a semiconductor structure includes a semiconductor device of a first conductivity type having a plurality of vertically stacked nanowires disposed above a substrate. The semiconductor structure also includes a semiconductor device of a second conductivity type opposite the first conductivity type, the second semiconductor device having a semiconductor fin disposed above the substrate.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: Cory E. Weber, Rishabh Mehandru, Stephen M. Cea
  • Patent number: 10403754
    Abstract: Semiconductor devices are provided. A semiconductor device includes a channel. The semiconductor device includes a gate structure having first and second portions. The channel is between the first and second portions of the gate structure. A contact structure is adjacent a portion of a side surface of the channel. Related methods of forming semiconductor devices are also provided.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Dae Suk, Sunhom Steve Paak, Yeon-Ho Park, Dong-Ho Cha
  • Patent number: 10396214
    Abstract: Non-planar semiconductor devices including semiconductor fins or stacked semiconductor nanowires that are electrostatically enhanced are provided. The electrostatic enhancement is achieved in the present application by epitaxially growing a semiconductor material protruding portion on exposed sidewalls of alternating semiconductor material portions of at least one hard mask capped semiconductor-containing fin structure that is formed on a substrate.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 10374035
    Abstract: Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Junli Wang
  • Patent number: 10367033
    Abstract: A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Ombretta Donghi, Marcello Ravasio, Samuele Sciarrillo, Roberto Somaschini
  • Patent number: 10347719
    Abstract: A semiconductor structure. The structure includes first source/drain located in a first source/drain region. The structure includes a second source/drain located in a second source/drain region. The structure includes a plurality of semiconductor nanosheets located between the first source/drain and the second source/drain in a gate region. The structure includes an insulating layer separating the first source drain from a bulk substrate. The bulk substrate may have a first horizontal surface in the gate region, a second horizontal surface in the first source/drain region, and a connecting surface forming an at least partially vertical connection between the first horizontal surface and the second horizontal surface. The insulating layer may be directly on the second horizontal surface and the connecting surface.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 10347760
    Abstract: A reconfigurable field effect transistor (RFET) includes a nanowire, wherein the nanowire comprises two Schottky contacts, as well as two gate contacts partially enclosing the nanowire in cross section. An integrated circuit can be produced therefrom. The aim of producing CMOS circuits with enhanced functionality and a more compact design is achieved in that the nanowire is divided along the cross section thereof into two nanowire parts, wherein each nanowire part comprises a respective Schottky contact and a respective gate contact, and the two nanowire parts are connected electrically to one another via a common substrate and stand vertically on the substrate. In a nanowire-parts-array, between the nanowire parts, a respective top-gate contact and/or back-gate contact can be formed in a substrate defining a substrate plane.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: July 9, 2019
    Assignees: Technische Universität Dresden, NaMLab gGmbH
    Inventors: Tim Baldauf, André Heinzig, Walter Michael Weber
  • Patent number: 10333027
    Abstract: Disclosed in one embodiment is a light-emitting device comprising: a first semiconductor layer; an active layer arranged on the first semiconductor layer and including a plurality of first uneven portions; an electron blocking layer including a plurality of second uneven portions arranged on the plurality of first uneven portions; and a second semiconductor layer formed on the electron blocking layer, wherein the electron blocking layer has at least two doping concentration peak sections of a p-type dopant in the thickness direction.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: June 25, 2019
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Chong Cook Kim
  • Patent number: 10332961
    Abstract: Embodiments are directed to a method of fabricating inner spacers of a nanosheet FET. The method includes forming sacrificial and channel nanosheets over a substrate, removing sidewall portions of the sacrificial nanosheet, and forming a dielectric that extends over the channel nanosheet and within a space that was occupied by the removed sidewall portions of the sacrificial nanosheet. The method further includes forming a top protective spacer over the channel nanosheet and the dielectric, as well as applying a directional etch to the top protective spacer, the channel nanosheet, and the dielectric, wherein the directional etch is configured to be selective to the channel nanosheet and the dielectric, wherein the directional etch is configured to not be selective to the top protective spacer, and wherein applying the directional etch etches portions of the channel nanosheet and portions of the flowable dielectric that are not under the top dielectric.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: June 25, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-chen Yeh