Abstract: A transistor device having fin structures, source and drain terminals, channel layers and a gate structure is provided. The fin structures are disposed on a material layer. The fin structures are arranged in parallel and extending in a first direction. The source and drain terminals are disposed on the fin structures and the material layer and cover opposite ends of the fin structures. The channel layers are disposed respectively on the fin structures, and each channel layer extends between the source and drain terminals on the same fin structure. The gate structure is disposed on the channel layers and across the fin structures. The gate structure extends in a second direction perpendicular to the first direction. The materials of the channel layers include a transition metal and a chalcogenide, the source and drain terminals include a metallic material, and the channel layers are covalently bonded with the source and drain terminals.

Abstract: Gate-all-around (GAA) device and the manufacturing method thereof are disclosed herein. An exemplary integrated circuit (IC) device comprises a first nanostructure and a second nanostructure formed on a substrate, wherein each of the first nanostructure and the second nanostructure includes a plurality of semiconductor layers and each of the first nanostructure and the second nanostructure includes a channel region and a source/drain (S/D) region; a first gate structure wrapping the plurality of semiconductor layers of the first nanostructure and a second gate structure wrapping the plurality of semiconductor layers of the second nanostructure; and a S/D contact that contacts at least one of the plurality of semiconductor layers of the first nanostructure and at least one of the plurality of semiconductor layers of the second nanostructure.

Abstract: A field-effect transistor and a method for controlling such is provided herein. The field-effect transistor includes a source terminal and a drain terminal arranged on a first side of a semiconductor layer and a single gate arranged on a second side of the semiconductor layer opposite the first side. The gate and the source terminal are arranged to overlap with a first common region of the semiconductor layer and the gate and the drain terminal are arranged to overlap with a second common region of the semiconductor layer.

Abstract: High-performance carbon nanotube (CNT) based millimeter-wave transistor technologies and demonstrate monolithic millimeter-wave integrated circuits (MMICs) based thereon, and methods and processes for the fabrication thereof are also provided. CNT technologies and MMICs demonstrate improved power efficiency, linearity, noise and dynamic range performance over existing GaAs, SiGe and RF-CMOS technologies. Methods and processes in CNT alignment and deposition, material contact and doping are configured to fabricate high quality CNT arrays beyond the current state-of-the-art and produce high performance RF transistors that are scalable to wafer size to enable fabrication of monolithic integrated circuits based on CNTs.

Abstract: A semiconductor structure includes a semiconductor substrate, a first source/drain portion, a second source/drain portion, a first metal contact, a second metal contact and a first conductive carbon layer. The first and second source/drain portions are formed over the semiconductor substrate, and are spaced apart from each other. The first source/drain portion has a conductivity type different from that of the second source/drain portion. The first and second metal contacts are respectively formed on the first and second source/drain portions. The first conductive carbon layer is formed between the first source/drain portion and the first metal contact.

Abstract: Channel engineering is employed to obtain a gate-all-around field-effect transistor having an asymmetric threshold voltage. A dual channel profile enables a steep potential distribution near the source side that enhances the lateral channel electric field and thus increases the carrier mobility.

Abstract: The present disclosure combines chemical mechanical polishing (CMP), wet etch and deposition processes to provide improved processes and methods for planarizing an uneven surface of a material layer deposited over a plurality of structures formed on a substrate. A CMP process is initially used to smooth the uneven surface and provide complete local planarization of the material layer above the plurality of structures. After achieving complete local planarization, a wet etch process is used to etch the material layer until a uniform recess is formed between the plurality of structures and the material layer is provided with a uniform thickness across the substrate. In some embodiments, an additional material layer may be deposited and a second CMP process may be used to planarize the additional material layer to provide the substrate with a globally planarized surface.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a channel member including a first channel layer and a second channel layer over the first channel layer, and a gate structure over the channel member. The first channel layer includes silicon, germanium, a III-V semiconductor, or a II-VI semiconductor and the second channel layer includes a two-dimensional material.

Abstract: In a method of forming a gate-all-around field effect transistor, a gate structure is formed surrounding a channel portion of a carbon nanotube. An inner spacer is formed surrounding a source/drain extension portion of the carbon nanotube, which extends outward from the channel portion of the carbon nanotube. The inner spacer includes two dielectric layers that form interface dipole. The interface dipole introduces doping to the source/drain extension portion of the carbon nanotube.

Abstract: One type of plasmonic organic electrochemical transistor (POECT) includes a channel comprising an organic semiconductor, a gate electrode comprising at least one of: an ensemble of nanoparticles and an array of nanostructures, wherein each of the at least one of: an ensemble of nanoparticles and an array of nanostructures comprises localized plasmonic material, an analyte formed at least one of: (a) over the at least one of: the ensemble of nanoparticles and the array of nanostructures and (b) around the at least one of: the ensemble of nanoparticles and the array of nanostructures, wherein an electrolyte is configured to be formed at least one of: between the channel and the gate electrode and over the channel and the gate electrode, a source electrode electrically connected to a first end of the channel; and a drain electrode electrically connected to a second end of the channel which is opposite the first end.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a heat transfer layer disposed over a substrate, a channel material layer, a gate structure and source and drain terminals. The channel material layer has a first surface and a second surface opposite to the first surface, and the channel material layer is disposed on the heat transfer layer with the first surface in contact with the heat transfer layer. The gate structure is disposed above the channel material layer. The source and drain terminals are in contact with the channel material layer and located at two opposite sides of the gate structure.

Abstract: A method for making a graphene nanoribbon composite structure includes providing a substrate including a plurality of protrusions spaced apart from each other. A graphene film is grown on a growth substrate, an adhesive layer is on a surface of the graphene film away from the growth substrate. After removing the growth substrate, the graphene film and the adhesive layer are cleaned with water or an organic solvent. The graphene film, the adhesive layer, and the substrate are combined and then are dried, so that a plurality of wrinkles are formed near the plurality of protrusions. The adhesive layer is removed, and after etching a surface of the graphene film away from the substrate, the graphene films except for the plurality of wrinkles are removed, to form a plurality of graphene nanoribbons.

Abstract: According to embodiments of the present disclosure, two-dimensional (2D) materials may be used as nanosheet channels for multi-channel transistors. Nanosheet channels made two-dimensional (2D) materials can achieve the same drive current at smaller dimensions and/or fewer number of channels, therefore enable scaling down and/or boost derive current. Embodiments of the present disclosure also provide a solution of P-type and N-type balancing in a device without increasing footprint of the device.

Abstract: Provided are methods of manufacturing comprising providing a FET base structure, the FET base structure comprising a substrate, a drain and a source; and providing a channel layer on the FET base structure; and providing a first layer on the FET base structure. The first layer comprises a one-dimensional or two-dimensional material and is arranged on an upper surface of the channel layer so as to form a sensing surface of the FET. The step of providing the channel layer comprises forming the channel layer and subsequently transferring the channel layer onto the FET base structure. Alternatively or additionally, the step of providing the first layer on the FET base structure comprises forming the first layer and subsequently transferring the first layer onto the FET base structure.

Abstract: Provided are a superlattice structure including a two-dimensional material and a device including the superlattice structure. The superlattice structure may include at least two different two-dimensional (2D) materials bonded to each other in a lateral direction, and an interfacial region of the at least two 2D materials may be strained. The superlattice structure may have a bandgap adjusted by the interfacial region that is strained. The at least two 2D materials may include first and second 2D materials. The first 2D material may have a first bandgap in an intrinsic state thereof. The second 2D material may have a second bandgap in an intrinsic state thereof. An interfacial region of the first and second 2D materials and an adjacent region may have a third bandgap between the first bandgap and the second bandgap.

Abstract: Disclosed herein is a system and method for transistor pathogen virus detector in which one embodiment may include a substrate layer, a silicon dioxide layer on the substrate layer, a nanocrystalline diamond layer on the silicon dioxide layer, a graphene oxide layer on the nanocrystalline diamond layer, fluorinated graphene oxide portions; and a linker layer, the linker layer including a plurality of pathogen receptors.

Abstract: In a method of forming a gate-all-around field effect transistor (GAA FET), a bottom support layer is formed over a substrate and a first group of carbon nanotubes (CNTs) are disposed over the bottom support layer. A first support layer is formed over the first group of CNTs and the bottom support layer such that the first group of CNTs are embedded in the first support layer. A second group of carbon nanotubes (CNTs) are disposed over the first support layer. A second support layer is formed over the second group of CNTs and the first support layer such that the second group of CNTs are embedded in the second support layer. A fin structure is formed by patterning at least the first support layer and the second support layer.

Abstract: Field effect transistors (FET) including quantum layers. A FET may include a substrate, and an oxide layer disposed over the substrate. The oxide layer may include a first section and a second section positioned adjacent the first section. The FET may also include a first quantum layer disposed over the first section of the oxide layer, and a second quantum layer disposed over the second section of the oxide layer, and a first segment of the first quantum layer. Additionally, the FET may include a drain region disposed directly over a second segment the first quantum layer. The second segment of the first quantum layer may be positioned adjacent the first segment of the first quantum layer. The FET may further include a source region disposed over the second quantum layer, and a channel region formed over the second quantum layer, between the drain region and the source region.

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.

Abstract: A method for making a field effect transistor includes providing a graphene nanoribbon composite structure. The graphene nanoribbon composite structure includes a substrate and a plurality of graphene nanoribbons spaced apart from each other. The substrate includes a plurality of protrusions spaced apart from each other, and one of the plurality of graphene nanoribbons is on the substrate and between two adjacent protrusions. An interdigital electrode is placed on the graphene nanoribbon composite structure, and the interdigital electrode covers the plurality of protrusions and is electrically connected to the plurality of graphene nanoribbons.

Abstract: A large-area wrinkled graphene substrate capable of being manufactured in a large-area, and a method for manufacturing the same is provided. A method for manufacturing a wrinkled graphene substrate includes: i) providing a graphene unit; ii) inserting a carrier film and a graphene unit between a pair of rolls and rotating the pair of rolls in opposite directions to attach a carrier film on the graphene unit, iii) immersing the graphene unit in an etching solution to provide graphene, iv) between a pair of rolls, graphene and poly(4-styrene sulfonic acid)/polystyrene (PSS/PS) substrate attaching graphene onto the PSS/PS substrate, v) attaching an ethylene vinyl acetate/polyethylene terephthalate (EVA/PET) substrate to wrinkled graphene on PSS/PS substrate by inserting EVA/PET and WGr/PSS/PS stack between the rolls, viii) removing the PSS/PS substrate by immersing PET/EVA/WGr/PSS/PS stack in water, and ix) providing a wrinkled graphene substrate on the EVA/PET substrate.

Abstract: Embodiments include two-dimensional (2D) semiconductor sheet transistors and methods of forming such devices. In an embodiment, a semiconductor device comprises a stack of 2D semiconductor sheets, where individual ones of the 2D semiconductor sheets have a first end and a second end opposite from the first end. In an embodiment, a first spacer is over the first end of the 2D semiconductor sheets, and a second spacer is over the second end of the 2D semiconductor sheets. Embodiments further comprise a gate electrode between the first spacer and the second spacer, a source contact adjacent to the first end of the 2D semiconductor sheets, and a drain contact adjacent to the second end of the 2D semiconductor sheets.

Abstract: Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.

Abstract: A gate-controlled diode includes a substrate, a gate stacked on the substrate, a gate insulation layer, a first two-dimensional semiconductor layer, a second two-dimensional semiconductor layer, a source, and a drain disposed separately from the source. The gate is embedded in a surface of the substrate, and the gate insulation layer covers the surface of the substrate in which the gate is disposed. The first two-dimensional semiconductor layer is stacked on the gate insulation layer, a portion of the second two-dimensional semiconductor layer is stacked on the gate insulation layer, another portion is stacked on the first two-dimensional semiconductor layer. The another portion of the second two-dimensional semiconductor layer stacked on the first two-dimensional semiconductor layer forms a heterojunction. An orthographic projection of the heterojunction onto the substrate is in an orthographic projection of the gate onto the substrate.

Abstract: A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.

Abstract: A quantum Hall resistance apparatus is to improve resistance standards and includes a substrate, a graphene epitaxially grown on the substrate and having a plurality of first contact patterns at edges of the graphene, a plurality of contacts, each including a second contact pattern and configured to connect to a corresponding first contact pattern, and a protective layer configured to protect the graphene and to increase adherence between the first contact patterns and the second contact patterns. The contacts become a superconductor at a temperature lower than or equal to a predetermined temperature and under up to a predetermined magnetic flux density.

Abstract: An array substrate, a method for fabricating the same, and a display device are provided. The method includes: forming a passivation layer on an array substrate, wherein the array substrate includes a thin film transistor and a conductive pad, and the passivation layer covers the thin film transistor and the conductive pad; forming a full-surface carbon film on the passivation layer; and patterning the carbon film and the passivation layer to remove the passivation layer and the carbon film corresponding to the conductive pad by a patterning process to obtain the array substrate.

Abstract: Heterostructures include a layer of a two-dimensional material placed on a multiferroic layer. An ordered array of differing polarization domains in the multiferroic layer produces corresponding domains having differing properties in the two-dimensional material. When the multiferroic layer is ferroelectric, the ferroelectric polarization domains in the layer produce local electric fields that penetrate the two-dimensional material. The local electric fields modulate the charge carriers and carrier density on a nanometer length scale, resulting in the formation of lateral p-n or p-i-n junctions, and variations thereof appropriate for device functions.

Abstract: In one example aspect, the present disclosure is directed to a device. The device includes an active region on a semiconductor substrate. The active region extends along a first direction. The device also includes a gate structure on the active region. The gate structure extends along a second direction that is perpendicular to the first direction. Moreover, the gate structure engages with a channel on the active region. The device further includes a source/drain feature on the active region and connected to the channel. A projection of the source/drain feature onto the semiconductor substrate resembles a hexagon.

Abstract: A method of fabricating a semiconductor device includes forming a channel member suspended above a substrate, depositing a dielectric material layer wrapping around the channel member, performing an oxidation treatment to a surface portion of the dielectric material layer, selectively etching the surface portion of the dielectric material layer to expose sidewalls of the channel member, performing a nitridation treatment to remaining portions of the dielectric material layer and the exposed sidewalls of the channel member, thereby forming a nitride passivation layer partially wrapping around the channel member. The method also includes repeating the steps of performing the oxidation treatment and selectively etching until top and bottom surfaces of the channel member are exposed, removing the nitride passivation layer from the channel member, and forming a gate structure wrapping around the channel member.

Abstract: A transistor device having fin structures, source and drain terminals, channel layers and a gate structure is provided. The fin structures are disposed on a material layer. The fin structures are arranged in parallel and extending in a first direction. The source and drain terminals are disposed on the fin structures and the material layer and cover opposite ends of the fin structures. The channel layers are disposed respectively on the fin structures, and each channel layer extends between the source and drain terminals on the same fin structure. The gate structure is disposed on the channel layers and across the fin structures. The gate structure extends in a second direction perpendicular to the first direction. The materials of the channel layers include a transition metal and a chalcogenide, the source and drain terminals include a metallic material, and the channel layers are covalently bonded with the source and drain terminals.

Abstract: Various embodiments relate to a superlattice photodetector and a method of manufacturing the same. The superlattice photodetector includes an absorption layer for absorbing incident light and a waveguide layer coupled with the absorption layer and enabling the incident light to be waveguided within the absorption layer. The waveguide layer may include a periodic structure in which a plurality of metal patterns and a plurality of dielectric patterns are repeatedly arranged. According to various embodiments, the superlattice photodetector can be thinned while having improved performance.

Abstract: A mid-infrared light emitting diode is provided, including a graphene lower electrode layer, a black phosphorous layer, and a graphene upper electrode layer sequentially arranged along a thickness direction of the mid-infrared light emitting diode, in which the black phosphorous layer contacts the graphene lower electrode layer and the graphene upper electrode layer. A manufacturing method of the mid-infrared light emitting diode, a silicon photonic circuit and a manufacturing method thereof are also provided.

Abstract: Semiconductor device packages include a redistribution layer (RDL) with carbon-based conductive elements. The carbon-based material of the RDL may have low electrical resistivity and may be thin (e.g., less than about 0.2 ?m). Adjacent passivation material may also be thin (e.g., less than about 0.2 ?m). Methods for forming the semiconductor device packages include forming the carbon-based material (e.g., at high temperatures (e.g., at least about 550° C.)) on an initial support wafer with a sacrificial substrate. Later or separately, components of a device region of the package may be formed and then joined to the initial support wafer before the sacrificial substrate is removed to leave the carbon-based material joined to the device region.

Abstract: Semiconductor devices and methods of forming the same are provided. A method includes providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming a source feature and a drain feature electrically connected to the semiconductor structure and the 2D material layer, wherein the source feature and drain feature include a semiconductor material; and forming a gate structure over the two-dimensional material layer and interposed between the source feature and the drain feature. The gate structure, the source feature, the drain feature, the semiconductor structure and the 2D material layer are configured to form a field-effect transistor. The semiconductor structure and the 2D material layer function, respectively, as a first channel and a second channel between the source feature and the drain feature.

Abstract: A device for detecting energy beam is provided. The device comprises a carbon nanotube structure, a support structure and an infrared detector. The carbon nanotube structure comprises a plurality of carbon nanotubes, and an extending direction of each carbon nanotube is parallel to a direction of an energy beam to be detected. The support structure is configured to support the carbon nanotube structure, and make a portion of the carbon nanotube structure suspended in the air. The infrared detector is located below and spaced apart from the carbon nanotube structure. The infrared detector is configured to detect a temperature of a suspended portion of the carbon nanotube structure, and image according to a temperature distribution of the carbon nanotube structure. A method for detecting energy beam is also provided.

Abstract: Techniques regarding lithographic processes for fabricating Josephson junctions are provided. For example, one or more embodiments described herein can comprise a method that can include depositing a first resist layer onto a second resist layer. The first resist layer can include a bridge portion that defines an opening for forming a Josephson junction. The method can also comprise depositing a third resist layer onto the bridge portion. The third resist layer can shield the opening from an angled deposition of a superconducting material during fabrication of the Josephson junction.

Abstract: Devices for fabrication of shielded modules. In some embodiments, a carrier assembly can be provided for processing of packaged modules. The carrier assembly can include a plate having a first side that defines a plurality of openings, and an adhesive layer implemented on the first side of the plate. The adhesive layer can define a plurality of openings arranged to substantially match the openings of the plate, with each opening of the adhesive layer being dimensioned such that the adhesive layer is capable of providing an adhesive engagement between an underside perimeter portion of a package and a perimeter portion about the corresponding opening of the first side of the plate.

Abstract: An embodiment of the invention provides a fabrication method of a field-effect transistor. The method includes: forming a support structure with a superlattice feature on a semiconductor substrate, where the support structure includes a first semiconductor material layer and a second semiconductor material layer that are alternately disposed, and an isolation layer is disposed on two sides of the support structure; forming, along a boundary between the isolation layer and the support structure, a dummy gate structure that covers the support structure, where a length of the dummy gate structure in a gate length direction is less than the first semiconductor material layer; removing, along the gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove; and forming a source and a drain in a preset source drain area along the gate length direction.

Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.

Abstract: Embodiments relate to a computing device that may be configured as a biomimetic audiomorphic device. The device can include a field effect transistor (FET) having a split-gate architecture with different spacing between the split-gates. Embodiments of the device can include multiple split-gates. Some embodiments include the integration of delay elements and tunable resistor-capacitance (RC) circuits for imitating the interaural time delay neurons. Some embodiments include global back-gating structural features to provide neuroplasticity aspects so as to provide adaptation related changes.

Abstract: The invention relates to a vertical compound semiconductor structure having a substrate with a first main surface and an opposite second main surface, a vertical channel opening extending completely through the substrate between the first main surface and the second main surface and a layer stack arranged within the vertical channel opening. The layer stack includes an electrically conductive layer arranged within the vertical channel opening and a compound semiconductor layer arranged within the vertical channel opening. The compound semiconductor layer includes a compound semiconductor layer arranged on the electrically conductive layer and connected galvanically to the electrically conductive layer. Further, the invention relates to a method for producing such a vertical compound semiconductor structure.

Abstract: A negative transconductance device is disclosed. The negative transconductance device includes a first transistor having a P-type semiconductor channel, a second transistor having an N-type semiconductor channel, and a third transistor having an ambipolar semiconductor channel and positioned between the first and second transistors. A first drain electrode of the first transistor is electrically connected to a third source electrode of the third transistor, and a drain electrode of the third transistor is electrically connected to a second source electrode of the second transistor.

Abstract: A method includes forming a gate structure over a substrate. A dielectric cap is formed over the gate structure. A source/drain contact is formed over a source/drain region over the substrate. An etch stop layer is selectively formed over the dielectric cap such that the etch stop layer expose the source/drain contact. An interlayer dielectric is formed over the etch stop layer and the source/drain contact. A source/drain via is formed in the ILD and is connected to the source/drain contact.

Abstract: A field effect transistor includes a substrate, a passivation layer on the substrate forming a passivated substrate, wherein the passivation layer is inert to XeF2, and a graphene lateral heterostructure field effect transistor (LHFET) on the passivated substrate.

Abstract: An optoelectronic apparatus, such as a photodetector apparatus comprising a substrate (1), a dielectric layer (2), a transport layer, and a photosensitizing layer (5). The transport layer comprises at least a 2-dimensional semiconductor layer (3), such as MoS2, and the photosensitizing layer (5) comprises colloidal quantum dots. Enhanced responsivity and extended spectral coverage are achieved with the disclosed structures.

Abstract: A method of manufacturing a flexible array substrate, a flexible array substrate, and a flexible display device are disclosed. The method of manufacturing the flexible array substrate is implemented by using silver nanowire to form an electrically conductive pattern on a flexible substrate. In this manner, using the silver nanowire to replace metal or indium tin oxide as conventionally used to form the electrically conductive pattern can reduce trace resistance, increase panel transmittance, improve bending resistance of the flexible array substrate, avoid line breaks in products, improve production yield, and reduce manufacturing costs of products.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a channel member including a first channel layer and a second channel layer over the first channel layer, and a gate structure over the channel member. The first channel layer includes silicon, germanium, a III-V semiconductor, or a II-VI semiconductor and the second channel layer includes a two-dimensional material.

Abstract: A graphene nanostructure has a nanographene, a ? conjugated functional group bonded to the nanographene via a pyrazine skeleton, and at least one Br group and/or at least one CN group introduced into the ? conjugated functional group. A graphene nanostructure preferably has an average size of 1 nm or larger to 100 nm or smaller, a band gap of 0.01 eV or higher to 1.2 eV or lower, and/or a HOMO level of ?6.0 eV or higher to ?4.0 eV or lower. As the ? conjugated functional group into which the Br group(s) and/or the CN group(s) are/is introduced, a 4-bromobenzene group, a 4,5-dibromobenzene group, a 5-bromopyridine group, a 5-bromopyrazine group, a benzonitrile group, a phthalonitrile group, or a 2,3-dicyanopyrazine group is desirable.

Abstract: According to embodiments of the present disclosure, two-dimensional (2D) materials may be used as nanosheet channels for multi-channel transistors. Nanosheet channels made two-dimensional (2D) materials can achieve the same drive current at smaller dimensions and/or fewer number of channels, therefore enable scaling down and/or boost derive current. Embodiments of the present disclosure also provide a solution of P-type and N-type balancing in a device without increasing footprint of the device.