Ballistic Transport Device (e.g., Hot Electron Transistor) Patents (Class 257/29)
  • Patent number: 11569367
    Abstract: A field effect transistor includes a substrate, a passivation layer on the substrate forming a passivated substrate, wherein the passivation layer is inert to XeF2, and a graphene lateral heterostructure field effect transistor (LHFET) on the passivated substrate.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: January 31, 2023
    Assignee: HRL LABORATORIES, LLC
    Inventors: Kyung-Ah Son, Jeong-Sun Moon, Hwa Chang Seo
  • Patent number: 11527662
    Abstract: An optoelectronic apparatus, such as a photodetector apparatus comprising a substrate (1), a dielectric layer (2), a transport layer, and a photosensitizing layer (5). The transport layer comprises at least a 2-dimensional semiconductor layer (3), such as MoS2, and the photosensitizing layer (5) comprises colloidal quantum dots. Enhanced responsivity and extended spectral coverage are achieved with the disclosed structures.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: December 13, 2022
    Assignee: FUNDACIÓ INSTITUT DE CIÈNCIES FOTÔNIQUES
    Inventors: Gerasimos Konstantatos, Frank Koppens, Dominik Kufer, Ivan Nikitskiy
  • Patent number: 11508759
    Abstract: A method of manufacturing a flexible array substrate, a flexible array substrate, and a flexible display device are disclosed. The method of manufacturing the flexible array substrate is implemented by using silver nanowire to form an electrically conductive pattern on a flexible substrate. In this manner, using the silver nanowire to replace metal or indium tin oxide as conventionally used to form the electrically conductive pattern can reduce trace resistance, increase panel transmittance, improve bending resistance of the flexible array substrate, avoid line breaks in products, improve production yield, and reduce manufacturing costs of products.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: November 22, 2022
    Inventor: Zhuhui Li
  • Patent number: 11476333
    Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a channel member including a first channel layer and a second channel layer over the first channel layer, and a gate structure over the channel member. The first channel layer includes silicon, germanium, a III-V semiconductor, or a II-VI semiconductor and the second channel layer includes a two-dimensional material.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: October 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mrunal Abhijith Khaderbad, Dhanyakumar Mahaveer Sathaiya, Keng-Chu Lin, Tzer-Min Shen
  • Patent number: 11453649
    Abstract: A graphene nanostructure has a nanographene, a ? conjugated functional group bonded to the nanographene via a pyrazine skeleton, and at least one Br group and/or at least one CN group introduced into the ? conjugated functional group. A graphene nanostructure preferably has an average size of 1 nm or larger to 100 nm or smaller, a band gap of 0.01 eV or higher to 1.2 eV or lower, and/or a HOMO level of ?6.0 eV or higher to ?4.0 eV or lower. As the ? conjugated functional group into which the Br group(s) and/or the CN group(s) are/is introduced, a 4-bromobenzene group, a 4,5-dibromobenzene group, a 5-bromopyridine group, a 5-bromopyrazine group, a benzonitrile group, a phthalonitrile group, or a 2,3-dicyanopyrazine group is desirable.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: September 27, 2022
    Assignee: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO
    Inventor: Hiroyuki Tetsuka
  • Patent number: 11450666
    Abstract: According to embodiments of the present disclosure, two-dimensional (2D) materials may be used as nanosheet channels for multi-channel transistors. Nanosheet channels made two-dimensional (2D) materials can achieve the same drive current at smaller dimensions and/or fewer number of channels, therefore enable scaling down and/or boost derive current. Embodiments of the present disclosure also provide a solution of P-type and N-type balancing in a device without increasing footprint of the device.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mrunal Abhijith Khaderbad, Dhanyakumar Mahaveer Sathaiya
  • Patent number: 11437482
    Abstract: A field effect transistor (FET), a method of fabricating the field effect transistor, and an electronic device are provided. The field effect transistor comprises: a source and a drain, the source being made of a Dirac material (103); a channel disposed between the source and the drain, and doped opposite to the source; and a gate (106) disposed on the channel and electrically insulated from the channel.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: September 6, 2022
    Assignees: BEIJING HUA TAN YUAN XIN ELECTRONICS TECHNOLOGY CO., LTD, BEIJING HUATAN TECHNOLOGY CO., LTD.
    Inventor: Shibo Liang
  • Patent number: 11424365
    Abstract: A semiconductor structure includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed upon the sidewalls of the fins.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: August 23, 2022
    Assignee: TESSERA LLC
    Inventors: Sami Rosenblatt, Rasit O. Topaloglu
  • Patent number: 11417528
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a carbon structure on a handle substrate at a first surface of the handle substrate. The method further includes attaching a first surface of a semiconductor substrate to the first surface of the handle substrate. The method further includes processing the semiconductor substrate and performing a separation process to separate the handle substrate from the semiconductor substrate. The separation process comprises modifying the carbon structure.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: August 16, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Francisco Javier Santos Rodriguez, Roland Rupp, Hans-Joachim Schulze
  • Patent number: 11410996
    Abstract: A transistor that is formed with a transition metal dichalcogenide material is provided. The transition metal dichalcogenide material is formed using a direct deposition process and patterned into one or more fins. A gate dielectric and a gate electrode are formed over the one or more fins. Alternatively, the transition metal dichalcogenide material may be formed using a deposition of a non-transition metal dichalcogenide material followed by a treatment to form a transition metal dichalcogenide material. Additionally, fins that utilized the transition metal dichalcogenide material may be formed with sidewalls that are either perpendicular to a substrate or else are sloped relative to the substrate.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yee-Chia Yeo, Ling-Yen Yeh, Yuan-Chen Sun
  • Patent number: 11393815
    Abstract: The present disclosure relates to an integrated circuit. In one implementation, the integrated circuit may include a semiconductor substrate; at least one source region comprising a first doped semiconductor material; at least one drain region comprising a second doped semiconductor material; at least one gate formed between the at least one source region and the at least one drain region; and a nanosheet formed between the semiconductor substrate and the at least one gate. The nanosheet may be configured as a routing channel for the at least one gate and may have a first region having a first width and a second region having a second width. The first width may be smaller than the second width.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsiung Lin, Yi-Hsun Chiu, Shang-Wen Chang, Ching-Wei Tsai, Yu-Xuan Huang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11387375
    Abstract: The embodiment provides a graphene-containing membrane producible by wet-coating and excellent in electric properties, a process for producing the membrane, a graphene-containing membrane laminate, and a photoelectric conversion device using the graphene-containing membrane. The graphene-containing membrane contains graphene having a graphene skeleton combined with polyalkyleneimine chains. The membrane has a ratio of the photoelectron intensity at the energy peak position of C1s orbital to that at the bonding energy on an X-ray photoelectron spectrum measured on an ITO film of 288 eV in a range of 5.5 to 20. This membrane can be produced by heating a graphene oxide-containing film in the presence of polyalkyleneimine and further heating the film in the presence of a reducing agent. The graphene-containing membrane can be so installed in a photoelectric conversion device that it is placed between the photoelectric conversion layer and the electrode.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: July 12, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ENERGY SYSTEMS & SOLUTIONS CORPORATION
    Inventors: Katsuyuki Naito, Naomi Shida, Yutaka Saita
  • Patent number: 11374187
    Abstract: Through selective incorporation of high carrier mobility graphene monolayers into low cost, NIR-sensitive SiGe detector layer structures, a device combining beneficial features from both technologies can be achieved. The SiGe in such hybrid SiGe/graphene detector devices serves as the NIR absorbing layer, or as the quantum dot material in certain device iterations. The bandgap of this SiGe layer where absorption of photons and photogeneration of carriers mainly takes place may be tuned by varying the concentrations of Ge in the SixGe1-x material. This bandgap and the thickness of this layer largely impact the degree and spectral characteristics of absorption properties, and thus the quantum efficiency or responsivity of the device. The main function and utility of the graphene monolayers, which are nearly transparent to incident light, is to facilitate the extraction and transport of electron and hole carriers from the SiGe absorbing layer through the device.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: June 28, 2022
    Assignee: Magnolia Optical Technologies, Inc.
    Inventors: John W. Zeller, Yash R. Puri, Ashok K. Sood
  • Patent number: 11358868
    Abstract: The present invention relates to a device comprising physical properties controlled by a microstructure and a method of manufacturing the same. The present invention discloses a base layer having a patterned surface; and a two-dimensional structure layer formed on the patterned surface of the base layer, the two-dimensional structure layer extending on and in compliance to topography of the patterned surface of the base layer, such that change of physical properties of the two-dimensional structure layer conforms to the stress generated along the topography.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: June 14, 2022
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Tse-Ming Chen, Sheng-Chin Ho, Yu-Chiang Hsieh, Ching-Hao Chang
  • Patent number: 11307161
    Abstract: It is an object to improve detection accuracy of an object as compared with prior arts. A flow passage (10) provided in a detection device (10) includes a substrate (1) and a covering member (2) provided at a position corresponding to the substrate (1). A covering member opening (HL2) of the covering member (2) is provided such that a substrate opening (HL1) of the substrate (1) is not covered with the covering member (2). The covering member (2) is arranged onto the substrate (1) such that a substrate capacitance and a covering member capacitance are connected in series. The covering member capacitance is lower than the substrate capacitance.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: April 19, 2022
    Assignee: Aipore Inc.
    Inventors: Makusu Tsutsui, Kazumichi Yokota, Akihide Arima, Wataru Tonomura, Masateru Taniguchi, Takashi Washio, Tomoji Kawai
  • Patent number: 11309446
    Abstract: The present disclosure relates to a resistive switching element in which polarization of a ferroelectric material layer and electron-hole separation phenomenon of a two dimensional semiconducting material layer are combined to induce resistive switching phenomenon, and a photovoltaic device such as a solar cell, including the resistive switching element.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: April 19, 2022
    Assignee: EWHA UNIVERSITY—INDUSTRY COLLABORATION FOUNDATION
    Inventors: William Jo, Hye Jin Jin
  • Patent number: 11276691
    Abstract: Gate-all-around integrated circuit structures having self-aligned source or drain undercut for varied widths are described. In an example, a structure includes first and second vertical arrangements of nanowires above a substrate, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stack portions are over the first and second vertical arrangements of nanowires, respectively. First embedded epitaxial source or drain regions are at ends of the first vertical arrangement of nanowires and extend beneath dielectric sidewalls spacers of the first gate stack portion by a first distance. Second embedded epitaxial source or drain regions are at ends of the second vertical arrangement of nanowires and extend beneath the dielectric sidewalls spacers of the second gate stack portion by a second distance substantially the same as the first distance.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Biswajeet Guha, Jun Sung Kang, Bruce Beattie, Stephen M. Cea, Tahir Ghani
  • Patent number: 11271088
    Abstract: Semiconductor structure is provided. The semiconductor structure includes at least one fin on a semiconductor substrate; at least one stacked channel layer formed on the at least one fin, each stacked channel layer having a sacrificial layer and a channel layer on the sacrificial layer; a dummy gate structure formed on the dummy gate structure; openings formed in the at least one stacked channel layer at both sides of the dummy gate structure; and a protective layer formed on sidewall surfaces of the sacrificial layer.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: March 8, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, SMIC New Technology Research and Development (Shanghai) Corporation
    Inventor: Fei Zhou
  • Patent number: 11257905
    Abstract: A semiconductor device including an active region defined in a substrate; at least one channel layer on the active region; a gate electrode intersecting the active region and on the active region and surrounding the at least one channel layer; and a pair of source/drain regions adjacent to both sides of the gate electrode, on the active region, and in contact with the at least one channel layer, wherein the pair of source/drain regions includes a selective epitaxial growth (SEG) layer, and a maximum width of each of the pair of source/drain regions in a first direction is 1.3 times or less a width of the active region in the first direction.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: February 22, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Uk Jang, Seung Hun Lee, Su Jin Jung, Young Dae Cho
  • Patent number: 11251307
    Abstract: A device includes a substrate, a first electrode on the substrate, an insulating pattern on the substrate, a second electrode on an upper end of the insulating pattern, a two-dimensional (2D) material layer on a side surface of the insulating pattern, a gate insulating layer covering the 2D material layer, and a gate electrode contacting the gate insulting layer. The insulating pattern extends from the first electrode in a direction substantially vertical to the substrate. The 2D material layer includes at least one atomic layer of a 2D material that is substantially parallel to the side surface of the insulating pattern.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: February 15, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-jin Park, Jin-bum Kim, Bong-soo Kim, Kyu-pil Lee, Hyeong-sun Hong, Yoo-sang Hwang
  • Patent number: 11245021
    Abstract: A silicene electronic device includes a silicene material layer. The silicene material layer of the silicene electronic device has a 2D honeycomb structure of silicon atoms, is doped with at least one material of Group I, Group II, Group XVI, and Group XVII, and includes at least one of a p-type dopant region doped with a p-type dopant and an n-type dopant region doped with an n-type dopant. An electrode material layer including a material having a work function lower than the electron affinity of silicene is formed on the silicene material layer.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: February 8, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngtek Oh, Jinwook Jung, Hyeokshin Kwon, Wontaek Seo, Insu Jeon
  • Patent number: 11239354
    Abstract: A transistor device having fin structures, source and drain terminals, channel layers and a gate structure is provided. The fin structures are disposed on a material layer. The fin structures are arranged in parallel and extending in a first direction. The source and drain terminals are disposed on the fin structures and the material layer and cover opposite ends of the fin structures. The channel layers are disposed respectively on the fin structures, and each channel layer extends between the source and drain terminals on the same fin structure. The gate structure is disposed on the channel layers and across the fin structures. The gate structure extends in a second direction perpendicular to the first direction. The materials of the channel layers include a transition metal and a chalcogenide, the source and drain terminals include a metallic material, and the channel layers are covalently bonded with the source and drain terminals.
    Type: Grant
    Filed: July 12, 2020
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lu, Chao-Ching Cheng, Tzu-Ang Chao, Lain-Jong Li
  • Patent number: 11233038
    Abstract: A light emitting diode display substrate, a manufacturing method thereof, and a display device are provided. The light emitting diode display substrate includes a base substrate; a light emitting diode located on the base substrate, and a self-assembled monolayer. The light emitting diode includes a graphene layer, and the graphene layer is located on a side of the light emitting diode close to the base substrate; the self-assembled monolayer is located between the graphene layer and the base substrate and connected with the graphene layer.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: January 25, 2022
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Xiang Feng, Sha Liu, Ruizhi Yang, Xiao Sun, Yun Qiu
  • Patent number: 11211539
    Abstract: The present invention provides thermoelectric conversion elements and thermoelectric conversion modules which are possible to effectively use oxide materials having high Seebeck coefficient, and excellently improve their outputs. The present invention provides thermoelectric conversion elements which comprise at least a charge transport layer, thermoelectric conversion material layers and electrodes, wherein the charge transport layer comprises a graphite treated to dope charge-donating materials so that the graphite has an n-type semiconductor property, or a graphite treated to dope charge-accepting materials so that the graphite has a p-type semiconductor property, and provides thermoelectric conversion modules using the thermoelectric conversion elements.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: December 28, 2021
    Inventor: Hiroaki Nakaya
  • Patent number: 11205715
    Abstract: A method comprising: forming a substrate; forming a first nanowire over the substrate; forming a second nanowire over the substrate; forming a gate over a portion of the first and second nanowires; implanting a dopant such that a region between the first and second nanowires under the gate does not receive the dopant while a region between the first and second nanowires away from the gate receives the dopant, wherein the dopant amorphize a material of the region between the first and second nanowires away from the gate; and isotopically etching of the region between the first and second nanowires away from the gate.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: December 21, 2021
    Assignee: INTEL CORPORATION
    Inventors: Mark Armstrong, Biswajeet Guha, Jun Sung Kang, Bruce Beattie, Tahir Ghani
  • Patent number: 11183599
    Abstract: A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a core region, and one or more shell regions. The core region has an approximately square-shape cross section and a first shell of the one or more shells forms a first shell region of an approximately rhombus-shape cross section around the core region and is connected to an adjacent first shell region corresponding to a neighboring semiconductor wire.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: November 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Sheng Chen, Szu-Wei Huang, Hung-Li Chiang, Cheng-Hsien Wu, Chih Chieh Yeh
  • Patent number: 11171212
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a substrate, a first active area over the substrate, a second active area over the substrate, a graphene channel between the first active area and the second active area, and a first in-plane gate. In some embodiments, the graphene channel, the first in-plane gate, the first active area, and the second active area include graphene. A method of forming the first in-plane gate, the first active area, the second active area, and the graphene channel from a single layer of graphene is also provided.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: November 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Meng-Yu Lin, Shih-Yen Lin, Si-Chen Lee
  • Patent number: 11155866
    Abstract: The present disclosure relates to a gene sequencing structure, chip, system, and method. The gene sequencing structure includes: a first electrode and a second electrode spaced apart from each other, a semiconductor layer, a sensing electrode, an insulating layer, and a sensitive film layer. The first electrode is connected to the second electrode via the semiconductor layer, the sensing electrode is in contact with the sensitive film layer, and the insulating layer isolates each of the sensitive film layer and the sensing electrode from each of the first electrode, the second electrode, and the semiconductor layer, wherein the sensitive film layer generates charges in response to receiving ions generated by base pairing during gene sequencing.
    Type: Grant
    Filed: February 11, 2018
    Date of Patent: October 26, 2021
    Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Peizhi Cai, Fengchun Pang, Huazhe Liu
  • Patent number: 11152473
    Abstract: A device includes a phosphide-containing structure, a dopant source layer and a conductive contact. The phosphide-containing structure has a first chemical element in a compound with phosphorus. The dopant source layer is over the phosphide-containing structure and has a second chemical element the same as the first chemical element. The conductive contact is over the dopant source layer.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: October 19, 2021
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Yu-Ming Lin, Chao-Hsin Wu, Hsun-Ming Chang, Samuel C. Pan
  • Patent number: 11152491
    Abstract: A method for forming a semiconductor device structure is provided. The method for forming a semiconductor device structure includes forming a fin structure over a substrate. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method for forming the semiconductor device structure also includes removing the first semiconductor layers of the fin structure in a channel region thereby exposing the second semiconductor layers of the fin structure. The method for forming the semiconductor device structure also includes forming a dielectric material surrounding the second semiconductor layers, and treating a first portion of the dielectric material. The method for forming the semiconductor device structure also includes etching the first portion of the dielectric material to form gaps, and filling the gaps with a gate stack.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Yu Lin, Chansyun David Yang, Fang-Wei Lee, Tze-Chung Lin, Li-Te Lin, Pinyen Lin
  • Patent number: 11121176
    Abstract: An particle can include a first sheet comprising a layer including a first material, wherein the first sheet includes a first outer surface and a first inner surface; and a second sheet comprising a layer including a second material, where the second sheet includes a second outer surface and a second inner surface, wherein the first sheet and the second sheet form a space, the space is encapsulated by the first sheet and the second sheet.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: September 14, 2021
    Assignee: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Tianxiang Liu, Pingwei Liu, Volodymyr Koman, Daichi Kozawa, Michael S. Strano
  • Patent number: 11100971
    Abstract: A ferroelectric domain regulated optical readout mode memory and a preparing method thereof. The memory has such a structure that a two-dimensional semiconductor and a ferroelectric film layer are sequentially arranged on a conductive substrate. The method for preparing the memory includes the steps of preparing the two-dimensional semiconductor on the conductive substrate, preparing a ferroelectric film, then writing a periodic positive-reverse domain structure into the ferroelectric film on the two-dimensional semiconductor by using a piezoresponse force microscopy technology, and regulating a photoluminescent intensity of the two-dimensional semiconductor WS2 by using a ferroelectric domain. A fluorescent picture taken by a fluorescent camera shows light and dark areas corresponding to polarization directions, the light and dark areas represent an on state (‘1’) and an off state (‘0’) of the memory respectively, and accordingly the purpose of storage is achieved.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: August 24, 2021
    Inventors: Jianlu Wang, Guangjian Wu, Xudong Wang, Hong Shen, Tie Lin, Xiangjian Meng, Junhao Chu
  • Patent number: 11101376
    Abstract: Embodiments related to transistors having one or more non-planar transition metal dichalcogenide cladding layers, integrated circuits and systems incorporating such transistors, and methods for fabricating them are discussed.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: August 24, 2021
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Abhishek Sharma, Van H. Le, Gilbert Dewey, Willy Rachmady
  • Patent number: 10991696
    Abstract: An integrated circuit structure is provided which comprises: a stack of source regions of a stack of transistors and a stack of drain regions of the stack of transistors; and a gate stack that forms gate regions for the stack of transistors, wherein the gate stack comprises traces of a first polymer of a block copolymer, the block copolymer comprising the first polymer and a second polymer.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: April 27, 2021
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Patrick Theofanis, Cory E. Weber, Stephen M. Cea, Rishabh Mehandru
  • Patent number: 10985159
    Abstract: A method for manufacturing a monolithic three-dimensional (3D) integrated circuit (IC) with junctionless semiconductor devices (JSDs) is provided. A first interlayer dielectric (ILD) layer is formed over a semiconductor substrate, while also forming first vias and first interconnect wires alternatingly stacked in the first ILD layer. A first doping-type layer and a second doping-type layer are transferred to a top surface of the first ILD layer. The first and second doping-type layers are stacked and are semiconductor materials with opposite doping types. The first and second doping-type layers are patterned to form a first doping-type wire and a second doping-type wire overlying the first doping-type wire. A gate electrode is formed straddling the first and second doping-type wires. The gate electrode and the first and second doping-type wires at least partially define a JSD.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jean-Pierre Colinge, Carlos H. Diaz, Ta-Pen Guo
  • Patent number: 10985280
    Abstract: A method is presented for fine-tuning a threshold voltage of a nanosheet structure. The method includes forming a nanosheet stack over a substrate including a plurality of sacrificial layers and a plurality of nanowires, forming a sacrificial gate structure over the nanosheet stack, and partially etching one or more sacrificial layers to form cavities, the partial etching resulting in remaining sections of sacrificial layers. The method includes removing the sacrificial gate structure, removing at least one of the remaining sections of sacrificial layers to expose a surface of each of the plurality of nanowires, forming an oxidation channel on the exposed surface on only either a top side or bottom side of each of the plurality of nanowires, removing the oxidation channels to form a recess on each of the plurality of nanowires, and depositing a high-k metal gate extending into the recess of each of the plurality of nanowires.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: April 20, 2021
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10964691
    Abstract: A method for manufacturing a monolithic three-dimensional (3D) integrated circuit (IC) with junctionless semiconductor devices (JSDs) is provided. A first interlayer dielectric (ILD) layer is formed over a semiconductor substrate, while also forming first vias and first interconnect wires alternatingly stacked in the first ILD layer. A first doping-type layer and a second doping-type layer are transferred to a top surface of the first ILD layer. The first and second doping-type layers are stacked and are semiconductor materials with opposite doping types. The first and second doping-type layers are patterned to form a first doping-type wire and a second doping-type wire overlying the first doping-type wire. A gate electrode is formed straddling the first and second doping-type wires. The gate electrode and the first and second doping-type wires at least partially define a JSD.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jean-Pierre Colinge, Carlos H. Diaz, Ta-Pen Guo
  • Patent number: 10957763
    Abstract: A semiconductor structure includes a substrate and a channel stack disposed over a portion of a top surface of the substrate, the channel stack including two or more nanosheet channels, inner spacers disposed above and below outer edges of the two or more nanosheet channels, work function metal disposed between the inner spacers above and below each of the two or more nanosheet channels, and a dielectric layer disposed between the work function metal and the inner spacers and two or more nanosheet channels. The semiconductor structure further includes source/drain regions disposed over the top surface of the substrate surrounding the channel stack and a gate region disposed over a top surface of the channel stack, the gate region including the work function metal and a gate metal disposed over the work function metal. The semiconductor structure further includes a capping layer and contacts.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chun W. Yeung, Chen Zhang
  • Patent number: 10943977
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a channel region, extending along a direction, that has a U-shaped cross-section; a gate dielectric layer wrapping around the channel region; and a gate electrode wrapping around respective central portions of the gate dielectric layer and the channel region.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jie-Cheng Deng, Yi-Jen Chen, Chia-Yang Liao
  • Patent number: 10937885
    Abstract: Provided are electronic devices and methods of manufacturing the same. An electronic device may include a substrate, a gate electrode on the substrate, a ferroelectric layer between the substrate and the gate electrode, and a carbon layer between the substrate and the ferroelectric layer. The carbon layer may have an sp2 bonding structure.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: March 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinseong Heo, Yunseong Lee, Sanghyun Jo, Keunwook Shin, Hyeonjin Shin
  • Patent number: 10923348
    Abstract: A method for forming a semiconductor device comprises receiving a substrate with a silicon oxide layer formed over the substrate and a nano-wire based semiconductor device formed using template-assisted-selective epitaxy (TASE) over the silicon oxide layer. The semiconductor device serves as a seed layer to form at least one i) silicon nanowire which extends laterally in the semiconductor device and over the silicon oxide layer, ii) tunnel which extends laterally in the semiconductor device and over the silicon oxide layer, and iii) nuclei on the silicon oxide layer. A film is deposited over the semiconductor device and the silicon oxide layer. The film is removed over silicon oxide layer outside the semiconductor device. Next the nuclei on the silicon oxide layer are removed. Finally, the silicon oxide layer over the semiconductor device is removed.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: February 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Hiroyuki Miyazoe, Cheng-Wei Cheng, Sanghoon Lee
  • Patent number: 10910375
    Abstract: Aspects of the disclosure provide a semiconductor device and a method for forming the semiconductor device. The semiconductor device includes a first transistor formed in a first region of the semiconductor device. The first transistor includes a first channel structure extending between a source terminal and a drain terminal of the first transistor. The first transistor includes a second channel structure that is stacked on the first channel structure in a vertical direction above a substrate of the semiconductor device. Further, the first transistor includes a first gate structure configured to wrap around the first channel structure and the second channel structure with a first metal cap between the first channel structure and the second channel structure. The first metal cap has a different work function from another portion of the first gate structure.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: February 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10896956
    Abstract: FET transistor (100) comprising: a semiconductor portion (104) of which a first part (106) forms a channel; a gate (108) at least partly surrounding the first part; internal dielectric spacers (112) arranged around doped second parts (114) of the semiconductor portion between which the first part is arranged and which form extension regions; electrically conductive portions (120) in contact with doped surfaces of extremities (118) of the semiconductor portion and with doped surfaces of third parts (116) of the semiconductor portion, forming part of the source and drain regions, at least partly surrounding the third parts, with each of the second parts being arranged between the first part and one of the third parts.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: January 19, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Remi Coquand, Shay Reboh
  • Patent number: 10886265
    Abstract: An embodiment includes an apparatus comprising: a dielectric material including fixed charges, the fixed charges each having a first polarity; a channel comprising a channel material, the channel material including a 2-dimensional (2D) material; a drain node; and a source node including a source material, the source material including at least one of the 2D material and an additional 2D material; wherein the source material: (a) includes charges each having a second polarity that is opposite the first polarity, (b) directly contacts the dielectric material. Other embodiments are described herein.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Ashish Verma Penumatcha, Uygar Avci, Ian Young
  • Patent number: 10886272
    Abstract: Techniques are disclosed for forming dual-strain fins for co-integrated n-MOS and p-MOS devices. The techniques can be used to monolithically form tensile-strained fins to be used for n-MOS devices and compressive-strained fins to be used for p-MOS devices utilizing the same substrate, such that a single integrated circuit (IC) can include both of the devices. In some instances, the oppositely stressed fins may be achieved by employing a relaxed SiGe (rSiGe) layer from which the tensile and compressive-strained material can be formed. In some instances, the techniques include the formation of tensile-stressed Si and/or SiGe fins and compressive-stressed SiGe and/or Ge fins using a single relaxed SiGe layer to enable the co-integration of n-MOS and p-MOS devices, where each set of devices includes preferred materials and preferred stress/strain to enhance their respective performance. In some cases, improvements of at least 25% in drive current can be obtained.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Stephen M. Cea, Rishabh Mehandru, Anupama Bowonder, Anand S. Murthy, Tahir Ghani
  • Patent number: 10868127
    Abstract: Present disclosure provides gate-all-around structure including a first transistor. The first transistor includes a semiconductor substrate having a top surface, a first nanowire over the top surface of the semiconductor substrate and between a first source and a first drain, a first gate structure around the first nanowire, an inner spacer between the first gate structure and the first source and first drain, and an isolation layer between the top surface of the semiconductor substrate and the first source and the first drain. Present disclosure also provides a method for manufacturing the gate-all-around structure described herein.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Yu-Lin Yang, I-Sheng Chen, Tzu-Chiang Chen
  • Patent number: 10854445
    Abstract: Provided is an infrared optical sensor including a substrate, a channel layer on the substrate, optical absorption structures dispersed and disposed on the channel layer, and electrodes disposed on the substrate, and disposed on both sides of the channel layer, wherein the channel layer and the optical absorption structures include transition metal dichalcogenides.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: December 1, 2020
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Bok Ki Min, Choon Gi Choi
  • Patent number: 10835886
    Abstract: The present invention relates to a method for preparing graphene using a novel block copolymer. The present invention has features that, by using the block copolymer to mediate graphene that is hydrophobic and a solvent of a feed solution that is hydrophilic, the exfoliation efficiency of graphene as well as the dispersion stability thereof can be increased during high-pressure homogenization.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: November 17, 2020
    Inventors: Mi Jin Lee, Byeong-Hyeok Sohn, Seung Yong Chae, Won Jong Kwon, Kwon Nam Sohn
  • Patent number: 10830640
    Abstract: To provide an electromagnetic wave detection element capable of detecting an electromagnetic wave with an arbitrary wavelength and being miniaturized. An electromagnetic wave detection element according to the present technology includes an antenna unit and a detection unit. The antenna unit includes a first conductive layer, a first dielectric layer that is laminated on the first conductive layer and is constituted of a dielectric body, and a first graphene layer that is laminated on the first dielectric layer and is made of graphene. The detection unit includes a second conductive layer that is made of a conductive material and is separated from the first conductive layer, a second dielectric layer that is laminated on the second conductive layer and is constituted of a dielectric body, and a second graphene layer that is laminated on the second dielectric layer, is made of graphene, and is separated from the first graphene layer.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: November 10, 2020
    Assignee: Sony Corporation
    Inventors: Shinji Imaizumi, Koji Kadono
  • Patent number: 10833183
    Abstract: One device disclosed herein includes, among other things, first and second conductive features embedded in a first dielectric layer, a cap layer positioned above the first dielectric layer, a ballistic transport material contacting the first conductive member and positioned above a portion of the first dielectric layer, and first and second contacts contacting the first and second conductive features.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Joshua Dillon, Siva P. Adusumilli, Jagar Singh, Anthony Stamper, Laura Schutz