Ballistic Transport Device (e.g., Hot Electron Transistor) Patents (Class 257/29)
  • Patent number: 11948793
    Abstract: A method for making a field effect transistor includes providing a graphene nanoribbon composite structure. The graphene nanoribbon composite structure includes a substrate and a plurality of graphene nanoribbons spaced apart from each other. The substrate includes a plurality of protrusions spaced apart from each other, and one of the plurality of graphene nanoribbons is on the substrate and between two adjacent protrusions. An interdigital electrode is placed on the graphene nanoribbon composite structure, and the interdigital electrode covers the plurality of protrusions and is electrically connected to the plurality of graphene nanoribbons.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: April 2, 2024
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Tian-Fu Zhang, Li-Hui Zhang, Yuan-Hao Jin, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 11932542
    Abstract: A large-area wrinkled graphene substrate capable of being manufactured in a large-area, and a method for manufacturing the same is provided. A method for manufacturing a wrinkled graphene substrate includes: i) providing a graphene unit; ii) inserting a carrier film and a graphene unit between a pair of rolls and rotating the pair of rolls in opposite directions to attach a carrier film on the graphene unit, iii) immersing the graphene unit in an etching solution to provide graphene, iv) between a pair of rolls, graphene and poly(4-styrene sulfonic acid)/polystyrene (PSS/PS) substrate attaching graphene onto the PSS/PS substrate, v) attaching an ethylene vinyl acetate/polyethylene terephthalate (EVA/PET) substrate to wrinkled graphene on PSS/PS substrate by inserting EVA/PET and WGr/PSS/PS stack between the rolls, viii) removing the PSS/PS substrate by immersing PET/EVA/WGr/PSS/PS stack in water, and ix) providing a wrinkled graphene substrate on the EVA/PET substrate.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: March 19, 2024
    Assignee: KOREA RESEARCH INSTITUTE OF STANDARDS AND SCIENCE
    Inventors: Prashant Narute, Seong-Gu Hong
  • Patent number: 11908950
    Abstract: Embodiments include two-dimensional (2D) semiconductor sheet transistors and methods of forming such devices. In an embodiment, a semiconductor device comprises a stack of 2D semiconductor sheets, where individual ones of the 2D semiconductor sheets have a first end and a second end opposite from the first end. In an embodiment, a first spacer is over the first end of the 2D semiconductor sheets, and a second spacer is over the second end of the 2D semiconductor sheets. Embodiments further comprise a gate electrode between the first spacer and the second spacer, a source contact adjacent to the first end of the 2D semiconductor sheets, and a drain contact adjacent to the second end of the 2D semiconductor sheets.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: February 20, 2024
    Assignee: Intel Corporation
    Inventors: Kirby Maxey, Chelsey Dorow, Kevin P. O'Brien, Carl Naylor, Ashish Verma Penumatcha, Tanay Gosavi, Uygar E. Avci, Shriram Shivaraman
  • Patent number: 11901438
    Abstract: Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: February 13, 2024
    Assignee: Adeia Semiconductor Solutions LLC
    Inventors: Kangguo Cheng, Juntao Li, Heng Wu, Peng Xu
  • Patent number: 11894422
    Abstract: A gate-controlled diode includes a substrate, a gate stacked on the substrate, a gate insulation layer, a first two-dimensional semiconductor layer, a second two-dimensional semiconductor layer, a source, and a drain disposed separately from the source. The gate is embedded in a surface of the substrate, and the gate insulation layer covers the surface of the substrate in which the gate is disposed. The first two-dimensional semiconductor layer is stacked on the gate insulation layer, a portion of the second two-dimensional semiconductor layer is stacked on the gate insulation layer, another portion is stacked on the first two-dimensional semiconductor layer. The another portion of the second two-dimensional semiconductor layer stacked on the first two-dimensional semiconductor layer forms a heterojunction. An orthographic projection of the heterojunction onto the substrate is in an orthographic projection of the gate onto the substrate.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: February 6, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Wei Li
  • Patent number: 11869904
    Abstract: An array substrate, a method for fabricating the same, and a display device are provided. The method includes: forming a passivation layer on an array substrate, wherein the array substrate includes a thin film transistor and a conductive pad, and the passivation layer covers the thin film transistor and the conductive pad; forming a full-surface carbon film on the passivation layer; and patterning the carbon film and the passivation layer to remove the passivation layer and the carbon film corresponding to the conductive pad by a patterning process to obtain the array substrate.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: January 9, 2024
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Xiaobo Hu
  • Patent number: 11869973
    Abstract: A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: January 9, 2024
    Assignee: Intel Corporation
    Inventors: Erica J. Thompson, Aditya Kasukurti, Jun Sung Kang, Kai Loon Cheong, Biswajeet Guha, William Hsu, Bruce Beattie
  • Patent number: 11867775
    Abstract: A quantum Hall resistance apparatus is to improve resistance standards and includes a substrate, a graphene epitaxially grown on the substrate and having a plurality of first contact patterns at edges of the graphene, a plurality of contacts, each including a second contact pattern and configured to connect to a corresponding first contact pattern, and a protective layer configured to protect the graphene and to increase adherence between the first contact patterns and the second contact patterns. The contacts become a superconductor at a temperature lower than or equal to a predetermined temperature and under up to a predetermined magnetic flux density.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: January 9, 2024
    Assignees: Government of the United States of America, University of Maryland, College Park
    Inventors: Randolph Elmquist, Albert Rigosi, Mattias Kruskopf
  • Patent number: 11862716
    Abstract: Heterostructures include a layer of a two-dimensional material placed on a multiferroic layer. An ordered array of differing polarization domains in the multiferroic layer produces corresponding domains having differing properties in the two-dimensional material. When the multiferroic layer is ferroelectric, the ferroelectric polarization domains in the layer produce local electric fields that penetrate the two-dimensional material. The local electric fields modulate the charge carriers and carrier density on a nanometer length scale, resulting in the formation of lateral p-n or p-i-n junctions, and variations thereof appropriate for device functions.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: January 2, 2024
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Berend T. Jonker, Connie H. Li, Kathleen M. McCreary, Olaf M. J. van 't Erve
  • Patent number: 11855143
    Abstract: In one example aspect, the present disclosure is directed to a device. The device includes an active region on a semiconductor substrate. The active region extends along a first direction. The device also includes a gate structure on the active region. The gate structure extends along a second direction that is perpendicular to the first direction. Moreover, the gate structure engages with a channel on the active region. The device further includes a source/drain feature on the active region and connected to the channel. A projection of the source/drain feature onto the semiconductor substrate resembles a hexagon.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei Ju Lee, Chun-Fu Cheng, Chung-Wei Wu, Zhiqiang Wu
  • Patent number: 11830928
    Abstract: A method of fabricating a semiconductor device includes forming a channel member suspended above a substrate, depositing a dielectric material layer wrapping around the channel member, performing an oxidation treatment to a surface portion of the dielectric material layer, selectively etching the surface portion of the dielectric material layer to expose sidewalls of the channel member, performing a nitridation treatment to remaining portions of the dielectric material layer and the exposed sidewalls of the channel member, thereby forming a nitride passivation layer partially wrapping around the channel member. The method also includes repeating the steps of performing the oxidation treatment and selectively etching until top and bottom surfaces of the channel member are exposed, removing the nitride passivation layer from the channel member, and forming a gate structure wrapping around the channel member.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Han-Yu Lin, Chansyun David Yang, Tze-Chung Lin, Fang-Wei Lee, Fo-Ju Lin, Li-Te Lin, Pinyen Lin
  • Patent number: 11824106
    Abstract: A transistor device having fin structures, source and drain terminals, channel layers and a gate structure is provided. The fin structures are disposed on a material layer. The fin structures are arranged in parallel and extending in a first direction. The source and drain terminals are disposed on the fin structures and the material layer and cover opposite ends of the fin structures. The channel layers are disposed respectively on the fin structures, and each channel layer extends between the source and drain terminals on the same fin structure. The gate structure is disposed on the channel layers and across the fin structures. The gate structure extends in a second direction perpendicular to the first direction. The materials of the channel layers include a transition metal and a chalcogenide, the source and drain terminals include a metallic material, and the channel layers are covalently bonded with the source and drain terminals.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: November 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lu, Chao-Ching Cheng, Tzu-Ang Chao, Lain-Jong Li
  • Patent number: 11804562
    Abstract: Various embodiments relate to a superlattice photodetector and a method of manufacturing the same. The superlattice photodetector includes an absorption layer for absorbing incident light and a waveguide layer coupled with the absorption layer and enabling the incident light to be waveguided within the absorption layer. The waveguide layer may include a periodic structure in which a plurality of metal patterns and a plurality of dielectric patterns are repeatedly arranged. According to various embodiments, the superlattice photodetector can be thinned while having improved performance.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: October 31, 2023
    Assignee: Korea Advanced Institute Of Science and Technology
    Inventors: Sanghyeon Kim, DaeMyeong Geum, SeungYeop Ahn, Jinha Lim
  • Patent number: 11769859
    Abstract: A mid-infrared light emitting diode is provided, including a graphene lower electrode layer, a black phosphorous layer, and a graphene upper electrode layer sequentially arranged along a thickness direction of the mid-infrared light emitting diode, in which the black phosphorous layer contacts the graphene lower electrode layer and the graphene upper electrode layer. A manufacturing method of the mid-infrared light emitting diode, a silicon photonic circuit and a manufacturing method thereof are also provided.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: September 26, 2023
    Assignee: National Tsing Hua University
    Inventor: Chang-Hua Liu
  • Patent number: 11749608
    Abstract: Semiconductor device packages include a redistribution layer (RDL) with carbon-based conductive elements. The carbon-based material of the RDL may have low electrical resistivity and may be thin (e.g., less than about 0.2 ?m). Adjacent passivation material may also be thin (e.g., less than about 0.2 ?m). Methods for forming the semiconductor device packages include forming the carbon-based material (e.g., at high temperatures (e.g., at least about 550° C.)) on an initial support wafer with a sacrificial substrate. Later or separately, components of a device region of the package may be formed and then joined to the initial support wafer before the sacrificial substrate is removed to leave the carbon-based material joined to the device region.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: September 5, 2023
    Inventor: Eiichi Nakano
  • Patent number: 11728391
    Abstract: Semiconductor devices and methods of forming the same are provided. A method includes providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming a source feature and a drain feature electrically connected to the semiconductor structure and the 2D material layer, wherein the source feature and drain feature include a semiconductor material; and forming a gate structure over the two-dimensional material layer and interposed between the source feature and the drain feature. The gate structure, the source feature, the drain feature, the semiconductor structure and the 2D material layer are configured to form a field-effect transistor. The semiconductor structure and the 2D material layer function, respectively, as a first channel and a second channel between the source feature and the drain feature.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Dhanyakumar Mahaveer Sathaiya, Khaderbad Mrunal Abhijith, Tzer-Min Shen
  • Patent number: 11709098
    Abstract: A device for detecting energy beam is provided. The device comprises a carbon nanotube structure, a support structure and an infrared detector. The carbon nanotube structure comprises a plurality of carbon nanotubes, and an extending direction of each carbon nanotube is parallel to a direction of an energy beam to be detected. The support structure is configured to support the carbon nanotube structure, and make a portion of the carbon nanotube structure suspended in the air. The infrared detector is located below and spaced apart from the carbon nanotube structure. The infrared detector is configured to detect a temperature of a suspended portion of the carbon nanotube structure, and image according to a temperature distribution of the carbon nanotube structure. A method for detecting energy beam is also provided.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: July 25, 2023
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Ke Zhang, Guo Chen, Peng Liu, Kai-Li Jiang, Shou-Shan Fan
  • Patent number: 11683995
    Abstract: Techniques regarding lithographic processes for fabricating Josephson junctions are provided. For example, one or more embodiments described herein can comprise a method that can include depositing a first resist layer onto a second resist layer. The first resist layer can include a bridge portion that defines an opening for forming a Josephson junction. The method can also comprise depositing a third resist layer onto the bridge portion. The third resist layer can shield the opening from an angled deposition of a superconducting material during fabrication of the Josephson junction.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: June 20, 2023
    Assignee: International Business Machines Corporation
    Inventors: Kenneth P. Rodbell, Leonidas Ernesto Ocola, Charles Thomas Rettner, Mary E Rothwell, Elbert Emin Huang
  • Patent number: 11682585
    Abstract: Devices for fabrication of shielded modules. In some embodiments, a carrier assembly can be provided for processing of packaged modules. The carrier assembly can include a plate having a first side that defines a plurality of openings, and an adhesive layer implemented on the first side of the plate. The adhesive layer can define a plurality of openings arranged to substantially match the openings of the plate, with each opening of the adhesive layer being dimensioned such that the adhesive layer is capable of providing an adhesive engagement between an underside perimeter portion of a package and a perimeter portion about the corresponding opening of the first side of the plate.
    Type: Grant
    Filed: December 22, 2018
    Date of Patent: June 20, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventors: Yi Liu, Anthony James Lobianco, Matthew Sean Read, Hoang Mong Nguyen, Howard E. Chen
  • Patent number: 11664440
    Abstract: An embodiment of the invention provides a fabrication method of a field-effect transistor. The method includes: forming a support structure with a superlattice feature on a semiconductor substrate, where the support structure includes a first semiconductor material layer and a second semiconductor material layer that are alternately disposed, and an isolation layer is disposed on two sides of the support structure; forming, along a boundary between the isolation layer and the support structure, a dummy gate structure that covers the support structure, where a length of the dummy gate structure in a gate length direction is less than the first semiconductor material layer; removing, along the gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove; and forming a source and a drain in a preset source drain area along the gate length direction.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: May 30, 2023
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xiaolong Ma, Riqing Zhang, Stephane Badel
  • Patent number: 11626519
    Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: April 11, 2023
    Assignee: Intel Corporation
    Inventors: Van H. Le, Gilbert Dewey, Rafael Rios, Jack T. Kavalieros, Marko Radosavljevic, Kent E. Millard, Marc C. French, Ashish Agrawal, Benjamin Chu-Kung, Ryan E. Arch
  • Patent number: 11621355
    Abstract: Embodiments relate to a computing device that may be configured as a biomimetic audiomorphic device. The device can include a field effect transistor (FET) having a split-gate architecture with different spacing between the split-gates. Embodiments of the device can include multiple split-gates. Some embodiments include the integration of delay elements and tunable resistor-capacitance (RC) circuits for imitating the interaural time delay neurons. Some embodiments include global back-gating structural features to provide neuroplasticity aspects so as to provide adaptation related changes.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: April 4, 2023
    Assignee: The Penn State Research Foundation
    Inventors: Saptarshi Das, Sarbashis Das, Akhil Dodda
  • Patent number: 11610967
    Abstract: The invention relates to a vertical compound semiconductor structure having a substrate with a first main surface and an opposite second main surface, a vertical channel opening extending completely through the substrate between the first main surface and the second main surface and a layer stack arranged within the vertical channel opening. The layer stack includes an electrically conductive layer arranged within the vertical channel opening and a compound semiconductor layer arranged within the vertical channel opening. The compound semiconductor layer includes a compound semiconductor layer arranged on the electrically conductive layer and connected galvanically to the electrically conductive layer. Further, the invention relates to a method for producing such a vertical compound semiconductor structure.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: March 21, 2023
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Peter Ramm, Armin Klumpp
  • Patent number: 11605650
    Abstract: A negative transconductance device is disclosed. The negative transconductance device includes a first transistor having a P-type semiconductor channel, a second transistor having an N-type semiconductor channel, and a third transistor having an ambipolar semiconductor channel and positioned between the first and second transistors. A first drain electrode of the first transistor is electrically connected to a third source electrode of the third transistor, and a drain electrode of the third transistor is electrically connected to a second source electrode of the second transistor.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: March 14, 2023
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Sung Joo Lee, Jeong Ho Cho, Jae Ho Jeon, Hyeon Je Son, Hae Ju Choi, Min Je Kim
  • Patent number: 11588030
    Abstract: A method includes forming a gate structure over a substrate. A dielectric cap is formed over the gate structure. A source/drain contact is formed over a source/drain region over the substrate. An etch stop layer is selectively formed over the dielectric cap such that the etch stop layer expose the source/drain contact. An interlayer dielectric is formed over the etch stop layer and the source/drain contact. A source/drain via is formed in the ILD and is connected to the source/drain contact.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: February 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Tze-Liang Lee
  • Patent number: 11569367
    Abstract: A field effect transistor includes a substrate, a passivation layer on the substrate forming a passivated substrate, wherein the passivation layer is inert to XeF2, and a graphene lateral heterostructure field effect transistor (LHFET) on the passivated substrate.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: January 31, 2023
    Assignee: HRL LABORATORIES, LLC
    Inventors: Kyung-Ah Son, Jeong-Sun Moon, Hwa Chang Seo
  • Patent number: 11527662
    Abstract: An optoelectronic apparatus, such as a photodetector apparatus comprising a substrate (1), a dielectric layer (2), a transport layer, and a photosensitizing layer (5). The transport layer comprises at least a 2-dimensional semiconductor layer (3), such as MoS2, and the photosensitizing layer (5) comprises colloidal quantum dots. Enhanced responsivity and extended spectral coverage are achieved with the disclosed structures.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: December 13, 2022
    Assignee: FUNDACIÓ INSTITUT DE CIÈNCIES FOTÔNIQUES
    Inventors: Gerasimos Konstantatos, Frank Koppens, Dominik Kufer, Ivan Nikitskiy
  • Patent number: 11508759
    Abstract: A method of manufacturing a flexible array substrate, a flexible array substrate, and a flexible display device are disclosed. The method of manufacturing the flexible array substrate is implemented by using silver nanowire to form an electrically conductive pattern on a flexible substrate. In this manner, using the silver nanowire to replace metal or indium tin oxide as conventionally used to form the electrically conductive pattern can reduce trace resistance, increase panel transmittance, improve bending resistance of the flexible array substrate, avoid line breaks in products, improve production yield, and reduce manufacturing costs of products.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: November 22, 2022
    Inventor: Zhuhui Li
  • Patent number: 11476333
    Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a channel member including a first channel layer and a second channel layer over the first channel layer, and a gate structure over the channel member. The first channel layer includes silicon, germanium, a III-V semiconductor, or a II-VI semiconductor and the second channel layer includes a two-dimensional material.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: October 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mrunal Abhijith Khaderbad, Dhanyakumar Mahaveer Sathaiya, Keng-Chu Lin, Tzer-Min Shen
  • Patent number: 11453649
    Abstract: A graphene nanostructure has a nanographene, a ? conjugated functional group bonded to the nanographene via a pyrazine skeleton, and at least one Br group and/or at least one CN group introduced into the ? conjugated functional group. A graphene nanostructure preferably has an average size of 1 nm or larger to 100 nm or smaller, a band gap of 0.01 eV or higher to 1.2 eV or lower, and/or a HOMO level of ?6.0 eV or higher to ?4.0 eV or lower. As the ? conjugated functional group into which the Br group(s) and/or the CN group(s) are/is introduced, a 4-bromobenzene group, a 4,5-dibromobenzene group, a 5-bromopyridine group, a 5-bromopyrazine group, a benzonitrile group, a phthalonitrile group, or a 2,3-dicyanopyrazine group is desirable.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: September 27, 2022
    Assignee: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO
    Inventor: Hiroyuki Tetsuka
  • Patent number: 11450666
    Abstract: According to embodiments of the present disclosure, two-dimensional (2D) materials may be used as nanosheet channels for multi-channel transistors. Nanosheet channels made two-dimensional (2D) materials can achieve the same drive current at smaller dimensions and/or fewer number of channels, therefore enable scaling down and/or boost derive current. Embodiments of the present disclosure also provide a solution of P-type and N-type balancing in a device without increasing footprint of the device.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mrunal Abhijith Khaderbad, Dhanyakumar Mahaveer Sathaiya
  • Patent number: 11437482
    Abstract: A field effect transistor (FET), a method of fabricating the field effect transistor, and an electronic device are provided. The field effect transistor comprises: a source and a drain, the source being made of a Dirac material (103); a channel disposed between the source and the drain, and doped opposite to the source; and a gate (106) disposed on the channel and electrically insulated from the channel.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: September 6, 2022
    Assignees: BEIJING HUA TAN YUAN XIN ELECTRONICS TECHNOLOGY CO., LTD, BEIJING HUATAN TECHNOLOGY CO., LTD.
    Inventor: Shibo Liang
  • Patent number: 11424365
    Abstract: A semiconductor structure includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed upon the sidewalls of the fins.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: August 23, 2022
    Assignee: TESSERA LLC
    Inventors: Sami Rosenblatt, Rasit O. Topaloglu
  • Patent number: 11417528
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a carbon structure on a handle substrate at a first surface of the handle substrate. The method further includes attaching a first surface of a semiconductor substrate to the first surface of the handle substrate. The method further includes processing the semiconductor substrate and performing a separation process to separate the handle substrate from the semiconductor substrate. The separation process comprises modifying the carbon structure.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: August 16, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Francisco Javier Santos Rodriguez, Roland Rupp, Hans-Joachim Schulze
  • Patent number: 11410996
    Abstract: A transistor that is formed with a transition metal dichalcogenide material is provided. The transition metal dichalcogenide material is formed using a direct deposition process and patterned into one or more fins. A gate dielectric and a gate electrode are formed over the one or more fins. Alternatively, the transition metal dichalcogenide material may be formed using a deposition of a non-transition metal dichalcogenide material followed by a treatment to form a transition metal dichalcogenide material. Additionally, fins that utilized the transition metal dichalcogenide material may be formed with sidewalls that are either perpendicular to a substrate or else are sloped relative to the substrate.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yee-Chia Yeo, Ling-Yen Yeh, Yuan-Chen Sun
  • Patent number: 11393815
    Abstract: The present disclosure relates to an integrated circuit. In one implementation, the integrated circuit may include a semiconductor substrate; at least one source region comprising a first doped semiconductor material; at least one drain region comprising a second doped semiconductor material; at least one gate formed between the at least one source region and the at least one drain region; and a nanosheet formed between the semiconductor substrate and the at least one gate. The nanosheet may be configured as a routing channel for the at least one gate and may have a first region having a first width and a second region having a second width. The first width may be smaller than the second width.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsiung Lin, Yi-Hsun Chiu, Shang-Wen Chang, Ching-Wei Tsai, Yu-Xuan Huang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11387375
    Abstract: The embodiment provides a graphene-containing membrane producible by wet-coating and excellent in electric properties, a process for producing the membrane, a graphene-containing membrane laminate, and a photoelectric conversion device using the graphene-containing membrane. The graphene-containing membrane contains graphene having a graphene skeleton combined with polyalkyleneimine chains. The membrane has a ratio of the photoelectron intensity at the energy peak position of C1s orbital to that at the bonding energy on an X-ray photoelectron spectrum measured on an ITO film of 288 eV in a range of 5.5 to 20. This membrane can be produced by heating a graphene oxide-containing film in the presence of polyalkyleneimine and further heating the film in the presence of a reducing agent. The graphene-containing membrane can be so installed in a photoelectric conversion device that it is placed between the photoelectric conversion layer and the electrode.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: July 12, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ENERGY SYSTEMS & SOLUTIONS CORPORATION
    Inventors: Katsuyuki Naito, Naomi Shida, Yutaka Saita
  • Patent number: 11374187
    Abstract: Through selective incorporation of high carrier mobility graphene monolayers into low cost, NIR-sensitive SiGe detector layer structures, a device combining beneficial features from both technologies can be achieved. The SiGe in such hybrid SiGe/graphene detector devices serves as the NIR absorbing layer, or as the quantum dot material in certain device iterations. The bandgap of this SiGe layer where absorption of photons and photogeneration of carriers mainly takes place may be tuned by varying the concentrations of Ge in the SixGe1-x material. This bandgap and the thickness of this layer largely impact the degree and spectral characteristics of absorption properties, and thus the quantum efficiency or responsivity of the device. The main function and utility of the graphene monolayers, which are nearly transparent to incident light, is to facilitate the extraction and transport of electron and hole carriers from the SiGe absorbing layer through the device.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: June 28, 2022
    Assignee: Magnolia Optical Technologies, Inc.
    Inventors: John W. Zeller, Yash R. Puri, Ashok K. Sood
  • Patent number: 11358868
    Abstract: The present invention relates to a device comprising physical properties controlled by a microstructure and a method of manufacturing the same. The present invention discloses a base layer having a patterned surface; and a two-dimensional structure layer formed on the patterned surface of the base layer, the two-dimensional structure layer extending on and in compliance to topography of the patterned surface of the base layer, such that change of physical properties of the two-dimensional structure layer conforms to the stress generated along the topography.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: June 14, 2022
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Tse-Ming Chen, Sheng-Chin Ho, Yu-Chiang Hsieh, Ching-Hao Chang
  • Patent number: 11309446
    Abstract: The present disclosure relates to a resistive switching element in which polarization of a ferroelectric material layer and electron-hole separation phenomenon of a two dimensional semiconducting material layer are combined to induce resistive switching phenomenon, and a photovoltaic device such as a solar cell, including the resistive switching element.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: April 19, 2022
    Assignee: EWHA UNIVERSITY—INDUSTRY COLLABORATION FOUNDATION
    Inventors: William Jo, Hye Jin Jin
  • Patent number: 11307161
    Abstract: It is an object to improve detection accuracy of an object as compared with prior arts. A flow passage (10) provided in a detection device (10) includes a substrate (1) and a covering member (2) provided at a position corresponding to the substrate (1). A covering member opening (HL2) of the covering member (2) is provided such that a substrate opening (HL1) of the substrate (1) is not covered with the covering member (2). The covering member (2) is arranged onto the substrate (1) such that a substrate capacitance and a covering member capacitance are connected in series. The covering member capacitance is lower than the substrate capacitance.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: April 19, 2022
    Assignee: Aipore Inc.
    Inventors: Makusu Tsutsui, Kazumichi Yokota, Akihide Arima, Wataru Tonomura, Masateru Taniguchi, Takashi Washio, Tomoji Kawai
  • Patent number: 11276691
    Abstract: Gate-all-around integrated circuit structures having self-aligned source or drain undercut for varied widths are described. In an example, a structure includes first and second vertical arrangements of nanowires above a substrate, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stack portions are over the first and second vertical arrangements of nanowires, respectively. First embedded epitaxial source or drain regions are at ends of the first vertical arrangement of nanowires and extend beneath dielectric sidewalls spacers of the first gate stack portion by a first distance. Second embedded epitaxial source or drain regions are at ends of the second vertical arrangement of nanowires and extend beneath the dielectric sidewalls spacers of the second gate stack portion by a second distance substantially the same as the first distance.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Biswajeet Guha, Jun Sung Kang, Bruce Beattie, Stephen M. Cea, Tahir Ghani
  • Patent number: 11271088
    Abstract: Semiconductor structure is provided. The semiconductor structure includes at least one fin on a semiconductor substrate; at least one stacked channel layer formed on the at least one fin, each stacked channel layer having a sacrificial layer and a channel layer on the sacrificial layer; a dummy gate structure formed on the dummy gate structure; openings formed in the at least one stacked channel layer at both sides of the dummy gate structure; and a protective layer formed on sidewall surfaces of the sacrificial layer.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: March 8, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, SMIC New Technology Research and Development (Shanghai) Corporation
    Inventor: Fei Zhou
  • Patent number: 11257905
    Abstract: A semiconductor device including an active region defined in a substrate; at least one channel layer on the active region; a gate electrode intersecting the active region and on the active region and surrounding the at least one channel layer; and a pair of source/drain regions adjacent to both sides of the gate electrode, on the active region, and in contact with the at least one channel layer, wherein the pair of source/drain regions includes a selective epitaxial growth (SEG) layer, and a maximum width of each of the pair of source/drain regions in a first direction is 1.3 times or less a width of the active region in the first direction.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: February 22, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Uk Jang, Seung Hun Lee, Su Jin Jung, Young Dae Cho
  • Patent number: 11251307
    Abstract: A device includes a substrate, a first electrode on the substrate, an insulating pattern on the substrate, a second electrode on an upper end of the insulating pattern, a two-dimensional (2D) material layer on a side surface of the insulating pattern, a gate insulating layer covering the 2D material layer, and a gate electrode contacting the gate insulting layer. The insulating pattern extends from the first electrode in a direction substantially vertical to the substrate. The 2D material layer includes at least one atomic layer of a 2D material that is substantially parallel to the side surface of the insulating pattern.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: February 15, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-jin Park, Jin-bum Kim, Bong-soo Kim, Kyu-pil Lee, Hyeong-sun Hong, Yoo-sang Hwang
  • Patent number: 11245021
    Abstract: A silicene electronic device includes a silicene material layer. The silicene material layer of the silicene electronic device has a 2D honeycomb structure of silicon atoms, is doped with at least one material of Group I, Group II, Group XVI, and Group XVII, and includes at least one of a p-type dopant region doped with a p-type dopant and an n-type dopant region doped with an n-type dopant. An electrode material layer including a material having a work function lower than the electron affinity of silicene is formed on the silicene material layer.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: February 8, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngtek Oh, Jinwook Jung, Hyeokshin Kwon, Wontaek Seo, Insu Jeon
  • Patent number: 11239354
    Abstract: A transistor device having fin structures, source and drain terminals, channel layers and a gate structure is provided. The fin structures are disposed on a material layer. The fin structures are arranged in parallel and extending in a first direction. The source and drain terminals are disposed on the fin structures and the material layer and cover opposite ends of the fin structures. The channel layers are disposed respectively on the fin structures, and each channel layer extends between the source and drain terminals on the same fin structure. The gate structure is disposed on the channel layers and across the fin structures. The gate structure extends in a second direction perpendicular to the first direction. The materials of the channel layers include a transition metal and a chalcogenide, the source and drain terminals include a metallic material, and the channel layers are covalently bonded with the source and drain terminals.
    Type: Grant
    Filed: July 12, 2020
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lu, Chao-Ching Cheng, Tzu-Ang Chao, Lain-Jong Li
  • Patent number: 11233038
    Abstract: A light emitting diode display substrate, a manufacturing method thereof, and a display device are provided. The light emitting diode display substrate includes a base substrate; a light emitting diode located on the base substrate, and a self-assembled monolayer. The light emitting diode includes a graphene layer, and the graphene layer is located on a side of the light emitting diode close to the base substrate; the self-assembled monolayer is located between the graphene layer and the base substrate and connected with the graphene layer.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: January 25, 2022
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Xiang Feng, Sha Liu, Ruizhi Yang, Xiao Sun, Yun Qiu
  • Patent number: 11211539
    Abstract: The present invention provides thermoelectric conversion elements and thermoelectric conversion modules which are possible to effectively use oxide materials having high Seebeck coefficient, and excellently improve their outputs. The present invention provides thermoelectric conversion elements which comprise at least a charge transport layer, thermoelectric conversion material layers and electrodes, wherein the charge transport layer comprises a graphite treated to dope charge-donating materials so that the graphite has an n-type semiconductor property, or a graphite treated to dope charge-accepting materials so that the graphite has a p-type semiconductor property, and provides thermoelectric conversion modules using the thermoelectric conversion elements.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: December 28, 2021
    Inventor: Hiroaki Nakaya
  • Patent number: 11205715
    Abstract: A method comprising: forming a substrate; forming a first nanowire over the substrate; forming a second nanowire over the substrate; forming a gate over a portion of the first and second nanowires; implanting a dopant such that a region between the first and second nanowires under the gate does not receive the dopant while a region between the first and second nanowires away from the gate receives the dopant, wherein the dopant amorphize a material of the region between the first and second nanowires away from the gate; and isotopically etching of the region between the first and second nanowires away from the gate.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: December 21, 2021
    Assignee: INTEL CORPORATION
    Inventors: Mark Armstrong, Biswajeet Guha, Jun Sung Kang, Bruce Beattie, Tahir Ghani