Ballistic Transport Device (e.g., Hot Electron Transistor) Patents (Class 257/29)
  • Patent number: 11183599
    Abstract: A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a core region, and one or more shell regions. The core region has an approximately square-shape cross section and a first shell of the one or more shells forms a first shell region of an approximately rhombus-shape cross section around the core region and is connected to an adjacent first shell region corresponding to a neighboring semiconductor wire.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: November 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Sheng Chen, Szu-Wei Huang, Hung-Li Chiang, Cheng-Hsien Wu, Chih Chieh Yeh
  • Patent number: 11171212
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a substrate, a first active area over the substrate, a second active area over the substrate, a graphene channel between the first active area and the second active area, and a first in-plane gate. In some embodiments, the graphene channel, the first in-plane gate, the first active area, and the second active area include graphene. A method of forming the first in-plane gate, the first active area, the second active area, and the graphene channel from a single layer of graphene is also provided.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: November 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Meng-Yu Lin, Shih-Yen Lin, Si-Chen Lee
  • Patent number: 11155866
    Abstract: The present disclosure relates to a gene sequencing structure, chip, system, and method. The gene sequencing structure includes: a first electrode and a second electrode spaced apart from each other, a semiconductor layer, a sensing electrode, an insulating layer, and a sensitive film layer. The first electrode is connected to the second electrode via the semiconductor layer, the sensing electrode is in contact with the sensitive film layer, and the insulating layer isolates each of the sensitive film layer and the sensing electrode from each of the first electrode, the second electrode, and the semiconductor layer, wherein the sensitive film layer generates charges in response to receiving ions generated by base pairing during gene sequencing.
    Type: Grant
    Filed: February 11, 2018
    Date of Patent: October 26, 2021
    Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Peizhi Cai, Fengchun Pang, Huazhe Liu
  • Patent number: 11152473
    Abstract: A device includes a phosphide-containing structure, a dopant source layer and a conductive contact. The phosphide-containing structure has a first chemical element in a compound with phosphorus. The dopant source layer is over the phosphide-containing structure and has a second chemical element the same as the first chemical element. The conductive contact is over the dopant source layer.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: October 19, 2021
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Yu-Ming Lin, Chao-Hsin Wu, Hsun-Ming Chang, Samuel C. Pan
  • Patent number: 11152491
    Abstract: A method for forming a semiconductor device structure is provided. The method for forming a semiconductor device structure includes forming a fin structure over a substrate. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method for forming the semiconductor device structure also includes removing the first semiconductor layers of the fin structure in a channel region thereby exposing the second semiconductor layers of the fin structure. The method for forming the semiconductor device structure also includes forming a dielectric material surrounding the second semiconductor layers, and treating a first portion of the dielectric material. The method for forming the semiconductor device structure also includes etching the first portion of the dielectric material to form gaps, and filling the gaps with a gate stack.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Yu Lin, Chansyun David Yang, Fang-Wei Lee, Tze-Chung Lin, Li-Te Lin, Pinyen Lin
  • Patent number: 11121176
    Abstract: An particle can include a first sheet comprising a layer including a first material, wherein the first sheet includes a first outer surface and a first inner surface; and a second sheet comprising a layer including a second material, where the second sheet includes a second outer surface and a second inner surface, wherein the first sheet and the second sheet form a space, the space is encapsulated by the first sheet and the second sheet.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: September 14, 2021
    Assignee: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Tianxiang Liu, Pingwei Liu, Volodymyr Koman, Daichi Kozawa, Michael S. Strano
  • Patent number: 11101376
    Abstract: Embodiments related to transistors having one or more non-planar transition metal dichalcogenide cladding layers, integrated circuits and systems incorporating such transistors, and methods for fabricating them are discussed.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: August 24, 2021
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Abhishek Sharma, Van H. Le, Gilbert Dewey, Willy Rachmady
  • Patent number: 11100971
    Abstract: A ferroelectric domain regulated optical readout mode memory and a preparing method thereof. The memory has such a structure that a two-dimensional semiconductor and a ferroelectric film layer are sequentially arranged on a conductive substrate. The method for preparing the memory includes the steps of preparing the two-dimensional semiconductor on the conductive substrate, preparing a ferroelectric film, then writing a periodic positive-reverse domain structure into the ferroelectric film on the two-dimensional semiconductor by using a piezoresponse force microscopy technology, and regulating a photoluminescent intensity of the two-dimensional semiconductor WS2 by using a ferroelectric domain. A fluorescent picture taken by a fluorescent camera shows light and dark areas corresponding to polarization directions, the light and dark areas represent an on state (‘1’) and an off state (‘0’) of the memory respectively, and accordingly the purpose of storage is achieved.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: August 24, 2021
    Inventors: Jianlu Wang, Guangjian Wu, Xudong Wang, Hong Shen, Tie Lin, Xiangjian Meng, Junhao Chu
  • Patent number: 10991696
    Abstract: An integrated circuit structure is provided which comprises: a stack of source regions of a stack of transistors and a stack of drain regions of the stack of transistors; and a gate stack that forms gate regions for the stack of transistors, wherein the gate stack comprises traces of a first polymer of a block copolymer, the block copolymer comprising the first polymer and a second polymer.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: April 27, 2021
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Patrick Theofanis, Cory E. Weber, Stephen M. Cea, Rishabh Mehandru
  • Patent number: 10985159
    Abstract: A method for manufacturing a monolithic three-dimensional (3D) integrated circuit (IC) with junctionless semiconductor devices (JSDs) is provided. A first interlayer dielectric (ILD) layer is formed over a semiconductor substrate, while also forming first vias and first interconnect wires alternatingly stacked in the first ILD layer. A first doping-type layer and a second doping-type layer are transferred to a top surface of the first ILD layer. The first and second doping-type layers are stacked and are semiconductor materials with opposite doping types. The first and second doping-type layers are patterned to form a first doping-type wire and a second doping-type wire overlying the first doping-type wire. A gate electrode is formed straddling the first and second doping-type wires. The gate electrode and the first and second doping-type wires at least partially define a JSD.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jean-Pierre Colinge, Carlos H. Diaz, Ta-Pen Guo
  • Patent number: 10985280
    Abstract: A method is presented for fine-tuning a threshold voltage of a nanosheet structure. The method includes forming a nanosheet stack over a substrate including a plurality of sacrificial layers and a plurality of nanowires, forming a sacrificial gate structure over the nanosheet stack, and partially etching one or more sacrificial layers to form cavities, the partial etching resulting in remaining sections of sacrificial layers. The method includes removing the sacrificial gate structure, removing at least one of the remaining sections of sacrificial layers to expose a surface of each of the plurality of nanowires, forming an oxidation channel on the exposed surface on only either a top side or bottom side of each of the plurality of nanowires, removing the oxidation channels to form a recess on each of the plurality of nanowires, and depositing a high-k metal gate extending into the recess of each of the plurality of nanowires.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: April 20, 2021
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10964691
    Abstract: A method for manufacturing a monolithic three-dimensional (3D) integrated circuit (IC) with junctionless semiconductor devices (JSDs) is provided. A first interlayer dielectric (ILD) layer is formed over a semiconductor substrate, while also forming first vias and first interconnect wires alternatingly stacked in the first ILD layer. A first doping-type layer and a second doping-type layer are transferred to a top surface of the first ILD layer. The first and second doping-type layers are stacked and are semiconductor materials with opposite doping types. The first and second doping-type layers are patterned to form a first doping-type wire and a second doping-type wire overlying the first doping-type wire. A gate electrode is formed straddling the first and second doping-type wires. The gate electrode and the first and second doping-type wires at least partially define a JSD.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jean-Pierre Colinge, Carlos H. Diaz, Ta-Pen Guo
  • Patent number: 10957763
    Abstract: A semiconductor structure includes a substrate and a channel stack disposed over a portion of a top surface of the substrate, the channel stack including two or more nanosheet channels, inner spacers disposed above and below outer edges of the two or more nanosheet channels, work function metal disposed between the inner spacers above and below each of the two or more nanosheet channels, and a dielectric layer disposed between the work function metal and the inner spacers and two or more nanosheet channels. The semiconductor structure further includes source/drain regions disposed over the top surface of the substrate surrounding the channel stack and a gate region disposed over a top surface of the channel stack, the gate region including the work function metal and a gate metal disposed over the work function metal. The semiconductor structure further includes a capping layer and contacts.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chun W. Yeung, Chen Zhang
  • Patent number: 10943977
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a channel region, extending along a direction, that has a U-shaped cross-section; a gate dielectric layer wrapping around the channel region; and a gate electrode wrapping around respective central portions of the gate dielectric layer and the channel region.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jie-Cheng Deng, Yi-Jen Chen, Chia-Yang Liao
  • Patent number: 10937885
    Abstract: Provided are electronic devices and methods of manufacturing the same. An electronic device may include a substrate, a gate electrode on the substrate, a ferroelectric layer between the substrate and the gate electrode, and a carbon layer between the substrate and the ferroelectric layer. The carbon layer may have an sp2 bonding structure.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: March 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinseong Heo, Yunseong Lee, Sanghyun Jo, Keunwook Shin, Hyeonjin Shin
  • Patent number: 10923348
    Abstract: A method for forming a semiconductor device comprises receiving a substrate with a silicon oxide layer formed over the substrate and a nano-wire based semiconductor device formed using template-assisted-selective epitaxy (TASE) over the silicon oxide layer. The semiconductor device serves as a seed layer to form at least one i) silicon nanowire which extends laterally in the semiconductor device and over the silicon oxide layer, ii) tunnel which extends laterally in the semiconductor device and over the silicon oxide layer, and iii) nuclei on the silicon oxide layer. A film is deposited over the semiconductor device and the silicon oxide layer. The film is removed over silicon oxide layer outside the semiconductor device. Next the nuclei on the silicon oxide layer are removed. Finally, the silicon oxide layer over the semiconductor device is removed.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: February 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Hiroyuki Miyazoe, Cheng-Wei Cheng, Sanghoon Lee
  • Patent number: 10910375
    Abstract: Aspects of the disclosure provide a semiconductor device and a method for forming the semiconductor device. The semiconductor device includes a first transistor formed in a first region of the semiconductor device. The first transistor includes a first channel structure extending between a source terminal and a drain terminal of the first transistor. The first transistor includes a second channel structure that is stacked on the first channel structure in a vertical direction above a substrate of the semiconductor device. Further, the first transistor includes a first gate structure configured to wrap around the first channel structure and the second channel structure with a first metal cap between the first channel structure and the second channel structure. The first metal cap has a different work function from another portion of the first gate structure.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: February 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10896956
    Abstract: FET transistor (100) comprising: a semiconductor portion (104) of which a first part (106) forms a channel; a gate (108) at least partly surrounding the first part; internal dielectric spacers (112) arranged around doped second parts (114) of the semiconductor portion between which the first part is arranged and which form extension regions; electrically conductive portions (120) in contact with doped surfaces of extremities (118) of the semiconductor portion and with doped surfaces of third parts (116) of the semiconductor portion, forming part of the source and drain regions, at least partly surrounding the third parts, with each of the second parts being arranged between the first part and one of the third parts.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: January 19, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Remi Coquand, Shay Reboh
  • Patent number: 10886272
    Abstract: Techniques are disclosed for forming dual-strain fins for co-integrated n-MOS and p-MOS devices. The techniques can be used to monolithically form tensile-strained fins to be used for n-MOS devices and compressive-strained fins to be used for p-MOS devices utilizing the same substrate, such that a single integrated circuit (IC) can include both of the devices. In some instances, the oppositely stressed fins may be achieved by employing a relaxed SiGe (rSiGe) layer from which the tensile and compressive-strained material can be formed. In some instances, the techniques include the formation of tensile-stressed Si and/or SiGe fins and compressive-stressed SiGe and/or Ge fins using a single relaxed SiGe layer to enable the co-integration of n-MOS and p-MOS devices, where each set of devices includes preferred materials and preferred stress/strain to enhance their respective performance. In some cases, improvements of at least 25% in drive current can be obtained.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Stephen M. Cea, Rishabh Mehandru, Anupama Bowonder, Anand S. Murthy, Tahir Ghani
  • Patent number: 10886265
    Abstract: An embodiment includes an apparatus comprising: a dielectric material including fixed charges, the fixed charges each having a first polarity; a channel comprising a channel material, the channel material including a 2-dimensional (2D) material; a drain node; and a source node including a source material, the source material including at least one of the 2D material and an additional 2D material; wherein the source material: (a) includes charges each having a second polarity that is opposite the first polarity, (b) directly contacts the dielectric material. Other embodiments are described herein.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Ashish Verma Penumatcha, Uygar Avci, Ian Young
  • Patent number: 10868127
    Abstract: Present disclosure provides gate-all-around structure including a first transistor. The first transistor includes a semiconductor substrate having a top surface, a first nanowire over the top surface of the semiconductor substrate and between a first source and a first drain, a first gate structure around the first nanowire, an inner spacer between the first gate structure and the first source and first drain, and an isolation layer between the top surface of the semiconductor substrate and the first source and the first drain. Present disclosure also provides a method for manufacturing the gate-all-around structure described herein.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Yu-Lin Yang, I-Sheng Chen, Tzu-Chiang Chen
  • Patent number: 10854445
    Abstract: Provided is an infrared optical sensor including a substrate, a channel layer on the substrate, optical absorption structures dispersed and disposed on the channel layer, and electrodes disposed on the substrate, and disposed on both sides of the channel layer, wherein the channel layer and the optical absorption structures include transition metal dichalcogenides.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: December 1, 2020
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Bok Ki Min, Choon Gi Choi
  • Patent number: 10835886
    Abstract: The present invention relates to a method for preparing graphene using a novel block copolymer. The present invention has features that, by using the block copolymer to mediate graphene that is hydrophobic and a solvent of a feed solution that is hydrophilic, the exfoliation efficiency of graphene as well as the dispersion stability thereof can be increased during high-pressure homogenization.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: November 17, 2020
    Inventors: Mi Jin Lee, Byeong-Hyeok Sohn, Seung Yong Chae, Won Jong Kwon, Kwon Nam Sohn
  • Patent number: 10833183
    Abstract: One device disclosed herein includes, among other things, first and second conductive features embedded in a first dielectric layer, a cap layer positioned above the first dielectric layer, a ballistic transport material contacting the first conductive member and positioned above a portion of the first dielectric layer, and first and second contacts contacting the first and second conductive features.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Joshua Dillon, Siva P. Adusumilli, Jagar Singh, Anthony Stamper, Laura Schutz
  • Patent number: 10830640
    Abstract: To provide an electromagnetic wave detection element capable of detecting an electromagnetic wave with an arbitrary wavelength and being miniaturized. An electromagnetic wave detection element according to the present technology includes an antenna unit and a detection unit. The antenna unit includes a first conductive layer, a first dielectric layer that is laminated on the first conductive layer and is constituted of a dielectric body, and a first graphene layer that is laminated on the first dielectric layer and is made of graphene. The detection unit includes a second conductive layer that is made of a conductive material and is separated from the first conductive layer, a second dielectric layer that is laminated on the second conductive layer and is constituted of a dielectric body, and a second graphene layer that is laminated on the second dielectric layer, is made of graphene, and is separated from the first graphene layer.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: November 10, 2020
    Assignee: Sony Corporation
    Inventors: Shinji Imaizumi, Koji Kadono
  • Patent number: 10818765
    Abstract: A silicene electronic device includes a silicene material layer. The silicene material layer of the silicene electronic device has a 2D honeycomb structure of silicon atoms, is doped with at least one material of Group I, Group II, Group XVI, and Group XVII, and includes at least one of a p-type dopant region doped with a p-type dopant and an n-type dopant region doped with an n-type dopant. An electrode material layer including a material having a work function lower than the electron affinity of silicene is formed on the silicene material layer.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: October 27, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngtek Oh, Jinwook Jung, Hyeokshin Kwon, Wontaek Seo, Insu Jeon
  • Patent number: 10797147
    Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having a fin material layer on the semiconductor substrate; forming an isolation material layer having a bandgap greater than a bandgap of the fin material layer on the fin material layer; and forming a stacked channel material layer on the isolation material layer. The stacked channel material layer includes a sacrificial material layer and a channel material layer on the sacrificial material layer. The method also includes etching the stacked channel material layer, the isolation material layer and the fin material layer to form fins protruding from the semiconductor substrate, an isolation layer on the fins and a stacked channel layer on the isolation layer. The stacked channel layer includes a sacrificial layer and a channel layer on the sacrificial material layer.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: October 6, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, SMIC New Technology Research and Development (Shanghai) Corporation
    Inventor: Fei Zhou
  • Patent number: 10784394
    Abstract: An electromagnetic wave detector, which photoelectrically converts and detects an electromagnetic wave incident on a graphene layer, including: a substrate having a front surface and a back surface; a lower insulating layer provided on the front surface of the substrate; a ferroelectric layer and a pair of electrodes provided on the lower insulating layer, the pair of electrodes arranged to face each other with the ferroelectric layer sandwiched therebetween; an upper insulating layer provided on the ferroelectric layer; and a graphene layer arranged on the lower insulating layer and the upper insulating layer to connect the two electrodes. Alternatively, the electromagnetic wave detector includes: a graphene layer provided on the lower insulating layer; and a ferroelectric layer provided on the graphene layer with an upper insulating layer interposed therebetween and a pair of electrodes provided on the graphene layer to face each other with the ferroelectric layer sandwiched therebetween.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: September 22, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shimpei Ogawa, Daisuke Fujisawa, Masaaki Shimatani, Satoshi Okuda
  • Patent number: 10763362
    Abstract: A FinFET device structure and method for forming the same are provided. The Fin PET device structure includes a stop layer formed over a substrate and a fin structure formed over the stop layer. The FinFET device structure includes a gate structure formed over the fin structure and a source/drain (S/D) structure adjacent to the gate structure. A bottom surface of the S/D structure is located at a position that is higher than or level with a bottom surface of the stop layer.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: September 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10763357
    Abstract: A semiconductor device includes a substrate, a first dielectric layer on the substrate, a hard mask layer on the first dielectric layer, a trench in the hard mask layer and the first dielectric layer, a first source/drain electrode layer on a sidewall of the trench, a second dielectric layer on the first source/drain electrode layer in the trench, a second source/drain electrode layer on the second dielectric layer in the trench, a third dielectric layer on the second source/drain electrode layer in the trench, an ILD layer overlying the trench, an nFET disposed over the trench, and a pFET disposed over the trench and spaced apart from the nFET.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: September 1, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Ching-Wen Hung
  • Patent number: 10763490
    Abstract: Methods are disclosed in which an electrically conductive substrate is immersed in electrodepositable composition including graphenic carbon particles, the substrate serving as an electrode in an electrical circuit comprising the electrode and a counter-electrode immersed in the composition, a coating being applied onto or over at least a portion of the substrate as electric current is passed between the electrodes. The electrodepositable composition comprises an aqueous medium, an ionic resin, and solid particles including graphenic carbon particles. The solid particles may also include lithium-containing particles.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: September 1, 2020
    Assignee: PPG Industries Ohio, Inc.
    Inventors: Randy E. Daughenbaugh, Noel R. Vanier, Stuart D. Hellring, Cheng-Hung Hung
  • Patent number: 10727361
    Abstract: An apparatus configured to alternate the application of first and second gate voltages to a gate electrode of a photodetector. A first change in electrical current is relative to a predetermined measurement of electrical current taken at the first gate voltage in the absence of incident electromagnetic radiation, and a second change in electrical current is relative to a predetermined measurement of electrical current taken at the second gate voltage in the absence of the incident electromagnetic radiation. The photodetector comprises a channel, and source and drain electrodes configured to enable flow of electrical current through the channel. Quantum dots are configured to generate charge carriers on exposure to the incident electromagnetic radiation. The gate electrode is configured to generate an electric field upon the application of a gate voltage thereto, and process the signal to at least partially remove any changes in electrical current which are attributed to noise.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: July 28, 2020
    Assignee: EMBERION OY
    Inventors: Michael Robert Astley, Alan Colli
  • Patent number: 10720508
    Abstract: Methods of selectively nitriding surfaces of semiconductor devices are disclosed. For example, a hardmask is formed on the top portion of the fins to create SOI structure. The hardmask may be formed by nitriding the top portion of the fin. In other embodiments, silicon nitride is grown on the top portion of the fin to form the hard masks. In another example, internal spacers are formed between adjacent nanowires in a gate-all-around structure. The internal spacers may be formed by nitriding the remaining interlayer material between the channel region and source and drain regions.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: July 21, 2020
    Assignee: Intel Corporation
    Inventors: Van H. Le, Scott B. Clendenning, Martin M. Mitan, Szuya S. Liao
  • Patent number: 10714648
    Abstract: Disclosed are a solar cell and a method of manufacturing the same. The solar cell with a graphene-silicon quantum dot hybrid structure according to an embodiment of the present disclosure includes a hybrid structure including a silicon quantum dot layer, in which a silicon oxide layer includes a plurality of silicon quantum dots; a doped graphene layer formed on the silicon quantum dot layer, and an encapsulation layer formed on the doped graphene layer; and electrodes formed on upper and lower parts of the hybrid structure.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: July 14, 2020
    Assignee: UNIVERSITY-INDUSTRY COOPERATION GROUP OF KYUNG HEE UNIVERSITY
    Inventors: Suk Ho Choi, Sung Kim, Jong Min Kim
  • Patent number: 10679906
    Abstract: Nanosheet transistor structures with reduced parasitic capacitance and improved junction sharpness generally include a bilayer spacer adjacent a dummy gate disposed on a nanosheet stack. The bilayer spacer includes an inner spacer layer on sidewalls of the gate and a sacrificial layer on the inner spacer layer. The sacrificial layer can be laterally trimmed to bring the in situ doped source/drain regions closer to the channel, which improves junction sharpness. Additionally, the sacrificial spacer layer can be later removed during the process for forming the transistor so as to form an airgap spacer adjacent the gate, which minimizes parasitic capacitance.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: June 9, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Chanro Park, Ruilong Xie, Tenko Yamashita
  • Patent number: 10665707
    Abstract: Techniques are disclosed for co-integrating transition metal dichalcogenide (TMDC)-based p-channel transistor devices and III-N semiconductor-based n-channel transistor devices. In accordance with some embodiments, a p-channel transistor device configured as described herein may include a layer of TMDC material such as, for example, tungsten diselenide, tungsten disulfide, molybdenum diselenide, or molybdenum disulfide, and an n-channel transistor device configured as described herein may include a layer of III-V material such as, for example, gallium nitride, aluminum nitride, aluminum gallium nitride, and indium aluminum nitride. Transistor structures provided as described herein may be utilized, for instance, in power delivery applications where III-N semiconductor-based n-channel power transistor devices can benefit from being integrated with low-leakage, high-performance p-channel devices providing logic and control circuitry.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: May 26, 2020
    Assignee: INTEL CORPORATION
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic
  • Patent number: 10658470
    Abstract: A method includes providing a black phosphorus (BP) layer over a substrate, forming a dopant source layer over the BP layer, annealing the dopant source layer to drive a dopant from the dopant source layer into the BP layer, and forming a conductive contact over the dopant source layer.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: May 19, 2020
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Yu-Ming Lin, Chao-Hsin Wu, Hsun-Ming Chang, Samuel C. Pan
  • Patent number: 10644168
    Abstract: Semiconductor structures including two-dimensional (2-D) materials and methods of manufacture thereof are described. By implementing 2-D materials in transistor gate architectures such as field-effect transistors (FETs), the semiconductor structures in accordance with this disclosure include vertical gate structures and incorporate 2-D materials such as graphene, transition metal dichalcogenides (TMDs), or phosphorene.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jean-Pierre Colinge, Chung-Cheng Wu, Carlos H. Diaz, Chih-Hao Wang, Ken-Ichi Goto, Ta-Pen Guo, Yee-Chia Yeo, Zhiqiang Wu, Yu-Ming Lin
  • Patent number: 10629740
    Abstract: A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are disposed at a plurality of levels, respectively, and spaced apart from each other in a vertical direction on an upper surface of a substrate. The gate structure is disposed on the substrate, at least partially surrounds a surface of each of the channels, and extends in a first direction substantially parallel to the upper surface of the substrate. The source/drain layer is disposed at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction and is connected to sidewalls of the channels. A length of the gate structure in the second direction changes along the first direction at a first height from the upper surface of the substrate in the vertical direction.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: April 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Gil Yang, Beom-Jin Park, Seung-Min Song, Geum-Jong Bae, Dong-Il Bae
  • Patent number: 10629680
    Abstract: Provided are embodiments of a method for forming active regions of a semiconductor device. Embodiments include forming a nanosheet stack on a substrate, forming the nanosheet stack includes forming a sacrificial nanosheet layer on the substrate, and forming a nanosheet layer on the sacrificial nanosheet layer. Embodiments also include forming an etch stop layer on the nanosheet stack, forming a mandrel layer on the etch stop layer, removing portions of the mandrel layer to form a mandrel on the etch stop layer, and forming sidewalls adjacent to sidewalls of the mandrel. The embodiments include depositing a fill layer on exposed portions of the etch stop layer, removing the sidewalls and removing exposed portions of the etch stop layer and the nanosheet stack to expose portions of the substrate.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: April 21, 2020
    Assignee: Tessera, Inc.
    Inventors: Effendi Leobandung, Tenko Yamashita
  • Patent number: 10608085
    Abstract: The disclosed technology relates generally to semiconductor devices, and more particularly to field-effect transistors (FETs) comprising nanostructures, such as nanowires, fins, and two dimensional materials. In an aspect, a FET device comprises a substrate having an insulating surface and a vertical structure extending in a direction substantially perpendicular to the insulating surface, where the vertical structure has at least outer surfaces formed of an insulating material. The FET device additionally includes a thin layer of two-dimensional (2D) material enveloping the vertical structure and at least part of the insulating surface. The FET device additionally includes two electrodes in electrical contact with the thin layer of 2D material, where one of the electrodes is formed on top of the vertical structure.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: March 31, 2020
    Assignee: IMEC vzw
    Inventors: AliReza Alian, Salim El Kazzi
  • Patent number: 10593778
    Abstract: The present invention disclose an Electrostatic doping (ED)-based graphene nanoribbon (GNR) tunneling field-effect transistor (TFET) with tri-gate design. This device uses hydrogen-passivated GNR heterojunction as a carrier path way and functions as a power switch providing a switching speed of ˜0.3 ps?1 an ION/IOFF ratio as high as 1014 with the on-state current in the order of 103 ?A/?m. This disclosed invention consists of two electrode, two electrode extensions, six metallic gate regions, and six dielectric regions.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: March 17, 2020
    Inventors: Cemalettin Basaran, Weixiang Zhang, Tarek Ragab
  • Patent number: 10580952
    Abstract: A light-emitting device according to one embodiment includes: a substrate; a graphite thin film disposed on the substrate; and an electrode provided on a second surface of the graphite thin film on an edge portion of the graphite thin film, the second surface of the graphite thin film being opposite from a first surface of the graphite thin film, the first surface of the graphite thin film opposed to the substrate. A plurality of protrusions for supporting the graphite thin film is formed on a surface of the substrate opposed to the graphite thin film, at least over an entire region where the substrate and a portion of the graphite thin film other than the edge portion overlap each other when viewed along a thickness direction of the substrate.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: March 3, 2020
    Assignees: KEIO UNIVERSITY, HAMAMATSU PHOTONICS K.K.
    Inventors: Hideyuki Maki, Motohiro Suyama, Takaaki Nagata, Takeo Fujii
  • Patent number: 10577246
    Abstract: A carbon nanotube triode apparatus includes a plurality of Horizontally Aligned Single Wall Carbon Nano Tubes (HA-SWCNT disposed on an electrically insulating thermally conductive substrate. A first contact is disposed on the substrate and electrically coupled to a first end of the HA-SWCNT. A second contact is disposed on the substrate and separated from a second end of the HA-SWCNT by a gap. A gate terminal is coincident with a plane of the substrate.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: March 3, 2020
    Assignee: United States of America as represented by the Secretary of the Air Force
    Inventors: Ahmad Ehteshamul Islam, Benji Maruyama
  • Patent number: 10563306
    Abstract: A production method for a layer structure, including providing a substrate, wherein at least a top surface of the substrate is made from a non-conductive material; depositing a catalyst structure onto the top surface of the substrate; depositing a graphene structure onto the catalyst structure; and at least partially removing the catalyst structure situated between the substrate and the graphene structure.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: February 18, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Fabian Purkl, Franziska Rohlfing, Robert Roelver, Theresa Lutz
  • Patent number: 10541135
    Abstract: An approach to deposit, by a self-aligning process, a layer of graphene on a gate formed on a dielectric layer on a semiconductor substrate where the gate includes a metal catalyst material. The approach includes removing a portion of the dielectric layer and a portion of the semiconductor substrate not under the gate and depositing, by a self-aligning atomic layer deposition process, a layer of a material capable of creating a source and a drain in a semiconductor device on exposed surfaces of the semiconductor substrate and the dielectric layer. The approach includes removing the layer of graphene from the gate, and, then removing a portion of the layer of the material capable of creating the source and the drain in the semiconductor device.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: January 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Seyoung Kim, Yun Seog Lee, Devendra Sadana, Joel de Souza
  • Patent number: 10535559
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphene barrier layer. The present disclosure provides a method of forming a graphene barrier layer on select surfaces using a self-assembly monolayer (SAM). The SAM layer can be selectively formed on dielectric surfaces and annealed to form thin graphene barrier layers. The thickness of the graphene barrier layers can be selected by choosing different alkyl groups of the SAM layer.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue
  • Patent number: 10535754
    Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate, forming a second semiconductor layer including a first concentration of germanium on the first semiconductor layer, and forming a third semiconductor layer on the second semiconductor layer. The first and third semiconductor layers each have a concentration of germanium, which is greater than the first concentration of germanium. The first, second and third semiconductor layers are patterned into at least one fin. The method further includes covering the second semiconductor layer with a mask layer. In the method, a bottom source/drain region and a top source/drain region are simultaneously grown from the first semiconductor layer and the third semiconductor layer, respectively. The mask layer is removed from the second semiconductor layer, and a gate structure is formed on and around the second semiconductor layer.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: January 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Peng Xu, ChoongHyun Lee, Kangguo Cheng, Juntao Li
  • Patent number: 10522616
    Abstract: A semiconductor device includes: a fin-type active region protruding from a substrate and extending in a first direction; at least one nano-sheet spaced apart from an upper surface of the fin-type active region and facing the upper surface of the fin-type active region, the at least one nano-sheet having a channel region; a gate extending on the fin-type active region in a second direction crossing the first direction and surrounding at least a portion of the at least one nano-sheet; a source/drain region on the fin-type active region on both sides of the at least one nano-sheet; and a source/drain protection layer on a sidewall of the at least one nano-sheet and between the source/drain region and the at least one nano-sheet.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: December 31, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Edward Nam-kyu Cho, Tae-soon Kwon, Bo-ra Lim, Jeong-yun Lee
  • Patent number: 10522628
    Abstract: A multilayer graphene composite comprising a plurality of stacked graphene layers separated from one another by an ion gel, wherein the ion gel is intercalated between adjacent graphene layers such that ions within the ion gel are able to arrange themselves at the surfaces of the graphene layers to cause a detectable change in one or more of an electrical and optical property of the graphene layers when a gate voltage is applied to a gate electrode in proximity to the ion gel.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: December 31, 2019
    Assignee: Nokia Technologies Oy
    Inventors: Samiul Md Haque, Alan Colli