With Specified Electrode Composition Or Configuration Patents (Class 257/4)
  • Patent number: 11404636
    Abstract: A crested barrier memory and selector device may include a first electrode, a first self-rectifying, tunneling layer having a first dielectric constant, and an active, barrier layer that has a second dielectric constant and another self-rectifying, tunneling layer having a third dielectric constant. The first self-rectifying layer may be between the first electrode and the active layer. The second dielectric constant may be at least 1.5 times larger than the first dielectric constant. The device may also include a second electrode, where the active, barrier layer is between the first self-rectifying, tunneling layer and the second electrode.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: August 2, 2022
    Assignee: Applied Materials, Inc
    Inventor: Milan Pe{hacek over (s)}ić
  • Patent number: 11404638
    Abstract: Various embodiments of the present disclosure are directed towards a memory device including a data storage structure overlying a substrate. A bottom electrode overlies the substrate and a top electrode overlies the bottom electrode. The data storage structure is disposed between the bottom electrode and the top electrode. The data storage structure comprises a dielectric material doped with a first dopant and a second dopant, where the first dopant is different from the second dopant.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bi-Shen Lee, Hai-Dang Trinh, Fa-Shen Jiang, Hsun-Chung Kuang
  • Patent number: 11404481
    Abstract: According to an embodiment, a semiconductor memory device comprises first wiring lines, second wiring lines, and first variable resistance elements. The first wiring lines are arranged in a first direction and have as their longitudinal direction a second direction intersecting the first direction. The second wiring lines are arranged in the second direction and have the first direction as their longitudinal direction. The first variable resistance elements are respectively provided at intersections of the first wiring lines and the second wiring lines. In addition, this semiconductor memory device comprises a first contact extending in a third direction that intersects the first direction and second direction and having one end thereof connected to the second wiring line. The other end and a surface intersecting the first direction of this first contact are covered by a first conductive layer.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: August 2, 2022
    Assignee: Kioxia Corporation
    Inventor: Takuya Konno
  • Patent number: 11393920
    Abstract: Some embodiments include an integrated assembly having a conductive structure, an annular structure extending through the conductive structure, and an active-material-structure lining an interior periphery of the annular structure. The annular structure includes dielectric material. The active-material-structure includes two-dimensional-material. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: David K. Hwang, John F. Kaeding, Richard J. Hill, Scott E. Sills
  • Patent number: 11393874
    Abstract: Embedded non-volatile memory structures having an independently sized selector element and memory element are described. In an example, a memory device includes a metal layer. A selector element is above the metal layer. A memory element is above the metal line. A spacer surrounds one of the selector element and the memory element having a smallest width, and wherein the one of the selector element and the memory element not surrounded by the spacer has a width substantially identical to the spacer and is in alignment with the spacer.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 19, 2022
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, Abhishek A. Sharma, Ravi Pillarisetty, Elijah V. Karpov, Prashant Majhi
  • Patent number: 11387411
    Abstract: A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Yang Chang, Hsia-Wei Chen, Chin-Chieh Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 11367750
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a vertical memory devices and methods of manufacture. The structure includes: a first bit cell with a first top electrode; a second bit cell with a second top electrode; and a common bottom electrode for both the first bit cell and the second bit cell.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: June 21, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Sunil Kumar Singh, Xuan Anh Tran, Eswar Ramanathan, Suryanarayana Kalaga, Craig M. Child, Robert Fox
  • Patent number: 11362139
    Abstract: A semiconductor memory may include: variable resistance layers and insulating layers alternately stacked; conductive pillars passing through the variable resistance layers and the insulating layers; a slit insulating layer passing through the insulating layers and extending in a first direction; and conductive layers interposed between the slit insulating layer and the variable resistance layers. The variable resistance layers may remain in an amorphous state during a program operation.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: June 14, 2022
    Assignee: SK hynix Inc.
    Inventor: Si Jung Yoo
  • Patent number: 11362141
    Abstract: A variable resistance memory device includes lower conductive lines on a substrate, upper conductive lines on the lower conductive lines to cross the lower conductive lines, and memory cells between the lower conductive lines and the upper conductive lines. The lower conductive lines are extended in a first direction and are spaced apart from each other in a second direction crossing the first direction. Each of the lower conductive lines include a first line portion extended in the first direction, a second line portion offset from the first line portion in the second direction and extended in the first direction, and a connecting portion connecting the first line portion to the second line portion.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: June 14, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Taehong Ha, Jaerok Kahng
  • Patent number: 11348973
    Abstract: Embodiments include a threshold switching selector. The threshold switching selector may include a threshold switching layer and a semiconductor layer between two electrodes. A memory cell may include the threshold switching selector coupled to a storage cell. The storage cell may be a PCRAM storage cell, a MRAM storage cell, or a RRAM storage cell. In addition, a RRAM device may include a RRAM storage cell, coupled to a threshold switching selector, where the threshold switching selector may include a threshold switching layer and a semiconductor layer, and the semiconductor layer of the threshold switching selector may be shared with the semiconductor layer of the RRAM storage cell.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: May 31, 2022
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Rafael Rios, Jack T. Kavalieros, Shriram Shivaraman
  • Patent number: 11342020
    Abstract: A variable resistive memory device includes a memory cell array and a control circuit block. The memory cell array includes a plurality of memory cells that are connected between a global word line and a global bit line. The control circuit block is positioned on at least one of edge portions of the memory cell array. The memory cell array is classified into a first group with the memory cells that are adjacent to the control circuit block and a second group with the memory cells that are remote in relation to the control circuit block. The second group is farther from the control circuit block than the first group. The control circuit block includes a write control unit that generates a control signal for writing on the memory cell in the first group in a different way compared to writing on the memory cell in the second group.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: May 24, 2022
    Assignee: SK hynix Inc.
    Inventors: Ki Myung Kyung, Jung Hyuk Yoon, Ki Won Lee
  • Patent number: 11329221
    Abstract: The present disclosure, in some embodiments, relates to a method of forming a resistive random access memory (RRAM) device. The method includes forming one or more bottom electrode films over a lower interconnect layer within a lower inter-level dielectric layer. A data storage film having a variable resistance is formed above the one or more bottom electrode films. A lower top electrode film including a metal is over the data storage film, one or more oxygen barrier films are over the lower top electrode film, and an upper top electrode film including a metal nitride is formed over the one or more oxygen barrier films. The one or more oxygen barrier films include one or more of a metal oxide film and a metal oxynitride film. The upper top electrode film is formed to be completely confined over a top surface of the one or more oxygen barrier films.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Ting Chu, Tong-Chern Ong, Ying-Lang Wang
  • Patent number: 11329225
    Abstract: A memory cell includes a heating element topped with a phase-change material. Two first silicon oxide regions laterally surround the heating element along a first direction. Two second silicon oxide regions laterally surround the heating element along a second direction orthogonal to the first direction. Top surfaces of the heating element and the two first silicon oxide regions are coplanar such that the heating element and the two first silicon oxide regions have a same thickness.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: May 10, 2022
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Olivier Hinsinger
  • Patent number: 11320647
    Abstract: Alloys of GeSbSeTe (GSST) can be used to make actively tunable infrared transmission filters that are small, fast, and solid-state. These filters can be used for hyperspectral imaging, 3D LIDAR, portable bio/chem sensing systems, thermal emission control, and tunable filters. GSST is a low-loss phase-change material that can switch from a low-index (n=3), amorphous state to a high-index (n=4.5), hexagonal state with low loss (k<0.3) over a wavelength range of 2-10 microns or more. The GSST thickness can be selected to provide pure phase modulation, pure amplitude modulation, or coupled phase and amplitude modulation. GSST can be switched thermally in an oven, optically with visible light, or electrically via Joule heating at speeds from kilohertz to Gigahertz. It operates with reversible and polarization independent transmission switching over a wide incident angle (e.g., 0-60 degrees).
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: May 3, 2022
    Assignee: Massachusetts Institute of Technology
    Inventors: Jeffrey Chou, Vladimir Liberman, Juejun Hu, Yifei Zhang, William Herzog, Jason Stewart, Christopher Roberts
  • Patent number: 11316097
    Abstract: According to one embodiment, a memory device includes a first wiring extending in a first direction, and a second wiring extending in a second direction that intersects the first direction. A memory cell is between the first wiring and the second wiring and includes a resistive memory element and a switching element that are connected in series between the first wiring and the second wiring. An insulating region surrounds side surfaces of the memory cell. The insulating region includes a first insulating part adjacent to a side surface of the resistive memory element and a second insulating part adjacent to a side surface of the switching element. The second insulating part has a higher thermal conductivity than the first insulating part.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: April 26, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Taichi Igarashi, Tadaomi Daibou, Junichi Ito, Tadashi Kai, Shogo Itai, Toshiyuki Enda
  • Patent number: 11309353
    Abstract: The present disclosure, in some embodiments, relates to a memory device. In some embodiments, the memory device comprises a substrate and an interconnect structure disposed over the substrate. The interconnect structure comprises stacked interconnect metal layers disposed within stacked interlayer dielectric (ILD) layers. A memory cell is disposed between an upper interconnect metal layer and an intermediate interconnect metal layer. A selecting transistor is connected to the memory cell and disposed between the intermediate interconnect metal layer and a lower interconnect metal layer. By placing the selecting transistor within the back-end interconnect structure between two interconnect metal layers, front-end space is saved, and more integration flexibility is provided.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ken-Ichi Goto, Chung-Te Lin, Mauricio Manfrini
  • Patent number: 11302748
    Abstract: A method of forming an array of memory cells, where the array comprises an elevationally-inner tier of memory cells comprising spaced-inner-tier-lower-first-conductive lines and inner-tier-programmable material directly there-above, an elevationally-outer tier of memory cells comprising spaced-outer-tier-lower-first-conductive lines and outer-tier-programmable material directly there-above, and spaced-upper-second-conductive lines that are electrically shared by the outer-tier memory cells and the inner-tier memory cells, comprises depositing conductor material for all of the shared-spaced-upper-second-conductive lines. All of the conductor material for all of the shared-spaced-upper-second-conductive lines is patterned using only a single masking step. Other method embodiments and arrays of memory cells independent of method of manufacture are disclosed.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Anna Maria Conti, Agostino Pirovano, Andrea Redaelli
  • Patent number: 11296147
    Abstract: A memory device includes a first bottom electrode, a first memory stack, and a second memory stack. The first bottom electrode has a first portion and a second portion connected to the first portion. The first memory stack is over the first portion of the first bottom electrode. The first memory stack includes a first resistive switching element and a first top electrode over the first resistive switching element. The second memory stack is over the second portion of the first bottom electrode. The second memory stack comprises a second resistive switching element and a second top electrode over the second resistive switching element.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: April 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chieh-Fei Chiu, Yong-Shiuan Tsair, Wen-Ting Chu, Yu-Wen Liao, Chin-Yu Mei, Po-Hao Tseng
  • Patent number: 11289646
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming an opening with a tapered profile in a first material layer. An upper width of the opening is greater than a bottom width of opening. The method also includes forming a second material layer in the opening and forming a hard mask to cover a portion of the second material layer. The hard mask aligns to the opening and has a width smaller than the upper width of the opening. The method also includes etching the second material layer by using the hard mask as an etch mask to form an upper portion of a feature with a tapered profile.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: March 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chieh Huang, Jieh-Jang Chen
  • Patent number: 11283015
    Abstract: A method of forming a phase change memory device is provided. The method includes forming a spacer layer on a substrate, and forming a heater terminal contact in the spacer layer. The method further includes forming a liner layer on the heater terminal contact and the spacer layer, and forming a heater terminal in electrical contact with the heater terminal contact in the liner layer. The method further includes forming a conductive projection segment on the heater terminal. The method further includes forming a phase change material layer on the conductive projection segment, and forming a phase change material terminal on the phase change material layer, wherein an electrical current can pass between the heater terminal and the phase change material terminal through the phase change material layer.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: March 22, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy Mathew Philip, Nicole Saulnier, Lawrence A. Clevenger
  • Patent number: 11283014
    Abstract: Technologies relating to RRAM crossbar array circuits with specialized interface layers for the low current operations are disclosed. An example apparatus includes: a substrate; a bottom electrode formed on the substrate; a first layer formed on the bottom electrode; an RRAM oxide layer formed on the first layer and the bottom electrode; and a top electrode formed on the RRAM oxide layer. The first layer may be a continuous layer or a discontinuous layer. The apparatus may further comprise a second layer formed between the RRAM oxide layer and the top electrode. The second layer may be a continuous layer or a discontinuous layer.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: March 22, 2022
    Assignee: TETRAMEM INC.
    Inventors: Minxian Zhang, Ning Ge
  • Patent number: 11283013
    Abstract: A resistive memory device includes a first electrode, a second electrode, a first metal oxide layer, a second metal oxide layer, and a multilayer insulator structure. The first metal oxide layer is disposed between the first electrode and the second electrode in a vertical direction. The second metal oxide layer is disposed between the first metal oxide layer and the second electrode in the vertical direction. The multilayer insulator structure is disposed between the first metal oxide layer and the second metal oxide layer in the vertical direction. The first metal oxide layer includes first metal atoms, the second metal oxide layer includes second metal atoms, and the multilayer insulator structure includes third metal atoms. Each of the third metal atoms is identical to each of the second metal atoms, and an atomic percent of the third metal atoms in the multilayer insulator structure gradually changes in the vertical direction.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: March 22, 2022
    Assignee: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Yuheng Liu, Yunfei Fu, Chih-Chien Huang, Kuo-Liang Huang, Wen Yi Tan
  • Patent number: 11283018
    Abstract: Technologies relating to RRAM-based crossbar array circuits with increase temperature stability are disclosed. An example apparatus includes: a bottom electrode; a filament forming layer formed on the bottom electrode; and a top electrode formed on the filament forming layer, wherein the filament forming layer is configured to form a filament within the filament forming layer when applying a switching voltage upon the filament forming layer, and wherein a material of the filament includes nitrogen-doped Ta2O5, Ta2N/Ta2O5, or TaNyOz.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: March 22, 2022
    Assignee: TETRAMEM INC.
    Inventors: Ning Ge, Minxian Zhang
  • Patent number: 11276731
    Abstract: Methods, systems, and devices for access line formation for a memory array are described. The techniques described herein may be used to fabricate access lines for one or more decks of a memory array. In some examples, one or more access lines of a deck may be formed using an independent processing step. For example, different fabrication processes may be used to form a plurality of access lines in a deck and to form the pillars (e.g., the memory cells) that are coupled with the access lines. In some examples, an offset between the access lines and the pillars may exist due to the components being fabricated in different processing steps.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: March 15, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Redaelli, Anna Maria Conti
  • Patent number: 11276820
    Abstract: Provided is a memristor that can be manufactured at a low temperature, and does not include metals of which resources might be depleted. This memristor includes a first electrode, a second electrode, and a memristor layer of an oxide having elements of Ga, Sn, and oxygen, disposed between the first electrode and the second electrode. When voltage is applied to the first electrode with respect to the second electrode, the voltage being positive or negative, a current flows; when voltage of a data-set voltage value is applied, a state is transitioned from a high-resistance state to a low-resistance state; and when voltage of a data-reset voltage value that is of an opposite sign to that of the data-set voltage value is applied, the state is transitioned from a low-resistance state to a high-resistance state.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: March 15, 2022
    Assignees: RYUKOKU UNIVERSITY, ROHM CO., LTD.
    Inventors: Mutsumi Kimura, Sumio Sugisaki, Yoshinori Miyamae
  • Patent number: 11276460
    Abstract: Structures for an optoelectronic memory and related fabrication methods. A metal oxide layer is located on an interlayer dielectric layer. A layer composed of a donor/acceptor dye is positioned on a portion of the first layer.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: March 15, 2022
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Jianxun Sun, Juan Boon Tan, Tu Pei Chen, Eng Huat Toh
  • Patent number: 11276748
    Abstract: A switchable metal insulator metal capacitor (MIMcap) and a method for fabricating the MIMcap. In another aspect of the invention operating the MIMcap is also described. A first capacitor plate and a second capacitor plate are separated by a capacitor dielectric and disposed over a substrate. A first via is electrically connected to the first capacitor plate and comprised of phase change material (PCM). The PCM is deposited in an electrically conductive state and convertible by application of heat to an insulating state. A first heater is proximate to and electrically isolated from the PCM in the first via. When the first heater is activated it converts the PCM in the first via to the insulating state. This isolates the first capacitor plate from an integrated circuit.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: March 15, 2022
    Assignee: International Business Machines Corporation
    Inventors: Baozhen Li, Chih-Chao Yang, Andrew Tae Kim, Barry Linder
  • Patent number: 11271040
    Abstract: A memory cell includes an ovonic threshold switch (OTS) selector containing a first electrode, a second electrode, an OTS located between the first electrode and the second electrode, and a current focusing layer containing discrete electrically conductive current focusing regions having a width of 30 nm or less located between the first electrode and the OTS, and a memory device located in electrical series with the OTS selector.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: March 8, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Derek Stewart, John Read, Michael Grobis
  • Patent number: 11258012
    Abstract: A resistive random access memory (RERAM) apparatus and method for forming the apparatus are provided. Oxygen content control in the RERAM is provided. To provide oxygen content control, a via to an electrode of the RERAM is formed utilizing an oxygen-free plasma etch step. In one embodiment, the dielectric within which the via is formed is silicon nitride (SiN). In exemplary embodiments, the plasma chemistry is a hydrofluorocarbon (CxHyFz)-based plasma chemistry or a fluorocarbon (CxFy)-based plasma chemistry. In one embodiment, the resistive layer of the RERAM is a metal oxide. In another embodiment, the oxygen concentrations in the electrode of the RERAM under the via and outside the via are the same after formation of the via.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: February 22, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Devi Koty, Qingyun Yang, Hiroyuki Miyazoe, Takashi Ando, Eduard Cartier, Vijay Narayanan, Sebastian Ulrich Englemann
  • Patent number: 11258968
    Abstract: Examples of image sensors are described herein. In an example, an image sensor may comprise an array of hybrid pixels, where each hybrid pixel includes light sensing unit and a non-volatile memory component coupled to the light sensing unit. The light sensing unit comprises a light detecting element and a charge to voltage conversion unit. The charge to voltage conversion unit is to provide an output pixel signal (VPD), based on photo-electrons generated by the light detecting element. Further, the non-volatile component when calibrated to an initial resistance state is to compress the output pixel signal (VPD) during exposure.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: February 22, 2022
    Assignee: Indian Institute of Technology Delhi
    Inventors: Manan Suri, Mukul Sarkar
  • Patent number: 11257864
    Abstract: An RRAM structure includes a substrate. The substrate is divided into a memory cell region and a logic device region. A metal plug is disposed within the memory cell region. An RRAM is disposed on and contacts the metal plug. The RRAM includes a top electrode, a variable resistive layer, and a bottom electrode. The variable resistive layer is disposed between the top electrode and the bottom electrode. The variable resistive layer includes a first bottom surface. The bottom electrode includes a first top surface. The first bottom surface and the first top surface are coplanar. The first bottom surface only overlaps and contacts part of the first top surface.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: February 22, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
  • Patent number: 11245072
    Abstract: A device and a method of forming the same are provided. The device includes a substrate, a first dielectric layer over the substrate, a bottom electrode extending through the first dielectric layer, a first buffer layer over the bottom electrode, a phase-change layer over the first buffer layer, a top electrode over the phase-change layer, and a second dielectric layer over the first dielectric layer. The second dielectric layer surrounds the phase-change layer and the top electrode. A width of the top electrode is greater than a width of the bottom electrode.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: February 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jau-Yi Wu
  • Patent number: 11245074
    Abstract: A RRAM and a method for fabricating the same, wherein the RRAM comprises: a bottom electrode; an oxide layer containing a bottom electrode metal, disposed on the bottom electrode; a resistance-switching layer, disposed on the oxide layer containing a bottom electrode metal, wherein the resistance-switching layer material is a nitrogen-containing tantalum oxide; an inserting layer, disposed on the resistance-switching layer, wherein the inserting layer material comprises a metal or a semiconductor; a top electrode, disposed on the inserting layer. By providing the to resistance-switching layer with a nitrogen-containing tantalum oxide, compared with Ta2O5, the RRAM of the present disclosure has a low activation voltage and a high on-off ratio, and can enhance the control capability over the device resistance by the number of oxygen vacancies.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: February 8, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Hangbing Lv, Ming Liu, Shibing Long, Qi Liu
  • Patent number: 11244952
    Abstract: A method of forming an array of capacitors comprises forming a plurality of horizontally-spaced groups that individually comprise a plurality of horizontally-spaced lower capacitor electrodes having a capacitor insulator thereover. Adjacent of the groups are horizontally spaced farther apart than are adjacent of the lower capacitor electrodes within the groups. A void space is between the adjacent groups. An upper capacitor electrode material is formed in the void space and in the groups over the capacitor insulator and the lower capacitor electrodes. The upper capacitor electrode material in the void space connects the upper capacitor electrode material that is in the adjacent groups relative to one another. The upper capacitor electrode material less-than-fills the void space. At least a portion of the upper capacitor electrode material is removed from the void space to disconnect the upper capacitor electrode material in the adjacent groups from being connected relative to one another.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: February 8, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Sameer Chhajed, Ashonita A. Chavan, Mark Fischer, Durai Vishak Nirmal Ramaswamy
  • Patent number: 11239417
    Abstract: Provided is a resistive random access memory (RRAM) including a dielectric layer, a lower electrode, a data storage layer, an isolation structure, a first oxygen reservoir layer, a second oxygen reservoir layer, and an upper electrode. The lower electrode protrudes from a top surface of the dielectric layer. The data storage layer conformally covers the lower electrode and the dielectric layer. The isolation structure is disposed on the lower electrode. The first oxygen reservoir layer is disposed on the data storage layer at a first side of the isolation structure. The second oxygen reservoir layer is disposed on the data storage layer at a second side of the isolation structure. The isolation structure separates the first oxygen reservoir layer from the second oxygen reservoir layer. The upper electrode is disposed on and shared by the first and second oxygen reservoir layers. A method of manufacturing the RRAM is also provided.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: February 1, 2022
    Assignee: Winbond Electronics Corp.
    Inventors: Bo-Lun Wu, Po-Yen Hsu
  • Patent number: 11239416
    Abstract: A variable resistance memory device includes a first conductive line extending in a first direction, a second conductive line extending in a second direction, the second direction intersecting the first direction on the first conductive line, a fixed resistance layer between the first conductive line and the second conductive line, and a variable resistance layer between the first conductive line and the second conductive line, wherein the fixed resistance layer and the variable resistance layer are electrically connected in parallel to each other between the first conductive line and the second conductive line.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: February 1, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jungho Yoon, Soichiro Mizusaki, Youngjin Cho
  • Patent number: 11227994
    Abstract: A non-volatile memory cell includes a bottom electrode, a top electrode having a conductive material, a resistive layer interposed between the bottom electrode and the top electrode, and side portions covering sides of the top electrode and the resistive layer. The side portions contain an oxide of the conductive material. The non-volatile memory cell further includes a contact wire disposed on the top electrode. A width of the contact wire is less than a width between lateral outer surfaces of the side portions.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: January 18, 2022
    Assignee: Hefei Reliance Memory Limited
    Inventors: Zhiqiang Wei, Zhichao Lu
  • Patent number: 11227997
    Abstract: Embodiments of the present invention are directed to forming a planar Resistive Random Access Memory (RRAM) device with a shared top electrode. In a non-limiting embodiment of the invention, a first trench having a first width and a second trench having a second width less than the first width are formed in a dielectric layer. A bottom liner is formed on sidewalls of the first trench. The bottom liner pinches off the second trench. A top liner is formed on sidewalls of the bottom liner in the first trench. The top liner is formed such that a portion of the bottom liner at a bottommost region of the first trench remains exposed. The exposed portion of the bottom liner is removed, and a memory cell material is formed in the first trench.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: January 18, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ashim Dutta, Saumya Sharma, Tianji Zhou, Chih-Chao Yang
  • Patent number: 11223012
    Abstract: A variable resistance semiconductor device includes a lower conductive wiring; a bottom electrode over the lower conductive wiring; a selection element pattern over the bottom electrode; a first intermediate electrode over the selection element pattern; a second intermediate electrode over the first intermediate electrode; a variable resistance element pattern over the second intermediate electrode; a top electrode over the variable resistance element pattern; and an upper conductive wiring over the top electrode. The first intermediate electrode includes a first material. The second intermediate electrode includes a second material which has a better oxidation resistance and a higher work function than the first material.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: January 11, 2022
    Assignee: SK hynix Inc.
    Inventors: Woo-Young Park, Young-Seok Ko, Soo-Gil Kim
  • Patent number: 11211555
    Abstract: A memory device may include at least one inert electrode, at least one mask element arranged over the at least one inert electrode, a switching layer arranged over the at least one mask element and the at least one inert electrode, and at least one active electrode arranged over the switching layer. Both of the at least one mask element and the switching layer may be in contact with a top surface of the at least one inert electrode. The switching layer in this memory device may thus include corners at which the conductive filaments may be confined. This memory device may be formed with a process that may utilize the at least one mask element to help reduce the chances of shorting between the inert and active electrodes.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: December 28, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Desmond Jia Jun Loy, Eng Huat Toh, Shyue Seng Tan
  • Patent number: 11205750
    Abstract: The present disclosure provides a 1S1R memory integrated structure and a method for fabricating the same, wherein the 1S1R memory integrated structure includes: a word line metal, a resistive material layer, a selector lower electrode, a selector material layer, a selector upper electrode, an interconnection wire, and a bit line metal; wherein the selector material layer is in a shape of a groove, and the selector upper electrode is formed in the groove. According to the 1S1R memory integrated structure and its fabricating method in the present disclosure, by the change of the integrated position of the selector, the device area of the selector is much larger than the device area of the memory, which significantly reduces the requirement for the on-state current density of the selector.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: December 21, 2021
    Assignee: Institute of Microelectronics Chinese Academy of Sciences
    Inventors: Qing Luo, Hangbing Lv, Ming Liu, Xiaoxin Xu, Cheng Lu
  • Patent number: 11201284
    Abstract: A method of fabricating a synaptic device is provided. The method includes forming a channel layer between a first terminal and a second terminal. The channel layer varies in resistance based on a magnesium concentration in the channel layer. The method further includes forming an electrolyte layer. The electrolyte layer includes a magnesium ion conductive material. A third terminal is formed over the electrolyte layer and applies a signal to the electrolyte layer and the channel layer.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: December 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Douglas M. Bishop, Martin Michael Frank, Teodor Krassimirov Todorov
  • Patent number: 11201191
    Abstract: A semiconductor memory device includes a first wiring extending in a first direction, a second wiring above the first wiring and extending in a second direction, first and second memory cells electrically connected in parallel between the first and second wirings and each including a phase change material, a first insulating film on a side portion of the first cell facing the second cell in the second direction, a third wiring above the second wiring and extending in the second direction, a fourth wiring above the third wiring and extending in the first direction, third and fourth memory cells electrically connected between the third and fourth wirings in parallel and each including a phase change material, and a second insulating film on a side of the third cell facing the fourth cell in the second direction. The first film has a higher thermal insulation capacity than the second film.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: December 14, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Atsushi Kawasumi, Tsuneo Inaba
  • Patent number: 11195853
    Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a substrate, a memory stack above the substrate, and a peripheral contact structure outside of the memory stack and in contact with the substrate. The peripheral contact structure includes a first peripheral contact portion in the substrate and having a conductive material different from the substrate. The peripheral contact structure also includes a second peripheral contact above, in contact with, and conductively connected to the first peripheral contact portion.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: December 7, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Ji Xia, Wei Xu, Pan Huang, Wenxiang Xu, Beihan Wang
  • Patent number: 11195999
    Abstract: A PCM cell is provided that includes a silver (Ag) doped Ge2Sb2Te5 (GST) alloy layer as the PCM material. The PCM cell containing the Ag doped GST alloy layer exhibits a reduced reset state resistance drift as compared to an equivalent PCM cell in which a non-Ag doped GST alloy layer is used. In some embodiments and depending on the Ag dopant concentration of the Ag doped GST alloy layer, a constant reset state resistance or even a negative reset state resistance drift can be obtained.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: December 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ning Li, Joel P. de Souza, Stephen W. Bedell, Devendra K. Sadana
  • Patent number: 11189788
    Abstract: An integrated circuit device has an RRAM cell that includes a top electrode, an RRAM dielectric layer, and a bottom electrode having a surface that interfaces with the RRAM dielectric layer. Oxides of the bottom electrode are substantially absent from the bottom electrode surface. The bottom electrode has a higher density in a zone adjacent the surface as compared to a bulk region of the bottom electrode. The surface has a roughness Ra of 2 nm or less. A process for forming the surface includes chemical mechanical polishing followed by hydrofluoric acid etching followed by argon ion bombardment. An array of RRAM cells formed by this process is superior in terms of narrow distribution and high separation between low and high resistance states.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: November 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fu-Chen Chang, Kuo-Chi Tu, Wen-Ting Chu
  • Patent number: 11183634
    Abstract: A method of manufacturing an electronic device including a semiconductor memory may include forming a first active layer, forming a first electrode material over the first active layer, performing a heat treatment process on the first electrode material and the first active layer, and forming a second electrode material over the heat-treated first electrode material.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: November 23, 2021
    Assignee: SK hynix Inc.
    Inventors: Woo Tae Lee, Beom Seok Lee
  • Patent number: 11177213
    Abstract: An anti-fuse device having enhanced programming efficiency is provided. The anti-fuse device includes via contact structures that have different critical dimensions located between a first electrode and a second electrode. Notably, a first via contact structure having a first critical dimension is provided between a pair of second via contact structures having a second critical dimension that is greater than the first critical dimension. When a voltage is applied to the device, dielectric breakdown will occur first through the first via contact structure having the first critical dimension.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: November 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Baozhen Li, Tianji Zhou, Ashim Dutta, Saumya Sharma
  • Patent number: 11177320
    Abstract: Disclosed are variable resistance memory devices and methods of fabricating the same. The variable resistance memory device may include: a plurality of memory cells, each comprising a variable resistance pattern and a switching pattern; a plurality of conductive lines to which the memory cell is connected; a bottom electrode connecting at least one of the conductive lines to the variable resistance pattern; and a spacer pattern formed on the bottom electrode to be in contact with the variable resistance pattern. The spacer pattern includes a dielectric material doped with an impurity.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: November 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byeongju Bae, Duckhee Lee
  • Patent number: 11177457
    Abstract: A display apparatus includes a substrate, an element layer, a protective film, a mechanical member, a first adhesive layer and a second adhesive layer. An opening of the protective film is located between a first portion of the protective film and a second portion of the protective film. The first portion of the protective film, the second portion of the protective film and the opening of the protective film are respectively overlapped with a first portion of the substrate, a second portion of the substrate and a third portion of the substrate. The first adhesive layer and the second adhesive layer are respectively disposed on a first surface and a second surface of the mechanical member. The third portion of the substrate is connected between the first portion of the substrate and the second portion of the substrate, and the third portion of the substrate is bent.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: November 16, 2021
    Assignee: Au Optronics Corporation
    Inventors: Chih-Tsung Lee, Zih-Shuo Huang, Yi-Wei Tsai, Ko-Chin Chung, Ming-Chang Hsu, Heng-Chia Hsu