With Specified Electrode Composition Or Configuration Patents (Class 257/4)
  • Patent number: 10446579
    Abstract: A method of forming a semiconductor device structure comprises forming a stack structure comprising stacked tiers. Each of the stacked tiers comprises a first structure comprising a first material and a second structure comprising a second, different material longitudinally adjacent the first structure. A patterned hard mask structure is formed over the stack structure. Dielectric structures are formed within openings in the patterned hard mask structure. A photoresist structure is formed over the dielectric structures and the patterned hard mask structure. The photoresist structure, the dielectric structures, and the stack structure are subjected to a series of material removal processes to form apertures extending to different depths within the stack structure. Dielectric structures are formed over side surfaces of the stack structure within the apertures. Conductive contact structures are formed to longitudinally extend to bottoms of the apertures.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Roger W. Lindsay, Michael A. Smith, Brett D. Lowe
  • Patent number: 10438959
    Abstract: A semiconductor memory device includes a first electrode film and a second electrode film spreading along a first direction and a second direction, first insulating plates intermittently disposed along the first direction and each of two columns separated in the second direction from each other, second insulating plates provided between the two columns, intermittently disposed along the first direction and each of n columns, third insulating plates provided between one of the two columns and a column formed of the second insulating plates, intermittently disposed along the first direction, a first insulating member provided between the first insulating plate and the third insulating plate, and a second insulating member provided between the second insulating plate and the third insulating plate. The first electrode film is divided into two parts between the two columns. The second electrode film is divided into {(n+1)×2} parts between the two columns.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: October 8, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tatsuya Kato, Atsushi Murakoshi, Fumitaka Arai
  • Patent number: 10424728
    Abstract: A self-selecting memory cell may be composed of a memory material that changes threshold voltages based on the polarity of the voltage applied across it. Such a memory cell may be formed at the intersection of a conductive pillar and electrode plane in a memory array. A dielectric material may be formed between the memory material of the memory cell and the corresponding electrode plane. The dielectric material may form a barrier that prevents harmful interactions between the memory material and the material that makes up the electrode plane. In some cases, the dielectric material may also be positioned between the memory material and the conductive pillar to form a second dielectric barrier. The second dielectric barrier may increase the symmetry of the memory array or prevent harmful interactions between the memory material and an electrode cylinder or between the memory material and the conductive pillar.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: September 24, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Lorenzo Fratin, Fabio Pellizzer
  • Patent number: 10410717
    Abstract: A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: September 10, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kikuko Sugimae, Yusuke Arayashiki
  • Patent number: 10411072
    Abstract: A method for manufacturing a memory cell includes forming a stack of layers comprising a first electrode and a dielectric layer, and forming a second electrode. Forming the second electrode includes depositing the second electrode on the dielectric layer, and defining the contour of the second electrode in such a way that the second electrode forms a protruding element above the dielectric layer having inclined flanks, the angle between the flanks of the second electrode forming an acute angle with the plane wherein the dielectric layer mainly extends.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 10, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sophie Bernasconi, Christelle Charpin-Nicolle, Anthony De Luca
  • Patent number: 10409384
    Abstract: A switch actuating device for actuating a switch by eight types of non-tactile gestures performed with an object emitting heat includes a gesture sensor with four pixels configured to detect heat emitted by the object. The pixels include thin films made of pyroelectric sensitive material which generate a signal that has signal deflections corresponding to a temporal intensity curve of the heat detected by the thin film of the corresponding pixel. The types of the gestures are determined with a signal processing unit which controls an actuator to actuate the switch when a performance of one of the types of the gestures is determined. The gesture types are determined during an approach phase when the object approaches the gesture sensor, a waiting phase during when the object remains close to the gesture sensor, and a subsequent translational phase when the object moves in one of eight directions.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: September 10, 2019
    Assignee: Pyreos Ltd.
    Inventors: Spyros Brown, Timothy John Chamberlain, Jonathan Ephraim David Hurwitz, Carsten Giebeler
  • Patent number: 10402565
    Abstract: A hardware platform includes a nonvolatile storage device that can store system firmware as well as code for the primary operating system for the hardware platform. The hardware platform includes a controller that determines the hardware platform lacks functional firmware to boot the primary operating system from the storage device. The controller accesses a firmware image from an external interface that interfaces a device external to the hardware platform, where the external device is a firmware image source. The controller provisions the firmware from the external device to the storage device and initiates a boot sequence from the provisioned firmware.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: September 3, 2019
    Assignee: Intel Corporation
    Inventors: Nitin V. Sarangdhar, Robert J. Royer, Jr., Eng Hun Ooi, Brian R. McFarlane, Mukesh Kataria
  • Patent number: 10396125
    Abstract: A cross-point memory array includes a plurality of variable resistance memory cell pillars. Adjacent memory cell pillars are separated by a partially filled gap that includes a buried void. In addition, adjacent memory cell pillars include storage material elements that are at least partially interposed by the buried void.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: August 27, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Fantini, Cristina Casellato, Fabio Pellizzer
  • Patent number: 10396126
    Abstract: Semiconductor devices and methods for forming the semiconductor devices include a gate structure disposed between a top electrode and a bottom electrode, the gate structure including a resistive switching medium contacting a first side of the top electrode and a first side of the bottom electrode. A bottom dielectric layer is disposed on the first side of the bottom electrode around the gate structure. A top dielectric layer is disposed on the first side of the top electrode around the gate structure. A gate electrode is disposed between the first dielectric layer and the second dielectric layer and contacting the gate structure in a middle portion thereof to modulate an electric field perpendicular to current flow between the top electrode and the bottom electrode.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Seyoung Kim, Takashi Ando, Choonghyun Lee, Injo Ok, Soon-Cheon Seo
  • Patent number: 10396280
    Abstract: A semiconductor memory device includes a plurality of first interconnections extending in a first direction, and a second interconnection extending in a second direction different from the first direction. The device further includes a resistance change film provided between the plurality of first interconnections and the second interconnection, the resistance change film including (a) silicon and a semiconductor layer including one or more elements selected from among oxygen, carbon, nitrogen, phosphorus, boron, and germanium, or (b) a first layer containing the germanium and a second layer containing the silicon.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: August 27, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Shinji Mori, Masayuki Tanaka, Kazuhiro Matsuo, Kenichiro Toratani, Keiichi Sawa, Kazuhisa Matsuda, Atsushi Takahashi, Yuta Saito
  • Patent number: 10388871
    Abstract: Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Shuichiro Yasuda, Noel Rocklein, Scott E. Sills, Durai Vishak Nirmal Ramaswamy, Qian Tao
  • Patent number: 10387792
    Abstract: A device for storing and/or transferring quantum data. The device has a plurality of elongate semiconductor structures arranged in side by said with each elongate semiconductor structure having a quantum well layer of one semiconductor material disposed between upper and lower layers of a different semiconductor material which share the same or essentially the same crystalline structure as that of the quantum well layer. Neighboring ones of the elongate semiconductor structures share a region forming a constriction between the neighboring ones of the elongate semiconductor structures.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: August 20, 2019
    Assignee: HRL Laboratories, LLC
    Inventors: Thaddeus D. Ladd, Andrey A. Kiselev, Danny M. Kim, Rongming Chu
  • Patent number: 10381561
    Abstract: Methods and devices are provided for fabricating a resistive random-access array having dedicated electroforming contacts. A lower conductive line is formed on an interlayer dielectric layer. A lower electrode is formed on the lower conductive line. An isolation layer is formed having an upper surface which is coplanar with an upper surface of the lower electrode. A stack structure including a metal-oxide layer and upper electrode is formed on the lower electrode. Insulating spacers are formed on sidewalls of the stack structure. The lower electrode, and stack structure form a resistive memory cell, wherein a footprint of the lower electrode is greater than that of the upper electrode. An upper conductive line contacts the upper electrode, and is arranged orthogonal to the lower conductive line. A dedicated electroforming contact contacts an extended portion of the lower electrode which extends past a cross-point of the upper and lower conductive lines.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: August 13, 2019
    Assignee: Internatoinal Business Machines Corporation
    Inventors: Takashi Ando, Lawrence A. Clevenger, Chih-Chao Yang, Benjamin D. Briggs
  • Patent number: 10381558
    Abstract: A memory device is disclosed. The memory device includes a bottom electrode. The memory device also includes a memory layer connected to the bottom electrode, where the memory layer has a variable resistance. The memory device also includes a conductive top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a retention layer between the memory layer and the top electrode, where the retention layer has a variable ionic conductivity, where the retention layer is configured to selectively resist ionic conduction, and where the resistivity of the retention layer is less than 1×10-4 ohm-m.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: August 13, 2019
    Assignee: 4D-S, LTD.
    Inventors: Seshubabu Desu, Michael Van Buskirk
  • Patent number: 10353528
    Abstract: A detection device includes a substrate; a plurality of first conductive thin wires provided in a plane parallel to the substrate and extending in a first direction; a plurality of second conductive thin wires provided in the same layer as that of the first conductive thin wires and extending in a second direction forming an angle with the first direction; first groups that are disposed in first strip-like regions respectively having a first width, each of the first groups including at least two of the first conductive thin wires displaced from one another in the second direction; and second groups that are disposed in second strip-like regions respectively having a second width, each of the second groups including at least two of the second conductive thin wires displaced from one another in the first direction.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: July 16, 2019
    Assignee: JAPAN DISPLAY INC.
    Inventors: Koji Ishizaki, Hayato Kurasawa
  • Patent number: 10355049
    Abstract: An apparatus is provided that includes a bit line above a substrate, a word line above the substrate, and a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a reversible resistance-switching memory element coupled in series with an isolation element. The isolation element includes a first selector element coupled in series with a second selector element.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: July 16, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Michael K. Grobis, Derek Stewart, Bruce D. Terris
  • Patent number: 10355205
    Abstract: Resistive memory cells are described. In some embodiments, the resistive memory cells include a switching layer having an inner region in which one or more filaments is formed. In some instances, the filaments is/are formed only within the inner region of the switching layer. Methods of making such resistive memory cells and devices including such cells are also described.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: July 16, 2019
    Assignee: Intel Corporation
    Inventors: Prashant Majhi, Ravi Pillarisetty, Niloy Mukherjee, Uday Shah, Elijah V. Karpov, Brian S. Doyle, Robert S. Chau
  • Patent number: 10340449
    Abstract: A resistive memory device, such as a BMC ReRAM device, includes at least one resistive memory element which contains a carbon barrier material portion and a resistive memory material portion that is disposed between a first electrode and a second electrode.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: July 2, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ming-Che Wu, Alvaro Padilla, Tanmay Kumar
  • Patent number: 10340311
    Abstract: According to one embodiment, a magnetoresistive effect element includes: a first magnetic layer; a nonmagnetic layer provided on the first magnetic layer; a second magnetic layer provided on the nonmagnetic layer; a first insulating layer provided at least on a side surface of the second magnetic layer; a second insulating layer covering at least a part of the first insulating layer; a conductive layer provided between the first insulating layer and the second insulating layer; and a first electrode including a first portion on the second magnetic layer and a second portion on a side surface of the second insulating layer. A height of a lower surface of the second portion is equal to or less than a height of an upper surface of the conductive layer.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: July 2, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Megumi Yakabe, Satoshi Seto, Chikayoshi Kamata, Saori Kashiwada, Junichi Ito
  • Patent number: 10312289
    Abstract: A semiconductor memory device comprises a substrate, a plurality of first wirings arranged in a first direction crossing a surface of the substrate, a second wiring extending in the first direction, a variable resistance film provided between the first wiring and the second wiring, a third wiring extending in a second direction crossing the first direction, a select transistor provided between an end of the second wiring and the third wiring. In addition, the semiconductor memory device comprises a chalcogen layer provided at at least a position between the end of the second wiring and the select transistor, and, a position between the third wiring and the select transistor.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: June 4, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kensuke Ota, Masumi Saitoh
  • Patent number: 10312442
    Abstract: Non-volatile memory (NVM) devices, resistive random access memory (RRAM) devices and methods for fabricating such devices are provided. In an exemplary embodiment, a non-volatile memory (NVM) device includes a first electrode and a second electrode positioned above the first electrode. Further, the NVM device includes a variable resistance material layer positioned between the first electrode and the second electrode. The variable resistance material layer contains magnesium oxide.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: June 4, 2019
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Danny Pak-Chum Shum, Desmond Jia Jun Loy, Wen Siang Lew
  • Patent number: 10305034
    Abstract: In order to improve the number rewrites by improving the dielectric breakdown resistance of an ion conducting layer in a variable resistance element, this variable resistance element is provided with: a first electrode that contains at least copper; a second electrode that contains at least Ru, nitrogen and a first metal; and an ion conducting layer that is positioned between the first electrode and the second electrode.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: May 28, 2019
    Assignee: NEC CORPORATION
    Inventors: Munehiro Tada, Naoki Banno, Koichiro Okamoto
  • Patent number: 10290804
    Abstract: Resistive memory cells containing nanoparticles are formed between two electrodes. The nanoparticles may be embedded in a matrix or sintered together without a matrix. The memory cells may be projected memory cells or barrier modulated cells. Polymeric ligands may be used to deposit the nanoparticles over a substrate, followed by an optional removal or replacement of the polymeric ligands.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: May 14, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ricardo Ruiz, Jeffrey Lille, Mac D. Apodaca, Derek Stewart, Lei Wan, Bruce Terris
  • Patent number: 10290802
    Abstract: The forming voltage of a variable resistance device used in a non-volatile memory and the like is decreased, and repetition characteristics are improved. In an element structure in which a metal oxide film is sandwiched between a lower electrode and an upper electrode, an island-shaped/particulate region of amorphous aluminum oxide or aluminum oxycarbide is formed on the metal oxide film. Because an oxide deficiency, serving as the nucleus of a filament for implementing an on/off operation of the variable resistance device, is formed from the beginning under the island-shaped or particulate aluminum oxide or the like, the conventional creation of an oxide deficiency by high-voltage application in the initial period of forming can be eliminated. Such a region can be fabricated using a small number of cycles of an ALD process.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: May 14, 2019
    Assignee: National Insitute for Materials Science
    Inventors: Toshihide Nabatame, Tadaaki Nagao
  • Patent number: 10283706
    Abstract: A memory device includes first interconnects extending in a first direction; a second interconnect extending in a second direction crossing the first interconnects; an insulating film provided between two first interconnects; and a resistance change film between the first interconnects and the second interconnect. The resistance change film includes a first layer and second layers, the first layer extending in the second direction along the second interconnect, and the second layers being provided selectively between the respective first interconnects and the first layer. The second layers protrude toward the second interconnect exceeding an end surface of the insulating film in a third direction from the respective first interconnects toward the second interconnect. The respective second layers have a surface on a side of the first interconnects, and a width in the second direction of the surface is wider than a width in the second direction of the first interconnect.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: May 7, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki Ishikawa, Sanggyu Koh, Tetsu Morooka
  • Patent number: 10276779
    Abstract: The present application relates to a method for forming a top-electrode cap structure on a memory cell. In some embodiments, a method for forming a top-electrode cap structure on a memory cell. The method includes providing a memory cell comprising a top electrode, a bottom electrode, and a resistive memory element sandwiched between the top and bottom electrodes. An etch is performed into an interlayer dielectric (ILD) layer covering the memory cell to form a via opening exposing the top electrode of the memory cell. A getter layer is then formed to line the via opening, and further, over and abutting the top electrode of the memory cell. An oxygen-resistant layer is formed over and abutting the getter layer.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yao-Wen Chang, Tsung-Hsueh Yang
  • Patent number: 10270029
    Abstract: A resistive switching memory stack is provided. The resistive switching memory stack includes a bottom electrode, formed from one or more conductors. The resistive switching memory stack further includes an oxide layer, disposed over the bottom electrode, formed from an Atomic Layer Deposition (ALD) of one or more oxides. The resistive switching memory stack also includes a top electrode, disposed over the oxide layer, formed from the ALD of a plurality of metals into a metal layer stack. An oxygen vacancy concentration of the resistive switching memory stack is controlled by (i) a thickness of the plurality of metals forming the top electrode and (ii) a percentage of a particular one of the plurality of metals in the metal layer stack of the top electrode.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: April 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Vijay Narayanan, John Rozen
  • Patent number: 10263184
    Abstract: A switching device includes a first switching element having a snap-back behavior characteristic, an output voltage of the first switching element decreasing when an input current increases from a turn-on threshold current of the first switching element. The switching device further includes a second switching element having a continuous-resistance behavior characteristic, an output voltage of the second switching element increasing when the input current increases from a turn-on threshold current of the second switching element. The turn-on threshold current of the first switching element is lower than the turn-on threshold current of the second switching element.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: April 16, 2019
    Assignee: SK hynix Inc.
    Inventors: Tae Jung Ha, Soo Gil Kim
  • Patent number: 10249820
    Abstract: The semiconductor device includes a plurality of first conductive patterns on a substrate, a first selection pattern on each of the plurality of first conductive patterns, a first structure on the first selection pattern, a plurality of second conductive patterns on the first structures, a second selection pattern on each of the plurality of second conductive patterns, a second structure on the second selection pattern, and a plurality of third conductive patterns on the second structures. Each of the plurality of first conductive patterns may extend in a first direction. The first structure may include a first variable resistance pattern and a first heating electrode. The first variable resistance pattern and the first heating electrode may contact each other to have a first contact area therebetween. Each of the plurality of second conductive patterns may extend in a second direction crossing the first direction.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: April 2, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang-Woo Lee, Dae-Hwan Kang, Gwan-Hyeob Koh
  • Patent number: 10249681
    Abstract: A method of manufacturing a cross-point memory array device is disclosed. In the method, a substrate is provided. A plurality of first conductive line patterns are formed over the substrate. An insulating layer is formed over the first conductive line patterns. The insulating layer includes an insulative oxide. A plurality of switching film patterns are formed on the first conductive line patterns by selectively doping a plurality regions of the insulating layer. A plurality of memory structures are formed on the plurality of switching film patterns, respectively. A plurality of second conductive line patterns are formed on the plurality of memory structures.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: April 2, 2019
    Assignee: SK HYNIX INC.
    Inventors: Jong Chul Lee, Jongho Lee
  • Patent number: 10243019
    Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory for storing data, and the semiconductor memory may include a substrate; an interlayer dielectric layer over the substrate and patterned to include a contact hole; a lower contact structure formed over the substrate in the contact hole; and a variable resistance element formed over and electrically coupled to the lower contact structure, wherein the lower contact structure may include: a spacer formed on sidewalls of the contact hole in the interlayer dielectric layer and having a substantially uniform thickness along a direction perpendicular to a surface of the substrate; a contact plug filling a portion of the contact hole; and a contact pad formed over the contact plug and filling a remaining portion of the contact hole.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: March 26, 2019
    Assignee: SK hynix Inc.
    Inventors: Hyung-Suk Lee, Do-Yeon Kim
  • Patent number: 10236444
    Abstract: A variable resistance memory device includes first conductive lines positioned above a substrate. Each of the first conductive lines extends in a first direction and a second direction. Second conductive lines extend in the first direction and the second direction. The second conductive lines are positioned above the first conductive lines. A memory is positioned between the first and second conductive lines. The memory unit overlaps the first and second conductive lines in a third direction. The memory unit includes a first electrode, a variable resistance pattern positioned on the first electrode, and a second electrode positioned on the variable resistance pattern. A selection pattern is positioned on each memory unit. A third electrode is positioned above the selection pattern. The third electrode is in direct contact with a lower surface of each of the second conductive lines.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: March 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hideki Horii, Seong-Geon Park, Dong-Ho Ahn, Jung-Moo Lee
  • Patent number: 10229736
    Abstract: Memristive devices based on ion-transfer between two meta-stable phases in an ion intercalated material are provided. In one aspect, a memristive device is provided. The memristive device includes: a first inert metal contact; a layer of a phase separated material disposed on the first inert metal contact, wherein the phase separated material includes interstitial ions; and a second inert metal contact disposed on the layer of the phase separated material. The first phase of the phase separated material can have a different concentration of the interstitial ions from the second phase of the phase separated material such that the first phase of the phase separated material has a different electrical conductivity from the second phase of the phase separated material. A method for operating the present memristive device is also provided.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kevin W. Brew, Talia S. Gershon, Seyoung Kim, Glenn J. Martyna, Dennis M. Newns, Teodor K. Todorov
  • Patent number: 10204919
    Abstract: A vertical memory device is provided as follows. A substrate has a cell array region and a connection region adjacent to the cell array region. A first gate stack includes gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate. The gate electrode layers extends from the cell array region to the connection region in a second direction perpendicular to the first direction to form a first stepped structure on the connection region. The first stepped structure includes a first gate electrode layer and a second gate electrode layer sequentially stacked. The second gate electrode layer includes a first region having the same length as a length of the first gate electrode layer and a second region having a shorter length than the length of the first gate electrode layer.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: February 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoung Il Lee, Joong Shik Shin, Dong Seog Eun, Kyung Jun Shin, Hyun Kook Lee
  • Patent number: 10199391
    Abstract: A semiconductor device includes an under layer, a stacked body comprising a plurality of conductive layers and insulating layers alternately stacked one over the other in a stacking direction, above the insulating layer, a columnar portion extending into the stacked body in the stacking direction of the stacked body, and a graphene film between at least one of the conductive layers and adjacent insulating layers and between the at least one of the conductive layers and the columnar portion.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: February 5, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Taishi Ishikura, Atsunobu Isobayashi, Masayuki Kitamura, Akihiro Kajita
  • Patent number: 10192600
    Abstract: A storage element is provided. The storage element includes a layer structure including a first layer having a first magnetization state of a first material, a second layer having a second magnetization state of a second material; and an intermediate layer including a nonmagnetic material and provided between the first layer and the second layer, wherein the intermediate layer includes a carbon layer.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: January 29, 2019
    Assignee: Sony Corporation
    Inventors: Hiroyuki Uchida, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Yutaka Higo, Tetsuya Asayama, Kazutaka Yamane
  • Patent number: 10192928
    Abstract: A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film; a first conductive body contacting the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a side surface of the projecting part contacting an upper surface of the one of the first conductive films.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: January 29, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Natsuki Fukuda, Mutsumi Okajima, Atsushi Oga, Toshiharu Tanaka, Takeshi Yamaguchi, Takeshi Takagi, Masanori Komura
  • Patent number: 10177309
    Abstract: According to one embodiment, a memory device includes a nonvolatile memory element including a stacked structure and having a first resistive state and a second resistive state having higher resistance than the first resistive state, the stacked structure including a first layer containing bismuth (Bi) and tellurium (Te) and a second layer containing germanium (Ge) and tellurium (Te).
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: January 8, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoshiki Kamata
  • Patent number: 10163981
    Abstract: The present disclosure relates to an integrated circuit having an interconnect wire contacting an upper electrode of the RRAM (resistive random access memory) device, and a method of formation. In some embodiments, the integrated circuit comprises an RRAM device having a dielectric data storage layer disposed between a lower electrode and an upper electrode. An interconnect wire contacts an upper surface of the upper electrode, and an interconnect via is arranged onto the interconnect wire. The interconnect via is set back from one or more outermost sidewalls of the interconnect wire. The interconnect wire has a relatively large size that provides for a good electrical connection between the interconnect wire and the upper electrode, thereby increasing a process window of the RRAM device.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 10161046
    Abstract: Disclosed is a method for forming a metal particle layer having irregular structures in a simpler manner. The method includes bringing a base into contact with an activation solution including a metal compound, an organic acid activator, and a complexing agent. The base is oxidized by the organic acid activator to produce electrons and the metal compound is reduced by the electrons to deposit metal particles on the surface of the base. Also disclosed is a method for fabricating a light emitting device with improved light extraction efficiency that uses a metal particle layer formed by the above method.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: December 25, 2018
    Assignee: LG CHEM, LTD.
    Inventors: Hee Han, Kyungjun Kim
  • Patent number: 10164178
    Abstract: In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: December 25, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Jun Liu, Kunal Parekh
  • Patent number: 10158067
    Abstract: A memory device includes a first conductive layer, a second conductive layer, and a variable resistance layer provided between the first and second conductive layers. The variable resistance layer includes a first layer having a semiconductor or a first metal oxide containing a first metal, and a second layer provided between the first layer and the second conductive layer, having a second metal oxide containing a second metal, and having crystal grains that are not in contact with at least one of an end face of the second layer on a side of the first conductive layer or an end face of the second layer on a side of the second conductive layer.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: December 18, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuhiko Yamamoto, Yosuke Murakami, Yusuke Arayashiki, Yusuke Kobayashi
  • Patent number: 10153327
    Abstract: A semiconductor device includes first isolation lines positioned above a substrate and extending in a first direction. Second isolation lines are positioned above the first isolation lines and extend in a second direction, perpendicular to the first direction, to have a right angle on a plane parallel to an upper surface of the substrate. A first conductive line is disposed between the first isolation lines. The first conductive line is spaced apart from the substrate. A second conductive line is disposed between the second isolation lines. First data storage patterns are disposed between the first isolation lines. The first data storage patterns are positioned above the first conductive line. Second data storage patterns are disposed between the second isolation lines. The second data storage patterns are positioned above the second conductive line. A third conductive line is positioned above the second isolation lines and extends in the first direction.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: December 11, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jong Chul Park
  • Patent number: 10153432
    Abstract: A resistive random access memory (RRAM) structure including a substrate, RRAM cells and protection layers is provided. The RRAM cells are adjacent to each other and disposed on the substrate. The protection layers are disposed respectively on sidewalls of the RRAM cells without covering top surfaces of the RRAM cells. Each of the protection layers includes a sidewall portion and an extension portion. The sidewall portion is disposed on each of the sidewalls of each of the RRAM cells. The extension portion is connected to a lower portion of the sidewall portion. An upper portion of the extension portion is lower than an upper portion of the sidewall portion. The extension portion is connected between the sidewall portions in a region between the RRAM cells.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: December 11, 2018
    Assignee: United Microelectronics Corp.
    Inventor: Mengkai Zhu
  • Patent number: 10153729
    Abstract: In some examples, a device includes a nano-scale oscillator that exhibits chaotic oscillation responsive to a control input to the nano-scale oscillator, where the control input including a tunable input parameter.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: December 11, 2018
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Suhas Kumar, John Paul Strachan, Gary Gibson, R. Stanley Williams
  • Patent number: 10147876
    Abstract: Systems and methods for providing a phase change memory that includes a phase change material, such as a chalcogenide material, in series with a heating element that comprises multiple thermal interfaces are described. The multiple thermal interfaces may cause the heating element to have a reduced bulk thermal conductivity or a lower heat transfer rate across the heating element without a corresponding reduction in electrical conductivity. The phase change material may comprise a germanium-antimony-tellurium compound or a chalcogenide glass. The heating element may include a plurality of conducting layers with different thermal conductivities. In some cases, the heating element may include two or more conducting layers in which the conducting layers comprise the same electrically conductive material or compound but are deposited or formed using different temperatures, carrier gas pressures, flow rates, and/or film thicknesses to create thermal interfaces between the two or more conducting layers.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: December 4, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Lidu Huang, Mac D. Apodaca, Toshiki Hirano, Ailian Zhao, Guy Charles Wicker, Federico Nardi
  • Patent number: 10141330
    Abstract: A method of forming a semiconductor device structure comprises forming a stack structure comprising stacked tiers. Each of the stacked tiers comprises a first structure comprising a first material and a second structure comprising a second, different material longitudinally adjacent the first structure. A patterned hard mask structure is formed over the stack structure. Dielectric structures are formed within openings in the patterned hard mask structure. A photoresist structure is formed over the dielectric structures and the patterned hard mask structure. The photoresist structure, the dielectric structures, and the stack structure are subjected to a series of material removal processes to form apertures extending to different depths within the stack structure. Dielectric structures are formed over side surfaces of the stack structure within the apertures. Conductive contact structures are formed to longitudinally extend to bottoms of the apertures.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: November 27, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Roger W. Lindsay, Michael A. Smith, Brett D. Lowe
  • Patent number: 10141502
    Abstract: Disclosed are a semiconductor memory device and a method of manufacturing the same. A first conductive line extends in a first direction on a substrate and has a plurality of protrusions and recesses that are alternately formed thereon. A second conductive line is arranged over the first conductive line in a second direction such that the first and the second conductive lines cross at the protrusions. A plurality of memory cell structures is positioned on the protrusions of the first conductive line and is contact with the second conductive line. A thermal insulating plug is positioned on the recesses of the first conductive line and reduces heat transfer between a pair of the neighboring cell structures in the first direction. Accordingly, the heat cross talk is reduced between the neighboring cell structures along the conductive line.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: November 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Il-Mok Park, Dae-Hwan Kang, Gwan-Hyeob Koh
  • Patent number: 10141509
    Abstract: Embodiments of the present invention provide systems and methods for the fabrication of a crossbar array fabrication of resistive random access memory (RRAM) cells. The array structure contains large grain copper and its alloy or silver and its alloy. A metal cap and spacer are used to protect copper or silver from chemical modifications during memory cell patterning.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: November 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Marwan H. Khater, Seyoung Kim, Hiroyuki Miyazoe
  • Patent number: 10141505
    Abstract: Methods of depositing silicon nitride encapsulation layers by atomic layer deposition over memory devices including chalcogenide material are provided herein. Methods include using iodine-containing and/or bromine-containing silicon precursors and depositing thermally using ammonia or hydrazine as a second reactant, or iodine-containing and/or bromine-containing silicon precursors and depositing using a nitrogen-based or hydrogen-based plasma.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: November 27, 2018
    Assignee: Lam Research Corporation
    Inventor: Dennis M. Hausmann