With Specified Electrode Composition Or Configuration Patents (Class 257/4)
  • Patent number: 10811602
    Abstract: Memory devices based on tungsten oxide memory elements are described, along with methods for manufacturing such devices. A memory device includes a plug extending upwardly from a top surface of a substrate through a dielectric layer; a bottom electrode having tungsten on an outside surface, the bottom electrode extending upwardly from a top surface of the plug; an insulating material in contact with the tungsten on the outside surface of, and surrounding, the bottom electrode; a memory element on an upper surface of the bottom electrode, the memory element comprising a tungsten oxide compound and programmable to at least two resistance states; and a top electrode overlying and contacting the memory element. The plug has a first lateral dimension, and the bottom electrode has a lateral dimension parallel with the first lateral dimension of the plug that is less than the first lateral dimension.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: October 20, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Dai-Ying Lee, Feng-Min Lee
  • Patent number: 10804465
    Abstract: A resistive random access memory and a manufacture method thereof are provided. The resistive random access memory includes: a first electrode, a second electrode, a resistive layer between the first electrode and the second electrode, and at least one thermal enhanced layer; the thermal enhanced layer is adjacent to the resistive layer, and a thermal conductivity of the thermal enhanced layer is less than a thermal conductivity of the first electrode and a thermal conductivity of the second electrode.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: October 13, 2020
    Assignee: TSINGHUA UNIVERSITY
    Inventors: Huaqiang Wu, Wei Wu, Bin Gao, He Qian
  • Patent number: 10804324
    Abstract: Technologies relating to a crossbar array circuit with a one-transistor-two-memristor (1T2R) Resistive Random-Access Memory (RRAM) and a common reactive electrode in the applications of the crossbar array circuit are disclosed. An example crossbar array circuit includes: a two-memristor structure, wherein the two-memristor structure includes: a first bottom electrode; a first RRAM stack formed on the first bottom electrode; a top electrode formed on the first RRAM stack; a second RRAM stack formed on the top electrode; and a second bottom electrode formed on the second RRAM stack, wherein the top electrode is a reactive or scavenging electrode which is configured to provide the first RRAM stack and the second RRAM stack with oxygen vacancies near the reactive electrode; and a one-transistor structure, wherein the one-transistor structure includes: a source electrode; a gate electrode; and a drain electrode, wherein the source electrode is connected to the top electrode.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: October 13, 2020
    Inventors: Minxian Zhang, Ning Ge
  • Patent number: 10796901
    Abstract: A core/shell semiconductor nanoparticle structure comprises a core comprising a halide perovskite semiconductor and a shell comprising a semiconductor material that is not a halide perovskite (and that is substantially free of halide perovskites). The halide perovskite semiconductor core may be of the form AMX3, wherein: A is an organic ammonium such as CH3NH3+, (C8H17)2(CH3NH3)+, PhC2H4NH3+, C6H11CH2NH3+ or 1-adamantyl methyl ammonium, an amidinium such as CH(NH2)2+, or an alkali metal cation such as Li+, Na+, K+, Rb+ or Cs+; M is a divalent metal cation such as Mg2+, Mn2+, Ni2+, Co2+, Pb2+, Sn2+, Zn2+, Ge2+, Eu2+, Cu2+ or Cd2+; and X is a halide anion (F?, Cl?, Br?, I?) or a combination of halide anions.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: October 6, 2020
    Assignee: Nanoco Technologies Ltd.
    Inventors: Nigel L. Pickett, Nathalie C. Gresty, Ombretta Masala, Jie Li
  • Patent number: 10797236
    Abstract: A resistive memory device and a method of operation of the resistive memory device are provided. The resistance memory device includes a resistance change layer that has a tunneling film and has many states. The conductance is changed symmetrically in a SET operation and a RESET operation. Thus, the resistive memory device can be used for efficient and accurate data storage as a RRAM in a high-capacity memory array, and as a synaptic device controlling the connection strength of a synapse in a neuromorphic system.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: October 6, 2020
    Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Byung-Gook Park, Min-Hwi Kim, Sungjun Kim
  • Patent number: 10790285
    Abstract: Disclosed is a method for forming a staircase structure of 3D memory. The method includes providing a substrate, forming an alternating layer stack over the substrate, forming a plurality of block regions over a surface of the alternating layer stack, forming a first plurality of staircase structures to expose a portion of a first number of top-most layer stacks at each of the block regions and removing the first number of the layer stacks at a second plurality of staircase structures at each of the block regions.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: September 29, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhong Zhang, Yan Ni Li
  • Patent number: 10790445
    Abstract: Embodiments of the invention are directed to a resistive switching device (RSD) that includes a first terminal, a second terminal, an active region having a switchable conduction state, and a protuberant contact communicatively coupled to the first terminal. The protuberant contact is configured to communicatively couple the first terminal through a first barrier liner to a first electrode line of a crossbar array. In embodiments of the invention, the protuberant contact is positioned with respect to the first barrier liner such that the first barrier liner does not impacting the switchable conduction state of the active region. In embodiments of the invention, the protuberant contact is positioned with respect to the first barrier liner such that the first barrier liner does not directly contact the first terminal.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: September 29, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Chih-Chao Yang, Lawrence A. Clevenger
  • Patent number: 10784313
    Abstract: A method is presented for forming a cell structure. The method includes constructing a resistive random access memory (RRAM) device, constructing a phase change memory (PCM) device in series with the RRAM device such that one of the electrodes of the PCM device is connected to a reactive electrode of the RRAM device, and connecting a complementary metal oxide semiconductor (CMOS) inverter to the RRAM and PCM devices to individually control switching behaviors of the RRAM and PCM devices.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Nanbo Gong, Takashi Ando, Guy M. Cohen
  • Patent number: 10770389
    Abstract: A radio frequency (RF) switch includes a phase-change material (PCM), a heating element underlying an active segment of the PCM and extending outward and transverse to the PCM, and RF terminals having lower metal portions and upper metal portions. At least one of the lower metal portions can be ohmically separated from and capacitively coupled to passive segments of the PCM, while the upper metal portions are ohmically connected to the lower metal portions. Alternatively, the lower metal portions can be ohmically connected to passive segments of the PCM, while a capacitor is formed in part by at least one of the upper metal portions. Alternatively, at least one of the RF terminals can have a trench metal liner separated from a trench metal plug by a dielectric liner. The trench metal liner can be ohmically connected to passive segments of the PCM, while the trench metal plug is ohmically separated from, but capacitively coupled to, the trench metal liner.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 8, 2020
    Assignee: Newport Fab, LLC
    Inventors: Nabil El-Hinnawy, Gregory P. Slovin, Jefferson E. Rose, David J. Howard
  • Patent number: 10770660
    Abstract: Provided is a novel heterocyclic compound, a novel heterocyclic compound that can be used in a light-emitting element, or a highly reliable light-emitting device, electronic device, and lighting device in each of which the light-emitting element using the novel heterocyclic compound is used. One embodiment of the present invention is a heterocyclic compound represented by General Formula (G1). In General Formula (G1), each of A1 and A2 independently represents nitrogen or carbon bonded to hydrogen, and at least one of A1 and A2 represents nitrogen; Ar represents a substituted or unsubstituted arylene group having 6 to 18 carbon atoms; B represents a substituted or unsubstituted fluorenyl group; and R1 represents hydrogen, an alkyl group having 1 to 6 carbon atoms, or an aryl group having 6 to 13 carbon atoms.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: September 8, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideko Inoue, Tomoka Hara, Yasushi Kitano, Hiromi Seo, Tatsuyoshi Takahashi, Satoshi Seo
  • Patent number: 10749040
    Abstract: A integrated device including a non-volatile memory (NVM) and a nanosheet field effect transistor (FET) and a method of fabricating the device include patterning fins for a channel region of the NVM and the FET. The method also includes depositing an organic planarization layer (OPL) and a block mask to protect the fins for the channel region of the FET, conformally depositing a set of layers that make up an NVM structure in conjunction with the channel region of the NVM while protecting the fins for the channel region of the FET with the OPL and the block mask, and removing the OPL and the block mask protecting the fins for the channel region of the FET. Source and drain regions of the NVM and the FET are formed, and a gate of the FET is formed while protecting the NVM by depositing another OPL and another block mask.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: August 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dexin Kong, Zhenxing Bi, Zheng Xu, Kangguo Cheng
  • Patent number: 10734579
    Abstract: Embodiments of the invention are directed to a resistive switching device (RSD) that includes a first terminal, a second terminal, an active region having a switchable conduction state, and a protuberant contact communicatively coupled to the first terminal. The protuberant contact is configured to communicatively couple the first terminal through a first barrier liner to a first electrode line of a crossbar array. In embodiments of the invention, the protuberant contact is positioned with respect to the first barrier liner such that the first barrier liner does not impacting the switchable conduction state of the active region. In embodiments of the invention, the protuberant contact is positioned with respect to the first barrier liner such that the first barrier liner does not directly contact the first terminal.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: August 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Chih-Chao Yang, Lawrence A. Clevenger
  • Patent number: 10727406
    Abstract: Subject matter herein disclosed relates to an improved CEM switching device and methods for its manufacture. In this device, a conductive substrate and/or conductive overlay comprises a primary layer of a conductive material and a secondary layer of a conductive material. The primary layer contacting the CEM layer is substantially inert to the CEM layer and/or acts as an oxygen barrier for the secondary layer at temperatures used for the manufacture of the device.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: July 28, 2020
    Assignee: Arm Limited
    Inventors: Carlos Alberto Paz de Araujo, Jolanta Bozena Celinska, Kimberly Gay Reid, Lucian Shifren
  • Patent number: 10727403
    Abstract: A resistive memory device may include a plurality of MATs, row control blocks, a plurality of word lines, a plurality of bit lines and memory cells. Each of the row control blocks may be interposed between the MATs. Each of the row control blocks may include a control element. The word lines may be arranged spaced apart from each other by a substantially uniform gap on the MATs. The bit lines may overlap with the word lines. The memory cells may be located between the word lines and the bit lines. Each of the word lines may be electrically connected with the control element of each of the row control blocks via a connection path.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: July 28, 2020
    Assignee: SK hynix Inc.
    Inventors: Hyuck Sang Yim, Myung Sun Song
  • Patent number: 10727407
    Abstract: A method is presented for facilitating oxygen vacancy generation in a resistive random access memory (RRAM) device. The method includes forming a RRAM stack having a first electrode and at least one sacrificial layer, encapsulating the RRAM stack with a dielectric layer, constructing a via resulting in removal of the at least one sacrificial layer of the RRAM stack, the via extending to a high-k dielectric layer of the RRAM stack, and forming a second electrode in the via such that the second electrode extends laterally into cavities defined by the removal of the at least one sacrificial layer.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: July 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Hiroyuki Miyazoe, Seyoung Kim, Vijay Narayanan
  • Patent number: 10714535
    Abstract: A method includes forming an insulator over a substrate. The insulator includes a first electrode, a second electrode, and a resistive element between the first electrode and the second electrode. The insulator is transformed into a resistor by applying a voltage to the insulator. The resistor is electrically connected to a transistor after transforming the insulator into the resistor.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ku-Feng Lin, Hung-Chang Yu, Kai-Chun Lin, Yu-Der Chih
  • Patent number: 10707415
    Abstract: Subject matter disclosed herein may relate to fabrication of correlated electron materials used, for example, to perform specified application performance parameters. In embodiments, CEM devices fabricated at a first stage of a wafer fabrication process, such as a front-end-of-line stage, may differ from CEM devices fabricated at a second stage of a wafer fabrication process, such as a middle-of-line stage or a back-end-of-line stage, for example.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: July 7, 2020
    Assignee: Arm Limited
    Inventors: Lucian Shifren, Kimberly Gay Reid, Gregory Munson Yeric, Manuj Rathor, Glen Arnold Rosendale
  • Patent number: 10700277
    Abstract: A memory device may include a bottom electrode, first and second switching elements over the bottom electrode, and first and second top electrodes over the first and second switching elements respectively. The first and second top electrodes may include first and second contact surfaces in contact with the first and second switching elements respectively. The first and second switching elements may each have a resistance configured to switch between resistance values in response to changes in voltages applied between the top electrodes and the bottom electrode. The bottom electrode may include at least one conductive layer having third and fourth contact surfaces in contact with the first and second switching elements respectively. An area of the first contact surface may be greater than an area of the third contact surface, and an area of the second contact surface may be greater than an area of the fourth contact surface.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: June 30, 2020
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Lanxiang Wang, Shyue Seng Tan, Eng Huat Toh
  • Patent number: 10700129
    Abstract: Embodiments of the invention are directed to a vertical resistive device. A non-limiting example of the vertical resistive device includes a conductive horizontal electrode, an opening extending through the horizontal electrode, a filament region positioned within the opening and communicatively coupled to a sidewall of the horizontal electrode, and a conductive vertical electrode positioned within the opening and communicatively coupled to the filament region. The vertical electrode includes a first conductive alloy material. Oxygen vacancy formation in the filament region is controlled by the first conductive alloy material of the vertical electrode. A room temperature resistivity of the first conductive alloy material is below about 5×10?8 ohm meters and controlled by at least one of the metals that form the first conductive alloy material.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: June 30, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Choonghyun Lee
  • Patent number: 10700274
    Abstract: A method of fabricating a phase change material (PCM) device is provided. The method includes disposing a dielectric layer above or below a PCM layer and disposing first and second contacts in a same plane within the dielectric layer with the first contact having a larger contact area than the second contact. The method also includes one of directing a short current pulse from the first contact to the second contact so as to form amorphous-PCM in a region of the PCM layer adjacent to the second contact with crystalline-PCM partially surrounding and in contact with the amorphous-PCM and directing a long current pulse from the first contact to the second contact so as to form crystalline-PCM in the region of the PCM layer adjacent to the second contact.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: June 30, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Guy Cohen
  • Patent number: 10693061
    Abstract: An IC (“integrated circuit”) chip includes a substrate and a phase-change material (PCM) radio frequency (RF) switch, having a heating element, a PCM situated over the heating element, and PCM contacts situated over passive segments of the PCM. The heating element extends transverse to the PCM and underlies an active segment of the PCM. An active device is situated in the substrate. In one approach, the PCM RF switch is situated over the substrate, and the substrate is a heat spreader for the PCM RF switch. In another approach, the PCM RF switch is situated in or above a first metallization level, and a dedicated heat spreader is situated under the PCM RF switch. Alternatively, a PCM RF switch is situated in a flip chip, an active device is situated in the IC chip, and the flip chip is situated over the IC chip forming a composite device.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: June 23, 2020
    Assignee: Newport Fab, LLC
    Inventors: Nabil El-Hinnawy, Gregory P. Slovin, Jefferson E. Rose, David J. Howard
  • Patent number: 10693060
    Abstract: The present disclosure provides a phase change memory structure, including a bottom electrode, a first phase change material contacting a top surface of the bottom electrode, a first switch over the first phase change material, a second phase change material over the first switch, and a top electrode over the second phase change material.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Jau-Yi Wu
  • Patent number: 10692931
    Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes stack structures, a gap-fill layer filling spaces between the stack structures, and nanopores located in the gap-fill layer. Each of the stack structures includes a memory pattern. The nanopores are distributed in a portion of the gap-fill layer that is located at a level corresponding to where the memory pattern is located in each of the stack structures.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: June 23, 2020
    Assignee: SK hynix Inc.
    Inventor: Hyung Suk Lee
  • Patent number: 10686130
    Abstract: A radio frequency (RF) switch includes a phase-change material (PCM) and a heating element underlying an active segment of the PCM, the PCM and heating element being situated over a substrate. A contact dielectric is over the PCM. PCM contacts have upper portions and uniform plate slot lower portions. The uniform plate slot lower portions have a total plate resistance RPLATE, and a total plate slot interface resistance RPLATE-INT. The upper portions have a total capacitance CUPPER to the uniform plate slot lower portions, and the PCM has a total capacitance CPCM to the substrate. The uniform plate slot lower portions significantly reduce a product of (RPLATE+RPLATE-INT) and (CUPPER+CPCM). As an alternative to the uniform plate slot lower portions, PCM contacts have segmented lower portions. The segmented lower portions significantly reduce CUPPER.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: June 16, 2020
    Assignee: Newport Fab, LLC
    Inventors: David J. Howard, Jefferson E. Rose, Gregory P. Slovin, Nabil El-Hinnawy, Michael J. DeBar
  • Patent number: 10686045
    Abstract: A semiconductor memory device according to an embodiment, includes a pair of first electrodes, a semiconductor pillar, an inter-pillar insulating member, a first insulating film, a second electrode, and a second insulating film. The pair of first electrodes are separated from each other, and extend in a first direction. The semiconductor pillar and the inter-pillar insulating member are arranged alternately along the first direction between the pair of first electrodes. The semiconductor pillar and the inter-pillar insulating member extend in a second direction crossing the first direction. The first insulating film is provided at a periphery of the semiconductor pillar. The second electrode is provided between the first insulating film and each electrode of the pair of first electrodes. The second electrode is not provided between the semiconductor pillar and the inter-pillar insulating member. The second insulating film is provided between the second electrode and the first electrode.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: June 16, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Tatsuya Kato, Fumitaka Arai, Katsuyuki Sekine, Toshiyuki Iwamoto, Yuta Watanabe, Wataru Sakamoto
  • Patent number: 10686128
    Abstract: A semiconductor device includes a substrate and a phase-change material (PCM) radio frequency (RF) switch, having a heating element, a PCM situated over the heating element, and PCM contacts situated over passive segments of the PCM. The heating element extends transverse to the PCM and underlies an active segment of the PCM. In one approach, the PCM RF switch is situated over the substrate, and the substrate is a heat spreader for the PCM RF switch. An integrated passive device (IPD) is disposed in an interlayer dielectric above the PCM RF switch, and is a metal resistor, a metal-oxide-metal (MOM) capacitor, and/or and inductor. In another approach, the PCM RF switch is disposed in an interlayer dielectric above the IPD, and the IPD is a poly resistor and/or a capacitor.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: June 16, 2020
    Assignee: Newport Fab, LLC
    Inventors: Nabil El-Hinnawy, Gregory P. Slovin, Jefferson E. Rose, David J. Howard
  • Patent number: 10680102
    Abstract: A method of forming a semiconductor device that includes forming at least two semiconductor fin structures having sidewalls with {100} crystalline planes that is present atop a supporting substrate; and epitaxially growing a source/drain region in a lateral direction from the sidewalls of each fin structure. The second source/drain regions have substantially planar sidewalls. A metal wrap around electrode is formed on an upper surface and the substantially planar sidewalls of the source/drain regions. Air gaps are formed between the source/drain regions of the at least two semiconductor fin structures.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: June 9, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Choonghyun Lee, Kangguo Cheng, Juntao Li, Shogo Mochizuki
  • Patent number: 10680597
    Abstract: The disclosed technology generally relates to a switching device and more particularly to a switching device based on an active portion capable of switching from an insulating state to a conductive state. In an aspect, a switching device comprises an active portion interposed between two electrodes and capable of switching from an insulating state to a conducting state when a voltage higher than a threshold value is applied between the two electrodes. The threshold value is lowered by a dielectric permittivity distribution which produces a concentration of electrical field at a location within the active portion. Thus, the switching device may be devoid of a third control electrode.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: June 9, 2020
    Assignee: IMEC vzw
    Inventors: Daniele Garbin, Robin Degraeve, Ludovic Goux
  • Patent number: 10680038
    Abstract: In some embodiments, the present disclosure relates to a method of forming a memory circuit. The method may be performed by forming an interconnect wire within an inter-level dielectric (ILD) layer over a substrate. A conjunct electrode structure is formed over the interconnect wire, a data storage film is formed over the conjunct electrode structure, and a disjunct electrode structure is formed over the data storage film. The data storage film, the disjunct electrode structure, and the conjunct electrode structure are patterned to form a first data storage layer between the interconnect wire and a first disjunct electrode and to form a second data storage layer between the interconnect wire and a second disjunct electrode.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Chieh Yang, Chih-Yang Chang, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 10672432
    Abstract: A semiconductor device comprises a stack structure comprising decks each comprising a memory element level comprising memory elements, and a control logic level in electrical communication with the memory element level and comprising control logic devices. At least one of the control logic devices of the control logic level of one or more of the decks comprises at least one device exhibiting a gate electrode shared by neighboring vertical transistors thereof. A control logic assembly, a control logic device, an electronic system, a method of forming a control logic device, and a method of operating a semiconductor device are also described.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kurt D. Beigel, Scott E. Sills
  • Patent number: 10658579
    Abstract: A storage device includes a first conductive layer and a second conductive layer, with an intermediate layer therebetween. The intermediate layer includes a first and second compound regions. The first compound region includes first and second adjacent portions and the second compound region includes third and fourth adjacent portions. Electrical resistance between the first and second conductive layers changes according to a polarity applied across the intermediate layer. In a first polarity state, a concentration of a first element in the first portion is higher than a concentration of the first element in the second portion of the first compound region. A thickness of the third portion in the first polarity state is greater than the thickness of the fourth portion in the first polarity state.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: May 19, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kensuke Ota, Yoko Yoshimura, Yoshihiko Moriyama
  • Patent number: 10658581
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a lower electrode over the semiconductor substrate. The semiconductor device structure also includes a first oxide layer over the lower electrode, a second oxide layer over the first oxide layer, and a third oxide layer over the second oxide layer. Oxygen ions are bonded more tightly in the second oxide layer than those in the first oxide layer, and oxygen ions are bonded more tightly in the second oxide layer than those in the third oxide layer. The semiconductor device structure further includes an upper electrode over the third oxide layer.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hai-Dang Trinh, Hsing-Lien Lin, Chii-Ming Wu, Cheng-Yuan Tsai
  • Patent number: 10658582
    Abstract: A vertical resistive unit is provided. The vertical resistive unit includes first and second resistive random access memory (ReRAM) cells. The first ReRAM cell includes first vertically aligned horizontal electrode layers and first vertical electrodes operably extending through the first vertically aligned horizontal electrode layers. The second ReRAM cell includes second vertically aligned horizontal electrode layers and second vertical electrodes operably extending through the second vertically aligned horizontal electrode layers. The first and second ReRAM cells are disposed to define an air gap between the first and second ReRAM cells.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: May 19, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Pouya Hashemi, Choonghyun Lee
  • Patent number: 10651380
    Abstract: In a non-limiting embodiment, a device may be formed having a substrate that has at least a first region. A base dielectric layer is arranged over the substrate. The base dielectric layer includes an interconnect in the first region. A first electrode is arranged over the interconnect in the first region. A mask structure is arranged over the first electrode. At least one spacer stack is arranged at least partially around the mask structure and the first electrode. The spacer stack(s) includes a resistive switching element at least partially lining sidewalls of the mask structure and the first electrode, and a second electrode arranged over the resistive switching element.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: May 12, 2020
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Curtis Chun-I Hsieh, Wei-Hui Hsu, Wanbing Yi, Yi Jiang, Juan Boon Tan
  • Patent number: 10644023
    Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: May 5, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Sup Lee, Sung-Hun Lee, Joonhee Lee, Seong Soon Cho
  • Patent number: 10629811
    Abstract: A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fu-Ting Sung, Ching-Pei Hsieh, Chia-Shiung Tsai, Chern-Yow Hsu, Shih-Chang Liu
  • Patent number: 10629651
    Abstract: A three dimensional (3D) memory array and method of manufacturing the same are described. The 3D memory array may include an electrode plane and a memory material disposed through and coupled to the electrode plane. A memory cell included in the memory material is aligned in a same plane as the electrode plane, and the memory cell is configured to exhibit a first threshold voltage representative of a first logic state and a second threshold voltage representative of a second logic state. A conductive pillar is disposed through and coupled to the memory cell, wherein the conductive pillar and electrode plane are configured to provide a voltage across the memory cell to write a logic state to the memory cell. Methods to operate and to form the 3D memory array are disclosed.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: April 21, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Fabio Pellizzer
  • Patent number: 10629652
    Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: April 21, 2020
    Assignee: Intel Corporation
    Inventors: Michael J. Bernhardt, Yudong Kim, Denzil S. Frost, Tuman Earl Allen, III, Kevin Lee Baker, Kolya Yastrebenetsky, Ronald Allen Weimer
  • Patent number: 10621267
    Abstract: A technique includes providing a first set of values to a memristor crossbar array and using the memristor crossbar array to perform a Fourier transformation. Using the memristor crossbar array to perform the Fourier transform includes using the array to apply a Discrete Fourier Transform (DFT) to the first set of values to provide a second set of values.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: April 14, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: John Paul Strachan, Miao Hu, R. Stanley Williams, Zhiyong Li
  • Patent number: 10615227
    Abstract: A resistance-switchable material containing: an insulating support; and a complementary resistance switchable filler dispersed in the insulating support, wherein the complementary resistance switchable filler has a spherical core-shell structure containing: a spherical conductive core containing a conductive material; and an insulating shell formed on the surface of the core and containing an insulating material. The resistance-switchable material is capable of exhibiting complementary resistive switching characteristics with improved reliability and stability as symmetrical uniform filament current paths are formed in respective resistive layers adjacent to two electrodes with the conductive core of the complementary resistance-switchable filler at the center due to the electric field control effect by the spherical complementary resistance-switchable filler.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: April 7, 2020
    Assignee: Korea Institute of Science and Technology
    Inventors: Sang-Soo Lee, Jong Hyuk Park, Jeong Gon Son, Minsung Kim, Young Jin Kim, Heesuk Kim
  • Patent number: 10615341
    Abstract: The semiconductor device includes a plurality of first conductive patterns on a substrate, a first selection pattern on each of the plurality of first conductive patterns, a first structure on the first selection pattern, a plurality of second conductive patterns on the first structures, a second selection pattern on each of the plurality of second conductive patterns, a second structure on the second selection pattern, and a plurality of third conductive patterns on the second structures. Each of the plurality first conductive patterns may extend in a first direction. The first structure may include a first variable resistance pattern and a first heating electrode. The first variable resistance pattern and the first heating electrode may contact each other to have a first contact area therebetween. Each of the plurality of second conductive patterns may extend in a second direction crossing the first direction.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: April 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang-Woo Lee, Dae-Hwan Kang, Gwan-Hyeob Koh
  • Patent number: 10615288
    Abstract: A integrated device including a non-volatile memory (NVM) and a nanosheet field effect transistor (FET) and a method of fabricating the device include patterning fins for a channel region of the NVM and the FET. The method also includes depositing an organic planarization layer (OPL) and a block mask to protect the fins for the channel region of the FET, conformally depositing a set of layers that make up an NVM structure in conjunction with the channel region of the NVM while protecting the fins for the channel region of the FET with the OPL and the block mask, and removing the OPL and the block mask protecting the fins for the channel region of the FET. Source and drain regions of the NVM and the FET are formed, and a gate of the FET is formed while protecting the NVM by depositing another OPL and another block mask.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dexin Kong, Zhenxing Bi, Zheng Xu, Kangguo Cheng
  • Patent number: 10608176
    Abstract: A memory cell pillar of a memory device includes a heating electrode having a base portion (leg) and a fin portion (ascender), and a selection device between a first conductive line and the heating electrode. A side surface of the selection device and a side surface of the fin portion extend along a first straight line. A method of fabricating a memory device includes forming a plurality of first insulating walls through a stack structure including a preliminary selection device layer and a preliminary electrode layer, forming a plurality of self-aligned preliminary heating electrode layers, forming a plurality of second insulating walls each between two of the plurality of first insulating walls, and forming a plurality of third insulating walls in a plurality of holes extending along a direction intersecting the plurality of first insulating walls.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: March 31, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Masayuki Terai
  • Patent number: 10593729
    Abstract: Embodiments of the invention are directed to a vertical resistive device. A non-limiting example of the vertical resistive device includes a horizontal plate having a conductive electrode region and a filament region. An opening extends through the filament region and is defined by sidewalls of the filament such that the filament region is positioned outside of the opening. A conductive pillar is positioned within the opening and is communicatively coupled to the filament region.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: March 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Robert L. Bruce, Hiroyuki Miyazoe, John Rozen
  • Patent number: 10593399
    Abstract: Methods, systems, and devices for self-selecting memory with horizontal access lines are described. A memory array may include first and second access lines extending in different directions. For example, a first access line may extend in a first direction, and a second access line may extend in a second direction. At each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material (SSM). Further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction. each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: March 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Lorenzo Fratin, Fabio Pellizzer, Agostino Pirovano, Russell L. Meyer
  • Patent number: 10586831
    Abstract: A light emitting diode memory includes a substrate, a tunneling structure, a current spreading layer, a first electrode layer and a second electrode layer. The tunneling structure is formed on the substrate. The tunneling structure includes first, second and third material layers. The current spreading layer is formed on the tunneling structure. The first electrode layer is formed on the substrate. The second electrode layer is formed on the current spreading layer. When a bias voltage applied to the first electrode layer and the second electrode layer is higher than a reset voltage, the light emitting diode memory is in a reset state. When the bias voltage is lower than a set voltage, the light emitting diode memory is in a set state. When the bias voltage is higher than a turn-on voltage, the light emitting diode memory emits a light beam.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: March 10, 2020
    Assignee: OPTO TECH CORPORATION
    Inventors: Jun-Jie Lin, Yi-Lin Ho, Lung-Han Peng
  • Patent number: 10586922
    Abstract: A phase change material (PCM) device is disclosed. The PCM device includes a bottom electrode and an insulator layer over the bottom electrode. The PCM device further includes a resistive electrode over the insulator layer with a via in the insulator layer between one end of the resistive electrode and the bottom electrode. The PCM device further includes a PCM region over the resistive electrode and a top electrode over the PCM region.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Guy M. Cohen, Paul M. Solomon
  • Patent number: 10580828
    Abstract: A method of manufacturing an integrated circuit system, includes, in part, providing a planar surface on an insulator, forming first and second bottom electrodes over the insulator substrate, forming a first electrolyte over the first and second bottom electrodes, forming a first top electrode over the first electrolyte, forming and depositing a second bottom electrode over the insulator substrate, patterning and removing the first top electrode and the first electrolyte from regions above the second bottom electrode, forming a second electrolyte above the second bottom electrode and the first tope electrode, forming a second top electrode above the second electrolyte, and patterning and removing the second top electrode and the second electrolyte from regions above the first bottom electrode.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: March 3, 2020
    Assignee: SYNOPSYS, INC.
    Inventor: Chung-Heng Yang
  • Patent number: 10573811
    Abstract: Various embodiments of the present application are directed towards an integrated circuit comprising a resistive random-access memory (RRAM) cell with recessed bottom electrode sidewalls to mitigate the effect of sidewall plasma damage. In some embodiments, the RRAM cell includes a lower electrode, a data storage element, and an upper electrode. The lower electrode includes a pair of recessed bottom electrode sidewalls respectively on opposite sides of the lower electrode. The data storage element overlies the lower electrode and includes a pair of storage sidewalls. The storage sidewalls are respectively on the opposite sides of the lower electrode, and the recessed bottom electrode sidewalls are laterally spaced from and laterally between the storage sidewalls. The upper electrode overlies the data storage element.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: February 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yuan-Tai Tseng, Shih-Chang Liu
  • Patent number: 10566206
    Abstract: Processing methods may be performed to remove unwanted materials from a substrate, such as a native oxide material. The methods may include forming an inert plasma within a processing region of a processing chamber. Effluents of the inert plasma may be utilized to modify a surface of an exposed material on a semiconductor substrate within the processing region of the semiconductor chamber. A remote plasma may be formed from a fluorine-containing precursor to produce plasma effluents. The methods may include flowing the plasma effluents to the processing region of the semiconductor processing chamber. The methods may also include removing the modified surface of the exposed material from the semiconductor substrate.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: February 18, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Mandar Pandit, Nitin Ingle