Abstract: A semiconductor memory device includes a semiconductor substrate, transistors formed in an upper surface of the semiconductor substrate, a stacked body provided on the semiconductor substrate, a first contact, and a second contact. The transistors are arranged along a first direction. A minimum period of an arrangement of the transistors is a first period. The stacked body includes electrode films. A configuration of a first portion of the stacked body is a staircase-like having terraces. A first region and a second region are set along the first direction in the first portion. A length in the first direction of the terrace disposed in the second region is longer than the first period. A length in the first direction of the terrace disposed in the first region is shorter than the first period.

Abstract: A semiconductor memory includes: first column lines extending in a first direction; first row lines extending in a second direction; first memory cells located between the first row lines and the first column lines; second column lines electrically connected to the first column lines; second row lines extending in the second direction; and second memory cells located between the second row lines and the second column lines. The first column lines and the second column lines may overlap with each other in a third direction. In a first region, current paths on the second row lines are shorter than current paths on the second row lines in a second region. An overlapping ratio of a second column line belonging to the first region with a first column line may be smaller than that of a second column line belonging to the second region with another first column line.

Abstract: A method of fabricating a memory device includes forming word lines and cell stacks with gaps between the cell stacks, forming a lower gap-fill insulator in the gaps, forming an upper gap-fill insulator on the lower gap-fill insulator, curing the lower gap-fill insulator and the upper gap-fill insulator to form a gap-fill insulator, and forming bit lines on the cell stacks and the gap-fill insulator. The lower gap-fill process may be performed using a first source gas that includes first and second precursors, and the upper gap-fill process may be performed using a second source gas that includes the first and second precursors, a volume ratio of the first precursor to the second precursor in the first source gas may be greater than 15:1, and a volume ratio of the first precursor to the second precursor in the second source gas may be less than 15:1.

Abstract: A method includes depositing a bottom electrode layer, a resistance switching element layer, and a top electrode layer over a first dielectric layer; etching the top electrode layer and the resistance switching element layer to form a resistance switching element over the bottom electrode layer and a top electrode over the resistance switching element; depositing a metal-containing compound layer over the top electrode, the resistance switching element, and the bottom electrode layer; and etching the metal-containing compound layer and the bottom electrode layer to form a bottom electrode over the first dielectric layer.

Abstract: Provided is a memory device including a substrate, a plurality of stack structures, a protective layer, and a plurality of contact plugs. The stack structures are disposed over the substrate. The protective layer conformally covers top surfaces and sidewalls of the stack structures. The contact plugs are respectively disposed over the substrate between the stack structures. One of the contact plugs includes a narrower portion and a wider portion over the narrower portion. In a top view, the wider portion is separated from an adjacent protective layer by a distance.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a 3D memory device includes a substrate, a peripheral device disposed on the substrate, a peripheral interconnect layer disposed above the peripheral device, a first source plate disposed above and electrically connected to the peripheral interconnect layer, a first memory stack disposed on the first source plate, a first memory string extending vertically through the first memory stack and in contact with the first source plate, and a first bit line disposed above and electrically connected to the first memory string and the peripheral device.

Abstract: A memory cell including a two-terminal re-writeable non-volatile memory element having at least two layers of conductive metal oxide (CMO), which, in turn, can include a first layer of CMO including mobile oxygen ions, and a second layer of CMO formed in contact with the first layer of CMO to cooperate with the first layer of CMO to form an ion obstruction barrier. The ion obstruction barrier is configured to inhibit transport or diffusion of a subset of mobile ion to enhance, among other things, memory effects and cycling endurance of memory cells. At least one layer of an insulating metal oxide that is an electrolyte to the mobile oxygen ions and configured as a tunnel barrier is formed in contact with the second layer of CMO.

Abstract: A semiconductor structure includes a plurality of stack structures overlying a substrate. Each stack structure includes a first chalcogenide material over a conductive material overlying the substrate, an electrode over the first chalcogenide material, a second chalcogenide material over the electrode, a liner on sidewalls of at least one of the first chalcogenide material or the second chalcogenide material, and a dielectric material over and in contact with sidewalls of the electrode and in contact with the liner. Related semiconductor devices and systems, methods of forming the semiconductor structure, semiconductor device, and systems, and methods of forming the liner in situ are disclosed.

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory may include memory elements. Each of the memory elements comprises: a selection element layer in which a first dopant is doped in an insulating material; and a variable resistance layer in which a second dopant is doped in the insulating material. A diffusivity of the second dopant in the insulating material is greater than a diffusivity of the first dopant in the insulating material.

Abstract: A radio frequency (RF) switching circuit includes stacked phase-change material (PCM) RF switches. Each of the PCM RF switches includes a PCM, a heating element transverse to the PCM, and first and second heating element contacts. The first heating element contact is coupled to an RF ground, and the second heating element contact may also be coupled to an RF ground. Each of the PCM RF switches can also include first and second PCM contacts. A compensation capacitor can be coupled across the first and second PCM contacts in at least one of the PCM RF switches.

Abstract: A radio frequency (RF) switch includes a phase-change material (PCM), a heating element underlying an active segment of the PCM and extending outward and transverse to the PCM, and RF terminals having lower metal portions and upper metal portions. At least one of the lower metal portions can be ohmically separated from and capacitively coupled to passive segments of the PCM, while the upper metal portions are ohmically connected to the lower metal portions. Alternatively, the lower metal portions can be ohmically connected to passive segments of the PCM, while a capacitor is formed in part by at least one of the upper metal portions. Alternatively, at least one of the RF terminals can have a trench metal liner separated from a trench metal plug by a dielectric liner. The trench metal liner can be ohmically connected to passive segments of the PCM, while the trench metal plug is ohmically separated from, but capacitively coupled to, the trench metal liner.

Abstract: Methods for controlling the resistance of a controllable resistive element include determining an amount of electrical resistance change for the controllable resistive element. A concentration difference is determined for a charge carrier ion in a resistor layer of the controllable resistance element that corresponds to the electrical resistance change for the controllable resistive element. A duration and amplitude of a current pulse is determined that changes the charge carrier ion concentration by the determined difference. A positive or negative current pulse is applied to a controllable resistive element for the determined duration.

Abstract: A phase change memory structure (100) includes a phase change material layer (110), a top electrode layer (120) above the phase change material layer, a metal silicon nitride layer (130) in contact with the top electrode layer opposite from the phase change material layer, a metal silicide layer (140) in contact with the metal silicon nitride layer opposite from the top electrode layer, and a conductive metal bit line (150) in contact with the metal silicide layer opposite from the metal silicon nitride layer.

Abstract: A semiconductor device structure is provided. The structure includes a semiconductor substrate and a lower electrode over the semiconductor substrate. The structure also includes a resistance variable layer over the lower electrode and an ion diffusion barrier layer over the resistance variable layer. The structure further includes a capping layer over the ion diffusion barrier layer, and the capping layer is made of a metal material. In addition, the structure includes an upper electrode over the capping layer. The structure includes a protective element extending along a sidewall of the ion diffusion barrier layer and in direct contact with an interface between the resistance variable layer and the ion diffusion barrier layer.

Abstract: This invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate; a bitline, suspended on the substrate; a bottom electrode, wrapped around the bitline; a resistive layer, wrapped around the bottom electrode; a top electrode, wrapped around the resistive layer; and a wordline electrode, disposed around the top electrode and connected to the top electrode.

Abstract: The disclosure provides a method and apparatus for designing a resistive random access memory, and the method comprise: receiving a preset first parameter standard of a resistive switching material, searching for and outputting a first resistive switching material based on the first parameter standard, first parameters including: band gap, charge transfer, vacancy, migration barrier, carrier activation energy.

Abstract: First electrically conductive lines, first pillar structures, second electrically conductive lines, second pillar structures, third electrically conductive lines, third pillar structures, fourth electrically conductive lines, and fourth pillar structures are formed over a substrate. Each pillar structure includes a memory element. Interconnection structures are formed on the first electrically conductive lines. The first electrically conductive lines may have thinned segments located outside the area of the arrays of memory elements, and the interconnection structures may be formed on the thinned segments. Alternatively or additionally, the interconnection structures may include a vertical stack of a first conductive via structure contacting a respective one of the first electrically conductive lines, a conductive pad structure, and a second conductive via structure.

Abstract: Embodiments of the invention are directed to a vertical resistive device. A non-limiting example of the vertical resistive device includes a horizontal plate having a conductive electrode region and a filament region. An opening extends through the filament region and is defined by sidewalls of the filament such that the filament region is positioned outside of the opening. A conductive pillar is positioned within the opening and is communicatively coupled to the filament region.

Abstract: A semiconductor device includes: a substrate having a magnetic tunneling junction (MTJ) region and a logic region; a magnetic tunneling junction (MTJ) on the MTJ region, wherein a top view of the MTJ comprises a circle; and a first metal interconnection on the MTJ. Preferably, a top view of the first metal interconnection comprises a flat oval overlapping the circle.

Abstract: A memristor device is disclosed comprising: a first electrode; a second electrode; a cathode metal layer disposed on a surface of the first electrode; and an active region disposed between and in electrical contact with the second electrode and the cathode metal layer, the active region comprising at least one layer of an amorphous metal oxide, wherein when a switching voltage is applied between the first and second electrodes, the active region exhibits a resistive switching behaviour. A method of fabricating a memristor device is also disclosed.

Abstract: A method of forming a semiconductor device structure comprises forming a stack structure comprising stacked tiers. Each of the stacked tiers comprises a first structure comprising a first material and a second structure comprising a second, different material longitudinally adjacent the first structure. A patterned hard mask structure is formed over the stack structure. Dielectric structures are formed within openings in the patterned hard mask structure. A photoresist structure is formed over the dielectric structures and the patterned hard mask structure. The photoresist structure, the dielectric structures, and the stack structure are subjected to a series of material removal processes to form apertures extending to different depths within the stack structure. Dielectric structures are formed over side surfaces of the stack structure within the apertures. Conductive contact structures are formed to longitudinally extend to bottoms of the apertures.

Abstract: A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.

Abstract: Provided is a resistance variation element including a resistance variation film of a metal depositing type, a first electrode which contacts with a first surface of the resistance variation film in a predetermined first region and supplies metallic ions via the first region, and a second electrode laminated on a second surface of the resistance variation film. The first region includes a recessed region surrounded by a simple closed curve or a region surrounded by a plurality of simple closed curves. A line segment which passes through a point outside of the first region, ends of which exist on the simple closed curve, and each point of which in the vicinity of both the ends other than both the ends is outside of the first region, exists, and an edge of the first electrode is formed in a part of the simple closed curve including both the ends.

Abstract: A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a barrier layer over at least one conductive line of the plurality of conductive lines, the barrier layer directly contacting an entire upper surface of the at least one conductive line, and forming a RRAM stack including a bottom electrode, a high-k dielectric layer, and a top electrode over the barrier layer.

Abstract: Embodiments of methods for forming a staircase structure of a three-dimensional (3D) memory device are disclosed. In an example, a first plurality of stairs of the staircase structure are formed based on a first photoresist mask. Each of the first plurality of stairs includes a number of divisions at different depths. After forming the first plurality of stairs, a second plurality of stairs of the staircase structure are formed based on a second photoresist mask. Each of the second plurality of stairs includes the number of divisions. The staircase structure tilts downward and away from a memory array structure of the 3D memory device from the first plurality of stairs to the second plurality of stairs.

Abstract: A semiconductor device of an embodiment includes a control circuit arranged on a substrate, a first conductive layer arranged on the control circuit and containing a first element as a main component, a multilayer structure arranged on the first conductive layer and configured such that multiple second conductive layers and multiple insulating layers are alternately stacked on each other, a memory layer penetrating the multilayer structure and reaching the first conductive layer at a bottom portion, a first layer arranged between the control circuit and the first conductive layer and containing the first element as a main component, and a second layer arranged between the control circuit and the first layer and containing, as a main component, a second element different from the first element.

Abstract: Methods, systems, and devices for techniques for forming memory structures are described. Forming a memory structure may include etching a stack of material including a conductive line, a first electrode and a sacrificial material to divide the stack of material into multiple sections. The process may further include depositing an oxide material in each of the first quantity of channels to form multiple oxide materials. The sacrificial material may be etched to form a second channel between two oxide materials of the multiple oxide materials. Memory material may be deposited over the two oxide materials and the second channel, which may create a void in the second channel between the memory material and the first electrode. The memory material may be heated to fill the void in the second channel.

Abstract: A memory device according to an embodiment includes a first conductive layer; a second conductive layer; a ferroelectric layer provided between the first conductive layer and the second conductive layer and containing hafnium oxide; a paraelectric layer provided between the first conductive layer and the ferroelectric layer and containing a first oxide; and an oxide layer provided between the paraelectric layer and the ferroelectric layer and containing a second oxide having an oxygen area density lower than an oxygen area density of the first oxide.

Abstract: A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a barrier layer over at least one conductive line of the plurality of conductive lines, the barrier layer directly contacting an entire upper surface of the at least one conductive line, and forming a RRAM stack including a bottom electrode, a high-k dielectric layer, and a top electrode over the barrier layer.

Abstract: A semiconductor storage device is disclosed. The device includes: a first conductive layer; a second conductive layer apart from the first conductive layer in a first direction; a variable resistance layer provided between the first conductive layer and the second conductive layer; a third conductive layer provided between the first conductive layer and the variable resistance layer; a nonlinear layer provided between the first conductive layer and the third conductive layer; and a first insulating layer provided at least between the first conductive layer and the nonlinear layer or between the third conductive layer and the nonlinear layer. The first insulating layer includes nitrogen (N) and boron (B).

Abstract: There are disclosed herein various implementations of a semiconductor device including a group III-V layer situated over a substrate, and a phase-change material (PCM) radio frequency (RF) switch situated over the group III-V layer. The PCM RF switch couples a group III-V transistor situated over the group III-V layer to one of an integrated passive element or another group III-V transistor situated over the group III-V layer. The PCM RF switch includes a heating element transverse to the PCM, the heating element underlying an active segment of the PCM. The PCM RF switch is configured to be electrically conductive when the active segment of the PCM is in a crystalline state, and to be electrically insulative when the active segment of the PCM is in an amorphous state.

Abstract: An optoelectronic memristor includes a first electrode, a second electrode, and a solid electrolyte in between that is in electrical communication with the first electrode and the second electrode. The solid electrolyte has an electronic conductivity of about 10?10 Siemens/cm to about 10?4 Siemens/cm at room temperature. The first electrode, and optionally the second electrode, can be optically transparent at a specific wavelength and/or a wavelength range. A direct current (DC) voltage source is employed to apply an electric field across the solid electrolyte, which induces a spatial redistribution of ionic defects in the solid electrolyte. In turn, this causes a change in electrical resistance of the solid electrolyte. The application of the electric field can also cause a change in an optical property of the solid electrolyte at the specific wavelength, and/or at the wavelength range (or a portion thereof).

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over one or more interconnect layers and a diffusion barrier layer is arranged over the bottom electrode. A data storage layer is separated from the bottom electrode by the diffusion barrier layer. A top electrode is over the data storage layer.

Abstract: A method of manufacturing a DRAM includes isolation structures and word line sets are formed in the substrate. A conductive material is formed on the substrate. Conductive material is removed to form first openings in the conductive material. The first openings expose surfaces of the substrate in the first areas and divide the conductive material into conductive layers, thereby the conductive layers are located on surfaces of the substrate in the second areas. A first dielectric material is filled in the first openings so as to form first dielectric layers on the substrate in the first areas. Top surfaces of the conductive layers are lower than top surfaces of the first dielectric layers. Second dielectric layers are formed respectively in the conductive layers. Capacitors are formed respectively on the conductive posts.

Abstract: A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.

Abstract: Embodiments of the invention are directed to a fabrication method that includes forming a dielectric region of a wafer, forming a bottom contact embedded within the dielectric region such that a top surface of the bottom contact is exposed, and forming a dummy resistive switching element over the top surface of the bottom electrode. Portions of the dummy resistive switching element are exposed to at least one oxide source. The dummy resistive switching element is replaced with a resistive switching element stack.

Abstract: A resistive memory device may include a plurality of MATs, row control blocks, a plurality of word lines, a plurality of bit lines and memory cells. Each of the row control blocks may be interposed between the MATs. Each of the row control blocks may include a control element. The word lines may be arranged spaced apart from each other by a substantially uniform gap on the MATs. The bit lines may overlap with the word lines. The memory cells may be located between the word lines and the bit lines. Each of the word lines may be electrically connected with the control element of each of the row control blocks via a connection path.

Abstract: The present invention provides PCM devices with gradual SET and RESET characteristics. In one aspect, a method of forming a PCM computing device includes: forming word lines and an insulating hardmask cap on a substrate; forming a PCM material over the word lines, having a tapered thickness; and forming bit lines over the PCM material, the insulating hardmask cap, and the word lines, wherein the tapered thickness of the PCM material varies gradually between the word lines and the bit lines. The tapered thickness can be formed by depositing a non-conformal layer of the PCM material or by depositing a conformal layer and then tapering the PCM material using a directional etch. A PCM device is also provided.

Abstract: A phase change material (“PCM”) device is described. A non-limiting example of the PCM device includes a bottom electrode including a low resistivity material and a PCM material over the bottom electrode. The PCM device has a top electrode over the PCM material.

Abstract: Resistive memory cells, precursors thereof, and methods of making resistive memory cells are described. In some embodiments, the resistive memory cells are formed from a resistive memory precursor that includes a switching layer precursor containing a plurality of oxygen vacancies that are present in a controlled distribution therein, optionally without the use of an oxygen exchange layer. In these or other embodiments, the resistive memory precursors described may include a second electrode formed on a switching layer precursor, wherein the second electrode is includes a second electrode material that is conductive but which does not substantially react with oxygen. Devices including resistive memory cells are also described.

Abstract: A method of fabricating an electronic device including a semiconductor memory includes forming a first conductive structure extending in a first direction and having a closed-loop shape, forming a second conductive structure extending in a second direction and having a closed-loop shape, the second direction intersecting the first direction, forming a memory cell located at an intersection of the first conductive structure and the second conductive structure, forming first conductive patterns extending in the first direction by etching an end portion of the first conductive structure, forming second conductive patterns extending in the second direction by etching an end portion of the second conductive structure, forming a first protective layer on an etched surface of each of the first conductive patterns and the second conductive patterns, and forming a gap-fill layer on the first protective layer.

Abstract: A phase change memory array and method for fabricating the same. The phase change memory array includes a plurality of bottom electrodes, top electrodes, and memory pillars. Each of the memory pillars includes phase change material surrounded by a dielectric casing. The phase change material is positioned between, and in series circuit with, a respective bottom electrode from the bottom electrodes and a respective top electrode from the top electrodes. A continuous layer of selector material is positioned between the memory pillars and the plurality of bottom electrodes. The selector material is configured to conduct electricity only when a voltage across the selector material exceeds a voltage threshold.

Abstract: A method for controlling accumulated resistance property of a ReRAM device, wherein the method includes steps as follows: A first programing pulse set is firstly applied to a ReRAM device for acquiring a reference accumulated resistance distribution. A second programing pulse set is then provided according to the reference accumulated resistance distribution, and the second programing pulse set is applied to the ReRAM device, to make the ReRAM device having a predetermined accumulated resistance distribution.

Abstract: A method is presented for constructing conductive bridging random access memory (CBRAM) stacks. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a CBRAM stack including at least an electrolyte layer, a conductive layer, a metal cap layer, and a top electrode such that a top end of the CBRAM stack has a smaller critical dimension than a bottom end of the CBRAM stack, forming a low-k dielectric layer over the CBRAM stack, and exposing a top surface of the CBRAM stack during a via opening.

Abstract: A memory cell includes: a first contact feature partially embedded in a first dielectric layer; a barrier layer, lining the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer; a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer; and a second contact feature embedded in a second dielectric layer above the first dielectric layer.

Abstract: A reconfigurable circuit includes: a plurality of first lines; one or more second lines; a non-volatile resistive cell coupling one of the first lines with one of the second lines at each cross-point between the first lines and the second lines; and first switch elements including first terminals respectively coupled to the first lines, wherein each of the first switch elements is separately turned on or off in accordance with a control signal applied thereto.

Abstract: Technologies relating to folded crossbar array circuits and methods for reducing pitch match issues within folded crossbar array circuits and increasing the scalability of folded crossbar array circuits are disclosed. An example crossbar array circuit includes: a first folded column circuit folded as at least two portions; a first ADC; a first plurality of DACs; and a first plurality of access controls, wherein the first folded column circuit connected to the first ADC, the first plurality of DACs, and the first plurality of access controls. In some implementations, the three portions comprises a first column of crossbar devices, a second column of crossbar devices, and a third column of crossbar devices, and wherein the first column of crossbar devices, the second column of crossbar devices, and the third column of crossbar devices are configured to be controlled by the first plurality of access controls.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a lower electrode over the semiconductor substrate. The semiconductor device structure also includes a first dielectric layer over the lower electrode, a second dielectric layer over the first dielectric layer, and a third dielectric layer over the second dielectric layer. Oxygen ions are bonded more tightly in the second dielectric layer than those in the first dielectric layer, and oxygen ions are bonded more tightly in the second dielectric layer than those in the third dielectric layer.

Abstract: Conductive bridge random access memory (CBRAM) devices with low thermal conductivity electrolyte sublayers are described. In an example, a conductive bridge random access memory (CBRAM) device includes a conductive interconnect disposed in an inter-layer dielectric (ILD) layer disposed above a substrate. The CBRAM device also includes a CBRAM element disposed on the conductive interconnect. The CBRAM element includes an active electrode layer disposed on the conductive interconnect, and a resistance switching layer disposed on the active electrode layer. The resistance switching layer includes a first electrolyte material layer disposed on a second electrolyte material layer, the second electrolyte material layer disposed on the active electrode layer and having a thermal conductivity lower than a thermal conductivity of the first electrolyte material layer. A passive electrode layer is disposed on the first electrolyte material of the resistance switching layer.

Abstract: A radio frequency (RF) switch includes a heating element, thermally conductive and electrically insulating layer over the heating element, a wetting dielectric layer over the thermally conductive and electrically insulating layer, and a phase-change material (PCM) over the wetting dielectric layer. At least one cladding dielectric layer can be situated over sides and/or over a top surface of the PCM. Each of the wetting dielectric layer, phase change material, and cladding dielectric layer can comprise at least germanium. A transitional dielectric layer can be situated between the thermally conductive and electrically insulating layer and the wetting dielectric layer. A contact uniformity support layer can be situated over the cladding dielectric layer.