Semiconductor Is Selenium Or Tellurium In Elemental Form Patents (Class 257/42)
  • Patent number: 10444364
    Abstract: An imaging device includes a focal plane array of demodulation pixel cells. Each of the demodulation pixel cells includes a pinned photodiode, demodulation gates operable to demodulate optical signals sensed by the pinned photodiode and to transfer accumulated photo-charges to a respective one of a multitude of sense nodes, a readout circuit operable selectively to read out signals from the sense nodes, and a background light suppression circuit including cross-coupled current mirrors.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: October 15, 2019
    Assignee: AMS SENSORS SINGAPORE PTE. LTD.
    Inventor: Radoslaw Marcin Gancarz
  • Patent number: 10269981
    Abstract: A device includes a semiconductor substrate, a buried oxide over the substrate, a first transition metal dichalcogenide layer over the buried oxide, an insulator over the first transition metal dichalcogenide layer, and a second transition metal dichalcogenide layer over the insulator. A gate dielectric is over the second transition metal dichalcogenide layer, and a gate is over the gate dielectric.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: April 23, 2019
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Pin-Shiang Chen, Hung-Chih Chang, Chee-Wee Liu, Samuel C. Pan
  • Patent number: 10074687
    Abstract: A semiconductor device including pixels arranged in a matrix of n rows and m columns, in which the pixels in the m-th column are shielded from light, is provided.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: September 11, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 9879143
    Abstract: A chalcogen element can be effectively dissolved in a non-explosive hydrazine-based solvent by the aid of sodium in a non-explosive hydrazine-based solvent. Therefore, a precursor solution for forming a metal chalcogenide film containing as a solvent a non-explosive hydrazine-based solvent which is less poisonous than hydrazine and which is free of explosiveness is provided. A metal chacogenide thin film may be formed employing the metal chalcogenide precursor solution.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: January 30, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kyungsang Cho
  • Patent number: 9252359
    Abstract: In one embodiment of the present invention, a resistive switching device includes a first electrode disposed over a substrate and coupled to a first potential node, a switching layer disposed over the first electrode, a conductive amorphous layer disposed over the switching layer, and a second electrode disposed on the conductive amorphous layer and coupled to a second potential node.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 2, 2016
    Assignee: Adesto Technologies Corporation
    Inventors: John R. Jameson, III, John E. Sanchez, Wei Ti Lee, Foroozan Sarah Koushan
  • Patent number: 9246093
    Abstract: A low resistivity interface material is provided between a self-aligned vertical heater element and a contact region of a selection device. A phase change chalcogenide material is deposited directly on the vertical heater element. In an embodiment, the vertical heater element in L-shaped, having a curved vertical wall along the wordline direction and a horizontal base. In an embodiment, the low resistivity interface material is deposited into a trench with a negative profile using a PVD technique. An upper surface of the low resistivity interface material may have a tapered bird-beak extension.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: January 26, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Barbara Zanderighi, Francesco Pipia
  • Patent number: 9196828
    Abstract: A resistive memory and a fabricating method thereof are provided. The resistive memory includes first and second electrodes, a variable resistance material layer, a first dielectric layer, and a second dielectric layer. The first electrode includes a first portion and a second portion. The second electrode is disposed opposite to the first electrode. The variable resistance material layer includes a sidewall and first and second surfaces opposite to each other, wherein the first surface is connected with the first portion of the first electrode and the second surface is electrically connected with the second electrode. The second portion surrounds the sidewall of the variable resistance material layer and is connected with the first portion. The first dielectric layer is disposed between the first and the second electrodes. The second dielectric layer is disposed between the variable resistance material layer and the second portion of the first electrode.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: November 24, 2015
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Ming-Hsiu Lee, Wei-Chih Chien
  • Patent number: 9190613
    Abstract: A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device includes a multi-layered insulating layer including a plurality of holes formed on a semiconductor substrate, a lower electrode formed in a bottom of each of the holes, a first spacer formed on the lower electrode and a sidewall of each of the holes, a second spacer formed on an upper sidewall of the first spacer, a third spacer formed on a lower sidewall of the first spacer below the second spacer, a variable resistance part that is formed on the lower electrode has a height lower than a height of a top of each hole, and an upper electrode formed on the variable resistance part to be buried in each hole.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: November 17, 2015
    Assignee: SK Hynix Inc.
    Inventors: Ha Chang Jung, Gi A Lee
  • Patent number: 9157019
    Abstract: A ternary particle size filler composition with addition of nano particles is provided to formulate thermally conductive interface materials such as soft gel having a high thermal conductivity, a relative low viscosity, and a low complex storage modulus. The thermally conductive material containing thermal particle composition and polymer matrix is used to create a thermal transfer path between the electronic component and the heat dissipation member. The composition is a mixture of a ternary particle size fillers constituted of the same or different chemical compounds in a predefined size ranges and volume ratios in terms of low viscosity and thermal interface nominal size. A silicone based polymer used as filler bonding matrix contains base resin, dispersant, cross-linker and polymerization catalyst. Thermal conductivity of the soft gel varied according to the change of volume percentage, particle size, and chemical compound of individual thermal particles.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: October 13, 2015
    Inventor: Jiali Wu
  • Patent number: 9153779
    Abstract: According to one embodiment, a memory element includes: a first electrode layer; a second electrode layer; and a memory layer provided between the first electrode layer and the second electrode layer, and the memory layer including a plurality of first oxide layers in a second oxide layer, a resistivity of each of the plurality of first oxide layers being higher than a resistivity of the second oxide layer.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: October 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomotaka Ariga, Junichi Wada, Kouji Matsuo, Noritake Oomachi, Yoshio Ozawa
  • Patent number: 9082954
    Abstract: An improved phase change memory device has a phase change structure including a thin part between a contact surface of an electrode and a dielectric structure. For example, the thin part has a maximum thickness that is smaller than a maximum width of the contact surface of the electrode. In another example, the phase change structure surrounds the dielectric structure. Several variations improve the contact between the phase change structure and an electrode.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: July 14, 2015
    Assignees: Macronix International Co., Ltd., International Business Machines
    Inventors: Hsiang-Lan Lung, Chung Hon Lam
  • Patent number: 8980679
    Abstract: Provided are apparatus and methods for forming phase change layers, and methods of manufacturing a phase change memory device. A source material is supplied to a reaction chamber, and purges from the chamber. A pressure of the chamber is varied according to the supply of the source material and the purge of the source material.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Hyun Im, Byoungjae Bae, Dohyung Kim, Sunglae Cho, Jinil Lee, Juhyung Seo, Hyeyoung Park, Takehiko Fujita
  • Publication number: 20150063543
    Abstract: A radiation detector may include: a first photoconductor layer including a plurality of photosensitive particles; and/or a second photoconductor layer on the first photoconductor layer, and including a plurality of crystals obtained by crystal-growing photosensitive material. At least some of the plurality of photosensitive particles of the first photoconductor layer may fill gaps between the plurality of crystals of the second photoconductor layer. A method of manufacturing a radiation detector may include: forming a first photoconductor layer by applying paste, including solvent mixed with a plurality of photosensitive particles, to a first substrate; forming a second photoconductor layer by crystal-growing photosensitive material on a second substrate; pressing the crystal-grown second photoconductor layer on the first photoconductor layer that is applied to the first substrate; and/or removing the solvent in the first photoconductor layer via a drying process.
    Type: Application
    Filed: September 1, 2014
    Publication date: March 5, 2015
    Inventors: Seung-hyup LEE, Sun-il KIM, Young KIM, Chang-jung KIM
  • Publication number: 20150014627
    Abstract: Two-terminal electronic devices, such as photodetectors, photovoltaic devices and electroluminescent devices, are provided. The devices include a first electrode residing on a substrate, wherein the first electrode comprises a layer of metal; an I-layer comprising an inorganic insulating or broad band semiconducting material residing on top of the first electrode, and aligned with the first electrode, wherein the inorganic insulating or broad band semiconducting material is a compound of the metal of the first electrode; a semiconductor layer, preferably comprising a p-type semiconductor, residing over the I-layer; and a second electrode residing over the semiconductor layer, the electrode comprising a layer of a conductive material. The band gap of the material of the semiconductor layer, is preferably smaller than the band gap of the I-layer material. The band gap of the material of the I-layer is preferably greater than 2.5 eV.
    Type: Application
    Filed: July 23, 2014
    Publication date: January 15, 2015
    Inventors: Gang Yu, Chan-Long Shieh, Zhao Chen
  • Patent number: 8933430
    Abstract: A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device includes a multi-layered insulating layer including a plurality of holes formed on a semiconductor substrate, a lower electrode formed in a bottom of each of the holes, a first spacer formed on the lower electrode and a sidewall of each of the holes, a second spacer formed on an upper sidewall of the first spacer, a third spacer formed on a lower sidewall of the first spacer below the second spacer, a variable resistance part that is formed on the lower electrode has a height lower than a height of a top of each hole, and an upper electrode formed on the variable resistance part to be buried in each hole.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: January 13, 2015
    Assignee: SK Hynix Inc.
    Inventors: Ha Chang Jung, Gi A Lee
  • Patent number: 8927329
    Abstract: The amount of water and hydrogen contained in an oxide semiconductor film is reduced, and oxygen is supplied sufficiently from a base film to the oxide semiconductor film in order to reduce oxygen deficiencies. A stacked base film is formed, a first heat treatment is performed, an oxide semiconductor film is formed over and in contact with the stacked base film, and a second heat treatment is performed. In the stacked base film, a first base film and a second base film are stacked in this order. The first base film is an insulating oxide film from which oxygen is released by heating. The second base film is an insulating metal oxide film. An oxygen diffusion coefficient of the second base film is smaller than that of the first base film.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: January 6, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuki Imoto, Yuhei Sato
  • Patent number: 8927957
    Abstract: A memory device includes a first conductor, a diode, a memory element, and a second conductor arranged in series. The diode includes a first semiconductor layer over and in electrical communication with the first conductor. A patterned insulating layer has a sidewall over the first semiconductor layer. The diode includes an intermediate semiconductor layer on a first portion of the sidewall, and in contact with the first semiconductor layer. The intermediate semiconductor layer has a lower carrier concentration than the first semiconductor layer, and can include an intrinsic semiconductor. A second semiconductor layer on a second portion of the sidewall, and in contact with the intermediate semiconductor layer, has a higher carrier concentration than the intermediate semiconductor layer. A memory element is electrically coupled to the second semiconductor layer. The second conductor is electrically coupled to the memory element.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: January 6, 2015
    Assignee: Macronix International Co., Ltd.
    Inventor: Hsiang-Lan Lung
  • Patent number: 8916414
    Abstract: To form a memory cell with a phase change element, a hole is formed through an insulator to a bottom electrode, and a phase change material is deposited on the insulator surface covering the hole. A confining structure is formed over the phase change material so the phase change material expands into the hole when heated to melting to become electrically connected to the bottom electrode. A top electrode is formed over and electrically connects to the phase change material. The bottom electrode can include a main portion and an extension having a reduced lateral dimension. The confining structure can include capping material having a higher melting temperature than the phase change material, and sufficient tensile strength to ensure the phase change material moves into the hole when the phase change material melts and expands. The hole can be a J shaped hole.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: December 23, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Huai-Yu Cheng, Hsiang-Lan Lung
  • Patent number: 8916847
    Abstract: A variable resistance memory device includes a plurality of first conductive lines extended in a first direction, a plurality of second conductive lines arranged over or under the first conductive lines and extended in a second direction crossing the first direction, an insulating layer disposed between the first conductive lines and the second conductive lines and having a trench extended in the second direction and defined by a first side wall and a second sidewall facing each other and a bottom surface connecting the first sidewall and the second sidewall, and a variable resistance material layer formed on the first and second sidewalls and the bottom surface of the trench, wherein the first and second sidewalls of the trench overlap two adjacent second conductive lines, respectively.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: December 23, 2014
    Assignee: SK Hynix Inc.
    Inventors: Hyun-Min Lee, Jung-Taik Cheong
  • Patent number: 8847386
    Abstract: An electrical contact for a detector, the electrical component, comprising a cadmium tellurium component, a first layer formed onto the cadmium tellurium component, wherein the first layer comprises indium and a contact agent being bonded directly or indirectly to the first layer to be in electrical contact with the first layer. The contact agent may be a stud bump or a conductive adhesive interconnect being bonded indirectly to the first layer via noble metal shielding layer.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: September 30, 2014
    Assignee: Koninklijke Philips N.V.
    Inventors: Nicolaas Johannes Anthonius Van Veen, Rob Van Asselt, Gerard Kums
  • Patent number: 8847192
    Abstract: In accordance with an embodiment of the present invention, a resistive switching device comprises a bottom electrode, a switching layer disposed over the bottom electrode, and a top electrode disposed over the switching layer. The top electrode comprises an alloy of a memory metal and an alloying element. The top electrode provides a source of the memory metal. The memory metal is configured to change a state of the switching layer.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: September 30, 2014
    Assignees: Adesto Technologies France SARL, Adesto Technologies Corporation
    Inventors: Wei Ti Lee, Chakravarthy Gopalan, Yi Ma, Jeffrey Shields, Philippe Blanchard, John Ross Jameson, Foroozan Sarah Koushan, Janet Wang, Mark Kellam
  • Patent number: 8841646
    Abstract: Disclosed are a semiconductor storage device and a manufacturing method. The storage device has: a substrate; a first word line above the substrate; a first laminated body above the first word line and having N+1 first inter-gate insulating layers and N first semiconductor layers alternately laminated; a first bit line above the laminated body and extending in a direction that intersects the first word line; a first gate insulating layer on side surfaces of the first inter-gate insulating layers and the first semiconductor layers; a first channel layer on the side surface of the first gate insulating layer; and a first variable resistance material layer on the side surface of the first channel layer. The first variable resistance material layer is in a region where the first word line and the first bit line intersect. A polysilicon diode is used as a selection element.
    Type: Grant
    Filed: October 6, 2013
    Date of Patent: September 23, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Yoshitaka Sasago, Akio Shima, Satoru Hanzawa, Takashi Kobayashi, Masaharu Kinoshita, Norikatsu Takaura
  • Patent number: 8828774
    Abstract: Herein disclosed is a method of forming a thermoelectric material having an optimized stoichiometry, the method comprising: reacting a precursor material including a population of nanocrystals with a first ionic solution and a second ionic solution to form a reacted mixture.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: September 9, 2014
    Assignee: Evident Technologies Inc.
    Inventors: Susanthri Perera, Dave Socha, Adam Z. Peng, Clinton T. Ballinger
  • Patent number: 8809829
    Abstract: A memory device having a phase change material element with a modified stoichiometry in the active region does not exhibit drift in set state resistance. A method for manufacturing the memory device includes first manufacturing an integrated circuit including an array of phase change memory cells with bodies of phase change material having a bulk stoichiometry; and then applying forming current to the phase change memory cells in the array to change the bulk stoichiometry in active regions of the bodies of phase change material to the modified stoichiometry, without disturbing the bulk stoichiometry outside the active regions. The bulk stoichiometry is characterized by stability under the thermodynamic conditions outside the active region, while the modified stoichiometry is characterized by stability under the thermodynamic conditions inside the active region.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: August 19, 2014
    Assignee: Macronix International Co., Ltd.
    Inventor: Ming-Hsiu Lee
  • Patent number: 8803141
    Abstract: A method of depositing a film of a metal chalcogenide including the steps of: contacting an isolated hydrazinium-based precursor of a metal chalcogenide and a solvent having therein a solubilizing additive to form a solution of a complex thereof; applying the solution of the complex onto a substrate to produce a coating of the solution on the substrate; removing the solvent from the coating to produce a film of the complex on the substrate; and thereafter annealing the film of the complex to produce a metal chalcogenide film on the substrate. Also provided is a process for preparing an isolated hydrazinium-based precursor of a metal chalcogenide as well as a thin-film field-effect transistor device using the metal chalcogenides as the channel layer.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: David B. Mitzi, Matthew W. Copel
  • Patent number: 8785230
    Abstract: A localized surface plasmon resonance sensor may include a localized surface plasmon excitation layer including a chalcogenide material. The chalcogenide material may include: a first material including at least one of selenium (Se) and tellurium (Te); and a second material including at least one of germanium (Ge) and antimony (Sb). The localized surface plasmon excitation layer may be prepared by forming a thin film including the chalcogenide material and crystallizing the thin film to have a predetermined pattern by irradiating laser on the thin film.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: July 22, 2014
    Assignee: Korea Institute of Science and Technology
    Inventors: Taek Sung Lee, Kyeong Seok Lee, In Ho Kim, Wook Seong Lee, Doo Seok Jeong, Won Mok Kim, Byung Ki Cheong
  • Patent number: 8772077
    Abstract: The present invention concerns a method of forming a chalcogenide thin film for a phase-change memory. In the method of forming a chalcogenide thin film according to the present invention, a substrate with a pattern formed is loaded into a reactor, and a source gas is supplied onto the substrate. Here, the source gas includes at least one source gas selected from germanium (Ge) source gas, gallium (Ga) source gas, indium (In) source gas, selenium (Se) source gas, antimony (Sb) source gas, tellurium (Te) source gas, tin (Sn) source gas, silver (Ag) source gas, and sulfur (S) source gas. A first purge gas is supplied onto the substrate in order to purge the source gas supplied onto the substrate, a reaction gas for reducing the source gas is then supplied onto the substrate, and a second purge gas is supplied onto the substrate in order to purge the reaction gas supplied onto the substrate.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: July 8, 2014
    Assignee: IPS Ltd.
    Inventors: Ki-Hoon Lee, Jung-Wook Lee, Dong-Ho You
  • Publication number: 20140167030
    Abstract: A vertical memory device and a method of fabricating the same are provided. The vertical type semiconductor device includes a common source region formed in a cell area of a semiconductor substrate. A channel region is formed on the common source region. The channel region has a predetermined height and a first diameter. A drain region is formed on the channel region. The drain region has a predetermined height and a second diameter larger than the first diameter. A first gate electrode surrounding the channel region.
    Type: Application
    Filed: March 18, 2013
    Publication date: June 19, 2014
    Applicant: SK HYNIX INC.
    Inventor: Nam Kyun PARK
  • Patent number: 8729543
    Abstract: Methods and devices are provided for forming multi-nary semiconductor. In one embodiment, a method is provided comprising of depositing a precursor material onto a substrate, wherein the precursor material may include or may be used with an additive to minimize concentration of group IIIA material such as Ga in the back portion of the final semiconductor layer. The additive may be a non-copper Group IB additive in elemental or alloy form. Some embodiments may use both selenium and sulfur, forming a senary or higher semiconductor alloy.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: May 20, 2014
    Assignee: aeris CAPITAL Sustainable IP Ltd.
    Inventors: David B. Jackrel, Katherine Dickey, Kristin Pollock, Jacob Woodruff, Peter Stone, Gregory Brown
  • Publication number: 20140131698
    Abstract: A channel layer may include a plurality of transition metal dichalcogenide (TMD) material layers and an insulator layer between a pair of the plurality of TMD material layers.
    Type: Application
    Filed: June 20, 2013
    Publication date: May 15, 2014
    Inventors: Eok-su KIM, Sun-Hee LEE
  • Publication number: 20140103330
    Abstract: A gas sensor operable at ambient conditions, the sensor includes functionalized feather-like tellurium (Te) nanostructures on single-walled carbon nanotube (SWNTs) networks.
    Type: Application
    Filed: October 10, 2013
    Publication date: April 17, 2014
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Nosang V. MYUNG, Miluo Zhang
  • Patent number: 8685291
    Abstract: Variable resistance memory compositions and devices exhibiting superior data retention characteristics at elevated temperature. The compositions are composite materials that include a variable resistance component and an inert component. The variable resistance component may include a phase-change material and the inert component may include a dielectric material. The phase-change material may include Ge, Sb, and Te, where the atomic concentration of Sb is between 3% and 16% and/or the Sb/Ge ratio is between 0.07 and 0.68 and/or the Ge/Te ratio is between 0.6 and 1.1 and/or the concentration of dielectric component (expressed as the sum of the atomic concentrations of the constituent elements thereof) is between 5% and 50%. The compositions exhibit high ten-year data retention temperatures and long data retention times at elevated temperatures.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: April 1, 2014
    Assignee: Ovonyx, Inc.
    Inventors: Carl Schell, Wolodymyr Czubatyj
  • Patent number: 8673401
    Abstract: A method for depositing gallium using a gallium ink, comprising, as initial components: a gallium component comprising gallium; a stabilizing component; an additive; and, a liquid carrier; is provided comprising applying the gallium ink on the substrate; heating the applied gallium ink to eliminate the additive and the liquid carrier, depositing gallium on the substrate; and, optionally, annealing the deposited gallium.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: March 18, 2014
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: David Mosley, David Thorsen
  • Patent number: 8674334
    Abstract: A memory element and method of forming the same. The memory element includes a substrate supporting a first electrode, a dielectric layer over the first electrode having a via exposing a portion of the first electrode, a phase change material layer formed over sidewalls of the via and contacting the exposed portion of the first electrode, insulating material formed over the phase change material layer and a second electrode formed over the insulating material and contacting the phase change material layer.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: March 18, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Jun Liu
  • Patent number: 8653515
    Abstract: Provided is a thin film transistor and thin film transistor panel array. The thin film transistor includes: a substrate; a gate electrode disposed on the substrate; a semiconductor layer disposed on the substrate and partially overlapping with the gate electrode; a source electrode and a drain electrode spaced apart from each other with respect to a channel region of the semiconductor layer; an insulating layer disposed between the gate electrode and the semiconductor layer; and a barrier layer disposed between the semiconductor layer and the source electrode and between the semiconductor layer and the drain electrode, in which the barrier layer comprises graphene. An ohmic contact is provided based on the type of material used for the semiconductor layer.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: February 18, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yong-Su Lee, Yoon Ho Khang, Se Hwan Yu, Chong Sup Chang
  • Patent number: 8653616
    Abstract: It is aimed to provide a photoelectric conversion device having high adhesion between a first semiconductor layer and an electrode layer as well as high photoelectric conversion efficiency. A photoelectric conversion device comprises an electrode layer, a first semiconductor layer located on the electrode layer and comprising a chalcopyrite-based compound semiconductor of group I-III-VI and oxygen, and a second semiconductor layer located on the first semiconductor layer and forming a pn junction with the first semiconductor layer. In the photoelectric conversion device, the first semiconductor layer has a higher molar concentration of oxygen in a part located on the electrode layer side with respect to a center portion in a lamination direction of the first semiconductor layer than a molar concentration of oxygen in the whole of the first semiconductor layer.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: February 18, 2014
    Assignee: KYOCERA Corporation
    Inventors: Rui Kamada, Shuichi Kasai
  • Patent number: 8624236
    Abstract: A device includes a substrate having a first region and a second region. The first region comprises a first field effect transistor having a horizontal channel region within the substrate, a gate overlying the horizontal channel region, and a first dielectric covering the gate of the first field effect transistor. The second region of the substrate includes a second field effect transistor comprising a first terminal extending through the first dielectric to contact the substrate, a second terminal overlying the first terminal and having a top surface, and a vertical channel region separating the first and second terminals. The second field effect transistor also includes a gate on the first dielectric and adjacent the vertical channel region, the gate having a top surface that is co-planar with the top surface of the second terminal.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: January 7, 2014
    Assignees: Macronix International Co., Ltd., International Business Machines Corporation
    Inventors: Hsiang-Lan Lung, Chung Hon Lam
  • Patent number: 8624219
    Abstract: A memory device can include at least one cathode formed in first opening of a first insulating layer; at least one anode formed in a second opening of second insulating layer, the second insulating layer being a different vertical layer than the first insulating layer; and a memory layer comprising an ion conductor layer extending laterally between the at least one anode and cathode on the first insulating layer, the ion conductor layer having a thickness in the vertical direction less than a depth of the first opening.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: January 7, 2014
    Assignee: Adesto Technologies Corporation
    Inventors: John Ross Jameson, Antonio R. Gallo, Foroozan Sarah Koushan, Michael A. Van Buskirk
  • Patent number: 8614135
    Abstract: A phase change memory is manufactured by providing a substrate including a layer of phase-change material, forming a damascene pattern on the layer of phase-change material, and forming both a top electrode and a bit line in the damascene pattern.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: December 24, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-ho Eun, JaeHee Oh
  • Patent number: 8598576
    Abstract: A spin toque transfer magnetic random access memory (STTMRAM) element comprises a reference layer, formed on a substrate, with a fixed perpendicular magnetic component. A junction layer is formed on top of the reference layer and a free layer is formed on top of the junction layer with a perpendicular magnetic orientation, at substantially its center of the free layer and switchable. A spacer layer is formed on top of the free layer and a fixed layer is formed on top of the spacer layer, the fixed layer has a fixed perpendicular magnetic component opposite to that of the reference layer. The magnetic orientation of the free layer switches relative to that of the fixed layer. The perpendicular magnetic components of the fixed layer and the reference layer substantially cancel each other and the free layer has an in-plane edge magnetization field.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: December 3, 2013
    Assignee: Avalanche Technology, Inc.
    Inventors: Yuchen Zhou, Yiming Huai, Rajiv Yadav Ranjan
  • Patent number: 8563961
    Abstract: Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: October 22, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Yoshitaka Sasago, Akio Shima, Satoru Hanzawa, Takashi Kobayashi, Masaharu Kinoshita, Norikastsu Takaura
  • Patent number: 8563844
    Abstract: Embodiments of a thin-film heterostructure thermoelectric material and methods of fabrication thereof are disclosed. In general, the thermoelectric material is formed in a Group IIa and IV-VI materials system. The thermoelectric material includes an epitaxial heterostructure and exhibits high heat pumping and figure-of-merit performance in terms of Seebeck coefficient, electrical conductivity, and thermal conductivity over broad temperature ranges through appropriate engineering and judicious optimization of the epitaxial heterostructure.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: October 22, 2013
    Assignees: Phononic Devices, Inc., Board of Regents of the University of Oklahoma
    Inventors: Allen L. Gray, Robert Joseph Therrien, Patrick John McCann
  • Patent number: 8563088
    Abstract: A method for preparing a Group 1a-1b-3a-6a material using a selenium/Group 1b ink comprising, as initial components: a selenium component comprising selenium, an organic chalcogenide component having a formula selected from RZ—Z?R? and R2—SH, a Group 1b component and a liquid carrier; wherein Z and Z? are each independently selected from sulfur, selenium and tellurium; wherein R is selected from H, C1-20 alkyl group, a C6-20 aryl group, a C1-20 alkylhydroxy group, an arylether group and an alkylether group; wherein R? and R2 are selected from a C1-20 alkyl group, a C6-20 aryl group, a C1-20 alkylhydroxy group, an arylether group and an alkylether group; and wherein the selenium/Group 1b ink is a stable dispersion.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: October 22, 2013
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Kevin Calzia, David Mosley, David L. Thorsen, Charles R. Szmanda
  • Patent number: 8531867
    Abstract: A memory element can include a memory layer formed between two electrodes; at least one element within the memory layer that is oxidizable in the presence of an electric field applied across the electrodes; and an inhibitor material incorporated into at least a portion of the memory layer that decreases an oxidation rate of the at least one element within the memory layer with respect to the memory layer alone. Methods of forming such a memory element are also disclosed.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: September 10, 2013
    Assignee: Adesto Technologies Corporation
    Inventor: Antonio R. Gallo
  • Patent number: 8513050
    Abstract: A Bi—Se doped with Cu, p-type semiconductor, preferably used as an absorber material in a photovoltaic device. Preferably the semiconductor has at least 20 molar percent Cu. In a preferred embodiment, the semiconductor comprises at least 28 molar percent of Cu. In one embodiment, the semiconductor comprises a molar percentage of Cu and Bi whereby the molar percentage of Cu divided by the molar percentage of Bi is greater than 1.2. In a preferred embodiment, the semiconductor is manufactured as a thin film having a thickness less than 600 nm.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: August 20, 2013
    Assignee: U.S. Department of Energy
    Inventors: Raghu Nath Bhattacharya, Sovannary Phok, Philip Anthony Parilla
  • Patent number: 8466534
    Abstract: The construction of this invention includes an active matrix substrate, an amorphous selenium layer, a high resistance layer, a gold electrode layer, an insulating layer and an auxiliary plate laminated in this order. In one aspect of the present invention, the insulating layer has an inorganic anion exchanger added thereto in order to provide a radiation detector which prevents void formation and pinhole formation in the amorphous semiconductor layer and carrier selective high resistance film, without accumulating electric charges on the auxiliary plate. The inorganic anion exchanger adsorbs chloride ions in the insulating layer, thereby preventing destruction of X-ray detector due to the chloride ions drawn to the gold electrode layer.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: June 18, 2013
    Assignee: Shimadzu Corporation
    Inventors: Shingo Furui, Toshinori Yoshimuta, Junichi Suzuki, Koji Watadani, Satoru Morita
  • Patent number: 8440991
    Abstract: A phase change memory device having a heater that exhibits a temperature dependent resistivity which provides a way of reducing a reset current is presented. The phase change memory device includes a phase change pattern and a heating electrode contacted with the phase change pattern. The heating electrode includes a smart heating electrode such that the smart heating layer is formed of a conduction material that exhibits an increase in resistance as a function of an increase in temperature, i.e., a positive temperature dependent resistivity.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: May 14, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hae Chan Park, Se Ho Lee
  • Publication number: 20130099226
    Abstract: It is aimed to provide a photoelectric conversion device having high adhesion between a first semiconductor layer and an electrode layer as well as high photoelectric conversion efficiency. A photoelectric conversion device comprises an electrode layer, a first semiconductor layer located on the electrode layer and comprising a chalcopyrite-based compound semiconductor of group I-III-VI and oxygen, and a second semiconductor layer located on the first semiconductor layer and forming a pn junction with the first semiconductor layer. In the photoelectric conversion device, the first semiconductor layer has a higher molar concentration of oxygen in a part located on the electrode layer side with respect to a center portion in a lamination direction of the first semiconductor layer than a molar concentration of oxygen in the whole of the first semiconductor layer.
    Type: Application
    Filed: June 28, 2011
    Publication date: April 25, 2013
    Applicant: KYOCERA CORPORATION
    Inventors: Rui Kamada, Shuichi Kasai
  • Patent number: RE45356
    Abstract: Provided are a phase-change memory device using a phase-change material having a low melting point and a high crystallization speed, and a method of fabricating the same. The phase-change memory device includes an antimony (Sb)-selenium (Se) chalcogenide SbxSe100-x phase-change material layer contacting a heat-generating electrode layer exposed through a pore and filling the pore. Due to the use of SbxSe100-x in the phase-change material layer, a higher-speed, lower-power consumption phase-change memory device than a GST memory device can be manufactured.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: February 3, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung Min Yoon, Nam Yeal Lee, Sang Ouk Ryu, Seung Yun Lee, Young Sam Park, Kyu Jeong Choi, Byoung Gon Yu
  • Patent number: RE45861
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a first insulating film region that is embedded in a trench formed on the semiconductor substrate, a gate electrode that covers a lower surface of the first insulating film region, and a gate insulating film that is provided between the gate electrode and the semiconductor substrate. The semiconductor device further includes a first diffusion region that covers a first side surface of the first insulating film region, a second diffusion region that covers a second side surface of the first insulating film region, and a third diffusion region that covers an upper surface of the second diffusion region. A selective element includes a field-effect transistor that is constituted by the gate electrode, the first diffusion region, and the second diffusion region, and a bipolar transistor that is constituted by the substrate and the second and third diffusion regions.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: January 19, 2016
    Assignee: PS4 LUXCO S.A.R.L.
    Inventors: Shuichi Tsukada, Yasuhiro Uchiyama