Semiconductor Is An Oxide Of A Metal (e.g., Cuo, Zno) Or Copper Sulfide Patents (Class 257/43)
  • Patent number: 10818795
    Abstract: A semiconductor device comprising a pixel portion comprising a capacitor and a transistor is provided. The capacitor comprises a first oxide semiconductor film and a transparent conductive material. The transistor comprises a second oxide semiconductor film, a source electrode, and a drain electrode. The transistor is electrically connected to the capacitor. The capacitor is provided to overlap with a first opening portion in an insulating film and a second opening portion in an organic resin film. The transparent conductive material comprises a region over the organic resin film. The second oxide semiconductor film comprises a channel formation region and a first region outside the channel formation region. Each of a carrier density of the first oxide semiconductor film and a carrier density of the first region is higher than a carrier density of the channel formation region.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: October 27, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Masami Jintyou, Yukinori Shima, Takashi Hamochi, Yasutaka Nakazawa
  • Patent number: 10818801
    Abstract: A manufacturing method of a thin-film transistor is provided. The method include: forming a gate pattern layer on a substrate; forming a gate insulating layer covering the gate pattern layer; depositing semi-conductive oxide material on the gate insulating layer to form an active pattern layer on the gate insulating layer; depositing reducing material on the active pattern layer to form a reducing pattern layer; and forming a source pattern layer and a drain pattern layer on the reducing pattern layer. A thin-film transistor is further provided.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: October 27, 2020
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Qianyi Zhang
  • Patent number: 10818798
    Abstract: A method for manufacturing a thin film transistor includes forming a light shielding layer and a buffer layer covering the light shielding layer on a substrate. The method includes forming an active layer including a peripheral region and a channel region. The method includes forming a gate insulating layer covering the channel region and forming a contact hole exposing the light shielding layer. The method includes forming a source region and a drain region disposed on both sides of the channel region. The method includes forming an electrode layer including a gate electrode, a source electrode and a drain electrode spaced apart one another. The method includes forming a dielectric layer covering the gate electrode, the source electrode, the drain electrode and the buffer layer.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: October 27, 2020
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yingbin Hu, Ce Zhao, Yuankui Ding, Jun Wang, Jun Liu, Guangyao Li, Yongchao Huang, Wei Li, Liangchen Yan
  • Patent number: 10815426
    Abstract: A liquid crystal cell according to the present invention includes a TFT board including a first dielectric substrate, TFTs supported by the first dielectric substrate, and patch electrodes, a slot board including a second dielectric substrate and a slot electrode having slots and supported by the second dielectric substrate, and a liquid crystal layer between the TFT board and the slot board, which are positioned with the patch electrodes and the slot electrode facing each other, and a sealant disposed between the TFT board and the slot board and surrounding the liquid crystal layer. The liquid crystal layer includes a liquid crystal compound containing an isothiocyanate group. The sealant includes an ene-thiol compound in which an ene compound and a thiol compound are bonded by using a radical.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: October 27, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masanobu Mizusaki, Kiyoshi Minoura
  • Patent number: 10816865
    Abstract: Provided is an active matrix substrate provided with a substrate (1), a peripheral circuit that includes a first oxide semiconductor thin-film transistor (TFT) (101), a plurality of second oxide semiconductor TFTs (102) disposed in a display area, and a first inorganic insulating layer (11) covering the plurality of second oxide semiconductor TFTs (102), the first oxide semiconductor TFT (101) having a lower gate electrode (3A), a gate insulating layer (4), an oxide semiconductor (5A) disposed so as to face the lower gate electrode with the gate insulating layer interposed therebetween, a source electrode (7A) and a drain electrode (8A), and an upper gate electrode (BG) disposed on the oxide semiconductor (5A) with an insulating layer that includes the first inorganic insulating layer (11) interposed therebetween, and furthermore having, on the upper gate electrode (BG), a second inorganic insulating layer (17) covering the first oxide semiconductor TFT (101).
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: October 27, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tetsuo Kikuchi, Tohru Daitoh, Hajime Imai, Toshikatsu Itoh, Hisao Ochi, Hideki Kitagawa, Masahiko Suzuki, Teruyuki Ueda, Ryosuke Gunji, Kengo Hara, Setsuji Nishimiya
  • Patent number: 10818766
    Abstract: An active matrix substrate according to an embodiment of the present invention includes a plurality of thin film transistors supported on a substrate and an inorganic insulating layer covering the plurality of thin film transistors. Each thin film transistor includes a gate electrode, an oxide semiconductor layer, a gate insulating layer, a source electrode, and a drain electrode. At least one of the gate insulating layer and the inorganic insulating layer is an insulating layer stack having a multilayer structure including a silicon oxide layer and a silicon nitride layer. The insulating layer stack further includes an intermediate layer disposed between the silicon oxide layer and the silicon nitride layer, the intermediate layer having a refractive index nC higher than a refractive index nA of the silicon oxide layer and lower than a refractive index nB of the silicon nitride layer.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: October 27, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masahiko Suzuki, Hideki Kitagawa, Tetsuo Kikuchi, Toshikatsu Itoh, Setsuji Nishimiya, Teruyuki Ueda, Kengo Hara, Hajime Imai, Tohru Daitoh
  • Patent number: 10818694
    Abstract: The present disclosure relates to array substrate, preparation method thereof and display panel. An array substrate comprises: a first thin film transistor and a second thin film transistor over a substrate; wherein the first thin film transistor comprises a first portion of a first insulating layer, the first insulating layer comprises a first recess corresponding to the second thin film transistor, and the second thin film transistor is located in the first recess; and wherein a thickness of a second portion of the first insulating layer, which is below the bottom of the first recess, is smaller than that of the first portion of the first insulating layer.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: October 27, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wei Yang, Hehe Hu, Xinhong Lu
  • Patent number: 10809864
    Abstract: A film touch sensor includes a base film, an adhesive layer, a separation layer and a conductive pattern layer, which are sequentially laminated. The base film has a retardation value Ro in a plane direction of 0 to 10 nm, and a retardation value Rth in a thickness direction of ?10 to 10 nm. When the film touch sensor is applied to a final product, interference between laminates may be minimized to significantly reduce a change in color sense of an image.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: October 20, 2020
    Assignee: DONGWOO FINE-CHEM CO., LTD.
    Inventors: Byung Muk Yu, Min Hyuk Park, Myung Young An
  • Patent number: 10804272
    Abstract: A semiconductor device capable of retaining data for a long time is provided. A leakage current path between adjacent memory cells in a memory cell array included in the semiconductor device is blocked without increasing the number of manufacturing steps, so that memory retention characteristics can be improved.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: October 13, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Miki Suzuki
  • Patent number: 10802362
    Abstract: A display panel and manufacturing method for the same. The display panel includes an array substrate, a passivation layer, an organic planarization layer, a first color resist layer and a second color resist layer and an organic planarization layer. Each sub-pixel circuit includes at least two thin-film transistors; at least two via holes are prepared on the passivation layer and the organic planarization layer. The first color resist layer includes a first color resist region and multiple second color resist regions connected thereto. A projection of the first color resist region on the array substrate is located at two sides of the sub-pixel circuit. Each second color resist region is located above the at least two thin-film transistors; the second color resist layer is stacked above the second color resist region. The first color resist layer will not crack, and the main region spacer can reach a desired height.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: October 13, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Yanxi Ye
  • Patent number: 10804406
    Abstract: The present invention provides a thin-film transistor substrate including a base substrate and a thin-film transistor, the thin-film transistor including: a gate electrode; a gate insulating layer; a source electrode and a drain electrode; and an oxide semiconductor layer in this order. The source electrode and the drain electrode each include a first conductive layer and a second conductive layer covering the first conductive layer. The second conductive layer contains at least one element selected from the group consisting of molybdenum, tantalum, tungsten, and nickel. The gate insulating layer in a region between the source electrode and the drain electrode has a smaller thickness than in a region below the source electrode and in a region below the drain electrode.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: October 13, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Katsunori Misaki
  • Patent number: 10797088
    Abstract: A semiconductor device includes an insulating substrate, a polysilicon layer, a first-gate-insulating layer, a first metal layer, an oxide-semiconductor layer, a second-gate-insulating layer, a second metal layer, a first insulating interlayer, a third metal layer, a first top gate planar type thin film transistor in which the polysilicon layer serves as a channel, and a second top gate planar self-aligned type thin film transistor in which the oxide-semiconductor layer serves as a channel. The gates of the first top gate planar type thin film transistor and the second top gate planar self-aligned type thin film transistor are made of the first and second metal layers, respectively. The sources and the drains of the first top gate planar type thin film transistor and the second top gate planar self-aligned type thin film transistor are made of the third metal layer.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: October 6, 2020
    Assignee: TIANMA MICROELECTRONICS CO., LTD.
    Inventor: Kazushige Takechi
  • Patent number: 10795478
    Abstract: Provided are an array substrate and preparation method therefor, and a display apparatus. The array substrate includes: a substrate, the substrate having a first TFT region, a touch control region and a second TFT region; a photosensitive PN junction, the photosensitive PN junction being provided in the touch control region; a first thin-film transistor, provided in the first TFT region, and electrically connected to the photosensitive PN junction; and a second thin-film transistor, provided in the second TFT region, and electrically connected to a pixel electrode.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: October 6, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wenlin Zhang, Wei Yang, Ce Ning
  • Patent number: 10797166
    Abstract: A manufacturing method for an IGZO active layer is disclosed. The method comprises steps of: after depositing a first metal layer and a gate insulation layer on a substrate, depositing an IGZO material on the gate insulation layer, and forming an IGZO film; and performing a plasma cleaning treatment on a surface of the IGZO film by using an argon gas or a helium gas to adjust element contents on the surface of the IGZO film, and forming an IGZO active layer. The present invention also correspondingly discloses a manufacturing method for an oxide thin film transistor. By implementing the embodiments of the present invention, the elements on the film surface of the IGZO active layer can be adjusted to improve electrical properties.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: October 6, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Yue Wu, Wei Wu
  • Patent number: 10797123
    Abstract: A display panel includes a base layer having a first region and a bent second region. An inorganic layer is disposed on the base layer. A lower opening is formed within the inorganic layer and overlaps the second region. A first thin-film transistor is disposed on the inorganic layer and includes a silicon semiconductor pattern overlapping the first region. A second thin-film transistor is disposed on the inorganic layer and includes an oxide semiconductor pattern overlapping the first region. Insulating layers overlap the first and second regions. An upper opening is formed within the insulating layers. A signal line electrically connects the second thin-film transistor. An organic layer overlaps the first and second regions and is disposed in the lower and upper openings. A luminescent device is disposed on the organic layer and overlaps the first region.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: October 6, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yoon-Jong Cho, Suyeon Yun, Seokje Seong, Seongjun Lee, Joonhoo Choi, Semyung Kwon, Kyunghyun Baek
  • Patent number: 10788696
    Abstract: A method for attaching display panel comprises: preparing a frame-shaped body comprising a first rod-like member and two second rod-like members, the two second rod-like members being substantially parallel to each other and crossing the first rod-like member; bonding the first rod-like member and the two second rod-like members to a given plane surface or a given curved surface; and moving a display panel having a width to be supported between the two second rod-like members from one of the ends of two second rod-like members towards the first rod-like member along a first surface of the two second rod-like members and a second surface of the two second rod-like members, the first surface and the second surface facing each other.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: September 29, 2020
    Assignee: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventor: Katsuhiko Kishimoto
  • Patent number: 10790308
    Abstract: A field-effect transistor including: a gate electrode, which is configured to apply gate voltage; a source electrode and a drain electrode, which are configured to transfer an electrical signal; an active layer, which is formed between the source electrode and the drain electrode; and a gate insulating layer, which is formed between the gate electrode and the active layer, the active layer including at least two kinds of oxide layers including layer A and layer B, and the active layer satisfying at least one of condition (1) and condition (2) below: condition (1): the active layer includes 3 or more oxide layers including 2 or more of the layer A; and condition (2): a band-gap of the layer A is lower than a band-gap of the layer B and an oxygen affinity of the layer A is equal to or higher than an oxygen affinity of the layer B.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: September 29, 2020
    Assignee: Ricoh Company, Ltd.
    Inventors: Naoyuki Ueda, Yuki Nakamura, Yukiko Abe, Shinji Matsumoto, Yuji Sone, Ryoichi Saotome, Sadanori Arae, Minehide Kusayanagi
  • Patent number: 10784116
    Abstract: There is provided a technique that includes: (a) providing a substrate having a film containing a predetermined element, oxygen and carbon formed on a surface of the substrate; and (b) modifying at least a surface of the film by supplying a carbon-free fluorine-based gas to the substrate under a condition in which etching of the film does not occur.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: September 22, 2020
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Tsukasa Kamakura, Koei Kuribayashi, Daigo Yamaguchi
  • Patent number: 10784285
    Abstract: A novel display device or the like in which a transistor connected to a scan line has small gate capacitance is provided. A novel display device or the like in which a scan line has low resistance is provided. A novel display device or the like in which pixels can be arranged with high density is provided. A novel display device or the like that can be manufactured without an increase in cost is provided. In a transistor including a first gate electrode and a second gate electrode, the first gate electrode is formed using a metal material with low resistance and the second gate electrode is formed using a metal oxide material that can reduce oxygen vacancies in an oxide semiconductor layer. The first gate electrode is connected to the scan line, and the second gate electrode is connected to a wiring to which a constant potential is supplied.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: September 22, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kouhei Toyotaka, Kei Takahashi, Hideaki Shishido, Koji Kusunoki
  • Patent number: 10784284
    Abstract: To provide a highly reliable semiconductor device that is suitable for miniaturization and an increase in density. The semiconductor device includes a first insulator over a substrate, a transistor including an oxide semiconductor over the first insulator, a second insulator over the transistor, and a third insulator over the second insulator. The first insulator and the third insulator have a barrier property with respect to oxygen and hydrogen. The second insulator includes an excess-oxygen region. The transistor is enclosed with the first insulator and the third insulator that are in contact with each other in an edge of a region where the transistor is positioned.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: September 22, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10777581
    Abstract: A method for manufacturing an IGZO thin-film transistor includes: manufacturing a buffer layer, an active layer, a gate electrode layer, and a gate insulator layer in sequence on a substrate, and performing a patterning process; depositing a transparent insulating metal oxide layer on the patterned buffer layer, the active layer, the gate electrode layer, and the gate insulator layer by sputtering, and annealing the transparent insulating metal oxide layer so as to improve electric properties of a thin-film transistor; depositing a dielectric layer on the transparent insulating metal oxide layer, and patterning the dielectric layer and the transparent insulating metal oxide layer by means of a photolithography process and a dry etch process; depositing S/D (source/drain) contact regions on the dielectric layer; and performing a patterning process.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: September 15, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Songshan Li
  • Patent number: 10777686
    Abstract: The present disclosure provides a thin film transistor and a method for manufacturing the same, an array substrate and a display panel. The thin film transistor includes a base substrate; a partially transparent layer on one side of the base substrate; a first gate electrode on one side of the partially transparent layer away from the base substrate; a second gate insulation layer on one side of the first gate electrode away from the base substrate; and an active layer on one side of the second gate insulation layer away from the base substrate. An orthographic projection of the partially transparent layer to the base substrate covers an orthographic projection of the active layer to the base substrate.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: September 15, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Guoying Wang, Zhen Song
  • Patent number: 10777644
    Abstract: Current conducting devices and methods for their formation are disclosed. Described are vertical current devices that include a substrate, an n-type material layer, a plurality of p-type gates, and a source. The n-type material layer disposed on the substrate and includes a current channel. A plurality of p-type gates are disposed on opposite sides of the current channel. A source is disposed on a distal side of the current channel with respect to the substrate. The n-type material layer comprises beta-gallium oxide.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: September 15, 2020
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Travis J. Anderson, Marko J. Tadjer, Andrew D. Koehler, Karl D. Hobart
  • Patent number: 10777587
    Abstract: Provided is an active matrix substrate (1001) that includes multiple inspection TFTs (10Q) that are arranged in a non-display area (900), and an inspection circuit (200) that includes multiple inspection TFTs (10Q). At least one or more of the multiple inspection TFTs (10Q) are arranged within a semiconductor chip mounting area (R) in which a semiconductor chip is mounted. Each of the multiple inspection TFTs (10Q) includes a semiconductor layer, a lower gate electrode (FG) that is positioned on a side of the substrate of the semiconductor layer with a gate insulation layer in between, an upper gate electrode (BG) that is positioned on a side opposite to the side of the substrate of the semiconductor layer with an insulation layer including a first insulation layer in between, and a source electrode and a drain electrode that are connected to the semiconductor layer.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: September 15, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Jun Nishimura, Yoshihito Hara, Yoshimasa Chikama, Yukinobu Nakata
  • Patent number: 10770010
    Abstract: An information terminal capable of switching display and non-display of images by strain. The information terminal includes a display portion and a strain sensor. The display portion includes a liquid crystal element, a light-emitting element, and a first and a second transistors. The strain sensor includes a strain sensor element and a resistor. The first transistor has a function of controlling current flowing into the light-emitting element. The strain sensor element has a function as a variable resistor. A first terminal of the strain sensor element is electrically connected to a first terminal of the resistor. A gate of the first transistor is electrically connected to a first terminal of the strain sensor element via the second transistor.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: September 8, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yuki Okamoto
  • Patent number: 10770488
    Abstract: The present disclosure provides a method for manufacturing an active switch array substrate, and the active switch array substrate, the method includes: providing a substrate; coating a first metal layer on the substrate; forming a gate electrode by treating the first metal layer; depositing an amorphous silicon layer on the substrate and the gate electrode; coating a second metal layer on the amorphous silicon layer; forming a patterned second metal layer; coating a passivation layer on the patterned second metal layer; forming a through hole in the passivation layer; coating a light permeability conductive layer on the passivation layer; and carrying out a fourth photolithography process to the light permeability conductive layer, the passivation layer, and the patterned second metal layer, to form a channel, a source electrode, and a drain electrode on the light permeability conductive layer, the passivation layer, and the patterned second metal layer.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: September 8, 2020
    Assignees: HKC Corporation Limited, Chongqing HKC Optoelectronics Technology Co., Ltd.
    Inventor: En-tsung Cho
  • Patent number: 10763371
    Abstract: A thin film transistor is provided. The thin film transistor includes an oxide semiconductor layer including a source region, a drain region, and a channel region wherein a portion of the source and drain regions has an oxygen concentration less than the channel region. Further provided is a thin film transistor that includes an oxide semiconductor layer including a source region, a drain region, and a channel region, wherein a portion of the source and drain regions includes a dopant selected from the group consisting of aluminum, boron, gallium, indium, titanium, silicon, germanium, tin, lead, and combinations thereof.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: September 1, 2020
    Assignee: Joled Inc.
    Inventors: Narihiro Morosawa, Yoshihiro Oshima
  • Patent number: 10763280
    Abstract: A semiconductor device includes a first fin field effect transistor (FinFET) device, the first FinFET device including a plurality of fins formed in a substrate, an epitaxial layer of semiconductor material formed on the fins forming non-planar source/drain regions, and a first gate structure traversing across the plurality of fins. The semiconductor device includes a second FinFET device, the second FinFET device including a substantially planar fin formed in the substrate, an epitaxial layer of the semiconductor material formed on the substantially planar fin and forming substantially planar source/drain regions, and a second gate structure traversing across the substantially planar fin.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Chen Liu, Guan-Jie Shen, Chia-Der Chang
  • Patent number: 10756156
    Abstract: A display device includes a substrate, a pixel circuit unit which is disposed on the substrate and having a first hole, a light blocking layer which is disposed on the pixel circuit unit and having a second hole corresponding to the first hole, a light emitting layer disposed on the pixel circuit unit, and a sealing unit on the light blocking layer. The substrate includes a first layer having a depression corresponding to the first hole, and a second layer which is disposed between the first layer and the pixel circuit unit and having a third hole between the depression and the second hole. The sealing unit includes a cover portion on the light blocking layer, and an extension portion extending from the cover portion. The depression has a width larger than a width of the third hole.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: August 25, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Wooyong Sung, Junghan Seo, Kwanhyuck Yoon, Sooyoun Kim, Jongki Kim, Seungho Yoon, Heeyeon Lee, Moonwon Chang
  • Patent number: 10756118
    Abstract: A display device includes a liquid crystal element, a transistor, a scan line, and a signal line. The liquid crystal element includes a pixel electrode, a liquid crystal layer, and a common electrode. The scan line and the signal line are each electrically connected to the transistor. The scan line and the signal line each include a metal layer. The transistor is electrically connected to the pixel electrode. A semiconductor layer of the transistor includes a stack of a first metal oxide layer and a second metal oxide layer. The first metal oxide layer includes a region with lower crystallinity than the second metal oxide layer. The transistor includes a first region connected to the pixel electrode. The pixel electrode, the common electrode, and the first region are each configured to transmit visible light. Visible light passes through the first region and the liquid crystal element and exits from the display device.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: August 25, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kenichi Okazaki, Daisuke Kurosaki, Yasutaka Nakazawa, Kazunori Watanabe, Koji Kusunoki
  • Patent number: 10748936
    Abstract: A thin film transistor array panel includes a substrate and a thin film transistor disposed on a surface of the substrate. The thin film transistor includes a semiconductor, a source electrode, and a drain electrode that are disposed on a same layer as one another. The semiconductor is between the source electrode and the drain electrode. The thin film transistor array panel further includes a buffer layer disposed between the semiconductor and the substrate and including an inorganic insulating material. The first edge of the buffer layer is substantially parallel to an adjacent edge of the semiconductor, a second edge of the buffer layer is substantially parallel to an adjacent edge of the source electrode, and a third edge of the buffer layer is substantially parallel to an adjacent edge of the drain electrode.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sung Ho Kim, Dong Won Kim, Jong Moo Huh
  • Patent number: 10749039
    Abstract: A high-performance TFT substrate (100) for a flat panel display includes a substrate (110), a first conductive layer (130) on the substrate (110), a semiconductor layer (103) positioned on the first conductive layer (130), and a second conductive layer (150) positioned on the semiconductor layer (103). The first conductive layer (130) defines a gate electrode (101). The second conductive layer (150) defines a source electrode (105) and a drain electrode (106) spaced apart from the source electrode (105). The second conductive layer (150) includes a first layer (151) on the semiconductor layer (103) and a second layer (152) positioned on the first layer (151). The first layer (151) can be made of metal oxide. The second layer (152) can be made of aluminum or aluminum alloy.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: August 18, 2020
    Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yi-Chun Kao, Po-Li Shih, Wei-Chih Chang, I-Wei Wu
  • Patent number: 10741690
    Abstract: It is an object of the present invention to provide a technique capable of reducing a contact resistance between source and drain electrodes and a channel region. A thin film transistor includes: a first semiconductor layer provided on a first insulation film lying on a gate electrode and adjacent to a partial region that is part of the first insulation film lying on the gate electrode as seen in plan view; a source electrode and a drain electrode sandwiching the partial region therebetween as seen in plan view; a second insulation film having an opening portion provided over the partial region; and a second semiconductor layer provided on the second insulation film. The second semiconductor layer is in contact with the source electrode and the drain electrode, and is in contact with the partial region and the first semiconductor layer through the opening portion of the second insulation film.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: August 11, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kazunori Inoue, Rii Hirano
  • Patent number: 10741696
    Abstract: A semiconductor device includes a thin film transistor including a semiconductor layer, a gate electrode, a gate insulating layer, a source electrode, a drain electrode, the semiconductor layer includes a layered structure including a first oxide semiconductor layer including In and Zn, in which an atomic ratio of In with respect to all metallic elements included in the first oxide semiconductor layer is higher than an atomic ratio of Zn, a second oxide semiconductor layer including In and Zn, in which an atomic ratio of Zn with respect to all metallic elements included in the second oxide semiconductor layer is higher than an atomic ratio of In, and an intermediate oxide semiconductor layer arranged between the first oxide semiconductor layer and the second oxide semiconductor layer, and the first and second oxide semiconductor layers are crystalline oxide semiconductor layers, and the intermediate oxide semiconductor layer is an amorphous oxide semiconductor layer, and the first oxide semiconductor layer is
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: August 11, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masahiko Suzuki, Hajime Imai, Hideki Kitagawa, Tetsuo Kikuchi, Setsuji Nishimiya, Teruyuki Ueda, Kengo Hara, Tohru Daitoh, Toshikatsu Itoh
  • Patent number: 10741679
    Abstract: Provided is a semiconductor device having favorable reliability.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: August 11, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kazutaka Kuriki, Yuji Egi, Hiromi Sawai, Yusuke Nonaka, Noritaka Ishihara, Daisuke Matsubayashi
  • Patent number: 10734461
    Abstract: An exemplary embodiment of the present invention provides a thin film transistor array panel and an organic light emitting diode display including the same including a substrate, a semiconductor disposed on the substrate, a first gate insulation layer disposed on the semiconductor, and a first diffusion barrier layer disposed on the first gate insulation layer. A second diffusion barrier layer is disposed on a lateral surface of the first diffusion barrier layer. A first gate electrode is disposed on the first diffusion barrier layer. A source electrode and a drain electrode are connected to the semiconductor. The first diffusion barrier layer comprises a metal, and the second diffusion barrier layer comprises a metal oxide including the metal.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: August 4, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Dong Hee Lee, Hyun Ju Kang, Sang Won Shin
  • Patent number: 10734487
    Abstract: A semiconductor device with a high on-state current is provided. The semiconductor device includes a first insulator over a substrate, an oxide over the first insulator, a second insulator over the oxide, a conductor overlapping with the oxide with the second insulator therebetween, a third insulator in contact with a top surface of the oxide, a fourth insulator in contact with a top surface of the third insulator, a side surface of the second insulator, and a side surface of the conductor, and a fifth insulator in contact with a side surface of the fourth insulator, a side surface of the third insulator, and the top surface of the oxide. The third insulator has a lower oxygen permeability than the fourth insulator.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: August 4, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Komagata, Naoki Okuno, Yutaka Okazaki, Hiroshi Fujiki
  • Patent number: 10734413
    Abstract: A novel metal oxide is provided. The metal oxide has a plurality of energy gaps, and includes a first region having a high energy level of a conduction band minimum and a second region having an energy level of a conduction band minimum lower than that of the first region. The second region comprises more carriers than the first region. A difference between the energy level of the conduction band minimum of the first region and the energy level of the conduction band minimum of the second region is 0.2 eV or more. The energy gap of the first region is greater than or equal to 3.3 eV and less than or equal to 4.0 eV and the energy gap of the second region is greater than or equal to 2.2 eV and less than or equal to 2.9 eV.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: August 4, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Motoki Nakashima, Haruyuki Baba
  • Patent number: 10727322
    Abstract: The invention provides a BCE TFT substrate and manufacturing method thereof. The method uses low deposition power and low oxygen content to deposit first silicon oxide thin film; then increases deposition power with low oxygen content to deposit second silicon oxide thin film. The first and second silicon oxide thin films form a passivation layer; the second silicon oxide film is implanted with oxygen to form a superficial layer so that the Si:O atomic ratio in the superficial layer is close to or same as Si:O atomic ratio of SiO2, to ensure the passivation layer in contact with the air side is strongly hydrophobic to prevent outside water vapor into the back-channel, while ensuring the side of passivation layer contacting IGZO active layer has a lower oxygen content to reduce the probability of forming unbalanced O-ions at the interface between passivation layer and IGZO active layer.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: July 28, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Chunsheng Jiang
  • Patent number: 10727273
    Abstract: A MRAM-TFT unit cell and a method for fabricating the same. The MRAM-TFT unit cell includes a MRAM device and a TFT device electrically coupled to the MRAM device. The MRAM device and the TFT device are situated within a common plane of the MRAM-TFT cell. The method includes forming a TFT device comprising a source/drain region, and a semiconducting layer on a substrate. A magnetic tunnel junction stack (MTJ) is formed in contact with the source region. A first contact is formed on the MTJ, and a second contact is formed on the drain region. A first interconnect metal layer is formed in contact with the first contact, and a second first interconnect metal layer is formed in contact with the second contact. A third contact is formed on a gate region of the TFT device. A third interconnect metal layer is formed in contact with the third contact.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: July 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Praveen Joseph, Xuefeng Liu, Gauri Karve, Eric Raymond Evarts
  • Patent number: 10727244
    Abstract: A semiconductor memory device includes a first semiconductor chip and a second semiconductor chip. Each semiconductor chip of the first and second semiconductor chips may include a cell array region and a peripheral circuit region. The cell array region may include an electrode structure including electrodes sequentially stacked on a body conductive layer and vertical structures extending through the electrode structure and connected to the body conductive layer. The peripheral circuit region may include a residual substrate on the body conductive layer and on which a peripheral transistor is located. A bottom surface of the body conductive layer of the second semiconductor chip may face a bottom surface of the body conductive layer of the first semiconductor chip.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: July 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Hwang, Joon-Sung Lim, Eunsuk Cho
  • Patent number: 10727138
    Abstract: A monocrystalline semiconductor layer is formed on a conductive layer on an insulating layer on a substrate. The conductive layer is a part of an interconnect layer. The monocrystalline semiconductor layer extends laterally on the insulating layer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Van H. Le, Marko Radosavljevic, Benjamin Chu-Kung, Rafael Rios, Gilbert Dewey
  • Patent number: 10727309
    Abstract: A thin film transistor array panel includes a first conductive layer (102) including a gate electrode; a channel layer (104) disposed over the gate; and a second conductive layer (105) disposed over the channel layer (104). The second conductive layer (105) includes a multi-layered portion defining a source electrode (105a) and a drain electrode (105b), which includes a first sub-layer (105-1), a second sub-layer (105-2), and a third sub-layer (105-3) sequentially disposed one over another. Both the third and the first sub-layers (105-3, 105-1) include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer (105-1) is greater than that in the third sub-layer (105-3).
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: July 28, 2020
    Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yi-Chun Kao, Hsin-Hua Lin, Po-Li Shih, Wei-Chih Chang, I-Min Lu, I-Wei Wu
  • Patent number: 10720334
    Abstract: In some embodiments, a selective cyclic (optionally dry) etching of a first surface of a substrate relative to a second surface of the substrate in a reaction chamber by chemical atomic layer etching comprises forming a modification layer using a first plasma and etching the modification layer. The first surface comprises carbon and/or nitride and the second surface does not comprise carbon and/or nitride.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: July 21, 2020
    Assignee: ASM IP HOLDING B.V.
    Inventors: Rene Henricus Jozef Vervuurt, Nobuyoshi Kobayashi, Takayoshi Tsutsumi, Masaru Hori
  • Patent number: 10720532
    Abstract: A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack. The third oxide semiconductor layer includes a first layer in contact with the stack and a second layer over the first layer. The first layer includes a microcrystalline layer, and the second layer includes a crystalline layer in which c-axes are aligned in a direction perpendicular to a surface of the first layer.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: July 21, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura, Hideomi Suzawa
  • Patent number: 10714053
    Abstract: The present disclosure provides a driving circuit, a method for controlling light emission, and a display device. The driving circuit includes one or more light emission shift registers, each of which includes a first processing module configured to control a signal at a first node based on signals at the input signal terminal, the first clock signal terminal and the second clock signal terminal; a second processing module including first and second transistors, wherein the first transistor is a dual-gate transistor, and the second transistor has a first terminal electrically connected to the pulse signal terminal and a second terminal electrically connected to the second node; and an output module configured to control a signal at an output signal terminal based on the signals at the first level signal terminal, the second level signal terminal, the first node and the second node.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: July 14, 2020
    Assignee: SHANGHAI TIANMA AM-OLED CO., LTD.
    Inventors: Renyuan Zhu, Yue Li, Dongxu Xiang, Yana Gao, Xingyao Zhou, Gaojun Huang, Yilin Xu, Zhonglan Cai, Juan Zhu
  • Patent number: 10714903
    Abstract: In some implementations, a VCSEL array may include a plurality of VCSELs that each operates concurrently and emits light at a same wavelength. A first distance between a first pair of adjacent VCSELs, of the plurality of VCSELs, may be different from a second distance between a second pair of adjacent VCSELs of the plurality of VCSELs. The first pair of adjacent VCSELs may be located closer to a center of the VCSEL array than the second pair of adjacent VCSELs. At least one of temperature non-uniformity or optical power non-uniformity among the plurality of VCSELs may be reduced as compared to another VCSEL array, with a same physical footprint as the VCSEL array, comprising uniformly spaced VCSELs.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: July 14, 2020
    Assignee: Lumentum Operations LLC
    Inventors: Albert Yuen, Ajit Vijay Barve
  • Patent number: 10714631
    Abstract: The present invention provides two methods for crystallizing a metal oxide semiconductor layer and a semiconductor structure. The first crystallization method is treating an amorphous metal oxide semiconductor layer including indium with oxygen at a pressure of about 550 mtorr to about 5000 mtorr and at a temperature of about 200° C. to about 750° C. The second crystallization method is, firstly, sequentially forming a first amorphous metal oxide semiconductor layer, an aluminum layer, and a second amorphous metal oxide semiconductor layer on a substrate, and, secondly, treating the first amorphous metal oxide semiconductor layer, the aluminum layer, and the second amorphous metal oxide semiconductor layer with an inert gas at a temperature of about 350° C. to about 650° C.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: July 14, 2020
    Assignee: AU OPTRONICS CORPORATION
    Inventor: Jia-Hong Ye
  • Patent number: 10714503
    Abstract: An object is to provide a display device which operates stably with use of a transistor having stable electric characteristics. In manufacture of a display device using transistors in which an oxide semiconductor layer is used for a channel formation region, a gate electrode is further provided over at least a transistor which is applied to a driver circuit. In manufacture of a transistor in which an oxide semiconductor layer is used for a channel formation region, the oxide semiconductor layer is subjected to heat treatment so as to be dehydrated or dehydrogenated; thus, impurities such as moisture existing in an interface between the oxide semiconductor layer and the gate insulating layer provided below and in contact with the oxide semiconductor layer and an interface between the oxide semiconductor layer and a protective insulating layer provided on and in contact with the oxide semiconductor layer can be reduced.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: July 14, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichiro Sakata, Toshinari Sasaki, Miyuki Hosoba
  • Patent number: 10714512
    Abstract: The disclosure discloses a thin film transistor, a method for fabricating the same, and a display device so as to avoid a source and a drain from being oxidized while the thin film transistor is being fabricated, to thereby improve the performance of the thin film transistor. The method for fabricating a thin film transistor includes: forming an active layer pattern on a base substrate, and a source-drain metal layer located above the active layer pattern and with a same pattern as the active layer pattern, using one patterning process; forming a first insulation layer above the source-drain metal layer; and patterning the source-drain metal layer and the first insulation layer using one patterning process so that portion of the active layer pattern corresponding to a channel area is exposed to form a source pattern and a drain pattern.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: July 14, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Shuang Sun, Fangzhen Zhang