Semiconductor Is An Oxide Of A Metal (e.g., Cuo, Zno) Or Copper Sulfide Patents (Class 257/43)
  • Patent number: 11515442
    Abstract: An optical semiconductor element having a mesa portion includes a substrate and semiconductor layers on the substrate. The optical semiconductor element further includes a first contact electrode, a second contact electrode on the semiconductor layer, first and second lead-out wires connected to the first and second contact electrodes, respectively, and an insulating film covering at least an upper surface of the semiconductor layer and the second contact electrode. The second lead-out wire is connected to the second contact electrode in an opening of the insulating film. An outer peripheral end of the second contact electrode in at least a portion where the second contact electrode and the second lead-out wire are connected is above and outside an outer peripheral end of a connection portion with the semiconductor layer, and an inner peripheral end is above and inside an inner peripheral end of the connection portion with the semiconductor layer.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: November 29, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenji Fujimoto, Koshi Himeda, Toshihiro Tada, Tetsuro Toritsuka, Shinji Kaburaki
  • Patent number: 11515426
    Abstract: A change in electrical characteristics of a semiconductor device including an interlayer insulating film over a transistor including an oxide semiconductor as a semiconductor film is suppressed. The structure includes a first insulating film which includes a void portion in a step region formed by a source electrode and a drain electrode over the semiconductor film and contains silicon oxide as a component, and a second insulating film containing silicon nitride, which is provided in contact with the first insulating film to cover the void portion in the first insulating film. The structure can prevent the void portion generated in the first insulating film from expanding outward.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: November 29, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Toshinari Sasaki, Katsuaki Tochibayashi, Shunpei Yamazaki
  • Patent number: 11515376
    Abstract: A display panel includes a base layer having a first region and a bent second region. An inorganic layer is disposed on the base layer. A lower groove is formed within the inorganic layer and overlaps the second region. A first thin-film transistor is disposed on the inorganic layer and includes a silicon semiconductor pattern overlapping the first region. A second thin-film transistor is disposed on the inorganic layer and includes an oxide semiconductor pattern overlapping the first region. Insulating layers overlap the first and second regions. An upper groove is formed within the insulating layers. A signal line electrically connects the second thin-film transistor. An organic layer overlaps the first and second regions and is disposed in the lower and upper grooves. A luminescent device is disposed on the organic layer and overlaps the first region.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: November 29, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yoon-Jong Cho, Suyeon Yun, Seokje Seong, Seongjun Lee, Joonhoo Choi, Semyung Kwon, Kyunghyun Baek
  • Patent number: 11515260
    Abstract: A method for fabricating a semiconductor package includes forming a release layer on a first carrier substrate. An etch stop layer is formed on the release layer. A first redistribution layer is formed on the etch stop layer and includes a plurality of first wires and a first insulation layer surrounding the plurality of first wires. A first semiconductor chip is formed on the first redistribution layer. A solder ball is formed between the first redistribution layer and the first semiconductor chip. A second carrier substrate is formed on the first semiconductor chip. The first carrier substrate, the release layer, and the etch stop layer are removed. The second carrier substrate is removed.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: November 29, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Da Hye Kim, Dong Kyu Kim, Jung-Ho Park
  • Patent number: 11515146
    Abstract: A method of forming a gallium oxide film is provided, and the method may include supplying mist of a material solution comprising gallium atoms and chlorine atoms to a surface of a substrate while heating the substrate so as to form the gallium oxide film on the surface of the substrate, in which a molar concentration of chlorine in the material solution is equal to or more than 3.0 times and equal to or less than 4.5 times a molar concentration of gallium in the material solution.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: November 29, 2022
    Assignees: DENSO CORPORATION, NATIONAL UNIVERSITY CORPORATION KYOTO INSTITUTE OF TECHNOLOGY
    Inventors: Tatsuji Nagaoka, Hiroyuki Nishinaka, Masahiro Yoshimoto
  • Patent number: 11508177
    Abstract: A display panel, a manufacturing method thereof and a display device are provided. The display panel includes: a photosensitive sensor; a light shield layer disposed on a sensing side of the photosensitive sensor and including at least one first opening and at least one second opening, the first opening and the photosensitive sensor are overlapped with each other in a direction perpendicular to a surface of the display panel, so that light running through the first opening is irradiated to the photosensitive sensor; and an optical processing film disposed in a region of the light shield layer close to the second opening and on at least a portion of a surface of the light shield layer away from the photosensitive sensor, and a light reflectivity of the optical processing film is less than a light reflectivity of the light shield layer.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: November 22, 2022
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
    Inventors: Guangdong Wang, Yiming Wang, Zhenyu Wang, Chen Wang
  • Patent number: 11502150
    Abstract: Provided is a display device including a plurality of pixels at least one of which has a first transistor and a light-emitting element. The first transistor includes a gate electrode, a gate insulating film over the gate electrode, an oxide semiconductor film over the gate insulating film, and a first terminal and a second terminal electrically connected to the semiconductor film. The second terminal is electrically connected to the light-emitting element. A region in which the first terminal overlaps with the gate electrode can be smaller than a region in which the second terminal overlaps with the gate electrode.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: November 15, 2022
    Assignee: Japan Display Inc.
    Inventors: Tetsuo Morita, Hiroyuki Kimura, Makoto Shibusawa, Hiroshi Tabatake, Yasuhiro Ogawa
  • Patent number: 11502111
    Abstract: A display apparatus includes a first silicon transistor including a first semiconductor layer including a silicon-based semiconductor and a first gate electrode; a first oxide transistor including a second semiconductor layer and a second gate electrode, the second semiconductor layer including an oxide-based semiconductor; an upper insulating layer on the first and second semiconductor layers; and a first connection electrode on the upper insulating layer, electrically connected to the first semiconductor layer through a first contact hole of the upper insulating layer, and electrically connected to the second semiconductor layer through a second contact hole of the upper insulating layer. The second semiconductor layer includes a channel region, a source region, and a drain region, and a first distance between the channel region of the second semiconductor layer and the first contact hole is about 2 ?m or greater.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: November 15, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sunwoo Lee, Kihyun Kim, Younggil Park, Seulgi Lee, Geunhyuk Choi, Jaebum Han
  • Patent number: 11495695
    Abstract: A semiconductor device with enhanced semiconductor characteristics that is useful for power devices. A semiconductor device, including: an n-type semiconductor layer; an electrode; two or more p-type semiconductors provided between the n-type semiconductor layer and the electrode, the n-type semiconductor layer containing a corundum-structured crystallin oxide semiconductor as a major component, a number of the two or more p-type semiconductor that is equal to or more than three, and the two or more p-type semiconductors that are embedded in the n-type semiconductor layer.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: November 8, 2022
    Assignee: FLOSFIA INC.
    Inventors: Masahiro Sugimoto, Isao Takahashi, Takashi Shinohe, Koji Amazutsumi
  • Patent number: 11495601
    Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a capacitor, an electrode, and an interlayer film. The transistor includes a semiconductor layer, a gate, a source, and a drain; the transistor and the capacitor are placed to be embedded in the interlayer film. Below the semiconductor layer, one of the source and the drain is in contact with the electrode. Above the semiconductor layer, the other of the source and the drain is in contact with one electrode of the capacitor.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: November 8, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takanori Matsuzaki, Ryo Tokumaru, Ryota Hodo
  • Patent number: 11495691
    Abstract: The semiconductor device includes a first conductor and a second conductor; a first insulator to a third insulator; and a first oxide to a third oxide. The first conductor is disposed to be exposed from a top surface of the first insulator. The first oxide is disposed over the first insulator and the first conductor. A first opening reaching the first conductor is provided in the first oxide. The second oxide is disposed over the first oxide. The second oxide comprises a first region, a second region, and a third region positioned between the first region and the second region. The third oxide is disposed over the second oxide. The second insulator is disposed over the third oxide. The second conductor is disposed over the second insulator. The third insulator is disposed to cover the first region and the second region and to be in contact with the top surface of the first insulator.
    Type: Grant
    Filed: May 27, 2019
    Date of Patent: November 8, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshihiko Takeuchi, Naoto Yamade, Yutaka Okazaki, Sachiaki Tezuka, Shunpei Yamazaki
  • Patent number: 11488982
    Abstract: An array substrate and a display panel; the array substrate includes a substrate (6), a gate electrode (2), a gate insulation layer (1), a semiconductor active layer, a first etching barrier layer (4), and a source-drain layer (5); the gate electrode (2) is disposed at the substrate (6); and the gate insulation layer (1) covers the gate electrode (2).
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: November 1, 2022
    Assignee: HKC CORPORATION LIMITED
    Inventor: Beizhou Huang
  • Patent number: 11489076
    Abstract: To improve field-effect mobility and reliability in a transistor including an oxide semiconductor film. A semiconductor device includes a transistor including an oxide semiconductor film. The transistor includes a region where the maximum value of field-effect mobility of the transistor at a gate voltage of higher than 0 V and lower than or equal to 10 V is larger than or equal to 40 and smaller than 150; a region where the threshold voltage is higher than or equal to minus 1 V and lower than or equal to 1 V; and a region where the S value is smaller than 0.3 V/decade.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: November 1, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Kenichi Okazaki, Yukinori Shima, Shinpei Matsuda, Haruyuki Baba, Ryunosuke Honda
  • Patent number: 11489065
    Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween. The second insulator has an opening and a side surface of the second insulator overlaps with a side surface of the first conductor in the opening with the first insulator positioned therebetween. Part of a surface of the second conductor and part of a surface of the third conductor are in contact with the first insulator in the opening. The oxide semiconductor overlaps with the second conductor and the third conductor.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: November 1, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoru Okamoto, Shinya Sasagawa
  • Patent number: 11488981
    Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: November 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Yi Fang Lee, Jaydip Guha, Lars P. Heineck, Kamal M. Karda, Si-Woo Lee, Terrence B. McDaniel, Scott E. Sills, Kevin J. Torek, Sheng-Wei Yang
  • Patent number: 11482626
    Abstract: A semiconductor device with favorable electrical characteristics is provided. A semiconductor device having stable electrical characteristics is provided. The semiconductor device includes a semiconductor layer containing a metal oxide, a first insulating layer, a second insulating layer, a third insulating layer containing a nitride, and a first conductive layer. The first insulating layer includes a projecting first region that overlaps with the semiconductor layer and a second region that does not overlap with the semiconductor layer and is thinner than the first region. The second insulating layer is provided to cover a top surface of the second region, a side surface of the first region, and the semiconductor layer. The first conductive layer is provided over the second insulating layer and a bottom surface of the first conductive layer over the second region includes a portion positioned below a bottom surface of the semiconductor layer.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: October 25, 2022
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Kenichi Okazaki, Masami Jintyou, Takahiro Iguchi, Yukinori Shima
  • Patent number: 11480840
    Abstract: A liquid crystal device includes, on a first base material, pixels and a capacitive element disposed in a light shielding region between the pixels, and the capacitive element includes a first capacitive wiring disposed along the light shielding region, a dielectric layer that covers at least consecutive three surfaces (a surface O, a surface P and a surface Q) of the first capacitive wiring, and a second capacitive wiring that faces at least the consecutive three surfaces of the first capacitive wiring through the dielectric layer.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: October 25, 2022
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Satoshi Ito
  • Patent number: 11476367
    Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: October 18, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Chen Chen, Xiao Wu, Hai Tao Liu, Ming Hua Du, Shouguo Zhang, Yao-Hung Liu, Chin-Fu Lin, Chun-Yuan Wu
  • Patent number: 11476281
    Abstract: An electronic device comprises a panel, a driving circuit configured to drive the panel, and a transistor disposed in the panel. The transistor includes a first insulation film on a substrate, an active layer disposed on the first insulation film, a second insulation film disposed on the active layer and the first insulation film to cover the active layer, the second insulation film having a thickness smaller than a thickness of the first insulation film, a source electrode disposed on the second insulation film and spaced apart from the active layer by the second insulation film, the source electrode overlapping an end of the active layer, and a drain electrode disposed on the second insulation film and spaced apart from the active layer by the second insulation film, the drain electrode overlapping another end of the active layer.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: October 18, 2022
    Assignee: LG Display Co., Ltd.
    Inventors: SeHee Park, JungSeok Seo, Jaeyoon Park, PilSang Yun, Jiyong Noh
  • Patent number: 11468844
    Abstract: A display device may include a first pixel coupled to an emission control line, and an emission control stage for selectively coupling the emission control line to a first or second supply voltage line. The emission control stage may include: a first emission control transistor including a first electrode coupled to the first supply voltage line, a second electrode coupled to the emission control line, and a main gate electrode coupled to a first node; a second emission control transistor including a first electrode coupled to the emission control line, a second electrode coupled to the second supply voltage line, and a main gate electrode coupled to a second node; and a third emission control transistor including a first electrode coupled to the first supply voltage line, a second electrode coupled to the first node, a main gate electrode coupled to the second node, and a sub-gate electrode.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: October 11, 2022
    Inventors: Seong Min Wang, Young In Hwang, Jin Woo Park, Yong Ho Yang
  • Patent number: 11468838
    Abstract: An organic light emitting display device includes a plurality of pixels. Each of the pixels includes an organic light emitting diode, first to third transistors, a storage capacitor, and a first capacitor. The second transistor includes a gate electrode receiving a first scan signal, a first electrode receiving a data signal, and a second electrode connected to a first electrode of the first transistor. The third transistor includes a gate electrode receiving a second scan signal, a first electrode connected to a second electrode of the first transistor, and a second electrode connected to a gate electrode of the first transistor. The storage capacitor includes a first electrode receiving a power voltage and a second electrode connected to the gate electrode of the first transistor. The first capacitor includes a first electrode connected to the gate electrode of the third transistor and a second electrode receiving the power voltage.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: October 11, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Dongwoo Kim, Sunghwan Kim, Kyoungju Shin, Cheol-Gon Lee, Sang-Uk Lim
  • Patent number: 11469254
    Abstract: An array substrate, a method of manufacturing an array substrate, a display panel, and an electronic device are provided. The array substrate includes a display area and a peripheral area; the display area includes a pixel region, the pixel region includes a first thin film transistor, and the first thin film transistor includes a first active layer; the peripheral area includes a second thin film transistor, and the second thin film transistor includes a second active layer; and the first active layer includes a material of oxide semiconductor, and the second active layer includes a material of poly-silicon semiconductor.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: October 11, 2022
    Assignees: Ordos Yuansheng Optoelectronics Co., Ltd., Beijing BOE Technology Development Co., Ltd.
    Inventors: Peng Liu, Fuqiang Li, Jun Fan, Bailing Liu, Jianjun Zhang, Yusheng Liu, Mei Li
  • Patent number: 11468832
    Abstract: An array substrate includes a base substrate, a pixel circuit, a flexible substrate, a lead structure, a control circuit and a planarization layer. The flexible substrate includes a first substrate portion and a second substrate portion, and the lead structure includes a first lead portion and a second lead portion. The pixel circuit, the first lead portion and the first substrate portion are all arranged on a first side of the base substrate, the control circuit, the second lead portion and the second substrate portion are all arranged on a second side of the base substrate, and the second side is opposite to the first side.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: October 11, 2022
    Assignee: Beijing BOE Technology Development Co., Ltd.
    Inventors: Xiaoyan Zhu, Hua Huang, Guangcai Yuan, Xue Dong
  • Patent number: 11455521
    Abstract: A neuromorphic semiconductor device includes a copper-based intercalation channel disposed on an insulative layer, a source contact and a drain contact of a substrate. A copper-based electrolyte layer is disposed on the copper-based intercalation channel and a copper-based gate electrode is disposed on the copper-based electrolyte layer.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: September 27, 2022
    Assignee: International Business Machines Corporation
    Inventors: Teodor K. Todorov, Douglas M. Bishop, Jianshi Tang, John Rozen
  • Patent number: 11455955
    Abstract: A display device may include a substrate, an organic light emitting element on the substrate, a pixel circuit between the substrate and the organic light emitting element, electrically connected to the organic light emitting element, and including a first transistor and a second transistor, a first metal layer between the substrate and the pixel circuit, overlapping the first transistor, and configured to receive a first voltage, and a second metal layer between the substrate and the pixel circuit, overlapping the second transistor, and configured to receive a second voltage different from the first voltage.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: September 27, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Myounggeun Cha, Sanggun Choi, Jiyeong Shin, Yongsu Lee
  • Patent number: 11450694
    Abstract: A highly reliable display apparatus is provided. In an EL display apparatus including a specific pixel having a function of adding data, a storage node is provided in the pixel, and first data can be held in the storage node. In the pixel, second data is added to the first data through capacitive coupling, whereby third data can be generated. A light-emitting device operates in accordance with the third data. In the pixel, a light-emitting device that requires a high voltage for light emission or a light-emitting device to which application of a high voltage is preferred is provided.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: September 20, 2022
    Inventors: Shunpei Yamazaki, Koji Kusunoki, Shingo Eguchi
  • Patent number: 11450691
    Abstract: To improve field-effect mobility and reliability of a transistor including an oxide semiconductor film. A semiconductor device includes an oxide semiconductor film, a gate electrode, an insulating film over the gate electrode, the oxide semiconductor film over the insulating film, and a pair of electrodes over the oxide semiconductor film. The oxide semiconductor film includes a first oxide semiconductor film and a second oxide semiconductor film over the first oxide semiconductor film. The first oxide semiconductor film and the second oxide semiconductor film, include the same element. The first oxide semiconductor film includes a region having lower crystallinity than the second oxide semiconductor film.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: September 20, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kenichi Okazaki, Daisuke Kurosaki, Yasutaka Nakazawa
  • Patent number: 11450773
    Abstract: A thin film transistor is provided. The thin film transistor includes a base substrate; a first target layer on the base substrate; a first insulating layer on a side of the first target layer away from the base substrate; an intermediate layer on a side of the first insulating layer away from the first target layer; a second insulating layer on a side of the intermediate layer away from the first insulating layer; and a second target layer on a side of the second insulating layer away from the intermediate layer. The first target layer is electrically connected to the second target layer. The intermediate layer is one of a gate electrode and an active layer, and the first target layer and the second target layer together constitute another one of the gate electrode and the active layer.
    Type: Grant
    Filed: May 5, 2019
    Date of Patent: September 20, 2022
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., Beijing BOE Technology Development Co., Ltd.
    Inventors: Shun Zhang, Bo Cheng, Kai Zhang
  • Patent number: 11450371
    Abstract: An object is to shorten the time for rewriting data in memory cells. A memory module includes a first memory cell, a second memory cell, a selection transistor, and a wiring WBL1. The first memory cell includes a first memory node. The second memory cell includes a second memory node. One end of the first memory cell is electrically connected to the wiring WBL1 through the selection transistor. The other end of the first memory cell is electrically connected to one end of the second memory cell. The other end of the second memory cell is electrically connected to the wiring WBL1. When the selection transistor is on, data in the first memory node is rewritten by a signal supplied through the selection transistor to the wiring WBL1. When the selection transistor is off, data in the first memory node is rewritten by a signal supplied through the second memory node to the wiring WBL1.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: September 20, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Takahiro Fukutome
  • Patent number: 11437405
    Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a first transistor, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor may be a p-type transistor including a channel in a substrate, a first source electrode, and a first drain electrode. A first metal contact may be coupled to the first source electrode, while a second metal contact may be coupled to the first drain electrode. The insulator layer may be next to the first metal contact, and next to the second metal contact. The second transistor may include a second source electrode, and a second drain electrode. The second source electrode may be coupled to the first metal contact, or the second drain electrode may be coupled to the second metal contact. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: September 6, 2022
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Patrick Morrow, Aaron Lilak, Willy Rachmady, Anh Phan, Ehren Mannebach, Hui Jae Yoo, Abhishek Sharma, Van H. Le, Cheng-Ying Huang
  • Patent number: 11437523
    Abstract: In a semiconductor device including a transistor including an oxide semiconductor film and a protective film over the transistor, an oxide insulating film containing oxygen in excess of the stoichiometric composition is formed as the protective film under the following conditions: a substrate placed in a treatment chamber evacuated to a vacuum level is held at a temperature higher than or equal to 180° C. and lower than or equal to 260° C.; a source gas is introduced into the treatment chamber so that the pressure in the treatment chamber is set to be higher than or equal to 100 Pa and lower than or equal to 250 Pa; and a high-frequency power higher than or equal to 0.17 W/cm2 and lower than or equal to 0.5 W/cm2 is supplied to an electrode provided in the treatment chamber.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: September 6, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kenichi Okazaki, Toshinari Sasaki, Shuhei Yokoyama, Takashi Hamochi
  • Patent number: 11437524
    Abstract: The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. One embodiment of the present invention is a semiconductor device which includes a gate electrode, an insulating film over the gate electrode, an oxide semiconductor film over the insulating film, and a pair of electrodes over the oxide semiconductor film. The oxide semiconductor film includes a first oxide semiconductor film, a second oxide semiconductor film over the first oxide semiconductor film, and a third oxide semiconductor film over the second oxide semiconductor film. The first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film include the same element. The second oxide semiconductor film includes a region having lower crystallinity than one or both of the first oxide semiconductor film and the third oxide semiconductor film.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: September 6, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Kenichi Okazaki, Yasutaka Nakazawa
  • Patent number: 11437500
    Abstract: The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: September 6, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Shinya Sasagawa, Motomu Kurata, Masashi Tsubuku
  • Patent number: 11430846
    Abstract: A work module includes a substrate and a transistor unit disposed on the substrate. The transistor unit includes an active layer, a source electrode, and a drain electrode. The active layer has a thickness, a first surface, and a second surface. The first surface is parallel with the second surface. The source electrode and the drain electrode at least partially overlap the active layer. The second surface contacts the source electrode and the drain electrode. A first zinc concentration exists within a first range from the second surface to a site located away from the second surface by a tenth of the thickness. A second zinc concentration exists within a second range from a site located away from the second surface by nine tenths of the thickness to the first surface. The first zinc concentration is higher than the second zinc concentration.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: August 30, 2022
    Assignee: InnoLux Corporation
    Inventors: Tsang-Lung Chen, Jhe-Ciou Jhu, Jian-Yu Wang, Chia-Hao Hsieh
  • Patent number: 11430898
    Abstract: Methods and apparatus for forming a thin film transistor (TFT) having a metal oxide layer. The method may include forming an amorphous metal oxide layer and treating the metal oxide layer with a silicon containing gas or plasma including Si4+ ions. The silicon treatment of the metal oxide layer helps fill the oxygen vacancies in the metal oxide channel layer, leading to a more stable TFT and preventing a negative threshold voltage in the TFT.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: August 30, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jose-Ignacio Del-Agua-Borniquel, Hendrik F. W. Dekkers, Hans Van Meer, Jae Young Lee
  • Patent number: 11430894
    Abstract: Provided is a semiconductor device in which deterioration of electric characteristics which becomes more noticeable as the semiconductor device is miniaturized can be suppressed. The semiconductor device includes a first oxide film, an oxide semiconductor film over the first oxide film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a second oxide film over the oxide semiconductor film, the source electrode, and the drain electrode, a gate insulating film over the second oxide film, and a gate electrode in contact with the gate insulating film. A top end portion of the oxide semiconductor film is curved when seen in a channel width direction.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: August 30, 2022
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kazuya Hanaoka, Daisuke Matsubayashi, Yoshiyuki Kobayashi, Shunpei Yamazaki, Shinpei Matsuda
  • Patent number: 11430856
    Abstract: In a bending portion, a slit that exposes a resin substrate is formed in at least one inorganic insulating film, a first flattening film is provided so as to fill in the slit, each of a plurality of wiring lines is provided on the first flattening film and both end portions of the inorganic insulating film, the slit being formed at both end portions, a second flattening film is provided on each of the wiring lines, a plurality of conductive layers each having an island shape are provided on the second flattening film, and each of the wiring lines and a corresponding conductive layer are electrically connected via contact holes formed in the second flattening film.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: August 30, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Takao Saitoh, Masahiko Miwa, Yohsuke Kanzaki, Seiji Kaneko, Yi Sun, Masaki Yamanaka
  • Patent number: 11430897
    Abstract: A semiconductor device with favorable electrical characteristics is provided. A semiconductor device having stable electrical characteristics is provided. A highly reliable semiconductor device is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, a second insulating layer, and a conductive layer. The first insulating layer is in contact with part of the top surface of the semiconductor layer, the conductive layer is positioned over the first insulating layer, and the second insulating layer is positioned over the semiconductor layer. The semiconductor layer contains a metal oxide and includes a first region overlapping with the conductive layer and a second region not overlapping with the conductive layer. The second region is in contact with the second insulating layer. The second insulating layer contains oxygen and a first element. The first element is one or more of phosphorus, boron, magnesium, aluminum, and silicon.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: August 30, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Yasutaka Nakazawa
  • Patent number: 11430840
    Abstract: An organic light-emitting diode display includes an auxiliary connection line on a substrate; an auxiliary cathode on and connected to the auxiliary connection line; a passivation layer covering the auxiliary cathode; an overcoat layer on the passivation layer; a connection terminal connected to the auxiliary cathode on the overcoat layer; an undercut opening on the overcoat layer exposing a portion of the auxiliary cathode, an under area being in the undercut opening and under one side of the connection terminal; a bank having a size larger than the undercut opening and exposing the entire undercut opening; an organic emission layer on a region other than the under area in the undercut opening exposing the portion of the auxiliary cathode; and a cathode directly connected to the exposed portion of the auxiliary cathode on which the organic emission layer is not formed in the under area of the undercut opening.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: August 30, 2022
    Assignee: LG Display Co., Ltd.
    Inventor: Imkuk Kang
  • Patent number: 11430817
    Abstract: A novel semiconductor device in which a metal film containing copper (Cu) is used for a wiring, a signal line, or the like in a transistor including an oxide semiconductor film is provided. The semiconductor device includes an oxide semiconductor film having conductivity on an insulating surface and a conductive film in contact with the oxide semiconductor film having conductivity. The conductive film includes a Cu—X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti).
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: August 30, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Yukinori Shima, Masami Jintyou, Takashi Hamochi, Satoshi Higano, Yasuharu Hosaka, Toshimitsu Obonai
  • Patent number: 11430886
    Abstract: A semiconductor device of an embodiment includes a substrate, a first electrode, a second electrode, the first electrode provided between the substrate and the second electrode, the oxide semiconductor layer in contact with the first electrode, an oxide semiconductor layer between the first electrode and the second electrode, the oxide semiconductor layer contains Zn and at least one first element selected from In, Ga, Si, Al, and Sn; a conductive layer between the oxide semiconductor layer and the second electrode, the conductive layer in contact with the second electrode, the conductive layer contains O and at least one second element selected from the group consisting of In, Ga, Si, Al, Sn, Zn, and Ti, a gate electrode; and a gate insulating layer between the oxide semiconductor layer and the gate electrode.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: August 30, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Yuta Sato, Tomomasa Ueda, Nobuyoshi Saito, Keiji Ikeda
  • Patent number: 11430847
    Abstract: A method of manufacturing a semiconductor device. A pre first semiconductor pattern having a crystalline semiconductor material is formed on a base substrate. A pre first insulation layer is formed on the pre first semiconductor pattern. A first semiconductor pattern is formed by defining a channel region in the pre first semiconductor pattern. A pre protection layer is formed on the pre first insulation layer. A pre second semiconductor pattern including an oxide semiconductor material is formed on the pre protection layer. A pre second insulation layer is formed on the pre second semiconductor pattern. The pre second insulation layer is patterned using an etching gas such that at least a portion of the pre second semiconductor pattern is exposed. A second semiconductor pattern is formed by defining a channel region in the pre second semiconductor pattern.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: August 30, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kyoungseok Son, Jaybum Kim, Eoksu Kim, Junhyung Lim, Jihun Lim
  • Patent number: 11430895
    Abstract: A transistor comprises a lower contact structure, a channel structure, a dielectric fill structure, and an upper contact structure. The lower contact structure comprises a first oxide semiconductive material. The channel structure contacts the lower contact structure and comprises a second oxide semiconductive material having a smaller atomic concentration of one or more metals than the first oxide semiconductive material. The dielectric fill structure contacts an inner side surface of the channel structure and has a recessed upper surface relative to the channel structure. The upper contact structure comprises a third oxide semiconductive material having a greater atomic concentration of the one or more metals than the channel structure. The upper contact structure comprises a first portion contacting the upper surface of the dielectric fill structure and the inner side surface of the channel structure, and a second portion contacting the upper surface of the channel structure.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: August 30, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Guangyu Huang, Haitao Liu, Akira Goda
  • Patent number: 11423839
    Abstract: A display device may include a substrate, an organic light emitting element on the substrate, a pixel circuit between the substrate and the organic light emitting element, electrically connected to the organic light emitting element, and including a first transistor and a second transistor, a first metal layer between the substrate and the pixel circuit, overlapping the first transistor, and configured to receive a first voltage, and a second metal layer between the substrate and the pixel circuit, overlapping the second transistor, and configured to receive a second voltage different from the first voltage.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: August 23, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Myounggeun Cha, Sanggun Choi, Jiyeong Shin, Yongsu Lee
  • Patent number: 11424334
    Abstract: A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with stable electrical characteristics is provided. The semiconductor device includes a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a semiconductor layer, and a first conductive layer. The second insulating layer is positioned over the first insulating layer and the island-shaped semiconductor layer is positioned over the second insulating layer. The second insulating layer has an island shape having an end portion outside a region overlapping with the semiconductor layer. The fourth insulating layer covers the second insulating layer, the semiconductor layer, the third insulating layer, and the first conductive layer, is in contact with part of a top surface of the semiconductor layer, and is in contact with the first insulating layer outside the end portion of the second insulating layer.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: August 23, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masami Jintyou, Takahiro Iguchi, Yukinori Shima, Kenichi Okazaki
  • Patent number: 11424307
    Abstract: The present disclosure is related to an organic light-emitting diode apparatus. The organic light-emitting diode apparatus may include a substrate and a plurality of pixels on a first side of the substrate. Each of the plurality of pixels may include a display region and a non-display region. The non-display region may be provided with a control circuit and a first color film, and the first color film may be between the control circuit and the substrate.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: August 23, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhen Song, Guoying Wang
  • Patent number: 11423855
    Abstract: A novel display panel that is highly convenient or reliable is provided. A pixel circuit includes a first switch, a node, a capacitor, and a second switch. The first switch includes a first terminal to which a first signal is supplied and a second terminal electrically connected to the node. The capacitor includes a first terminal electrically connected to the node and a second terminal electrically connected to the second switch. The second switch includes a first terminal to which a second signal is supplied and a second terminal electrically connected to the second terminal of the capacitor. In addition, the second switch has a function of changing from a non-conducting state to a conducting state when the first switch is in a non-conducting state and a function of changing from a conducting state to a non-conducting state when the first switch is in a non-conducting state. The display element performs display on the basis of a potential of the node.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: August 23, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kouhei Toyotaka, Kei Takahashi, Koji Kusunoki, Kazunori Watanabe, Susumu Kawashima
  • Patent number: 11424369
    Abstract: A semiconductor device having a large on-state current and high reliability is provided. The semiconductor device includes a first insulator, a first oxide over the first insulator, a second oxide over the first oxide, a third oxide and a fourth oxide over the second oxide, a first conductor over the third oxide, a second conductor over the fourth oxide, a fifth oxide over the second oxide, a second insulator over the fifth oxide, and a third conductor over the second insulator. The fifth oxide is in contact with a top surface of the second oxide, a side surface of the first conductor, a side surface of the second conductor, a side surface of the third oxide, and a side surface of the fourth oxide. The second oxide contains In, an element M, and Zn. The first oxide and the fifth oxide each contain at least one of constituent elements included in the second oxide. The third oxide and the fourth oxide each contain the element M.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: August 23, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Haruyuki Baba, Naoki Okuno, Yoshihiro Komatsu, Toshikazu Ohno
  • Patent number: 11417769
    Abstract: Provided are a thin film transistor and method for manufacturing the same, array substrate, display panel and display device. The thin film transistor includes: a gate pattern, a gate insulating layer, an active layer pattern, a source pattern and a drain pattern sequentially stacked. At least one of a surface of the source pattern facing the gate insulating layer, a surface of the drain pattern facing the gate insulating layer, and a surface of the gate pattern facing the gate insulating layer is a target surface which can diffusely reflect lights entering the target surface, to prevent part of the lights from entering the active layer pattern. The display device solves the problem of volt-ampere characteristic curve of the active layer pattern being deflected and a normal operation of the thin film transistor being affected, thereby weakening the influence of lights on the normal operation of the thin film transistor.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: August 16, 2022
    Assignees: BOE Technology Group Co., LTD., Hefei Xinsheng Optoelectronics Technology Co., LTD
    Inventors: Binbin Cao, Chao Wang, Lin Sun
  • Patent number: 11411121
    Abstract: An object is to stabilize electric characteristics of a semiconductor device including an oxide semiconductor to increase reliability. The semiconductor device includes an insulating film; a first metal oxide film on and in contact with the insulating film; an oxide semiconductor film partly in contact with the first metal oxide film; source and drain electrodes electrically connected to the oxide semiconductor film; a second metal oxide film partly in contact with the oxide semiconductor film; a gate insulating film on and in contact with the second metal oxide film; and a gate electrode over the gate insulating film.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: August 9, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki