Semiconductor Is An Oxide Of A Metal (e.g., Cuo, Zno) Or Copper Sulfide Patents (Class 257/43)
  • Patent number: 10439073
    Abstract: A highly reliable semiconductor device exhibiting stable electrical characteristics is provided. Further, a highly reliable semiconductor device is provided. Oxide semiconductor films are stacked so that the conduction band has a well-shaped structure. Specifically, a transistor having a multi-layer structure is manufactured in which a second oxide semiconductor film having a crystalline structure is stacked over a first oxide semiconductor film, and at least a third oxide semiconductor film is provided over the second oxide semiconductor film. When a buried channel is formed in the transistor, few oxygen vacancies are generated and the reliability of the transistor is improved.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: October 8, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10439010
    Abstract: The purpose of the present invention is to form both LTPS TFT and semiconductor TFT in a same substrate. The feature of the display device to realize the above purpose is that: a display device having a display area containing a pixel comprising: the pixel includes a first TFT having an oxide semiconductor, a gate insulating film is formed on the oxide semiconductor, a first gate electrode is formed on the gate insulating film, a first source/drain electrode formed by a metal or an alloy contacts a source or a drain of the semiconductor the first gate electrode and the first source/drain electrode are formed by the same material.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: October 8, 2019
    Assignee: Japan Display Inc.
    Inventor: Akihiro Hanada
  • Patent number: 10439070
    Abstract: A thin-film transistor (TFT) and a manufacturing method thereof. The manufacturing method for the TFT includes: depositing metal film layers on a substrate by a direct current (DC) sputtering method; and forming a metal oxide film layer or metal oxide film layers by completely oxidizing or partially oxidizing the metal film layers. The TFT includes a gate electrode layer and a gate insulating layer which are tightly integrated.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: October 8, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., SOUTH CHINA UNIVERSITY OF TECHNOLOGY
    Inventors: Liangchen Yan, Guangcai Yuan, Xiaoguang Xu, Lei Wang, Junbiao Peng, Linfeng Lan
  • Patent number: 10438815
    Abstract: In a semiconductor device including an oxide semiconductor, a change in electrical characteristics is inhibited and reliability is improved. The semiconductor device is manufactured by a method including first to fourth steps. The first step includes a step of forming an oxide semiconductor film, the second step includes a step of forming an oxide insulating film over the oxide semiconductor film, the third step includes a step of forming a protective film over the oxide insulating film, and the fourth step includes a step of adding oxygen to the oxide insulating film through the protective film. In the first step, the oxide semiconductor film is formed under a condition in which an oxygen vacancy is formed. The oxygen from the oxide insulating film fills the oxygen vacancy after the fourth step.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: October 8, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Daisuke Kurosaki, Yukinori Shima, Takuya Handa
  • Patent number: 10436746
    Abstract: Electrochemical and bio sensors using metal oxide semiconductors and method of making the same are described herein. The sensor includes a gate electrode, a dielectric layer over the gate electrode, a channel layer over the dielectric layer, and source and drain electrodes formed on the channel layer to provide a field effect transistor structure. The channel layer is a metal oxide semiconductor film that has a substantially uniform thickness of at least 3 nm thick and less than 10 nm thick. The metal oxide semiconductor film is functionalized with molecules attached thereto that are open to make contact with a fluid for detection of at least one component or at least one physical or chemical property of the fluid.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: October 8, 2019
    Assignee: The Regents of the University of California
    Inventors: Yang Yang, You Seung Rim, Jonathan Yang
  • Patent number: 10431601
    Abstract: A method for manufacturing an array substrate, and an array substrate, a display panel and a display device are provided. The method may include: forming, on one side of a substrate, a gate electrode layer, a gate insulation layer and a semiconductor layer, wherein the gate electrode layer has a same pattern as the semiconductor layer; forming an etching stop layer on the semiconductor layer; forming a first, second hole and third through holes by patterning the etching stop layer; forming a source electrode layer and a drain electrode layer on the etching stop layer, wherein the source electrode layer is electrically connected with the semiconductor layer via the first through hole, and the drain electrode layer is electrically connected with the semiconductor layer via the second through hole; forming an active layer by etching the semiconductor layer at the location corresponding to the third through hole.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: October 1, 2019
    Assignees: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD., TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Chuanzhi Xu, Zhengfang Xie, Xiongping Li, Xiaoyang Tong
  • Patent number: 10431600
    Abstract: A method for manufacturing a highly reliable semiconductor device is provided. The method includes the steps of: forming an oxide semiconductor film at a first temperature; processing the oxide semiconductor film into an island shape; not performing a process at a temperature higher than the first temperature, but depositing a material to be source and drain electrodes by a sputtering method; processing the material to form the source and drain electrodes; forming a protective insulating film, and then forming a first barrier film; adding excess oxygen or oxygen radicals to the protective insulating film through the first barrier film; performing heat treatment at a second temperature lower than 400° C. to diffuse the excess oxygen or oxygen radicals into the oxide semiconductor film; and removing part of the first barrier film and part of the protective insulating film by wet etching, and then forming a second barrier film.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: October 1, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Kenichi Okazaki, Daisuke Kurosaki, Masami Jintyou, Shunpei Yamazaki
  • Patent number: 10431704
    Abstract: This invention relates to a method for producing a photodetector based on the deposition of precursor system having a liquid phase. The photodetectors are characterized by a certain group of semiconductor materials which can be used as the absorber in solar-blind UV detectors. A facile route for the formation of thin layers of such absorber materials is disclosed.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: October 1, 2019
    Assignee: MERCK PATENT GMBH
    Inventors: Rebekah Hooker, Deepak Ranjan Deshmukh, Pawel Miskiewicz, Andreas Klyszcz, Klaus Bonrad, Thomas Albrecht
  • Patent number: 10431603
    Abstract: A semiconductor device includes a substrate, a first wiring line, a semiconductor film, a second wiring line, and an insulating film. The substrate includes first, second, and third regions provided adjacently in this order in a predetermined direction. The first wiring line is provided on the substrate and provided in each of the first, second, and third regions. The semiconductor film has a low-resistance region in at least a portion thereof. The semiconductor film is provided between the first wiring line and the substrate in the first region, and is in contact with the first wiring line in the second region. The second wiring line is provided at a position closer to the substrate than the semiconductor film, and is in contact with the first wiring line in the third region. The insulating film is provided between the first wiring line and the semiconductor film in the first region.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: October 1, 2019
    Assignee: JOLED INC.
    Inventors: Hiroshi Hayashi, Tokuaki Kuniyoshi, Yasuhiro Terai, Eri Matsuo, Toshiaki Yoshitani, Naoki Asano
  • Patent number: 10424262
    Abstract: A gate driving circuit includes a plurality of stages. A k-th stage from among the plurality of stages, the k-th stage includes a first input circuit to receive a (k?1)th gate signal from a (k?1)th stage and to precharge a first node, a second input circuit to receive a (k+2)th gate signal from a (k+2)th stage to transmit the received (k+2)th gate signal to a second node, an output circuit to output a first clock signal as a k-th gate signal in response to a signal of the first node, a discharge circuit configured to discharge the first node through the k-th gate signal in response to a signal of the second node, a first transfer circuit to transfer a second clock signal to the first node, and a second transfer circuit to transfer the first clock signal to the second node.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: September 24, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Masami Igawa, Noboru Takeuchi
  • Patent number: 10424676
    Abstract: A minute transistor is provided. A transistor with small parasitic capacitance is provided. A transistor with high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor and a second insulator embedded in a first insulator, a second conductor and a third conductor. Edges of the second conductor and the third conductor facing each other each has a taper angle of 30 degree or more and 90 degree or less.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: September 24, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Motomu Kurata, Satoru Okamoto, Shunpei Yamazaki
  • Patent number: 10424671
    Abstract: A novel semiconductor device or memory device is provided. Alternatively, a semiconductor device or memory device in which storage capacity per unit area is large is provided. The semiconductor device includes a sense amplifier provided to a semiconductor substrate and a memory cell provided over the sense amplifier. The sense amplifier includes a first transistor. The memory cell includes a capacitor over the semiconductor substrate, a second transistor provided over the capacitor, a conductor, and a groove portion. The capacitor includes a first electrode and a second electrode. The first electrode is formed along the groove portion. The second electrode has a region facing the first electrode in the groove portion. The second transistor includes an oxide semiconductor. One of a source and a drain of the second transistor is electrically connected to the second electrode through the conductor.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: September 24, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kiyoshi Kato, Hidekazu Miyairi, Akihisa Shimomura, Atsushi Hirose
  • Patent number: 10424673
    Abstract: High field-effect mobility is provided for a semiconductor device including an oxide semiconductor. Further, a highly reliable semiconductor device including the transistor is provided. In a transistor in which a stack of oxide semiconductor layers is provided over a gate electrode layer with a gate insulating layer provided therebetween, an oxide semiconductor layer functioning as a current path (channel) of the transistor and containing an n-type impurity is sandwiched between oxide semiconductor layers having lower conductivity than the oxide semiconductor layer. In the oxide semiconductor layer functioning as the channel, a region on the gate insulating layer side contains the n-type impurity at a higher concentration than a region on the back channel side. With such a structure, the channel can be separated from the interface between the oxide semiconductor stack and the insulating layer in contact with the oxide semiconductor stack, so that a buried channel can be formed.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: September 24, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10424675
    Abstract: A semiconductor device includes an oxide semiconductor layer above an insulating surface, a source electrode in contact with a side surface of the oxide semiconductor layer, a drain electrode in contact with a side surface of the oxide semiconductor layer, a gate insulating film above the oxide semiconductor layer, the source electrode, and the drain electrode, and, a gate electrode overlapping with the oxide semiconductor layer interposed by the gate insulating film. The gate electrode is arranged above and outside of the source electrode and the drain electrode.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: September 24, 2019
    Assignee: Japan Display Inc.
    Inventor: Hiroki Ohara
  • Patent number: 10418467
    Abstract: It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity. In a method for manufacturing a semiconductor device which includes a thin film transistor where a semiconductor layer having a channel formation region, a source region, and a drain region are formed using an oxide semiconductor layer, heat treatment (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor layer and reduce impurities such as moisture. Moreover, the oxide semiconductor layer subjected to the heat treatment is slowly cooled under an oxygen atmosphere.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: September 17, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshinari Sasaki, Junichiro Sakata, Hiroki Ohara, Shunpei Yamazaki
  • Patent number: 10418466
    Abstract: An object is to provide a high reliability thin film transistor using an oxide semiconductor layer which has stable electric characteristics. In the thin film transistor in which an oxide semiconductor layer is used, the amount of change in threshold voltage of the thin film transistor before and after a BT test is made to be 2 V or less, preferably 1.5 V or less, more preferably 1 V or less, whereby the semiconductor device which has high reliability and stable electric characteristics can be manufactured. In particular, in a display device which is one embodiment of the semiconductor device, a malfunction such as display unevenness due to change in threshold voltage can be reduced.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: September 17, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takahiro Tsuji, Kunihiko Suzuki
  • Patent number: 10418489
    Abstract: Embodiments of the present disclosure provide a thin film transistor and a method of manufacturing the same, and a display device. In an embodiment, the thin film transistor includes a gate, a gate insulation layer, an active layer, a source electrode and a drain electrode, and further includes a heat source disposed above or below the active layer and configured to heat a channel region of the active layer.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: September 17, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Shan Gao, Tingliang Liu, Yang Wang, Wei Guo
  • Patent number: 10411003
    Abstract: A transistor includes a first insulator over a substrate; a first oxide thereover; a second oxide in contact with at least part of the top surface of the first oxide; a first conductor and a second conductor each in contact with at least part of the top surface of the second oxide; a third oxide that is over the first conductor and the second conductor and is in contact with at least part of the top surface of the second oxide; a second insulator thereover; a third conductor which is over the second insulator and at least part of which overlaps with a region between the first conductor and the second conductor; and a third insulator which is over the third conductor and at least part of which is in contact with the top surface of the first insulator. The thickness of a region of the first insulator that is in contact with the third insulator is less than the thickness of a region of the first insulator that is in contact with the first oxide.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: September 10, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Naoki Okuno, Kosei Nei, Hiroaki Honda, Naoto Yamade, Hiroshi Fujiki
  • Patent number: 10411136
    Abstract: A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack. The third oxide semiconductor layer includes a first layer in contact with the stack and a second layer over the first layer. The first layer includes a microcrystalline layer, and the second layer includes a crystalline layer in which c-axes are aligned in a direction perpendicular to a surface of the first layer.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: September 10, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura, Hideomi Suzawa
  • Patent number: 10403651
    Abstract: An array substrate, a method for fabricating the same and a display device are disclosed. The array substrate includes: a gate electrode of a TFT and a gate insulation layer sequentially formed on a base substrate; a semiconductor active layer, an etch stop layer and a source electrode and a drain electrode of the TFT sequentially formed on a part of the gate insulation layer that corresponds to the gate electrode of the TFT, the source and drain electrodes of the TFT are respectively in contact with the semiconductor active layer by way of via holes. The array substrate further includes: a first insulation layer formed between the gate electrode of the TFT and the gate insulation layer and the gate electrode is in contact with the gate insulation layer at a channel region of the TFT between the source electrode and the drain electrode of the TFT.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: September 3, 2019
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Heecheol Kim, Youngsuk Song, Seongyeol Yoo, Seungjin Choi
  • Patent number: 10403700
    Abstract: A display device includes a driving transistor and an organic EL element. The driving transistor includes an oxide semiconductor layer; a first gate electrode that region overlapping the oxide semiconductor layer; a first insulting layer between the first gate electrode and the oxide semiconductor layer; a second gate electrode that includes a region overlapping the oxide semiconductor layer and the first gate electrode; a second insulating layer between the second gate electrode and the oxide semiconductor layer; and a first and a second transparent conductive layer that are provided between the oxide semiconductor layer and the first insulating layer and each include a region contacting the oxide semiconductor layer. The organic EL element includes a first electrode; a second electrode; a light emitting layer between the first electrode and the second electrode; and an electron transfer layer between the light emitting layer and the first electrode.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: September 3, 2019
    Assignee: MIKUNI ELECTRON CORPORATION
    Inventor: Sakae Tanaka
  • Patent number: 10403852
    Abstract: A display apparatus includes a substrate having a display area and a peripheral area outside the display area, a dam in the peripheral area, a first inorganic layer located in both the display area and the peripheral area and covering the dam, an upper surface of the first inorganic layer being nonplanar, and a roughness of the upper surface at a first part of the first inorganic layer outside the dam being greater than a roughness of the upper surface near a center of the display area, an organic layer covering the first inorganic layer in the display area and a portion of the peripheral area, and a second inorganic layer located in both the display area and the peripheral area and covering the dam and the organic layer.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: September 3, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Changmok Kim, Jaeho Lee
  • Patent number: 10403763
    Abstract: It is an object to provide an oxide semiconductor which is suitable for use in a semiconductor device. Alternatively, it is another object to provide a semiconductor device using the oxide semiconductor. Provided is a semiconductor device including an In—Ga—Zn—O based oxide semiconductor layer in a channel formation region of a transistor. In the semiconductor device, the In—Ga—Zn—O based oxide semiconductor layer has a structure in which crystal grains represented by InGaO3(ZnO)m (m=1) are included in an amorphous structure represented by InGaO3(ZnO)m (m>0).
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: September 3, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Junichiro Sakata, Takuya Hirohashi, Masahiro Takahashi, Hideyuki Kishida, Akiharu Miyanaga
  • Patent number: 10396211
    Abstract: A microelectronic device having a functional metal oxide channel may be fabricated on a microelectronic substrate that can be utilized in very large scale integration, such as a silicon substrate, by forming a buffer transition layer between the microelectronic substrate and the functional metal oxide channel. In one embodiment, the microelectronic device may be a microelectronic transistor with a source structure and a drain structure formed on the buffer transition layer, wherein the source structure and the drain structure abut opposing sides of the functional metal oxide channel and a gate dielectric is disposed between a gate electrode and the functional metal oxide channel. In another embodiment, the microelectronic device may be a two-terminal microelectronic device.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Elijah V. Karpov, Prashant Majhi, Roza Kotlyar, Niloy Mukherjee, Charles C. Kuo, Uday Shah, Ravi Pillarisetty, Robert S. Chau
  • Patent number: 10396187
    Abstract: A semiconductor device including a first oxide insulating layer, a barrier layer above the first oxide insulating layer, the barrier layer including an opening, a second oxide insulating layer above the first oxide insulating layer at a position overlapping the opening, an oxide semiconductor layer facing the first oxide insulating layer interposed by the second oxide insulating layer at a position overlapping the opening, a gate electrode facing the oxide semiconductor layer at side opposite to the first oxide insulating layer with respect to the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode. A contained amount of oxygen in the first oxide insulating layer is larger than a contained amount of oxygen in the second oxide insulating layer.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: August 27, 2019
    Assignee: Japan Display Inc.
    Inventors: Toshinari Sasaki, Masahiro Watabe, Masayoshi Fuchi, Isao Suzumura, Marina Shiokawa
  • Patent number: 10396099
    Abstract: Disclosed are an oxide thin film transistor (TFT), a method of manufacturing the same, and a display panel and a display device using the same, in which a first conductor and a second conductor are provided at end portions of a semiconductor layer formed of oxide semiconductor. The first conductor and second conductor are electrically connected to a first electrode and a second electrode, and covered by a gate insulation layer. The oxide TFT includes a semiconductor layer provided on a buffer and including an oxide semiconductor, a gate insulation layer covering the semiconductor layer and the buffer, a gate electrode provided on the gate insulation layer to overlap a portion of the semiconductor layer, and a passivation layer covering the gate and the gate insulation layer.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: August 27, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: JongUk Bae, YongHo Jang, JunHyeon Bae, Kwanghwan Ji, PilSang Yun, Jiyong Noh
  • Patent number: 10396213
    Abstract: An active device array substrate includes a substrate, first and second active devices, a gate insulation layer and an insulation barrier layer. The first and second active devices respectively includes first and second gate electrodes, first and second semiconductor blocks, first and second source electrodes, and first and second drain electrodes. A film layer of the second source electrode and the second drain electrode is the same with that of the first source electrode or the first drain electrode. The gate insulation layer is located between the first gate electrode and the first semiconductor block and between the second gate electrode and the second semiconductor block. The insulation barrier layer is disposed on the gate insulation layer, and covers the first semiconductor block. The insulation barrier layer has a first through hole for one of the first source electrode and the first drain electrode contacting the first semiconductor block.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: August 27, 2019
    Assignee: Chunghwa Picture Tubes, LTD.
    Inventors: Chin-Hai Huang, Ya-Ju Lu, Shang-Jung Yang, Yen-Yu Huang
  • Patent number: 10396110
    Abstract: A digital radiographic detector uses an IGZO active layer in the switching element for each imaging pixel in a two-dimensional array of imaging pixels. Each imaging pixel has a photo-sensitive element and the switching element. Read-out circuits electrically connected to the two-dimensional array generate a radiographic image by reading out image data by switching on and off the switching elements. The IGZO active layer may be formed having a thickness less than about 7 nm.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: August 27, 2019
    Assignees: Carestream Health, Inc., Kyung Hee University
    Inventors: Ravi K. Mruthyunjaya, Timothy J. Tredwell, Jin Jang, Mallory Mativenga, Jae Gwang Um, Mohammad Masum Billah
  • Patent number: 10388738
    Abstract: The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. A semiconductor layer of a transistor is formed using a composite oxide semiconductor in which a first region and a second region are mixed. The first region includes a plurality of first clusters containing one or more of indium, zinc, and oxygen as a main component. The second region includes a plurality of second clusters containing one or more of indium, an element M (M represents Al, Ga, Y, or Sn), zinc, and oxygen. The first region includes a portion in which the plurality of first clusters are connected to each other. The second region includes a portion in which the plurality of second clusters are connected to each other.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: August 20, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasutaka Nakazawa, Masashi Oota
  • Patent number: 10388798
    Abstract: The oxide semiconductor thin film transistor includes a source electrode and a drain electrode; a channel layer formed of an oxide semiconductor; a first insulating film; a first gate electrode formed on a surface side opposing a first channel region which is formed on an interface between the channel layer and the first insulating film; a second insulating film; and a second gate electrode formed on a surface side opposing a second channel region which is formed on an interface between the channel layer and the second insulating film, and in a case where a length of an apposition direction of the source electrode and the drain electrode in the first channel region is set to a first channel length, and a length of a apposition direction in the second channel region is set to a second channel length, the second channel length is shorter than the first channel length, and a potential applied to the second gate electrode is greater than or equal to a lower potential of potentials of the source electrode and the
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: August 20, 2019
    Assignee: TIANMA JAPAN, LTD.
    Inventor: Kazushige Takechi
  • Patent number: 10388797
    Abstract: Provided is a highly integrated semiconductor device, a semiconductor device with large storage capacity with respect to an area occupied by a capacitor, a semiconductor device capable of high-speed writing, a semiconductor device capable of high-speed reading, a semiconductor device with low power consumption, or a highly reliable semiconductor device. The semiconductor device includes a first transistor, a second transistor, and a capacitor. A conductor penetrates and connects the first transistor, the capacitor, and the second transistor. An insulator is provided on a side surface of the conductor that penetrates the capacitor.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: August 20, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa
  • Patent number: 10388679
    Abstract: An array substrate includes a substrate, a gate electrode, a gate insulating layer and an active layer formed in sequence in a stack. The active layer includes a source transfer portion and a drain transfer portion separated from the source transfer portion and a channel integrally connected to the source transfer portion and the drain transfer portion. Contact resistances between the source transfer portion, the drain transfer portion and the channel are reduced, and interface defects of the channel are reduced, so that through the source transfer portion and the drain transfer portion, an on-state current of a thin film transistor is increased and an off-state current is reduced so that is the on/off ratio is raised to improve the performance of the array substrate.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: August 20, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Zhiwu Wang
  • Patent number: 10380956
    Abstract: An information terminal capable of switching display and non-display of images by strain. The information terminal includes a display portion and a strain sensor. The display portion includes a liquid crystal element, a light-emitting element, and a first and a second transistors. The strain sensor includes a strain sensor element and a resistor. The first transistor has a function of controlling current flowing into the light-emitting element. The strain sensor element has a function as a variable resistor. A first terminal of the strain sensor element is electrically connected to a first terminal of the resistor. A gate of the first transistor is electrically connected to a first terminal of the strain sensor element via the second transistor.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: August 13, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yuki Okamoto
  • Patent number: 10381487
    Abstract: A thin film transistor includes a channel section formed from semiconductor material, a source electrode connected to one end of the channel section, a drain electrode connected to another end of the channel section, an upper gate electrode included in an upper layer than the channel section and overlapping the channel section, a lower gate electrode included in a lower layer than the channel section and overlapping the channel section, an upper gate insulation film disposed between the upper gate electrode and the channel section, and a lower gate insulation film disposed between the lower gate electrode and the channel section and having a film thickness relatively greater than that of the upper gate insulation film.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: August 13, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kengo Hara, Tohru Daitoh, Hajime Imai, Tetsuo Kikuchi, Masahiko Suzuki, Setsuji Nishimiya, Teruyuki Ueda
  • Patent number: 10381382
    Abstract: An array substrate, a manufacture method thereof and a display device are provided. The array substrate includes a base, and multiple metal layers configured to be insulated from each other and arranged on the base, each of at least two metal layers of the multiple metal layers includes a common electrode line and the common electrode lines in the at least two metal layers are connected to each other.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: August 13, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Guochen Du
  • Patent number: 10381557
    Abstract: Resistive RAM (RRAM) devices having increased reliability and related manufacturing methods are described. Greater reliability of RRAM cells over time can be achieved by avoiding direct contact of metal electrodes with the device switching layer. The contact can be avoided by cladding the switching layer in a material such as silicon or using electrodes that may contain metal but have regions that are adjacent the switching layer and lack free metal ions except for possible trace amounts.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: August 13, 2019
    Inventors: Shih-Yuan Wang, Shih-Ping Wang
  • Patent number: 10372000
    Abstract: There is disclosed a method of manufacturing an array substrate, the method including a step of forming thin film transistors on a substrate; wherein the step of forming the thin film transistors on the substrate includes: forming a first electrically conductive layer on the substrate; forming an insulating layer on the first electrically conductive layer; forming at least one common holes in the insulating layer to communicate with the first electrically conductive layer; forming a first connection portion, which is made of the same material as a second electrically conductive layer, in the at least one of the at least one common holes while forming the second electrically conductive layer on the insulating layer by using a single process, the first connection portion being in electrical contact with the first electrically conductive layer. In addition, there is disclosed an array substrate manufactured by the above method and a display device including the array substrate.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: August 6, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Botao Song, Liang Lin, Tao Ma, Wenlong Wang, Ling Han, Yu Wei
  • Patent number: 10372274
    Abstract: A touch panel including an oxide semiconductor film having conductivity is provided. The touch panel includes a transistor, a second insulating film, and a touch sensor. The transistor includes a gate electrode; a gate insulating film; a first oxide semiconductor film; a source electrode and a drain electrode; a first insulating film; and a second oxide semiconductor film. The second insulating film is over the second oxide semiconductor film so that the second oxide semiconductor film is positioned between the first insulating film and the second insulating film. The touch sensor includes a first electrode and a second electrode. One of the first and second electrodes includes the second oxide semiconductor film.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: August 6, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hajime Kimura, Masami Jintyou, Yasuharu Hosaka, Naoto Goto, Takahiro Iguchi, Daisuke Kurosaki, Junichi Koezuka
  • Patent number: 10374083
    Abstract: A method of forming a fin field effect transistor is provided. The method includes forming an elevated substrate tier on a substrate, and forming a fin mesa on the elevated substrate tier with a fin template layer on the fin mesa, wherein the elevated substrate tier is laterally larger than the fin mesa and fin template layer. The method includes forming a fill layer on the substrate, wherein the fill layer surrounds the fin mesa, elevated substrate tier, and fin template layer, forming a plurality of fin masks on the fill layer and fin template layer, and removing portions of the fill layer, fin template layer, and fin mesa to form a plurality of dummy fins from the fill layer, one or more vertical fins from the fin mesa, and a dummy fin portion on opposite ends of each of the one or more vertical fins from the fill layer.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chen Zhang, Kangguo Cheng, Xin Miao, Wenyu Xu
  • Patent number: 10373984
    Abstract: The purpose of the present invention is to improve reliability of the TFT of the oxide semiconductor. The feature of the invention is: A display device comprising: a substrate including a display area where plural pixels are formed, the pixel includes a first TFT of a first oxide semiconductor, a first gate insulating film is formed under the first oxide semiconductor, a first gate electrode is formed under the first gate insulating film, an interlayer insulating film is formed on the first oxide semiconductor; a drain wiring, which connects with the first oxide semiconductor, and a source wiring, which connects with the first oxide semiconductor, are formed on the interlayer insulating film; the drain wiring or the source wiring is a laminated structure of a second oxide semiconductor and a first metal, the second oxide semiconductor is under the first metal.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: August 6, 2019
    Assignee: Japan Display Inc.
    Inventor: Yohei Yamaguchi
  • Patent number: 10373983
    Abstract: A display device including a display portion with an extremely high resolution is provided. The display device includes a pixel circuit and a light-emitting element. The pixel circuit includes a first element layer including a first transistor and a second element layer including a second transistor. A channel formation region of the first transistor includes silicon. The first transistor has a function of driving the light-emitting element. The second transistor functions as a switch. A channel formation region of the second transistor includes a metal oxide. The metal oxide functions as a semiconductor. The second element layer is provided over the first element layer.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: August 6, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kei Takahashi, Hiroyuki Miyake
  • Patent number: 10367081
    Abstract: The present disclosure provides a thin film transistor (TFT) and its manufacturing method. The method includes the following steps: sequentially depositing a buffer layer and a shielding layer on a substrate; forming an IGZO layer on and covering the shielding layer; processing the IGZO layer by annealing so that a portion of the IGZO layer is diffused by the buffer layer and has a conductor property; and forming a source and a drain so that the source and drain contact the portion of the IGZO layer. The present disclosure, through annealing the IGZO layer, the buffer layer makes portions of the IGZO layer contacting the source and the drain to have conductor property, thereby avoiding the prior art's complex process, simplifying the manufacturing of the IGZO TFT, and enhancing the production efficiency.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: July 30, 2019
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Longqiang Shi
  • Patent number: 10367096
    Abstract: A semiconductor device which includes a transistor having a miniaturized structure is provided. A first insulator is provided over a stack in which a semiconductor, a first conductor, and a second conductor are stacked in this order. Over the first insulator, an etching mask is formed. Using the etching mask, the first insulator and the second conductor are etched until the first conductor is exposed. After etching the first conductor until the semiconductor is exposed so as to form a groove having a smaller width than the second conductor, a second insulator and a third conductor are formed sequentially.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: July 30, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Shinya Sasagawa, Satoru Okamoto, Motomu Kurata, Yuta Endo
  • Patent number: 10358742
    Abstract: A method of growing a conductive Ga2O3-based crystal film by MBE includes producing a Ga vapor and a Si-containing vapor and supplying the vapors as molecular beams onto a surface of a Ga2O3-based crystal substrate so as to grow the Ga2O3-based crystal film. The Ga2O3-based crystal film includes a Si-containing Ga2O3-based single crystal film. The Si-containing vapor is produced by heating Si or a Si compound and Ga while allowing the Si or a Si compound to contact with the Ga.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: July 23, 2019
    Assignees: TAMURA CORPORATION, Novel Crystal Technology, Inc.
    Inventors: Kohei Sasaki, Daiki Wakimoto
  • Patent number: 10355107
    Abstract: The present application discloses a method of fabricating a polycrystalline silicon thin film transistor, the method including forming an amorphous silicon layer on a base substrate having a pattern corresponding to a polycrystalline silicon active layer of the thin film transistor; the amorphous silicon layer having a first region corresponding to a source electrode and drain electrode contact region in the polycrystalline silicon active layer and a second region corresponding to a channel region in the polycrystalline silicon active layer; forming a first dopant layer on a side of the second region distal to the base substrate; forming a second dopant layer on a side of the first region distal to the base substrate; and crystallizing the amorphous silicon layer, the first dopant layer, and the second dopant layer to form the polycrystalline silicon active layer, the polycrystalline silicon active layer being doped with a dopant of the first dopant layer in the second region and doped with a dopant of the se
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: July 16, 2019
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Jian Min, Xiaolong Li, Tao Gao, Liangjian Li, Zhengyin Xu
  • Patent number: 10355021
    Abstract: A thin film transistor structure is provided with a glass substrate, a buffer layer, a metal oxide semiconductor layer, a gate insulating layer, a gate metal layer, an interlayer insulating layer, a source metal layer, a drain metal layer, and a protective layer. A shielding metal layer is disposed between the glass substrate and the buffer layer, the gate insulating layer has a shielding metal layer contact hole passing through the gate insulating layer and the buffer layer, and the gate metal layer connects with the shielding metal layer through the shielding metal layer contact hole.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: July 16, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Mingjue Yu, Jangsoon Im
  • Patent number: 10355456
    Abstract: In some implementations, a VCSEL array may include a plurality of VCSELs that each operates concurrently and emits light at a same wavelength. A first distance between a first pair of adjacent VCSELs, of the plurality of VCSELs, may be different from a second distance between a second pair of adjacent VCSELs of the plurality of VCSELs. The first pair of adjacent VCSELs may be located closer to a center of the VCSEL array than the second pair of adjacent VCSELs. At least one of temperature non-uniformity or optical power non-uniformity among the plurality of VCSELs may be reduced as compared to another VCSEL array, with a same physical footprint as the VCSEL array, comprising uniformly spaced VCSELs.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: July 16, 2019
    Assignee: Lumentum Operations LLC
    Inventors: Albert Yuen, Ajit Vijay Barve
  • Patent number: 10347662
    Abstract: The present disclosure discloses an array substrate comprising: a substrate; a gate electrode; a gate insulating layer formed on one side of the substrate facing the gate electrode, the gate insulating layer covering the gate electrode; an active layer formed on one side of the gate insulating layer away from the gate electrode and made of an indium gallium zinc tin oxide material; an ohmic contact layer formed on one side of the active layer away from the gate insulating layer and made of a conductive indium gallium zinc oxide material, the ohmic contact layer covering both ends of the active layer; and a source electrode and a drain electrode formed on one side of the ohmic contact layer away from the active layer, the source electrode and the drain electrode being electrically connected to both ends of the active layer by the ohmic contact layer, respectively.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: July 9, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Xiaobo Hu
  • Patent number: 10340392
    Abstract: A semiconductor device includes a thin film transistor including an oxide semiconductor layer and a wire connecting portion (201). The wire connecting portion (201) includes a lower electrically-conductive portion (3t) formed out of a same electrically-conductive film as the gate electrode, an insulating layer (15) having a contact hole (CH2) through which at least a part of the lower electrically-conductive portion (3t) is exposed, and an upper electrically-conductive portion (19t), at least a part of which is provided inside the contact hole (CH2). The insulating layer (15) includes the gate insulating layer (4), the protection layer (9) and the interlayer insulating layer (13).
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: July 2, 2019
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yoshihito Hara
  • Patent number: 10340472
    Abstract: A display device includes a base substrate, a first transistor, a second transistor, an organic light emitting diode, and a capacitor electrically connected to the first thin film transistor. The first transistor includes a first semiconductor pattern below a first interlayer insulation layer and a first control electrode above the first interlayer insulation layer and below a second interlayer insulation layer. The second transistor includes a second control electrode above the first interlayer insulation layer and below the second interlayer insulation layer. A second semiconductor pattern is above the second interlayer insulation layer.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: July 2, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jaybum Kim, Eoksu Kim, Kyoungseok Son, Junhyung Lim, Jihun Lim