Abstract: A pixel circuit of a display device includes a driving element comprising a first electrode connected to a first node to which a pixel driving voltage is applied, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode connected to a fourth node, and configured to supply an electric current to a light-emitting element; a first switch element configured to be turned on according to a gate-on voltage and supply a data voltage to the second node; a first capacitor connected between the second node and the third node; a second capacitor connected between the third node and the fourth node; and a third capacitor connected between the fourth node and the first node, or between the fourth node and a power line to which the pixel driving voltage is applied.

Abstract: A semiconductor device having favorable electrical characteristics is provided. A semiconductor device having stable electrical characteristics is provided. A highly reliable semiconductor device is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, and a first conductive layer. The semiconductor layer includes an island-shaped top surface. The first insulating layer is provided in contact with a top surface and a side surface of the semiconductor layer. The first conductive layer is positioned over the first insulating layer and includes a portion overlapping with the semiconductor layer. In addition, the semiconductor layer includes a metal oxide, and the first insulating layer includes an oxide. The semiconductor layer includes a first region overlapping with the first conductive layer and a second region not overlapping with the first conductive layer.

Abstract: A light-emitting element includes, in order of listing, an anode, an hole transport layer, an emission layer, and a cathode. The light-emitting element includes an reducing material disposed in at least a part between the anode and the hole transport layer, being in contact with the anode and the hole transport layer, and containing a reducing material that reduces a layer having the hole transport layer. The reducing material contains, in a structure of the reducing material, hydrogen either at a concentration ratio of 1 to 1 with resect to a base metal, or at a larger concentration ratio than the base metal.

Abstract: A pixel driving circuit and a display panel are provided. The pixel driving circuit includes a light-emitting module, an external detection module, and an internal compensation module. The light-emitting module is electrically connected to the external detection module and the internal compensation module. The external detection module is configured to acquire a threshold voltage of a second transistor when a display panel is turned on, and determine a shift direction of the threshold voltage. When the shift direction of the threshold voltage is a positive shift, the pixel driving circuit uses a first timing sequence to compensate the threshold voltage. When the shift direction of the threshold voltage is a negative shift, the pixel driving circuit uses a second timing sequence to compensate the threshold voltage.

Abstract: Disclosed are a thin film transistor (TFT) including an oxide semiconductor layer capable of being applied to high-resolution flat panel display devices requiring high-speed driving, a gate driver including the TFT, and a display device including the gate driver. The TFT includes first oxide semiconductor layer consisting of indium-gallium-zinc-tin oxide (IGZTO) and a second oxide semiconductor layer including indium-gallium-zinc oxide (IGZO). A content ratio (Ga/In) of gallium (Ga) to indium (In) of the second oxide semiconductor layer is higher than a content (Ga/In) of Ga to In of the first oxide semiconductor layer, and a content ratio (Zn/In) of zinc (Zn) to In of the second oxide semiconductor layer is higher than a content (Zn/In) of Zn to In of the first oxide semiconductor layer.

Abstract: A semiconductor device having a large storage capacity per unit area is provided.

Abstract: A semiconductor device having a large on-state current and high reliability is provided. The semiconductor device includes a first insulator, a first oxide over the first insulator, a second oxide over the first oxide, a third oxide and a fourth oxide over the second oxide, a first conductor over the third oxide, a second conductor over the fourth oxide, a fifth oxide over the second oxide, a second insulator over the fifth oxide, and a third conductor over the second insulator. The fifth oxide is in contact with a top surface of the second oxide, a side surface of the first conductor, a side surface of the second conductor, a side surface of the third oxide, and a side surface of the fourth oxide. The second oxide contains In, an element M, and Zn. The first oxide and the fifth oxide each contain at least one of constituent elements included in the second oxide. The third oxide and the fourth oxide each contain the element M.

Abstract: Semiconductor device includes a semiconductor layer, an insulating film provided on the semiconductor layer and having an opening formed therein, a gate electrode connected to the semiconductor layer through opening, a protection film covering gate electrode, and a Ni oxide film, wherein the insulating film has a first surface on the semiconductor layer side and a second surface opposite to the first surface, and the gate electrode has a third surface facing the second surface and spaced apart from the second surface and a fourth surface connecting the second surface and the third surface. The gate electrode includes a Ni film constituting the third surface and the fourth surface, and the Ni oxide film covers the Ni film on the third surface and the fourth surface. The protection film covers the third surface and the fourth surface by being placed over Ni oxide film.

Abstract: A transistor includes a multilayer film in which an oxide semiconductor film and an oxide film are stacked, a gate electrode, and a gate insulating film. The multilayer film overlaps with the gate electrode with the gate insulating film interposed therebetween. The multilayer film has a shape having a first angle between a bottom surface of the oxide semiconductor film and a side surface of the oxide semiconductor film and a second angle between a bottom surface of the oxide film and a side surface of the oxide film. The first angle is acute and smaller than the second angle. Further, a semiconductor device including such a transistor is manufactured.

Abstract: A backplane, a backlight source, an illumination device and a displaying device. The backplane comprises a substrate; a first metal trace layer disposed on one surface of the substrate; an insulating layer disposed on a side, away from the substrate, of the first metal trace layer; a second metal trace layer disposed on a side, away from the substrate, of the insulating layer, an overlapping area existing between an orthographic projection of the second metal trace layer on the substrate and an orthographic projection of the first metal trace layer on the substrate; and a barrier layer disposed between the first metal trace layer and the second metal trace layer, an orthographic projection of the barrier layer on the substrate covering the overlapping area, and the barrier layer being used for preventing metals in the first metal trace layer and the second metal trace layer from growing towards each other.

Abstract: An array substrate and a display panel are provided. The array substrate includes a substrate, a gate, a gate insulating layer, an oxide semiconductor layer, and a source-drain metal layer. Material of at least a portion of the gate insulating layer in contact with the oxide semiconductor layer and material of the oxide semiconductor layer include an oxide of the first metal element. Thus, a transition interface between the gate insulating layer and the oxide semiconductor layer has a lower density of defect states, which is beneficial to improve mobility and stability.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes an interconnect structure and an electrode layer formed over the interconnect structure. The semiconductor structure also includes a gate dielectric layer formed over the electrode layer and an oxide semiconductor layer formed over the gate dielectric layer. The semiconductor structure also includes an indium-containing feature covering a surface of the oxide semiconductor layer and a source/drain contact formed over the indium-containing feature.

Abstract: A display device includes a first transistor including a first transistor including a light blocking pattern on a substrate, an active pattern on the light blocking pattern, and a gate electrode on the active pattern, a second transistor configured to provide a data voltage to the first transistor in response to a gate signal, and a storage capacitor electrically connected to the gate electrode and the light blocking pattern, and including a first conductive pattern in a same layer as the light blocking pattern, a second conductive pattern on the first conductive pattern and overlapping the first conductive pattern, a third conductive pattern in a same layer as the gate electrode, overlapping the second conductive pattern, and electrically connected to the first conductive pattern, and a fourth conductive pattern on the third conductive pattern, overlapping the third conductive pattern, and electrically connected to the second conductive pattern.

Abstract: The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate, the thin film transistor including: a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each comprise a first conductive material touching the OS layer, and wherein the first conductive material has a work function less than 4.6. The memory cell further includes a dielectric material separating the source line and the bit line.

Abstract: A transistor with a high on-state current and a semiconductor device with high productivity are provided. Included are a first oxide, a second oxide, a third oxide, and a fourth oxide over a first insulator; a first conductor over the third oxide; a second conductor over the fourth oxide; a second insulator over the first conductor; a third insulator over the second conductor; a fifth oxide positioned over the second oxide and between the third oxide and the fourth oxide; a sixth oxide over the fifth oxide; a fourth insulator over the sixth oxide; a third conductor over the fourth insulator; and a fifth insulator over the first insulator to the third insulator. The fifth oxide includes a region in contact with the second oxide to the fourth oxide and the first insulator. The sixth oxide includes a region in contact with the fifth oxide, the first conductor, and the second conductor. The fourth insulator includes a region in contact with at least the sixth oxide, the third conductor, and the fifth insulator.

Abstract: The present application discloses a display panel, a display panel manufacturing method, and a display device. The display panel includes a source region and a drain region. A dielectric layer covering the source region and the drain region is provided with a first via hole and a second via hole separately. The first via hole is connected to the source region or the drain region, the second via hole is located on the top of the first via hole and is in communication with the first via hole, and an aperture of the second via hole is larger than an aperture of the first via hole.

Abstract: A semiconductor device having a large storage capacity is provided. The semiconductor device includes an oxide provided over a substrate, a plurality of first conductors over the oxide, a first insulator that is provided over the plurality of first conductors and includes a plurality of openings overlapping with regions between the plurality of first conductors, a plurality of second insulators provided in the respective plurality of openings, a plurality of charge retention layers provided over the respective plurality of second insulators, a plurality of third insulators provided over the respective plurality of charge retention layers, and a plurality of second conductors provided over the respective plurality of third insulators.

Abstract: A display device is provided. The display device includes a substrate, a driving layer, a light-emitting element, and a light-shielding element. The substrate has a surface. The driving layer includes a thin-film transistor. The thin-film transistor is disposed on the surface. The light-emitting element has a P-end and an N-end. The light-emitting element is disposed on the driving layer and arranged in such a way that a virtual line connecting the P-end and the N-end is parallel to the surface of the substrate. The light-shielding element is disposed between the light-emitting element and the thin-film transistor for blocking a light emitted from the light-emitting element from irradiating the thin-film transistor.

Abstract: A memory device and method of making the same, the memory device including bit lines disposed on a substrate; memory cells disposed on the bit lines; a first dielectric layer disposed on the substrate, surrounding the bit lines and the memory cells; a second dielectric layer disposed on the first dielectric layer; thin film transistors (TFTs) embedded in the second dielectric layer and configured to selectively provide electric power to corresponding memory cells, the TFTs comprising drain lines disposed on the memory cells, source lines disposed on the first dielectric layer, and selector layers electrically connected to the source lines and the drain lines; and word lines disposed on the second dielectric layer and electrically connected to the TFTs.

Abstract: A vertical field-effect transistor. The transistor includes: a drift region having a first conductivity type; a semiconductor fin on or over the drift region; and a source/drain electrode on or over the semiconductor fin, the semiconductor fin having an electrically conductive region that connects the source/drain electrode to the drift region in electrically conductive fashion, and having a limiting structure that is formed laterally next to the electrically conductive region and that extends from the source/drain electrode to the drift region, the limiting structure being set up to limit a conductive channel of the vertical field-effect transistor in the semiconductor fin to the area of the electrically conductive region.

Abstract: A display device includes a display panel having a display area and a non-display area. The display panel includes a pixel disposed in the display area and including a light emitting element and a pixel driving circuit electrically connected with the light emitting element, a sensor disposed in the display area and including a photo sensing element and a sensor driving circuit electrically connected with the photo sensing element, a data line electrically connected with the pixel and extended along a first direction, a scan line electrically connected with the pixel and extended along a second direction intersecting the first direction, and a readout line including a first readout portion in the display area. The first readout portion is electrically connected with the sensor and extended along the second direction in the display area.

Abstract: An array substrate and a manufacturing method therefor, and a display panel are provided. The manufacturing method includes: forming a scan line and a gate on a substrate; forming a first insulating layer covering the scan line and the gate on the substrate; forming a metal oxide semiconductor layer above the first insulating layer, the metal oxide semiconductor layer including a source, a drain and an active layer; coating an upper surface of the metal oxide semiconductor layer with a photosensitive material layer; photoetching the photosensitive material layer from the back side of the substrate by using a first metal layer as a mask to form a channel protection layer; performing conductorization treatment on the metal oxide semiconductor layer to enable the source and the drain to be conductive; forming a data line above the first insulating layer; and forming a pixel electrode above the first insulating layer.

Abstract: The present application provides a flexible display panel including: an underlay substrate; at least one first conductive line being continuous line-shaped, disposed on the underlay substrate; at least one second conductive line being broken line-shaped, corresponding to the first conductive line, and disposed on the first conductive line, wherein each of the second conductive line includes a plurality of conductive line sections, the conductive line sections are spaced from one another, and is electrically connected to a corresponding one of the first conductive line. A rigidity of the first conductive line is less than a rigidity of the conductive line sections, and a conductivity of the conductive line sections is greater than a conductivity of the first conductive line. The configuration of the first conductive line and the second conductive line makes the flexible display panel have both rigidity and conductivity.

Abstract: A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with stable electrical characteristics is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, and a first conductive layer. The first insulating layer is provided over the semiconductor layer. The first conductive layer is provided over the first insulating layer. The semiconductor layer includes a first region that overlaps with the first conductive layer and the first insulating layer, a second region that does not overlap with the first conductive layer and overlaps with the first insulating layer, and a third region that overlaps with neither the first conductive layer nor the first insulating layer. The semiconductor layer contains a metal oxide. The second region and the third region contain a first element. The first element is one or more elements selected from boron, phosphorus, aluminum, and magnesium.

Abstract: A transistor with small parasitic capacitance can be provided. A transistor with high frequency characteristics can be provided. A semiconductor device including the transistor can be provided. Provided is a transistor including an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor has a first region where the first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween; a second region where the first conductor overlaps with the second conductor with the first and second insulators positioned therebetween; and a third region where the first conductor overlaps with the third conductor with the first and second insulators positioned therebetween. The oxide semiconductor including a fourth region where the oxide semiconductor is in contact with the second conductor; and a fifth region where the oxide semiconductor is in contact with the third conductor.

Abstract: A stack including an active layer, a gate dielectric, and a gate electrode is formed in a forward or in a reverse order, over a substrate. The active layer includes a front channel layer, a bulk semiconductor layer, and a back channel layer. The front channel layer is formed by depositing a layer stack that include at least one post-transition metal oxide layer, a zinc oxide layer, and at least one acceptor-type oxide layer. The zinc oxide layer or at least one post transition metal oxide layer contacts the gate dielectric, and the at least one acceptor-type oxide layer is most distal from the gate dielectric. The front channel layer provides enhanced channel conductivity, while the back channel layer provides suppressed channel conductivity.

Abstract: An X-ray device including a sensing panel and a scintillator layer is provided. The sensing panel includes a substrate and a first pixel. The first pixel is disposed on the substrate and includes a first light sensing component and a first switch component. The first switch component is disposed on the first light sensing component. The scintillator layer is disposed on the sensing panel, and the first switch component is disposed between the scintillator layer and the first light sensing component.

Abstract: An example two transistor (2T) gain cell memory with indium-gallium-zinc-oxide (IGZO) transistors. Examples include IGZO transistors included in a dynamic random access memory (DRAM) cell. The IGZO transistors included in the DRAM cell are described as being formed or created in a back end (BE) metal process stack of an integrated circuit chip or die.

Abstract: The present disclosure provides a displaying backplane and a displaying device, and relates to the technical field of displaying. The displaying backplane includes: a substrate base plate; a first active layer and a second active layer that are provided on the substrate base plate, wherein the material of the first active layer and the second active layer is an oxide semiconductor, the first active layer has a first channel region and first no-channel regions, and the second active layer has a second channel region and second no-channel regions; a first grid insulating layer covering the first active layer and the second active layer; and a first grid and a second grid that are provided on the first grid insulating layer; wherein the oxygen-vacancy concentration of the first channel region is greater than the oxygen-vacancy concentrations of the first no-channel regions, the second no-channel regions and the second channel region.

Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, and a U-shaped channel above the substrate. The U-shaped channel may include a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area. A gate dielectric layer may be above the substrate and in contact with the channel bottom. A gate electrode may be above the substrate and in contact with the gate dielectric layer. A source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.

Abstract: A thin film transistor and a display apparatus comprising the same are provided, in which the thin film transistor comprises an active layer, a barrier layer on the active layer; a gate insulating layer on the barrier layer; and a gate electrode on the gate insulating layer, wherein at least a portion of the gate electrode overlaps at least a portion of the active layer, and the barrier layer includes an oxide semiconductor material and has a resistivity greater than a resistivity of the active layer and has a thickness less than a thickness of the active layer.

Abstract: A semiconductor device including at least one inversion channel region includes an oxide semiconductor film containing a crystal that has a corundum structure at the inversion channel region.

Abstract: A memory device includes a plurality of memory cells. A first memory cell of the plurality of memory cells includes a first write transistor includes a first write gate, a first write source, and a first write drain. A first read transistor includes first read gate, a first read source, a first read drain, and a first body region separating the first read source from the first read drain. The first read source is coupled to the first write source. A first capacitor has a first upper capacitor plate coupled to the first write drain and a first lower capacitor plate coupled to the first body region of the first read transistor.

Abstract: An active matrix substrate includes a substrate, a pixel TFT that is supported by the substrate, provided corresponding to each of a plurality of pixel areas, and includes an oxide semiconductor layer, an organic insulating layer disposed above at least the oxide semiconductor layer of the pixel TFT, and an inorganic insulating layer disposed in contact with an upper surface of the organic insulating layer on the organic insulating layer. The organic insulating layer and the inorganic insulating layer are provided with a plurality of dual-layer hole structure portions, each of the dual-layer hole structure portions includes a through-hole provided in the inorganic insulating layer and a bottomed hole provided in the organic insulating layer and positioned below the through-hole, and the through-hole is positioned on an inner side of an outer edge of the bottomed hole when viewed from a normal direction of the substrate.

Abstract: A method for manufacturing a HEMT device includes forming, on a heterostructure, a dielectric layer, forming a through opening through the dielectric layer, and forming a gate electrode in the through opening. Forming the gate electrode includes forming a sacrificial structure, depositing by evaporation a first gate metal layer layer, carrying out a lift-off of the sacrificial structure, depositing a second gate metal layer by sputtering, and depositing a third gate metal layer. The second gate metal layer layer forms a barrier against the diffusion of metal atoms towards the heterostructure.

Abstract: Various forms of MgxGe1?xO2?x are disclosed, where an epitaxial layer comprises single crystal MgxGe1?xO2?x, with x having a value of 0?x<1, wherein the single crystal MgxGe1?xO2?x has a crystal symmetry compatible with a substrate or with an underlying layer on which the single crystal MgxGe1?xO2?x is grown. Semiconductor structures and devices comprising the epitaxial layer of MgxGe1?xO2?x are disclosed, along with methods of making the epitaxial layers and semiconductor structures and devices.

Abstract: The present application discloses a display panel, a manufacturing method thereof, and a display device. The display panel includes a substrate; a gate layer; a gate insulating layer; an active layer; a source-drain layer including a source electrode and a drain electrode; a passivation layer provided with a contact hole; and a pixel electrode layer connected to the drain electrode through the contact hole; wherein a light-transmitting etch stop layer is disposed at a hole bottom of the contact hole, and the light-transmitting etch stop layer at least partially covers a hole bottom of the contact hole.

Abstract: The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a first conductive pattern and a second conductive pattern arranged at different layers and electrically connected to each other via at least two conductive connection structures.

Abstract: The present application discloses a display panel and a display device. In the display panel, a first substrate includes a substrate and a thin-film transistor disposed on the substrate, and the thin-film transistor includes an active layer. The second substrate is disposed on the first substrate. The liquid crystal layer is disposed between the first substrate and the second substrate. The first filter layer is disposed on at least one of the first substrate and the second substrate, and at least part of the first filter layer overlaps with the active layer. The first filter layer is a metal oxide film layer.

Abstract: A display device includes: a substrate including a display area and a peripheral area adjacent to the display area, pixels disposed in the display area on the substrate, each of the pixels including a pixel transistor and an emission element connected to the pixel transistor, and a driver disposed in the peripheral area on the substrate and including a driver transistor. The driver transistor includes an active pattern, a first gate pattern disposed on the active pattern and overlapping a first channel region of the active pattern, a second gate pattern disposed in a same layer as the first gate pattern and overlapping a second channel region of the active pattern, a first electrode pattern disposed on the active pattern and connected to a source region of the active pattern, and a second electrode pattern disposed on the active pattern and connected to a drain region of the active pattern.

Abstract: A semiconductor device having a reduced amount of oxygen vacancy in a channel formation region of an oxide semiconductor is provided. Further, a semiconductor device which includes an oxide semiconductor and has improved electric characteristics is provided. Furthermore, a methods for manufacturing the semiconductor device is provided. An oxide semiconductor film is formed; a conductive film is formed over the oxide semiconductor film at the same time as forming a low-resistance region between the oxide semiconductor film and the conductive film; the conductive film is processed to form a source electrode and a drain electrode; and oxygen is added to the low-resistance region between the source electrode and the drain electrode, so that a channel formation region having a higher resistance than the low-resistance region is formed and a first low-resistance region and a second low-resistance region between which the channel formation region is positioned are formed.

Abstract: The disclosure provides an electronic device includes a substrate and a pattern layer. The substrate with a step structure includes a high-level surface and a low-level surface. The pattern layer includes a first unit pattern and a second unit pattern adjacent to and separated from the first unit pattern, wherein the first unit pattern overlaps a first part of the low-level surface and overlaps a first part of the high-level surface, and the second unit pattern overlaps a second part of the low-level surface and overlaps a second part of the high-level surface.

Abstract: Embodiments of the present disclosure relate to a thin film transistor array substrate and display device in which a semiconductor layer has a heterogeneous conductorization structure including heterogeneous conductorization portions having different electrical conductivity, and the gate insulator layer is not etched enough to expose the semiconductor layer between the source electrode part and the gate electrode part and between the drain electrode part and the gate electrode part, so that the possibility of damage to the semiconductor layer can be eliminated or reduced.

Abstract: An imaging element includes a photoelectric conversion section 23 including a first electrode 21, a photoelectric conversion layer 23A including an organic material, and a second electrode 22 that are stacked. An inorganic oxide semiconductor material layer 23B including a first layer 23C and a second layer 23D, from side of the first electrode, is formed between the first electrode 21 and the photoelectric conversion layer 23A, and ?1?5.9 g/cm3 and ?1??2?0.1 g/cm3 are satisfied, where ?1 is an average film density of the first layer 23C and ?2 is an average film density of the second layer 23D in a portion extending for 3 nm from an interface between the first electrode 21 and the inorganic oxide semiconductor material layer 23B.

Abstract: A thin film transistor can include a first gate electrode, an active layer including a channel portion, and a second gate electrode. The active layer is between the first gate electrode and the second gate electrode, and at least a portion of the first gate electrode does not overlap with the second gate electrode. Further, at least a portion of the second gate electrode does not overlap with the first gate electrode, and the channel portion overlaps with at least one of the first gate electrode and the second gate electrode. In addition, a first portion of the channel portion can overlaps with one of the first gate electrode and the second gate electrode, and a second portion of the channel portion can overlap with a remaining one of the first gate electrode and the second gate electrode that is not overlapped by the first portion of the channel portion.

Abstract: A display panel includes a base layer including a first area and a second area. At least one inorganic layer disposed on the base layer overlaps the first area and the second area. The at least one inorganic layer comprises a lower opening. A first thin-film transistor is disposed on the at least one inorganic layer. The first thin-film transistor includes a silicon semiconductor pattern. A second thin-film transistor is disposed on the at least one inorganic layer. The second thin-film transistor includes an oxide semiconductor pattern. A plurality of insulation layers overlap the first area and the second area. An upper opening extends from the lower opening. A signal line is electrically connected to the second thin-film transistor. An organic layer is disposed in the lower opening and the upper opening. A light emitting element is disposed on the organic layer.

Abstract: A method of manufacturing a driving backplane for display includes: forming a first conductive pattern layer including first conductive lines on a base; and forming a second conductive pattern layer including electrode groups and second conductive lines on a side of the first conductive pattern layer away from the base. The first conductive lines and the second conductive lines cross and are insulated from each other; an electrode group includes a first electrode and a second electrode electrically connected to a corresponding second conductive line. Orthogonal projections, on the base, of the first electrode and a corresponding first conductive line have an overlapping region, and a portion of the first electrode, whose orthogonal projection on the base is located in the overlapping region, is in contact with a portion of the first conductive line, whose orthogonal projection on the base is located in the overlapping region.

Abstract: Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.

Abstract: A semiconductor device, an integrated circuit, and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a thin-film transistor (TFT) over the substrate, and a magnetoresistive random-access memory (MRAM) cell electrically coupled to the TFT. The TFT includes a gate electrode; an active layer disposed above the gate electrode; source/drain electrodes disposed above the gate electrode and separated by the active layer; and at least two dielectric layers disposed between the gate electrode and the source/drain electrodes.