Abstract: The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a first conductive pattern and a second conductive pattern arranged at different layers and electrically connected to each other via at least two conductive connection structures.

Abstract: The present application discloses a display panel and a display device. In the display panel, a first substrate includes a substrate and a thin-film transistor disposed on the substrate, and the thin-film transistor includes an active layer. The second substrate is disposed on the first substrate. The liquid crystal layer is disposed between the first substrate and the second substrate. The first filter layer is disposed on at least one of the first substrate and the second substrate, and at least part of the first filter layer overlaps with the active layer. The first filter layer is a metal oxide film layer.

Abstract: A display device includes: a substrate including a display area and a peripheral area adjacent to the display area, pixels disposed in the display area on the substrate, each of the pixels including a pixel transistor and an emission element connected to the pixel transistor, and a driver disposed in the peripheral area on the substrate and including a driver transistor. The driver transistor includes an active pattern, a first gate pattern disposed on the active pattern and overlapping a first channel region of the active pattern, a second gate pattern disposed in a same layer as the first gate pattern and overlapping a second channel region of the active pattern, a first electrode pattern disposed on the active pattern and connected to a source region of the active pattern, and a second electrode pattern disposed on the active pattern and connected to a drain region of the active pattern.

Abstract: The disclosure provides an electronic device includes a substrate and a pattern layer. The substrate with a step structure includes a high-level surface and a low-level surface. The pattern layer includes a first unit pattern and a second unit pattern adjacent to and separated from the first unit pattern, wherein the first unit pattern overlaps a first part of the low-level surface and overlaps a first part of the high-level surface, and the second unit pattern overlaps a second part of the low-level surface and overlaps a second part of the high-level surface.

Abstract: Embodiments of the present disclosure relate to a thin film transistor array substrate and display device in which a semiconductor layer has a heterogeneous conductorization structure including heterogeneous conductorization portions having different electrical conductivity, and the gate insulator layer is not etched enough to expose the semiconductor layer between the source electrode part and the gate electrode part and between the drain electrode part and the gate electrode part, so that the possibility of damage to the semiconductor layer can be eliminated or reduced.

Abstract: A semiconductor device having a reduced amount of oxygen vacancy in a channel formation region of an oxide semiconductor is provided. Further, a semiconductor device which includes an oxide semiconductor and has improved electric characteristics is provided. Furthermore, a methods for manufacturing the semiconductor device is provided. An oxide semiconductor film is formed; a conductive film is formed over the oxide semiconductor film at the same time as forming a low-resistance region between the oxide semiconductor film and the conductive film; the conductive film is processed to form a source electrode and a drain electrode; and oxygen is added to the low-resistance region between the source electrode and the drain electrode, so that a channel formation region having a higher resistance than the low-resistance region is formed and a first low-resistance region and a second low-resistance region between which the channel formation region is positioned are formed.

Abstract: A thin film transistor can include a first gate electrode, an active layer including a channel portion, and a second gate electrode. The active layer is between the first gate electrode and the second gate electrode, and at least a portion of the first gate electrode does not overlap with the second gate electrode. Further, at least a portion of the second gate electrode does not overlap with the first gate electrode, and the channel portion overlaps with at least one of the first gate electrode and the second gate electrode. In addition, a first portion of the channel portion can overlaps with one of the first gate electrode and the second gate electrode, and a second portion of the channel portion can overlap with a remaining one of the first gate electrode and the second gate electrode that is not overlapped by the first portion of the channel portion.

Abstract: An imaging element includes a photoelectric conversion section 23 including a first electrode 21, a photoelectric conversion layer 23A including an organic material, and a second electrode 22 that are stacked. An inorganic oxide semiconductor material layer 23B including a first layer 23C and a second layer 23D, from side of the first electrode, is formed between the first electrode 21 and the photoelectric conversion layer 23A, and ?1?5.9 g/cm3 and ?1??2?0.1 g/cm3 are satisfied, where ?1 is an average film density of the first layer 23C and ?2 is an average film density of the second layer 23D in a portion extending for 3 nm from an interface between the first electrode 21 and the inorganic oxide semiconductor material layer 23B.

Abstract: A display panel includes a base layer including a first area and a second area. At least one inorganic layer disposed on the base layer overlaps the first area and the second area. The at least one inorganic layer comprises a lower opening. A first thin-film transistor is disposed on the at least one inorganic layer. The first thin-film transistor includes a silicon semiconductor pattern. A second thin-film transistor is disposed on the at least one inorganic layer. The second thin-film transistor includes an oxide semiconductor pattern. A plurality of insulation layers overlap the first area and the second area. An upper opening extends from the lower opening. A signal line is electrically connected to the second thin-film transistor. An organic layer is disposed in the lower opening and the upper opening. A light emitting element is disposed on the organic layer.

Abstract: A method of manufacturing a driving backplane for display includes: forming a first conductive pattern layer including first conductive lines on a base; and forming a second conductive pattern layer including electrode groups and second conductive lines on a side of the first conductive pattern layer away from the base. The first conductive lines and the second conductive lines cross and are insulated from each other; an electrode group includes a first electrode and a second electrode electrically connected to a corresponding second conductive line. Orthogonal projections, on the base, of the first electrode and a corresponding first conductive line have an overlapping region, and a portion of the first electrode, whose orthogonal projection on the base is located in the overlapping region, is in contact with a portion of the first conductive line, whose orthogonal projection on the base is located in the overlapping region.

Abstract: A semiconductor device, an integrated circuit, and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a thin-film transistor (TFT) over the substrate, and a magnetoresistive random-access memory (MRAM) cell electrically coupled to the TFT. The TFT includes a gate electrode; an active layer disposed above the gate electrode; source/drain electrodes disposed above the gate electrode and separated by the active layer; and at least two dielectric layers disposed between the gate electrode and the source/drain electrodes.

Abstract: Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.

Abstract: Disclosed is a digital display system based on a common interface. More particularly, a cluster pixel circuit includes a row terminal connected to a row line for receiving PWM (Pulse Width Modulation) clock signal; a column terminal connected to a column line for receiving N-bit data; a first individual pixel driver for driving a first pixel in the cluster pixel; and a second individual pixel driver connected to the first individual pixel driver and for driving a second pixel in the cluster pixel.

Abstract: An electronic device includes a carrier, a plurality of electronic elements and a connecting terminal. The carrier has at least one bonding pad. The electronic elements are disposed on the carrier, and each of the electronic elements includes a substrate. A distance between two adjacent substrates of the electronic elements is not less than 300 ?m. The connecting terminal is disposed between one of the substrate and the carrier. One of the electronic elements are electrically connected to the at least one bonding pad via the connecting terminal.

Abstract: An active matrix substrate includes a thin film transistor including an oxide semiconductor layer, an interlayer insulating layer covering the thin film transistor, a pixel electrode provided above the interlayer insulating layer and electrically connected to the thin film transistor, a common electrode provided between the pixel electrode and the interlayer insulating layer, a first dielectric layer provided between the common electrode and the pixel electrode, and an alignment film covering the pixel electrode. The first dielectric layer includes a plurality of openings each of which exposes a part of the common electrode and includes the alignment film positioned therein.

Abstract: A transistor including an oxide semiconductor layer can have stable electrical characteristics. In addition, a highly reliable semiconductor device including the transistor is provided. A semiconductor device includes a multi-layer film including an oxide layer and an oxide semiconductor layer, a gate insulating film in contact with the multi-layer film, and a gate electrode overlapping with the multi-layer film with the gate insulating film provided therebetween. In the semiconductor device, the oxide semiconductor layer contains indium, the oxide semiconductor layer is in contact with the oxide layer, and the oxide layer contains indium and has a larger energy gap than the oxide semiconductor layer.

Abstract: An integrated circuit includes: a gate dielectric; a first layer adjacent to the gate dielectric; a second layer adjacent to the first layer, the second layer comprising an amorphous material; a third layer adjacent to the second layer, the third layer comprising a crystalline material; and a source or drain at least partially adjacent to the third layer. In some cases, the crystalline material of the third layer is a first crystalline material, and the first layer comprises a second crystalline material, which may be the same as or different from the first crystalline material. In some cases, the gate dielectric includes a high-K dielectric material. In some cases, the gate dielectric, the first layer, the second layer, the third layer, and the source or drain are part of a back-gate transistor structure (e.g., back-gate TFT), which may be part of a memory structure (e.g., located within an interconnect structure).

Abstract: A transistor in an embodiment includes an oxide semiconductor layer on a substrate, the oxide semiconductor layer including a first region and a second region, a first gate electrode including a region overlapping the oxide semiconductor layer, the first gate electrode being arranged on a surface of the oxide semiconductor layer opposite to the substrate, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a first oxide conductive layer and a second oxide conductive layer between the oxide semiconductor layer and the substrate, the first oxide conductive layer and the second oxide conductive layer each including a region in contact with the oxide semiconductor layer.

Abstract: A more convenient and highly reliable semiconductor device which has a transistor including an oxide semiconductor with higher impact resistance used for a variety of applications is provided. A semiconductor device has a bottom-gate transistor including a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer over a substrate, an insulating layer over the transistor, and a conductive layer over the insulating layer. The insulating layer covers the oxide semiconductor layer and is in contact with the gate insulating layer. In a channel width direction of the oxide semiconductor layer, end portions of the gate insulating layer and the insulating layer are aligned with each other over the gate electrode layer, and the conductive layer covers a channel formation region of the oxide semiconductor layer and the end portions of the gate insulating layer and the insulating layer and is in contact with the gate electrode layer.

Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a resistance change layer disposed on the substrate, a gate electrode layers disposed on the resistance change layer, and a first electrode pattern layer and a second electrode pattern layer that are disposed in the substrate and contact different portions of the resistance change layer. The resistance change layer includes movable oxygen vacancies or movable metal ions.

Abstract: The present invention provides an array substrate and a manufacturing method thereof, and a display panel. According to the present disclosure, a portion of a surface of an interlayer insulating layer of the array substrate away from a substrate is depressed to form a first groove, a portion of a surface of the first groove near a bottom surface of the substrate is depressed until a surface of an active layer away from the substrate forms a second groove, and the first groove and the second groove are connected with each other to form a through-hole.

Abstract: A metal oxide film containing a crystal part is provided. Alternatively, a metal oxide film with highly stable physical properties is provided. Alternatively, a metal oxide film with improved electrical characteristics is provided. Alternatively, a metal oxide film with which field-effect mobility can be increased is provided. A metal oxide film including In, M (M is Al, Ga, Y, or Sn), and Zn includes a first crystal part and a second crystal part; the first crystal part has c-axis alignment; the second crystal part has no c-axis alignment; and the existing proportion of the second crystal part is higher than the existing proportion of the first crystal part.

Abstract: An object of the disclosure is to provide a semiconductor device with low-loss and suppressed leakage current, which is particularly useful for power devices. A semiconductor device including a semiconductor layer including an oxide semiconductor having a corundum structure as a main component, and a Schottky electrode including a first electrode layer and a second electrode layer having a higher conductivity than the first electrode layer, wherein an outer edge portion of the second electrode layer is electrically connected to the semiconductor layer at an electrical connection region through the first electrode layer, and an outer edge portion of the first electrode layer is located outside an outer edge portion of the electrical connection region.

Abstract: An active element and a manufacturing method thereof are provided. The active element includes a substrate, a switching bottom gate and a driving bottom gate disposed on the substrate, a first gate insulating layer disposed on the substrate and covering the switching bottom gate and the driving bottom gate, a switching channel and a driving channel disposed on the first gate insulating layer, a second gate insulating layer disposed on the first gate insulating layer and covering the switching channel and the driving channel, and a switching top gate and a driving top gate disposed on the second gate insulating layer. The driving channel has a low potential end electrically connected to the driving bottom gate. A thickness of the second gate insulating layer is greater than a thickness of the first gate insulating layer. The switching top gate is electrically connected to the switching bottom gate.

Abstract: A semiconductor device includes an oxide semiconductor layer including indium, a gate electrode facing the oxide semiconductor layer, a gate insulating layer between the oxide semiconductor layer and the gate electrode, and a first electrode arranged above the oxide semiconductor layer and being in contact with the oxide semiconductor layer from above the oxide semiconductor layer. The indium is unevenly distributed in an unevenly distributed region among the oxide semiconductor layer. The unevenly distributed region overlaps with the first conductive layer in a planar view.

Abstract: A display substrate, a display panel, and a display device are provided. The display substrate includes: a base substrate; and a first transistor on the base substrate. The first transistor includes a first active layer, a first bottom gate electrode between the base substrate and the first active layer, and a first top gate electrode on a side of the first active layer away from the base substrate. A third gate insulating layer is provided between the first bottom gate electrode and the first active layer. The first active layer contains an oxide semiconductor material, and the third gate insulating layer contains a silicon oxide material. A surface of the first bottom gate electrode away from the base substrate is in direct contact with the silicon oxide material, and a surface of the first active layer close to the base substrate is in direct contact with the silicon oxide material.

Abstract: Discussed is a display device including a display panel that includes a substrate, a light shield layer disposed on the substrate, a light emitting element layer disposed on the light shield layer and including a plurality of subpixels, an encapsulation layer disposed on the light emitting element layer, and a polarizing layer disposed on the encapsulation layer, and a sensor disposed under the display panel. A display area of the display panel includes a main display area and a sensor area. The sensor is arranged to photoelectrically convert light received through the sensor area of the display panel, and the sensor area includes a radial pattern.

Abstract: A metal oxide film includes indium, M, (M is Al, Ga, Y, or Sn), and zinc and includes a region where a peak having a diffraction intensity derived from a crystal structure is observed by X-ray diffraction in the direction perpendicular to the film surface. Moreover, a plurality of crystal parts is observed in a transmission electron microscope image in the direction perpendicular to the film surface. The proportion of a region other than the crystal parts is higher than or equal to 20% and lower than or equal to 60%.

Abstract: A display panel and its fabrication method, and a display device are provided in the present disclosure. The display panel includes a substrate, including a display region; a light-emitting diode (LED) array at the display region, where the LED array includes a plurality of LED units arranged in an array; and a pulse-width modulation chip array at the display region, where the pulse-width modulation chip array includes a plurality of pulse-width modulation chips arranged in an array. The plurality of LED units is electrically connected to the plurality of pulse-width modulation chips in a one-to-one correspondence; and a pulse-width modulation chip of the plurality of pulse-width modulation chips is configured to adjust a light-emitting duration of a corresponding LED unit electrically connected thereto.

Abstract: A display device includes a substrate including a display area and a pad area, a lower electrode, a light emitting layer, an upper electrode on the light emitting layer, and a pad electrode in the pad area. The lower electrode is in the display area, the lower electrode including a first electrode, a second electrode, and a third electrode. The first electrode has a first etching rate with respect to an etching process. The second electrode is on the first electrode. The second electrode has a second etching rate with respect to the etching process that is higher than the first etching rate. The third electrode is on the second electrode. The third electrode has a third etching rate with respect to the etching process that is lower than the second etching rate and higher than the first etching rate. The light emitting layer is over the first electrode.

Abstract: A display device may include a first gate electrode on a substrate, a buffer layer on the first gate electrode, a first active pattern on the buffer layer, overlapping the first gate electrode, and including an oxide semiconductor, a source pattern and a drain pattern respectively on ends of the first active pattern, an insulation layer overlapping the source pattern and the drain pattern on the buffer layer, an oxygen supply pattern on the insulation layer, overlapping the first active pattern, and supplying oxygen to the first active pattern, a second active pattern on the insulation layer and spaced apart from the oxygen supply pattern, the second active pattern including a channel region, and a source region and a drain region, an insulation pattern on the channel region of the second active pattern, and a second gate electrode on the insulation pattern.

Abstract: A flexible circuit board according to an embodiment of the present invention comprises: a substrate; a first wiring pattern layer disposed on a first surface of the substrate; a second wiring pattern layer disposed on a second surface opposite the first surface of the substrate; a first dummy pattern part disposed on the second surface of the substrate on which the second wiring pattern layer is not disposed; a first protection layer disposed on the first wiring pattern layer; and a second protection layer disposed on the second wiring pattern layer and the first dummy pattern part, wherein at least a part of the first dummy pattern part overlaps with the first wiring pattern layer in a vertical direction.

Abstract: The present disclosure provides a display panel and a display panel manufacturing method. The display panel includes a drive circuit layer, a color photoresist layer disposed on the drive circuit layer, a common electrode layer disposed on the color photoresist layer, and a pixel electrode layer disposed on the common electrode layer. The drive circuit layer is provided with a common wire, the common electrode layer is provided with a transparent electrode, the transparent electrode is electrically connected to the common wire, and the pixel electrode layer is provided with a plurality of pixel electrodes.

Abstract: A memory device with large storage capacity is provided. A NAND memory device includes a plurality of connected memory cells each provided with a writing transistor, a reading transistor, and a capacitor. An oxide semiconductor is used in a semiconductor layer of the writing transistor. The reading transistor includes a back gate. When a reading voltage is applied to the back gate, information stored in the memory cell is read out.

Abstract: A semiconductor memory device with improved performance by improving interface characteristics while reducing a leakage current, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line on a substrate, a first interlayer insulating layer exposing the conductive line and defining a channel trench on the substrate, a channel layer extending along a bottom and side surface of the channel trench, a first gate electrode and a second gate electrode spaced apart from each other in the channel trench, a first gate insulating layer between the channel layer and the first gate electrode, and a second gate insulating layer between the channel layer and the second gate electrode. The channel layer includes a first oxide semiconductor layer and a second oxide semiconductor layer sequentially stacked on the conductive line. The first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer.

Abstract: A display panel includes: a substrate including a first area, a second area at least partially surrounding the first area, and an intermediate area between the first area and the second area; an insulating layer on the substrate; a plurality of display elements in the second area, and each including a pixel electrode, an opposite electrode, and an intermediate layer between the pixel electrode and the opposite electrode; a groove in the intermediate area; a thin-film encapsulation layer covering the plurality of display elements, and including an inorganic encapsulation layer and an organic encapsulation layer; and an inorganic layer over the thin-film encapsulation layer, wherein at least one sub-layer included in the intermediate layer is disconnected around the groove, and the inorganic layer directly contacts the insulating layer beyond an edge of the at least one sub-layer located in the intermediate area and an edge of the inorganic encapsulation layer.

Abstract: A transistor including an oxide semiconductor layer can have stable electrical characteristics. In addition, a highly reliable semiconductor device including the transistor is provided. A semiconductor device includes a multi-layer film including an oxide layer and an oxide semiconductor layer, a gate insulating film in contact with the multi-layer film, and a gate electrode overlapping with the multi-layer film with the gate insulating film provided therebetween. In the semiconductor device, the oxide semiconductor layer contains indium, the oxide semiconductor layer is in contact with the oxide layer, and the oxide layer contains indium and has a larger energy gap than the oxide semiconductor layer.

Abstract: The present invention provides an array substrate and a display panel. The array substrate includes: an underlay; a source electrode and drain electrode disposed on underlay; a light shielding portion disposed on underlay; an active layer correspondingly disposed on the source electrode, the drain electrode, and the light shielding portion. The active layer includes a channel region, and the light shielding portion is disposed to correspond to the channel region. The present invention reduces processes and lowers cost by disposing the source electrode, the drain electrode, and the light shielding portion in a same layer such that the source electrode, the drain electrode, and the light shielding portion are simultaneously formed with a same material by a same process.

Abstract: An array substrate and a manufacturing method thereof, and a display panel are disclosed. The array substrate includes a substrate, a switching transistor, and a driving transistor. The switching transistor and the driving transistor are disposed on the substrate. An orthogonal projection of the switching transistor on the substrate is staggered from an orthogonal projection of the driving transistor on the substrate. A mobility of the switching transistor is greater than a mobility of the driving transistor, and a threshold voltage of the driving transistor is less than a threshold voltage of the switching transistor.

Abstract: A liquid crystal display device includes a transistor, a pixel electrode, and a common electrode. The transistor includes a first gate electrode on a first substrate, a second gate electrode having a region overlapping the first gate electrode, an oxide semiconductor layer between the first gate electrode and the second gate electrode, a first insulating layer between the first gate electrode and the oxide semiconductor layer, a second insulating layer between the oxide semiconductor layer and the second gate electrode, and a first oxide conductive layer and a second oxide conductive layer disposed between the first insulating layer and the oxide semiconductor layer and disposed with the first gate electrode and the second gate electrode sandwiched from both sides. The pixel electrode is disposed between the first and the second insulating layer; the common electrode is disposed a region overlapping with the pixel electrode and on the second insulating layer.

Abstract: A display panel includes a substrate including a first opening and a second opening that are spaced apart from each other, a plurality of pixels located in a display area around the first opening and the second opening, each of the plurality of pixels including a pixel circuit including a first thin-film transistor, and a display element connected to the pixel circuit, a bottom metal layer located between the substrate and the first thin-film transistor, emission control lines located on the substrate, extending in a first direction and spaced apart from each other by the first opening and the second opening, and a first conductive layer located in an intermediate area surrounding each of the first opening and the second opening to bypass the first opening and the second opening.

Abstract: A display panel and a display device are provided. By manufacturing a first via hole and a second via hole first, and then manufacturing a third via hole and a fourth via hole, the first via hole and the second via hole have been covered by a corresponding first drain electrode and first source electrode before performing hydrofluoric acid cleaning processes, and a first drain region and a first source region of a first oxide transistor are not affected by the hydrofluoric acid cleaning process, thereby allowing an oxide channel of the first oxide transistor to also be prevented from being affected.

Abstract: A highly reliable semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes a first insulator; a first conductor and a second conductor over the first insulator; an oxide provided between the first conductor and the second conductor; a second insulator over the first conductor, the second conductor, and the oxide; and a third conductor over the second insulator. A side surface of the first conductor includes a region in contact with one side surface of the oxide, a side surface of the second conductor includes a region in contact with the other side surface of the oxide. The level of a top surface of the first conductor, the level of a top surface of the second conductor, and the level of a top surface of the oxide are substantially the same. The conductivity of the first conductor is higher than that of the oxide, and the conductivity of the second conductor is higher than that of the oxide.

Abstract: An electronic device includes a substrate, a first conductive wire, a plurality of semiconductors, an insulation layer and a plurality of conductive elements. The first conductive wire is disposed on the substrate and extends along a first direction. The semiconductors are disposed on the substrate and arranged along the first direction. The semiconductors are overlapped with the first conductive wire in a top view of the electronic device. The insulation layer is disposed between the first conductive wire and the semiconductors. The insulation layer includes a plurality of holes. The conductive elements are disposed on the substrate and overlapped with the semiconductors respectively in the top view of the electronic device. In the top view of the electronic device, each one of the holes overlaps with at least one semiconductor, and a number of the holes is less than a number of the conductive elements.

Abstract: A display panel includes a first thin-film transistor (“TFT”) arranged in a display area of a substrate and including a first semiconductor layer including a silicon semiconductor, a second TFT connected to the first TFT and including a second semiconductor layer including an oxide semiconductor, a voltage line connected to the first TFT, and a shield layer arranged between the substrate and the first semiconductor layer, and including a pattern and a connection line, the pattern overlapping the first semiconductor layer, the connection line extending from the pattern, and a voltage that is a same as a voltage applied to the voltage line being applied to the shield layer.

Abstract: A first transistor, a second transistor, a capacitor, and first to third conductors are included. The first transistor includes a first gate, a source, and a drain. The second transistor includes a second gate, a third gate over the second gate, first and second low-resistance regions, and an oxide sandwiched between the second gate and the third gate. The capacitor includes a first electrode, a second electrode, and an insulator sandwiched therebetween. The first low-resistance region overlaps with the first gate. The first conductor is electrically connected to the first gate and is connected to a bottom surface of the first low-resistance region. The capacitor overlaps with the first low-resistance region. The second conductor is electrically connected to the drain. The third conductor overlaps with the second conductor and is connected to the second conductor and a side surface of the second low-resistance region.

Abstract: Provided is a structure of a transistor, which enables a so-called normally-off switching element, and a manufacturing method thereof. Provided is a structure of a semiconductor device which achieves high-speed response and high-speed operation by improving on characteristics of a transistor, and a manufacturing method thereof. Provided is a highly reliable semiconductor device. In the transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating layer, and a gate electrode layer are stacked in that order. As the semiconductor layer, an oxide semiconductor layer which contains at least four kinds of elements of indium, gallium, zinc, and oxygen, and has a composition ratio (atomic percentage) of indium as twice or more as a composition ratio of gallium and a composition ratio of zinc, is used.

Abstract: A display device includes a gate electrode, a gate insulating film, a first metal oxide layer having crystallinity, and a second metal oxide layer having non-crystallinity. The first metal oxide layer and the second metal oxide layer are sequentially laminated on a substrate. The first metal oxide layer and the second metal oxide layer are in contact with each other in all regions where the first metal oxide layer and the second metal oxide layer overlap each other. The first metal oxide layer at least partially has a first semiconductor region serving as a semiconductor. One of the first metal oxide layer and the second metal oxide layer at least partially has a conductor region made electrically conductive.

Abstract: A plurality of thin film transistors provided in a peripheral region are first staggered thin film transistors where a first channel layer configured of low-temperature polysilicon is included, and the first channel layer is not interposed between a first source electrode and a first gate electrode, and between a first drain electrode and the first gate electrode. A plurality of thin film transistors provided in a display region are second staggered thin film transistors where a second channel layer configured of an oxide semiconductor is included, and the second channel layer is not interposed between a second source electrode and a second gate electrode, and between a second drain electrode and the second gate electrode. The first thin film transistor is located below the second thin film transistor.

Abstract: An array substrate structure is provided, which includes a substrate with a first surface and a second surface opposite to the first surface. A first TFT is on the first surface of the substrate, and a second TFT is on the second surface of the substrate. A through via passes through the substrate, and the first TFT is electrically connected to the second TFT through the through via.