Semiconductor Is An Oxide Of A Metal (e.g., Cuo, Zno) Or Copper Sulfide Patents (Class 257/43)
  • Patent number: 11152401
    Abstract: The flexible display substrate provided by the present disclosure includes a flexible substrate, on which at least one conductive composite layer is disposed, each of the at least one conductive composite layer includes two metal layers and an insulated layer between the two metal layers, each of the two metal layers includes metal line segments separated from each other, the insulated layer is provided with contact holes, and the metal line segments in the two metal layers are connected through metal in the contact holes to form a continuous metal wire.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: October 19, 2021
    Assignee: Kunshan New Flat Panel Display Technology Center Co., Ltd.
    Inventors: Bo Yuan, Yucheng Liu, Sheng Gao, Lin Xu
  • Patent number: 11152513
    Abstract: A semiconductor device with favorable reliability is provided. The semiconductor device includes a first insulator; a second insulator positioned over the first insulator; an oxide positioned over the second insulator; a first conductor and a second conductor positioned apart from each other over the oxide; a third insulator positioned over the oxide, the first conductor, and the second conductor; a third conductor positioned over the third insulator and at least partly overlapping with a region between the first conductor and the second conductor; a fourth insulator positioned to cover the oxide, the first conductor, the second conductor, the third insulator, and the third conductor; a fifth insulator positioned over the fourth insulator; and a sixth insulator positioned over the fifth insulator.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: October 19, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshinobu Asami, Takahisa Ishiyama, Motomu Kurata, Ryo Tokumaru, Noritaka Ishihara, Yusuke Nonaka
  • Patent number: 11153457
    Abstract: A light receiving unit includes photoelectric conversion elements (20) in which first pixels (201) are arrayed linearly along a long side of a parallelogram-shaped semiconductor substrate (22) and second pixels (202) are arrayed linearly at a location separated away from the first pixels (201) by a predetermined interpolation pixel distance. An output data processor that generates image data based on outputs of the photoelectric conversion elements (20) performs time correction of the image data by coupling image data based on outputs of the second pixels (202) with image data based on outputs of the first pixels (201) that have a time shift equal to a scanning time corresponding to the interpolation pixel distance.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: October 19, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Masatoshi Kodama, Masaki Ono, Mikio Uesugi, Takahiro Ishihara
  • Patent number: 11152399
    Abstract: A display device in which a display area and a non-display area are defined, the display device including a wiring substrate, the wiring substrate including: a base substrate; a first thin film transistor disposed on the base substrate, located in the non-display area, and including a first gate pattern, a first semiconductor pattern disposed on the first gate pattern, a first source pattern disposed on the first semiconductor pattern, and a first drain pattern disposed on the first semiconductor pattern and spaced apart from the first source pattern; and a second thin film transistor disposed on the base substrate and located in the display area. A first channel width of the first thin film transistor is greater than a first overlap length of the first gate pattern, the first semiconductor pattern, and the first drain pattern.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: October 19, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yeon Keon Moon, Kano Masataka, Myoung Hwa Kim, Jun Hyung Lim
  • Patent number: 11152472
    Abstract: A crystalline oxide semiconductor with excellent crystalline qualities that is useful for semiconductors requiring heat dissipation is provided. A crystalline oxide semiconductor including a first crystal axis, a second crystal axis, a first side, and a second side that is shorter than the first side, a linear thermal expansion coefficient of the first crystal axis is smaller than a linear thermal expansion coefficient of the second crystal axis, a direction of the first side is parallel and/or substantially parallel to a direction of the first crystal axis, and a direction of the second side is parallel and/or substantially parallel to a direction of the second crystal axis.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: October 19, 2021
    Assignees: FLOSFIA INC., DENSO CORPORATION
    Inventors: Isao Takahashi, Tatsuya Toriyama, Masahiro Sugimoto, Takashi Shinohe, Hideyuki Uehigashi, Junji Ohara, Fusao Hirose, Hideo Matsuki
  • Patent number: 11151920
    Abstract: A demultiplexer for sequentially outputting a data signal to a plurality of data lines disposed in a display panel can include a first switch connected to a first control node, the first switch being configured to electrically connect a first channel with a first data line among the plurality of data lines; a second switch connected to a second control node, the first switch being configured to electrically connect the first channel with a second data line among the plurality of data lines; a third switch connected to a third control node, the third switch being configured to electrically connect a second channel with a third data line among the plurality of data lines; and a fourth switch connected to a fourth control node, the fourth switch being configured to electrically connect the second channel with a fourth data line among the plurality of data lines, in which the first control node and the third control node are configured to receive a single first control signal, and be electrically disconnected fro
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: October 19, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Yewon Hong, JungHyun Lee, TaeWoong Moon
  • Patent number: 11152494
    Abstract: To reduce defects in an oxide semiconductor film in a semiconductor device. To improve the electrical characteristics and the reliability of a semiconductor device including an oxide semiconductor film. In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: October 19, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Yukinori Shima, Hajime Tokunaga, Toshinari Sasaki, Keisuke Murayama, Daisuke Matsubayashi
  • Patent number: 11143925
    Abstract: An object is to provide a display device that performs accurate display. A circuit is formed using a transistor that includes an oxide semiconductor and has a low off-state current. A precharge circuit or an inspection circuit is formed in addition to a pixel circuit. The off-state current is low because the oxide semiconductor is used. Thus, it is not likely that a signal or voltage is leaked in the precharge circuit or the inspection circuit to cause defective display. As a result, a display device that performs accurate display can be provided.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: October 12, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Atsushi Umezaki
  • Patent number: 11145731
    Abstract: Provided are an electronic device including a dielectric layer having an adjusted crystal orientation and a method of manufacturing the electronic device. The electronic device includes a seed layer provided on a substrate and a dielectric layer provided on the seed layer. The seed layer includes crystal grains having aligned crystal orientations. The dielectric layer includes crystal grains having crystal orientations aligned in the same direction as the crystal orientations of the seed layer.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: October 12, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Taehwan Moon, Eunha Lee, Junghwa Kim, Hyangsook Lee, Sanghyun Jo, Jinseong Heo
  • Patent number: 11145764
    Abstract: A display device includes a pixel layer for displaying an image and a circuit layer including a thin film transistor for driving the pixel layer. The thin film transistor includes a semiconductor layer including a channel region and a source region and a drain region sandwiching the channel region, a first gate electrode facing the channel region on a first side which is either above or below the semiconductor layer, a second gate electrode facing at least the channel region and the source region on a second side opposite to the first side, a source electrode connected to the source region, and a drain electrode connected to the drain region. The source electrode penetrates through the semiconductor layer and is connected to the second gate electrode on the second side.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: October 12, 2021
    Assignee: Japan Display Inc.
    Inventor: Hidekazu Miyake
  • Patent number: 11145766
    Abstract: An active matrix substrate of an embodiment of the present invention includes a substrate and a plurality of oxide semiconductor TFTs supported on the substrate. Each oxide semiconductor TFT includes a lower gate electrode provided on the substrate, a gate insulating layer covering the lower gate electrode, an oxide semiconductor layer provided on the gate insulating layer, a source electrode which is in contact with the source contact region of the oxide semiconductor layer, a drain electrode which is in contact with the drain contact region of the oxide semiconductor layer, an insulating layer covering the oxide semiconductor layer, the source electrode and the drain electrode, and an upper gate electrode provided on the insulating layer.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: October 12, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yujiro Takeda, Hiroshi Matsukizono, Akihiro Oda, Shogo Murashige, Kohhei Tanaka
  • Patent number: 11138929
    Abstract: A display device includes a pixel including a light emitting element connected to a scan line and a data line; a driving transistor that controls a driving current supplied to the light emitting element according to a data voltage applied from the data line. The driving transistor includes a first semiconductor layer, and a first gate electrode disposed on the first semiconductor layer. The display device includes a switching transistor that applies the data voltage to the driving transistor according to a scan signal applied to the scan line. The switching transistor includes a second semiconductor layer, and a second gate electrode disposed on the second semiconductor layer. The display device includes a light blocking layer and a first buffer layer disposed at a lower portion of the driving transistor. The light blocking layer and the first buffer layer do not overlap the switching transistor.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: October 5, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Joon Seok Park, Yeon Keon Moon, Myoung Hwa Kim, Tae Sang Kim, Hyung Jun Kim, Geun Chul Park, Sang Woo Sohn, Jun Hyung Lim, Kyung Jin Jeon, Hye Lim Choi
  • Patent number: 11139321
    Abstract: A drive backplane, a display panel, an electronic apparatus, and a method for preparing a drive backplane are provided in embodiments of the disclosure, all relating to the technical field of display technology, the drive backplane including: a base substrate; a driving device layer on the base substrate, comprising an electrode layer; a planarization layer, on a surface of the driving device layer facing away from the base substrate, and the planarization layer being provided with at least one projection portion and at least one base portion adjacent to the at least one projection portion both on a surface of the planarization layer facing away from the driving device layer, each projection portion having a greater thickness than that of each base portion; a conductive layer, on respective surface of each projection portion facing away from the driving device layer, the conductive layer being connected with the electrode layer of the driving device layer; a spacer layer, on a surface of the conductive layer
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: October 5, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Haixu Li
  • Patent number: 11133364
    Abstract: A light emitting diode display device includes a substrate, a first layer disposed on the substrate, a first transistor disposed on the first layer and including a first gate electrode, and a light emitting diode connected to the first transistor, wherein the first layer may overlap the first gate electrode, and may include a first region including a first material and a second region including a second material different from the first material, the first material may include amorphous silicon doped with impurities, and the second material may include amorphous silicon.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: September 28, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jun-Woo Hyung, Young-Cheol Jeong, Seung-Hoon Lee, Young-Ran Son, Jee-Hyun Lee
  • Patent number: 11133418
    Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: September 28, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Chen Chen, Xiao Wu, Hai Tao Liu, Ming Hua Du, Shouguo Zhang, Yao-Hung Liu, Chin-Fu Lin, Chun-Yuan Wu
  • Patent number: 11133420
    Abstract: A semiconductor device with high on-state current is provided.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: September 28, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Iida, Ryota Hodo, Kentaro Sugaya, Ryu Komatsu, Toshiya Endo, Shunpei Yamazaki
  • Patent number: 11127762
    Abstract: A semiconductor device includes a semiconductor film, a semiconductor auxiliary film, a wiring line, a first metal film, and an interlayer insulating film. The semiconductor film includes a channel region and a low-resistance region. The semiconductor film includes indium and oxygen. The semiconductor auxiliary film is in contact with the low-resistance region of the semiconductor film and reduces the electric resistance of the semiconductor film. The wiring line is electrically coupled to the low-resistance region of the semiconductor film. The first metal film covers the wiring line and has a higher standard electrode potential than the indium. The interlayer insulating film covers the semiconductor film with the first metal film interposed therebetween. The interlayer insulating film has a first hole and a second hole. The first hole is provided at a position opposed to the low-resistance region of the semiconductor film. The second hole reaches the first metal film.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: September 21, 2021
    Assignee: JOLED INC.
    Inventors: Eri Matsuo, Yasuhiro Terai
  • Patent number: 11127768
    Abstract: Provided are an array substrate, a display panel, a display device and a method for manufacturing the array substrate. The array substrate includes a first thin film transistor and a second thin film transistor. The first thin film transistor includes a first active layer, a first gate, a first A-type electrode and a first B-type electrode. The second thin film transistor includes a second active layer, a second gate, a second A-type electrode and a second B-type electrode. In a direction perpendicular to a plane where a substrate is located, a film where the first active layer is located, a film where the first A-type electrode is located, a film where the first B-type electrode is located, and a film where the first gate electrode is located each are disposed between a film where the second active layer is located and the substrate.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: September 21, 2021
    Assignee: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventor: Jujian Fu
  • Patent number: 11127353
    Abstract: A display device and a signal inversion device are provided. A display device includes: a display panel including: sub-pixels, and scan lines respectively connected to each of the sub-pixels, and light emission control lines respectively connected to each of the sub-pixels, a scan driver circuit for outputting respective scan signals to the scan lines, and a light emission control driver circuit for outputting respective light emission control signals to the light emission control lines, the light emission control driver circuit including: a resistance device electrically connected between: a first voltage node for receiving a first voltage, and an output node electrically connected to the light emission control lines, and a transistor electrically connected between the output node and a second voltage node for receiving a second voltage that is different from the first voltage, wherein an on/off operation of the transistor is controlled according to an input signal.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: September 21, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: Dohyung Lee, ChanYong Jeong, JuHeyuck Baeck, Kwangll Chun
  • Patent number: 11127711
    Abstract: According to one embodiment, a semiconductor device includes a first wafer, a first wiring layer, a first insulating layer, a first electrode, a second wafer, a second wiring layer, a second insulating layer, a second electrode, and a first layer. The first electrode includes a first surface, a second surface, a third surface, and a fourth surface. The second electrode includes a fifth surface, a sixth surface, a seventh surface, a second side surface, and an eighth surface. The first layer is provided between the fourth surface and a portion of the first insulating layer that surrounds the fourth surface, and is provided away from the third surface in the first direction.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: September 21, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Masato Shini
  • Patent number: 11127766
    Abstract: A display panel includes a base layer including a first area and a second area. At least one inorganic layer disposed on the base layer overlaps the first area and the second area. The at least one inorganic layer comprises a lower opening. A first thin-film transistor is disposed on the at least one inorganic layer. The first thin-film transistor includes a silicon semiconductor pattern. A second thin-film transistor is disposed on the at least one inorganic layer. The second thin-film transistor includes an oxide semiconductor pattern. A plurality of insulation layers overlap the first area and the second area. An upper opening extends from the lower opening. A signal line is electrically connected to the second thin-film transistor. An organic layer is disposed in the lower opening and the upper opening. A light emitting element is disposed on the organic layer.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: September 21, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yoon-jong Cho, Seokje Seong, Seongjun Lee, Yoonjee Shin, Suyeon Yun, Wooho Jeong, Joonhoo Choi
  • Patent number: 11121260
    Abstract: A thin-film transistor, a display device including a thin-film transistor, and a method of manufacturing a thin-film transistor are provided. A thin-film transistor includes: a base substrate, a semiconductor layer on the base substrate, the semiconductor layer including: a first oxide semiconductor layer, and a second oxide semiconductor layer on the first oxide semiconductor layer, the second oxide semiconductor layer having a Hall mobility smaller than a Hall mobility of the first oxide semiconductor layer, and a gate electrode spaced apart from the semiconductor layer and partially overlapping the semiconductor layer, wherein a concentration of gallium (Ga) in the second oxide semiconductor layer is higher than a concentration of gallium (Ga) in the first oxide semiconductor layer.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: September 14, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: SeHee Park, JungSeok Seo, PilSang Yun, Jeyong Jeon, Jaeyoon Park, ChanYong Jeong
  • Patent number: 11121261
    Abstract: A semiconductor substrate includes a substrate, a first metal oxide semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, and a second metal oxide semiconductor layer. The first transistor includes a first metal oxide semiconductor pattern of the first metal oxide semiconductor layer, a first gate of the first conductive layer, a first source of the second conductive layer, and a first drain of the second conductive layer. The second transistor includes a second metal oxide semiconductor pattern of the first metal oxide semiconductor layer, a second gate of the first conductive layer, a second source of the second conductive layer, a second drain of the second conductive layer, and a third metal oxide semiconductor pattern of the second metal oxide semiconductor layer.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: September 14, 2021
    Assignee: Au Optronics Corporation
    Inventors: Wei-Ting Lin, Dean Wang, Chun-Cheng Cheng
  • Patent number: 11121262
    Abstract: A semiconductor device includes a thin film transistor including: a substrate 1; a gate electrode 2 supported on the substrate 1; a semiconductor layer 4 provided on the gate electrode with a gate insulating layer 3 therebetween, wherein the semiconductor layer includes a first region Rs, a second region Rd, and a source-drain interval region SG that is located between the first region and the second region and overlaps with the gate electrode as seen from a direction normal to the substrate; a first contact layer Cs in contact with the first region and a second contact layer Cd in contact with the second region; a source electrode 8s electrically connected to the first region with the first contact layer therebetween; and a drain electrode 8d electrically connected to the second region with the second contact layer therebetween, wherein: the semiconductor layer includes a crystalline silicon region 4c, and at least a portion of the crystalline silicon region is located in the source-drain interval region SG;
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: September 14, 2021
    Assignee: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventors: Shigeru Ishida, Tomohiro Inoue, Ryohei Takakura
  • Patent number: 11112665
    Abstract: A display device may include a first base, a metal oxide layer overlapping a face of the first base, and a conductive metal layer directly contacting the metal oxide layer. The metal oxide layer may include molybdenum oxide. A side of the metal oxide layer may be oriented at a first angle relative to the face of the first base. A side of the conductive metal layer may be oriented at a second angle relative to the face of the first base. A size of the second angle may be in a range of 30° to 75°.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: September 7, 2021
    Inventors: Ju Hyun Lee, Gyung Min Baek, Hyun Eok Shin, Hong Sick Park, Sang Won Shin
  • Patent number: 11114474
    Abstract: A thin film transistor (TFT), a manufacturing method thereof, an array substrate and a display panel are disclosed. The manufacturing method includes: providing a base substrate; forming a first electrode, an isolating layer, an active layer and a gate insulating layer on the base substrate; simultaneously forming a second electrode and a gate electrode, wherein the second electrode is connected to the active layer.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: September 7, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Lianjie Qu
  • Patent number: 11107926
    Abstract: A new and useful oxide semiconductor film with enhanced p-type semiconductor property and the method of manufacturing the oxide semiconductor film are provided. A method of manufacturing an oxide semiconductor film including: generating atomized droplets by atomizing a raw material solution containing a metal of Group 9 of the periodic table and/or a metal of Group 13 of the periodic table and a p-type dopant; carrying the atomized droplets onto a surface of a base by using a carrier gas; causing a thermal reaction of the atomized droplets adjacent to the surface of the base under oxygen atmosphere to form the oxide semiconductor film on the base.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: August 31, 2021
    Assignee: FLOSFIA INC.
    Inventors: Tomochika Tanikawa, Toshimi Hitora
  • Patent number: 11107844
    Abstract: A display device can include a first thin film transistor including a first active layer including a first semiconductor material, a first gate electrode overlapping with the first active layer, and a first source electrode and a first drain electrode both electrically connected to the first active layer; a separation insulating layer disposed on the first thin film transistor; and a second thin film transistor disposed on the separation insulating layer and including: a second active layer including a second semiconductor material different from the first semiconductor material, a second gate electrode overlapping with the second active layer, and a second source electrode and a second drain electrode both electrically connected to the second active layer, in which the second active layer of the second thin film transistor has a first thickness and a second thickness greater than the first thickness.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: August 31, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: SoYeon Je, Hyuk Ji
  • Patent number: 11101257
    Abstract: A display device includes a pixel circuit, an insulating layer covering the pixel circuit, a first partition portion which is disposed on the insulating layer and extends in a first direction, a second partition portion which is spaced apart from the first partition portion in a second direction intersecting the first direction and extends in the first direction, a plurality of connection partition portions disposed between the first and second partition portions, where each of the plurality of connection partition portions extends in the second direction, a first electrode disposed on the first partition portion and electrically connected to the pixel circuit, a second electrode disposed on the second partition portion, and a light emitting element disposed between the plurality of connection partition portions and electrically connected to the first electrode and the second electrode.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: August 24, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sikwang Kim, Minsuk Ko, Taegyun Kim, Yong-hoon Yang
  • Patent number: 11101386
    Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes an oxide; a first conductor and a second conductor over the oxide; a third conductor over the oxide; a first insulator provided between the oxide and the third conductor and covering a side surface of the third conductor; a second insulator over the third conductor and the first insulator; a third insulator positioned over the first conductor and at a side surface of the second insulator; a fourth insulator positioned over the second conductor and at a side surface of the second insulator; a fourth conductor being in contact with a top surface and a side surface of the third insulator and electrically connected to the first conductor; and a fifth conductor being in contact with a top surface and a side surface of the fourth insulator and electrically connected to the second conductor.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: August 24, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Matsubayashi, Ryota Hodo, Daigo Ito, Hiroaki Honda, Satoru Okamoto
  • Patent number: 11100817
    Abstract: The present disclosure provides a flexible electronic device and a manufacturing method thereof, and a flexible display device. The flexible electronic device includes: a flexible base substrate including a plurality of functional element regions spaced away from each other; at least one thin-film transistor disposed in each of the plurality of functional element regions on the flexible base substrate; and a rigid protective layer disposed at least on a side of the at least one TFT opposite to a side where the flexible base substrate is located in each of the plurality of functional element regions and configured to protect the at least one TFT, and a thickness of a central region of the rigid protective layer in each of the plurality of functional element regions is greater than a thickness of an edge region.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: August 24, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Pinfan Wang
  • Patent number: 11092864
    Abstract: A display panel and a display device are provided. The display panel includes a substrate; a first metal layer disposed on the substrate; an insulating layer disposed on the first metal layer; a semiconductor layer disposed on the insulating layer and including a germanium-doped semiconductor compound; and a second metal layer disposed on the semiconductor layer. A mobility of the semiconductor compound is greater than a mobility of amorphous silicon.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: August 17, 2021
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: En-Tsung Cho, Yiqun Tian
  • Patent number: 11092856
    Abstract: A display device in which parasitic capacitance between wirings can be reduced is provided. Furthermore, a display device in which display quality is improved is provided. Furthermore, a display device in which power consumption can be reduced is provided. The display device includes a signal line, a scan line, a first electrode, a second electrode, a third electrode, a first pixel electrode, a second pixel electrode, and a semiconductor film.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: August 17, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroyuki Miyake, Makoto Kaneyasu
  • Patent number: 11085756
    Abstract: A human body distance detection module for an electronic device, includes: a first metal sheet; a capacitance sensor electrically connected to the first metal sheet and configured to obtain a capacitance to ground of the first metal sheet, the capacitance to ground configured to reflect a distance between a human body and the electronic device; and a second metal sheet, at least one part of the second metal sheet being disposed opposite to the first metal sheet, the second metal sheet and the first metal sheet being insulated from each other to enable mutual coupling, and at least one part of the second metal sheet being not parallel to the first metal sheet.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: August 10, 2021
    Assignee: Beijing Xiaomi Mobile Software Co., Ltd.
    Inventors: Yaqi Liu, Linchuan Wang
  • Patent number: 11088285
    Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: August 10, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming Lai, Yen-Chen Chen, Jen-Po Huang, Sheng-Yao Huang, Hui-Ling Chen, Qinggang Xing, Ding-Lung Chen, Li Li Ding, Yao-Hung Liu
  • Patent number: 11086175
    Abstract: A display device with a narrow frame is provided. A display device with high visibility is provided. A display device with low power consumption is provided. A novel display device is provided. A structure having a stack structure in which a gate driver including a first transistor and a common driver including a second transistor which includes a metal oxide in its channel formation region are stacked has been conceived. Because the gate driver has a larger area than the common driver, part of the gate driver may be formed on the same plane as the common driver.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: August 10, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kei Takahashi
  • Patent number: 11088286
    Abstract: A semiconductor device with excellent electric characteristics is provided. The semiconductor device includes an oxide in a channel formation region. The semiconductor device includes the oxide over a substrate, a first insulator over the oxide, a second insulator over the first insulator, a third insulator, and a conductor over the third insulator. The oxide and the first insulator are in contact with each other in a region. An opening exposing the oxide is provided in the first insulator and the second insulator. The third insulator is placed to cover an inner wall and a bottom surface of the opening. The conductor is placed to fill the opening. The conductor has a region overlapping with the oxide with the third insulator between the conductor and the oxide. The first insulator contains an element other than a main component of the oxide.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: August 10, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryota Hodo, Daisuke Matsubayashi, Motomu Kurata, Ryunosuke Honda
  • Patent number: 11081598
    Abstract: A trench MOS Schottky diode includes a first semiconductor layer including a Ga2O3-based single crystal, a second semiconductor layer that is a layer laminated on the first semiconductor layer and that includes a Ga2O3-based single crystal and a trench opened on a surface thereof opposite to the first semiconductor layer, an anode electrode formed on the surface of the second semiconductor layer, a cathode electrode formed on a surface of the first semiconductor layer, an insulating film covering an inner surface of the trench, and a trench MOS gate that is buried in the trench so as to be covered with the insulating film and is in contact with the anode electrode. The second semiconductor layer includes a lower layer on a side of the first semiconductor layer and an upper layer on a side of the anode electrode having a higher donor concentration than the lower layer.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: August 3, 2021
    Assignees: TAMURA CORPORATION, NOVEL CRYSTAL TECHNOLOGY, INC.
    Inventors: Kohei Sasaki, Masataka Higashiwaki
  • Patent number: 11081587
    Abstract: There is provided a thin film transistor including: a substrate; a gate electrode and a first electrode in a single layer on the substrate; an active layer above the first electrode, an orthographic projection of the active layer on the substrate at least partially covers an orthographic projection of the first electrode on the substrate; a first insulation layer covering the gate electrode, the first electrode, the active layer, a portion of the substrate exposed between the gate electrode and the active layer, and another portion of the substrate exposed between the gate electrode and the first electrode; and a second electrode above the first insulation layer, an orthographic projection of the second electrode on the substrate at least partially covers the orthographic projection of the active layer on the substrate, and the second electrode is connected to the active layer through a via-hole in the first insulation layer.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: August 3, 2021
    Assignees: CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hongru Zhou, Kai Wang, Kunkun Gao, Xiaonan Dong, Zhaojun Wang
  • Patent number: 11081501
    Abstract: A thin film transistor and a method of fabricating the same, an array substrate and a method of fabricating the same, and a display device are provided, the method of fabricating a thin film transistor includes: forming an active layer on a base substrate; forming a metal layer on the active layer; and processing the metal layer to form a source electrode, a drain electrode, and a metal oxide layer, the metal oxide layer covering the source electrode, the drain electrode, and the active layer, the source electrode and the drain electrode being spaced apart and insulated from each other by the metal oxide layer.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: August 3, 2021
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wei Song, Ce Zhao, Bin Zhou, Dongfang Wang, Yuankui Ding, Jun Liu, Yingbin Hu, Wei Li
  • Patent number: 11074944
    Abstract: According to one embodiment, a semiconductor memory device includes: first to fifth interconnects; a semiconductor layer having one end located between the fourth interconnect and the fifth interconnect and other end connected to the first interconnect; a memory cell; a conductive layer having one end connected to the second interconnect and other end connected to the semiconductor layer; a first insulating layer provided to extend between the third and fourth interconnects and the semiconductor layer, and between the fifth interconnect and the conductive layer; an oxide semiconductor layer provided to extend between the fourth and fifth interconnects and the first insulating layer; and a second insulating layer provided to extend between the fourth and fifth interconnects and the oxide semiconductor layer.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: July 27, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Fumitaka Arai, Keiji Hosotani, Nobuyuki Momo
  • Patent number: 11075288
    Abstract: A thin film transistor is provided and includes an active layer, a source electrode, a drain electrode, a gate electrode and a gate electrode insulating layer, the active layer includes a source electrode region, a drain electrode region and a channel region, the source electrode region and the drain electrode region include a first metal material, and the channel region includes a semiconductor material made from oxidation of the first metal material.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: July 27, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Guoying Wang, Hongda Sun, Zhen Song
  • Patent number: 11075305
    Abstract: According to one embodiment, the oxide semiconductor layer contains at least one of indium (In) and tin (Sn). The insulating film is provided between the control electrode and the oxide semiconductor layer, and contains silicon oxide. The metal oxide film is provided between the insulating film and the oxide semiconductor layer, and contacts the insulating film and the oxide semiconductor layer. The metal oxide film contains at least one selected from a group consisting of gallium (Ga), tungsten (W), germanium (Ge), aluminum (Al), molybdenum (Mo), and titanium (Ti).
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: July 27, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Nobuki Kanrei
  • Patent number: 11075075
    Abstract: Favorable electrical characteristics are provided to a semiconductor device, or a semiconductor device with high reliability is provided. A semiconductor device including a bottom-gate transistor with a metal oxide in a semiconductor layer includes a source region, a drain region, a first region, a second region, and a third region. The first region, the second region, and the third region are each sandwiched between the source region and the drain region along the channel length direction. The second region is sandwiched between the first region and the third region along the channel width direction, the first region and the third region each include the end portion of the metal oxide, and the length of the second region along the channel length direction is shorter than the length of the first region or the length of the third region along the channel length direction.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: July 27, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 11075300
    Abstract: The semiconductor device includes a first insulating layer; a first oxide semiconductor; a first insulator containing indium, an element M (M is gallium, aluminum, titanium, yttrium, or tin), and zinc; a second oxide semiconductor; a source electrode layer; a drain electrode layer; a second insulator containing indium, the element M, and zinc; a gate insulating layer; and a gate electrode layer. The first and second oxide semiconductors each include a region with c-axis alignment. In the first and second oxide semiconductors, the number of indium atoms divided by sum of numbers of the indium atoms, element M atoms, and zinc atoms is ? or more. In the first insulator, the number of zinc atoms divided by sum of the numbers of indium atoms, element M atoms, and zinc atoms is ? or less.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: July 27, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Shinpei Matsuda
  • Patent number: 11069815
    Abstract: A thin-film transistor comprises an annealed layer comprising crystalline zinc oxide. A passivation layer is adjacent to the thin-film transistor. The passivation layer has a thickness and material composition such that when a dose of radiation from a radiation source irradiates the thin-film transistor, a portion of the dose that includes an approximate maximum concentration of the dose is located within the annealed layer. The annealed layer has a thickness and threshold displacement energies after it has been annealed such that: a) a difference between a transfer characteristic value of the thin-film transistor before and after the dose is less than a first threshold; and b) a difference between a transistor output characteristic value of the thin-film before and after the dose is less than a second threshold. The thresholds are based on a desired performance of the thin-film transistor.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: July 20, 2021
    Assignee: Auburn University
    Inventors: Minseo Park, Michael C. Hamilton, Shiqiang Wang, Kosala Yapa Bandara
  • Patent number: 11063035
    Abstract: An ESD protection circuit includes a first fin structure having fins of a first conductivity type and a second fin structure having fins of a second conductivity type, the second fin structure being opposed to the first fin structure. A first power interconnect connected with the first fin structure and a signal interconnect connected with the second fin structure are formed in a first interconnect layer, and a second power interconnect connected with the first power interconnect is formed in a second interconnect layer. The width occupied by the second fin structure is greater than that of the first fin structure, and the width of the signal interconnect is greater than that of the first power interconnect.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: July 13, 2021
    Assignee: SOCIONEXT INC.
    Inventors: Chika Ito, Isaya Sobue, Hidetoshi Tanaka
  • Patent number: 11062818
    Abstract: Example embodiments relate to a stacking structure having a material layer formed on a graphene layer, and a method of forming the material layer on the graphene layer. In the stacking structure, when the material layer is formed on the graphene layer by using an ALD method, an intermediate layer as a seed layer may be formed on the graphene layer by using a linear type precursor.
    Type: Grant
    Filed: January 2, 2015
    Date of Patent: July 13, 2021
    Assignees: Samsung Electronics Co., Ltd., SUNGKYUNKWAN UNIVERSITY RESEARCH & BUSINESS FOUNDATION
    Inventors: Seong-jun Jeong, Seong-jun Park, Hyeon-jin Shin, Yea-hyun Gu, Hyoung-sub Kim, Jae-hyun Yang
  • Patent number: 11063125
    Abstract: A metal oxide film includes indium, M, (M is Al, Ga, Y, or Sn), and zinc and includes a region where a peak having a diffraction intensity derived from a crystal structure is observed by X-ray diffraction in the direction perpendicular to the film surface. Moreover, a plurality of crystal parts is observed in a transmission electron microscope image in the direction perpendicular to the film surface. The proportion of a region other than the crystal parts is higher than or equal to 20% and lower than or equal to 60%.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: July 13, 2021
    Inventors: Yasuharu Hosaka, Toshimitsu Obonai, Yukinori Shima, Masami Jintyou, Daisuke Kurosaki, Takashi Hamochi, Junichi Koezuka, Kenichi Okazaki, Shunpei Yamazaki
  • Patent number: 11063101
    Abstract: An organic light emitting display apparatus can include a substrate including a display area and a bending area; a pixel array layer including a driving wiring in the display area, and a thin film transistor electrically connected to the driving wiring; a planarization layer covering the pixel array layer; a light emitting device layer disposed on the planarization layer, the light emitting device layer being electrically connected to the thin film transistor; a routing wiring disposed in the bending area, the routing wiring being electrically connected to the driving wiring; a wiring contact part including a contact hole for electrically connecting the driving wiring to the routing wiring; and an encapsulation layer covering the light emitting device layer and the wiring contact part.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: July 13, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventor: Eunah Kim