Semiconductor Is An Oxide Of A Metal (e.g., Cuo, Zno) Or Copper Sulfide Patents (Class 257/43)
  • Patent number: 11430894
    Abstract: Provided is a semiconductor device in which deterioration of electric characteristics which becomes more noticeable as the semiconductor device is miniaturized can be suppressed. The semiconductor device includes a first oxide film, an oxide semiconductor film over the first oxide film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a second oxide film over the oxide semiconductor film, the source electrode, and the drain electrode, a gate insulating film over the second oxide film, and a gate electrode in contact with the gate insulating film. A top end portion of the oxide semiconductor film is curved when seen in a channel width direction.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: August 30, 2022
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kazuya Hanaoka, Daisuke Matsubayashi, Yoshiyuki Kobayashi, Shunpei Yamazaki, Shinpei Matsuda
  • Patent number: 11424334
    Abstract: A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with stable electrical characteristics is provided. The semiconductor device includes a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a semiconductor layer, and a first conductive layer. The second insulating layer is positioned over the first insulating layer and the island-shaped semiconductor layer is positioned over the second insulating layer. The second insulating layer has an island shape having an end portion outside a region overlapping with the semiconductor layer. The fourth insulating layer covers the second insulating layer, the semiconductor layer, the third insulating layer, and the first conductive layer, is in contact with part of a top surface of the semiconductor layer, and is in contact with the first insulating layer outside the end portion of the second insulating layer.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: August 23, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masami Jintyou, Takahiro Iguchi, Yukinori Shima, Kenichi Okazaki
  • Patent number: 11423839
    Abstract: A display device may include a substrate, an organic light emitting element on the substrate, a pixel circuit between the substrate and the organic light emitting element, electrically connected to the organic light emitting element, and including a first transistor and a second transistor, a first metal layer between the substrate and the pixel circuit, overlapping the first transistor, and configured to receive a first voltage, and a second metal layer between the substrate and the pixel circuit, overlapping the second transistor, and configured to receive a second voltage different from the first voltage.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: August 23, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Myounggeun Cha, Sanggun Choi, Jiyeong Shin, Yongsu Lee
  • Patent number: 11423855
    Abstract: A novel display panel that is highly convenient or reliable is provided. A pixel circuit includes a first switch, a node, a capacitor, and a second switch. The first switch includes a first terminal to which a first signal is supplied and a second terminal electrically connected to the node. The capacitor includes a first terminal electrically connected to the node and a second terminal electrically connected to the second switch. The second switch includes a first terminal to which a second signal is supplied and a second terminal electrically connected to the second terminal of the capacitor. In addition, the second switch has a function of changing from a non-conducting state to a conducting state when the first switch is in a non-conducting state and a function of changing from a conducting state to a non-conducting state when the first switch is in a non-conducting state. The display element performs display on the basis of a potential of the node.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: August 23, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kouhei Toyotaka, Kei Takahashi, Koji Kusunoki, Kazunori Watanabe, Susumu Kawashima
  • Patent number: 11424307
    Abstract: The present disclosure is related to an organic light-emitting diode apparatus. The organic light-emitting diode apparatus may include a substrate and a plurality of pixels on a first side of the substrate. Each of the plurality of pixels may include a display region and a non-display region. The non-display region may be provided with a control circuit and a first color film, and the first color film may be between the control circuit and the substrate.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: August 23, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhen Song, Guoying Wang
  • Patent number: 11424369
    Abstract: A semiconductor device having a large on-state current and high reliability is provided. The semiconductor device includes a first insulator, a first oxide over the first insulator, a second oxide over the first oxide, a third oxide and a fourth oxide over the second oxide, a first conductor over the third oxide, a second conductor over the fourth oxide, a fifth oxide over the second oxide, a second insulator over the fifth oxide, and a third conductor over the second insulator. The fifth oxide is in contact with a top surface of the second oxide, a side surface of the first conductor, a side surface of the second conductor, a side surface of the third oxide, and a side surface of the fourth oxide. The second oxide contains In, an element M, and Zn. The first oxide and the fifth oxide each contain at least one of constituent elements included in the second oxide. The third oxide and the fourth oxide each contain the element M.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: August 23, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Haruyuki Baba, Naoki Okuno, Yoshihiro Komatsu, Toshikazu Ohno
  • Patent number: 11417769
    Abstract: Provided are a thin film transistor and method for manufacturing the same, array substrate, display panel and display device. The thin film transistor includes: a gate pattern, a gate insulating layer, an active layer pattern, a source pattern and a drain pattern sequentially stacked. At least one of a surface of the source pattern facing the gate insulating layer, a surface of the drain pattern facing the gate insulating layer, and a surface of the gate pattern facing the gate insulating layer is a target surface which can diffusely reflect lights entering the target surface, to prevent part of the lights from entering the active layer pattern. The display device solves the problem of volt-ampere characteristic curve of the active layer pattern being deflected and a normal operation of the thin film transistor being affected, thereby weakening the influence of lights on the normal operation of the thin film transistor.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: August 16, 2022
    Assignees: BOE Technology Group Co., LTD., Hefei Xinsheng Optoelectronics Technology Co., LTD
    Inventors: Binbin Cao, Chao Wang, Lin Sun
  • Patent number: 11411121
    Abstract: An object is to stabilize electric characteristics of a semiconductor device including an oxide semiconductor to increase reliability. The semiconductor device includes an insulating film; a first metal oxide film on and in contact with the insulating film; an oxide semiconductor film partly in contact with the first metal oxide film; source and drain electrodes electrically connected to the oxide semiconductor film; a second metal oxide film partly in contact with the oxide semiconductor film; a gate insulating film on and in contact with the second metal oxide film; and a gate electrode over the gate insulating film.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: August 9, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 11404448
    Abstract: A display substrate, a manufacturing method thereof, and a display device are disclosed. The display substrate includes: a base substrate, the base substrate includes a bonding region; and a connection terminal located in the bonding region of the base substrate, the connection terminal includes a first conductive layer and a second conductive layer being in contact with each other, the first conductive layer and the second conductive layer are overlapped with each other in a direction perpendicular to the base substrate.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: August 2, 2022
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Bo Zhang, Jingni Wang, Kun Guo
  • Patent number: 11404543
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor channel layer, a gate structure, complex regions, a source terminal and a drain terminal. The gate structure is disposed on the semiconductor channel layer. The source terminal and the drain terminal are disposed on the semiconductor channel layer. The complex regions ae respectively disposed between the source terminal and the semiconductor channel layer and between the drain terminal and the semiconductor channel layer.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Georgios Vellianitis
  • Patent number: 11403868
    Abstract: A display substrate, a method for driving the same and a display device are provided. The display substrate includes a first base substrate, at least one vibrator and at least one identification unit. The at least one identification unit is on the first base substrate, the at least one identification unit is in a display area of the display substrate, and the at least one vibrator is on a side of the first base substrate facing away from the identification unit. The at least one vibrator is configured to drive the first base substrate to vibrate to emit an acoustic signal; and the at least one identification unit is configured to receive an ultrasonic signal reflected by an object to be detected, and convert the ultrasonic signal into a first electrical signal.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: August 2, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Shengji Yang, Xue Dong, Xiaochuan Chen, Hui Wang, Pengcheng Lu
  • Patent number: 11404516
    Abstract: A plurality of thin film transistors provided in a peripheral region are first staggered thin film transistors where a first channel layer configured of low-temperature polysilicon is included, and the first channel layer is not interposed between a first source electrode and a first gate electrode, and between a first drain electrode and the first gate electrode. A plurality of thin film transistors provided in a display region are second staggered thin film transistors where a second channel layer configured of an oxide semiconductor is included, and the second channel layer is not interposed between a second source electrode and a second gate electrode, and between a second drain electrode and the second gate electrode. The first thin film transistor is located below the second thin film transistor.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: August 2, 2022
    Assignee: Japan Display Inc.
    Inventor: Satoshi Maruyama
  • Patent number: 11398508
    Abstract: A first oxide semiconductor thin-fil transistor includes a top gate electrode, a first metal oxide film, and a top gate insulating film between the top gate electrode and the first metal oxide film. A second oxide semiconductor thin-film transistor includes a bottom gate electrode, a second metal oxide film, and a bottom gate insulating film between the bottom gate electrode and the second metal oxide film. A storage capacitor stores a signal voltage to the bottom gate electrode. A first electrode of the storage capacitor includes a part of the bottom gate electrode. A source/drain region of the first oxide semiconductor thin-film transistor is in contact with the bottom gate electrode in a contact hole in the bottom gate insulating layer. Capacitance per unit area of the bottom gate insulating film is smaller than capacitance per unit area of the top gate insulating film.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: July 26, 2022
    Assignees: TIANMA JAPAN, LTD., Wuhan Tianma Micro-Electronics Co., Ltd.
    Inventors: Yuya Kuwahara, Kazushige Takechi
  • Patent number: 11398599
    Abstract: Methods of manufacturing memory devices, and associated systems and devices, are disclosed herein. In one embodiment, a method of manufacturing a memory device includes (a) removing a portion of an insulative material to define a recess, (b) forming a memory stack in the recess, and (c) etching the memory stack to define a plurality of memory elements. In some embodiments, the method can further include forming conductive vias in a remaining portion of the insulative material, and forming a metallization structure electrically coupling the conductive vias to corresponding ones of the memory elements.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: July 26, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Michael B. Jeppson
  • Patent number: 11398523
    Abstract: At least one embodiment of the present disclosure relates to an array substrate and a manufacturing method thereof, a display panel and a display device. The array substrate includes: a pixel region including a first light emitting material layer; a hole region; a separating region including a separating structure, wherein the separating structure includes at least one first groove, and the separating structure is configured to separating the first light emitting material layer from the hole region through the first groove.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: July 26, 2022
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Chengjie Qin, Chunyan Xie, Tao Wang, Song Zhang
  • Patent number: 11398438
    Abstract: Provided is a drive backplane for a light-emitting diode, including a substrate and a drive structure on the substrate, the drive structure including a thin-film transistor and a stress relief structure; wherein the thin-film transistor includes an active layer on the substrate, a first insulation layer covering the active layer, and a first gate on the first insulation layer; and the stress relief structure is on the first insulation layer and includes a first metal strip on a first side of the first gate and a second metal strip on a second side of the first gate, wherein the first side is opposite to the second side. A method for preparing the light-emitting diode and a display device are further disclosed.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: July 26, 2022
    Assignee: BOE Technology Group Co., LTD.
    Inventor: Haixu Li
  • Patent number: 11393935
    Abstract: The present disclosure provides a phototransistor and a manufacturing method therefor, the phototransistor having a defective oxide ray absorption layer introduced to an oxide semiconductor phototransistor through a solution process or a defective oxide ray absorption part introduced to an interface between a gate insulation film and an oxide semiconductor layer through interface control, which forms damage, thereby improving light absorption in the range of a visible light region.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: July 19, 2022
    Assignees: LG DISPLAY CO., LTD., UIF (UNIVERSITY INDUSTRY FOUNDATION) YONSEI UNIVERSITY
    Inventors: Hyun Jae Kim, Young Jun Tak, Jusung Chung, Jeong Min Moon, Su Seok Choi, Sungpil Ryu, Jihwan Jung, Kiseok Chang
  • Patent number: 11387330
    Abstract: A novel metal oxide is provided. One embodiment of the present invention is a crystalline metal oxide. The metal oxide includes a first layer and a second layer; the first layer has a wider bandgap than the second layer; the first layer and the second layer form a crystal lattice; and in the case where a carrier is excited in the metal oxide, the carrier is transferred through the second layer. Furthermore, the first layer contains an element M (M is one or more selected from Al, Ga, Y, and Sn) and Zn, and the second layer contains In.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: July 12, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 11387302
    Abstract: A display device includes: a substrate; a first insulating layer disposed on the substrate and that includes an inorganic insulating material; an oxide semiconductor layer disposed on the first insulating layer; a second insulating layer disposed on the oxide semiconductor layer and that includes an inorganic insulating material; and a third insulating layer disposed on a gate electrode disposed on the second insulating layer and that includes an inorganic insulating material. The oxide semiconductor layer includes a first conductive region, a second conductive region, and a channel region located between the first conductive region and the second conductive region, and a value in the channel region of the oxide semiconductor layer of HC according to equation (1) is less than 30%.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: July 12, 2022
    Assignee: Samsung Display Co. , Ltd.
    Inventors: Jaebum Han, Younggil Park, Junghwa Park, Nari Ahn, Sooim Jeong
  • Patent number: 11387289
    Abstract: An array substrate includes a substrate, a packaging layer, and at least one sensor. The packaging layer is over the substrate. Each sensor includes a sensing thin-film transistor and a sensing unit, electrically coupled with each other. The sensing thin-film transistor is between the package layer and the substrate, and the sensing unit is over a side of the package layer away from the substrate. The array substrate can also include a plurality of display thin-film transistors. The sensing thin-film transistor in each sensor can be at substantially same film layers, or of a same structure and a same type, as each display thin-film transistor.
    Type: Grant
    Filed: December 25, 2018
    Date of Patent: July 12, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yunke Qin, Xue Dong, Zhifu Li, Haisheng Wang, Yingming Liu, Yuzhen Guo, Pinchao Gu, Lin Zhou
  • Patent number: 11380800
    Abstract: The oxide semiconductor film has the top and bottom surface portions each provided with a metal oxide film containing a constituent similar to that of the oxide semiconductor film. An insulating film containing a different constituent from the metal oxide film and the oxide semiconductor film is further formed in contact with a surface of the metal oxide film, which is opposite to the surface in contact with the oxide semiconductor film. The oxide semiconductor film used for the active layer of the transistor is an oxide semiconductor film highly purified to be electrically i-type (intrinsic) by removing impurities such as hydrogen, moisture, a hydroxyl group, and hydride from the oxide semiconductor and supplying oxygen which is a major constituent of the oxide semiconductor and is simultaneously reduced in a step of removing impurities.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: July 5, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 11380720
    Abstract: Provided are an array substrate, a manufacturing method therefor, a display panel and a display device. The array substrate includes: a photosensitive member and a thin film transistor that are located on a base substrate, the photosensitive member including a photosensitive layer; the thin film transistor is located at a side of the photosensitive member that is far from the base substrate. In the described array substrate, the photosensitive member is formed first, and then the thin film transistor is formed on the photosensitive member, which prevents the element hydrogen from influencing the thin film transistor when forming the photosensitive member, while source and drain layer patterns of the thin film transistor may be formed by means of one-time pattern processing, thus simplifying the manufacturing process.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: July 5, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Wei Liu
  • Patent number: 11380799
    Abstract: To provide a novel oxide semiconductor film. The oxide semiconductor film includes In, M, and Zn. The M is Al, Ga, Y, or Sn. In the case where the proportion of In in the oxide semiconductor film is 4, the proportion of M is greater than or equal to 1.5 and less than or equal to 2.5 and the proportion of Zn is greater than or equal to 2 and less than or equal to 4.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: July 5, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Junichi Koezuka, Kenichi Okazaki, Yasumasa Yamane, Yuhei Sato, Shunpei Yamazaki
  • Patent number: 11380795
    Abstract: A semiconductor device comprising an oxide semiconductor film, a gate electrode, a first insulating film, a source electrode, a drain electrode, and a second insulating film is provided. Each of a top surface of the gate electrode, a top surface of the source electrode, and a top surface of the drain electrode comprises a region in contact with the second insulating film. A top surface of the first insulating film comprises a region in contact with the gate electrode and a region in contact with the second insulating film and overlapping with the oxide semiconductor film in a cross-sectional view of the oxide semiconductor film. The oxide semiconductor film comprises a region in contact with the first insulating film and a region in contact with the second insulating film and adjacent to the region in contact with the first insulating film in the cross-sectional view.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: July 5, 2022
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Masami Jintyou, Yukinori Shima, Takashi Hamochi, Yasutaka Nakazawa
  • Patent number: 11374003
    Abstract: An integrated circuit includes a first transistor, a second transistor, and a first insulating layer. The first transistor is disposed in a first layer and comprises a first gate. The second transistor is disposed in a second layer above the first layer and comprises a second gate. The first gate and second gate are separated from each other in a first direction. The first insulating layer is disposed between the first gate of the first transistor and the second gate of the second transistor. The first insulating layer is configured to electrically insulate the first gate of the first transistor from the second gate of the second transistor.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Guo-Huei Wu, Po-Chun Wang, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien
  • Patent number: 11374007
    Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor and a capacitor. One of (a) a channel region of the transistor, or (b) a pair of electrodes of the capacitor, is directly above the other of (a) and (b). Additional embodiments and aspects are disclosed.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: June 28, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Martin C. Roberts
  • Patent number: 11374130
    Abstract: A semiconductor device of an embodiment includes: a first oxide semiconductor layer including a first region, a second region, and a third region between the first region and the second region; a gate electrode; a gate insulating layer provided between the third region and the gate electrode; a first electrode electrically connected to the first region; a second electrode electrically connected to the second region; and a second oxide semiconductor layer provided in at least one of a position between the first region and the first electrode and a position between the second region and the second electrode and containing indium (In), aluminum (Al), and zinc (Zn), an atomic ratio of aluminum to a sum of indium, aluminum, and zinc being 8% or more and 23% or less, and an atomic ratio of indium to the sum of indium, aluminum, and zinc being 45% or less.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: June 28, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Shigeki Hattori, Tomomasa Ueda, Keiji Ikeda
  • Patent number: 11374051
    Abstract: The present disclosure provides a photoelectric conversion array substrate and a photoelectric conversion device, and the photoelectric conversion array substrate includes: a base substrate; a thin film transistor located on the base substrate and including a gate, a gate insulating layer disposed on the gate, an active layer disposed on the gate insulating layer, and a source electrode and a drain electrode located on the active layer; a photodetection unit located on the base substrate and including a signal output electrode, a photosensitive layer and a transparent electrode that are located on the base substrate, the signal output electrode electrically connected to the drain electrode, wherein an orthographic projection of the transparent electrode on the base substrate is located within an orthographic projection of the photosensitive layer on the base substrate; a first protective layer covering the source electrode and the drain electrode.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: June 28, 2022
    Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Gang Yu
  • Patent number: 11374117
    Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device is manufactured by a first step of forming a semiconductor layer containing a metal oxide, a second step of forming a first insulating layer, a third step of forming a first conductive film over the first insulating layer, a fourth step of etching part of the first conductive film to form a first conductive layer, thereby forming a first region over the semiconductor layer that overlaps with the first conductive layer and a second region over the semiconductor layer that does not overlap with the first conductive layer, and a fifth step of performing first treatment on the conductive layer. The first treatment is plasma treatment in an atmosphere including a mixed gas of a first gas containing an oxygen element but not containing a hydrogen element, and a second gas containing a hydrogen element but not containing an oxygen element.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: June 28, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kenichi Okazaki, Yukinori Shima
  • Patent number: 11374193
    Abstract: A display device according to an embodiment may include a base substrate, a circuit layer, a light emitting element layer, and a module hole. The light emitting element layer may include a first electrode, a light emitting layer, and a second electrode. The second electrode may include a first portion that is not overlapped with the module hole and has a first thickness and a second portion between the module hole and the first portion and having a thickness that gradually increases in a direction toward the first portion. Thus, the display device may improve in durability in a hot and humid environment.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: June 28, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yunjung Choi, Sangyeol Kim, Sokwon Noh, HyungSik Kim, Suhyun Oh
  • Patent number: 11368645
    Abstract: The present disclosure generally relates to image sensors and methods for image sensing. More specifically, and without limitation, this disclosure relates to systems and methods for providing super-pixels, and implementing and using image sensors with super-pixels. In one implementation, an image sensor includes a plurality of super-pixels.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: June 21, 2022
    Assignee: PROPHESEE SA
    Inventors: Thomas Finateu, Daniel Matolin, Christoph Posch
  • Patent number: 11355594
    Abstract: A diode includes an n-type semiconductor layer including an n-type Ga2O3-based single crystal, and a p-type semiconductor layer including a p-type semiconductor in which a volume of an amorphous portion is higher than a volume of a crystalline portion. The n-type semiconductor layer and the p-type semiconductor layer form a pn junction.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: June 7, 2022
    Assignees: Tamura Corporation, Novel Crystal Technology, Inc.
    Inventor: Kohei Sasaki
  • Patent number: 11355646
    Abstract: Disclosed are a thin film transistor having an oxide semiconductor layer which is applicable to a flat display device requiring high-speed driving due to ultra-high definition, a gate driver including the same, and a display device including the same. The thin film transistor includes a first oxide semiconductor layer formed of iron-indium-zinc oxide (FIZO) and a second oxide semiconductor layer formed of indium-gallium-zinc oxide (IGZO), thus being capable of exhibiting effects, such as high reliability and high electron mobility.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: June 7, 2022
    Assignee: LG Display Co., Ltd.
    Inventors: Seung-Jin Kim, Jee-Ho Park, Seo-Yeon Im
  • Patent number: 11355529
    Abstract: A semiconductor device including an oxide semiconductor in which on-state current is high is provided. The semiconductor device includes a first transistor provided in a driver circuit portion and a second transistor provided in a pixel portion; the first transistor and the second transistor have different structures. Furthermore, the the first transistor and the second transistor are transistors having a top-gate structure. In an oxide semiconductor film of each of the transistors, an impurity element is contained in regions which do not overlap with a gate electrode. The regions of the oxide regions. Furthermore, the regions of the oxide semiconductor film which contain the impurity element are in contact with a film containing hydrogen. The first transistor provided in the driver circuit portion includes two gate electrodes between which the oxide semiconductor film is provided.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: June 7, 2022
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Junichi Koezuka, Masami Jintyou, Yukinori Shima, Daisuke Kurosaki, Masataka Nakada, Shunpei Yamazaki
  • Patent number: 11355378
    Abstract: A method includes forming an adhesive layer over a carrier, forming a sacrificial layer over the adhesive layer, forming through-vias over the sacrificial layer, and placing a device die over the sacrificial layer. The Method further includes molding and planarizing the device die and the through-vias, de-bonding the carrier by removing the adhesive layer, and removing the sacrificial layer.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsiang Hu, Chung-Shi Liu, Hung-Jui Kuo, Ming-Da Cheng
  • Patent number: 11352690
    Abstract: A metal oxide film containing a crystal part is provided. Alternatively, a metal oxide film with highly stable physical properties is provided. Alternatively, a metal oxide film with improved electrical characteristics is provided. Alternatively, a metal oxide film with which field-effect mobility can be increased is provided. A metal oxide film including In, M (M is Al, Ga, Y, or Sn), and Zn includes a first crystal part and a second crystal part; the first crystal part has c-axis alignment; the second crystal part has no c-axis alignment; and the existing proportion of the second crystal part is higher than the existing proportion of the first crystal part.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: June 7, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Kenichi Okazaki, Masashi Tsubuku
  • Patent number: 11351806
    Abstract: Provided is an electromagnetic wave generator including: an electromagnetic wave generation section that generates an electromagnetic wave; a high-frequency voltage generation section that generates a voltage applied to the electromagnetic wave generation section; and a transmission line that electrically couples the electromagnetic wave generation section and the high-frequency voltage generation section to each other, in which the electromagnetic wave generation section includes a first electrode, a second electrode, a first conductor that electrically couples the first electrode and the transmission line to each other, and a second conductor that electrically couples the second electrode and the transmission line to each other, one of the first electrode or the second electrode is a reference potential electrode to which a reference potential is applied and the other is a high-frequency electrode to which a high-frequency voltage is applied, a minimum separation distance between the first electrode and the
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: June 7, 2022
    Assignee: Seiko Epson Corporation
    Inventor: Tadashi Aizawa
  • Patent number: 11342235
    Abstract: A semiconductor device includes a substrate including a first part and a second part, a memory cell disposed on the first part, an insulation layer disposed on the first part and the second part, the insulation layer covering the memory cell, a portion of the insulation layer on the second part including a stepped sidewall, and a first pattern group disposed on the second part and in the portion of the insulation layer and the substrate. A first sidewall of the semiconductor device corresponds to the stepped sidewall including an upper sidewall, a lower sidewall and a connecting surface connecting the upper sidewall to the lower sidewall. The lower sidewall disposed under the upper sidewall is closer to the substrate than the upper sidewall, and has surface roughness different from surface roughness of the upper sidewall.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: May 24, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Minjung Choi, Junyong Noh, Yeonjin Lee, Junghoon Han
  • Patent number: 11342465
    Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.
    Type: Grant
    Filed: January 3, 2021
    Date of Patent: May 24, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming Lai, Yen-Chen Chen, Jen-Po Huang, Sheng-Yao Huang, Hui-Ling Chen, Qinggang Xing, Ding-Lung Chen, Li Li Ding, Yao-Hung Liu
  • Patent number: 11342463
    Abstract: A semiconductor device comprising: an oxide semiconductor layer including indium; a gate electrode facing to the oxide semiconductor layer; a gate insulating layer between the oxide semiconductor layer and the gate electrode; a first conductive layer arranged above the oxide semiconductor layer and being in contact with the oxide semiconductor layer from above the oxide semiconductor layer; an oxide portion formed on the oxide semiconductor layer and at an edge of the first conductive layer, the oxide portion being a oxide of the first conductive layer.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: May 24, 2022
    Assignee: Japan Display Inc.
    Inventors: Tatsuya Toda, Masashi Tsubuku
  • Patent number: 11342401
    Abstract: A display device includes: a base substrate having a display region including a first region and a second region, and a non-display region; a first semiconductor layer including polysilicon at the second region; a first conductive layer on a first insulating layer, and including a bottom gate electrode at the first region and a second-first gate electrode at the second region; a second semiconductor layer including an oxide on a second insulating layer at the first region; a second conductive layer on a third insulating layer, and including a top gate electrode at the first region and a second-second gate electrode at the second region; and a third conductive layer on a fourth insulating layer, and including a first source electrode and a first drain electrode connected to the second semiconductor layer, and a second source electrode and a second drain electrode connected to the first semiconductor layer.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: May 24, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ji Eun Choi, Deok Hoi Kim, Jeong Hwan Kim, Jong Baek Seon, Jun Cheol Shin, Jae Hak Lee
  • Patent number: 11342462
    Abstract: To improve field-effect mobility and reliability in a transistor including an oxide semiconductor film. A semiconductor device includes a transistor including an oxide semiconductor film. The transistor includes a region where the maximum value of field-effect mobility of the transistor at a gate voltage of higher than 0 V and lower than or equal to 10 V is larger than or equal to 40 and smaller than 150; a region where the threshold voltage is higher than or equal to minus 1 V and lower than or equal to 1 V; and a region where the S value is smaller than 0.3 V/decade.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: May 24, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Kenichi Okazaki, Yukinori Shima, Shinpei Matsuda, Haruyuki Baba, Ryunosuke Honda
  • Patent number: 11342420
    Abstract: Current conducting devices and methods for their formation are disclosed. Described are vertical current devices that include a substrate, an n-type material layer, a plurality of p-type gates, and a source. The n-type material layer disposed on the substrate and includes a current channel. A plurality of p-type gates are disposed on opposite sides of the current channel. A source is disposed on a distal side of the current channel with respect to the substrate. The n-type material layer comprises beta-gallium oxide.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: May 24, 2022
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Travis J. Anderson, Marko J. Tadjer, Andrew D. Koehler, Karl D. Hobart
  • Patent number: 11342364
    Abstract: A thin-film transistor substrate includes an insulating substrate, a first insulating layer, a first thin-film transistor including a first oxide semiconductor film, a second insulating layer located upper than the first insulating layer, and a second thin-film transistor including a second oxide semiconductor film different in composition from the first oxide semiconductor film. At least a part of the first oxide semiconductor film is provided above and in contact with the first insulating layer. The first insulating layer is the uppermost insulating layer among insulating layers located lower than and in contact with the first oxide semiconductor film. At least a part of the second oxide semiconductor film is provided above and in contact with the second insulating layer. The second insulating layer is the uppermost insulating layer among insulating layers located lower than and in contact with the second oxide semiconductor film.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: May 24, 2022
    Assignees: TIANMA JAPAN. LTD., Wuhan Tianma Micro-Electronics Co., Ltd.
    Inventors: Jun Tanaka, Kazushige Takechi
  • Patent number: 11335709
    Abstract: Array substrate, display panel, display device, and method for forming array substrate are provided. The array substrate includes a substrate and at least one first thin-film transistor on the substrate. the first thin-film transistor includes a first gate electrode; a first gate electrode insulating layer on a side of the first gate electrode facing away from the substrate; a first active layer on a side of the first gate electrode insulating layer facing away from the first gate electrode; a second gate electrode insulating layer on a side of the first active layer facing away from the first gate electrode insulating layer; a second gate electrode on a side of the second gate electrode insulating layer facing away from the first active layer; and a first source electrode and a first drain electrode on the first active layer facing away from the first gate electrode insulating layer.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: May 17, 2022
    Assignee: Xiamen Tianma Micro-Electronics Co., Ltd.
    Inventors: Shui He, Shanshan Zheng, Yaqi Kuang
  • Patent number: 11335273
    Abstract: A display device includes pixels connected to scan lines and data lines intersecting the scan lines, wherein each of the pixels includes a light emitting element and a first transistor configured to control a driving current supplied to the light emitting element according to a data voltage applied from a respective data line of the data lines, the first transistor includes a first active layer including an oxide semiconductor containing indium (In), and a content of the indium in the oxide semiconductor of the first active layer is 70 at % or more.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: May 17, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hye Lim Choi, Yeon Keon Moon, Joon Seok Park, Myoung Hwa Kim, Tae Sang Kim, Hyung Jun Kim, Geun Chui Park, Kyung Jin Jeon
  • Patent number: 11335699
    Abstract: In one embodiment, a semiconductor device includes a substrate, insulating films and first films alternately stacked on the substrate, at least one of the first films including an electrode layer and a charge storage layer provided on a face of the electrode layer via a first insulator, and a semiconductor layer provided on a face of the charge storage layer via a second insulator. The device further includes at least one of a first portion including nitrogen and provided between the first insulator and the charge storage layer with an air gap provided in the first insulator, a second portion including nitrogen, provided between the charge storage layer and the second insulator, and including a portion protruding toward the charge storage layer, and a third portion including nitrogen and provided between the second insulator and the semiconductor layer with an air gap provided in the first insulator.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: May 17, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Keiichi Sawa, Kazuhiro Matsuo, Kazuhisa Matsuda, Hiroyuki Yamashita, Yuta Saito, Shinji Mori, Masayuki Tanaka, Kenichiro Toratani, Atsushi Takahashi, Shouji Honda
  • Patent number: 11329166
    Abstract: In a transistor that includes an oxide semiconductor, a change in electrical characteristics is suppressed and the reliability is improved. A semiconductor device that includes a transistor is provided. The transistor includes a first conductive film that functions as a first gate electrode, a first gate insulating film, a first oxide semiconductor film that includes a channel region, a second gate insulating film, and a second oxide semiconductor film and a second conductive film that function as a second gate electrode. The second oxide semiconductor film includes a region higher in carrier density than the first oxide semiconductor film. The second conductive film includes a region in contact with the first conductive film.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: May 10, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuharu Hosaka, Yukinori Shima, Masataka Nakada, Masami Jintyou
  • Patent number: 11325113
    Abstract: The present invention discloses photostable composite of indium gallium nitride and zinc oxide for solar water splitting, comprising Indium content in the range of 1-40 wt %, Ga content in the range of 1 to 15 wt %, nitrogen content in the range of 0.1 to 5 wt %, and the remaining is ZnO. The combustion synthesis comprises the steps of: (a) dissolving 45 to 55 wt % urea, 75 to 80 wt % Zinc nitrate, 3 to 5 wt % Gallium nitrate, and 15 to 20 wt % Indium nitrate in water with stirring until a homogenous solution is formed; and (b) heating the homogenous solution of step (a) at a temperature in the range of 450-550 [deg.]C. for period in the range of 2 to 20 min to obtain the photostable composite.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: May 10, 2022
    Assignee: Council of Scientific & Industrial Research
    Inventors: Chinnakonda Subramanian Gopinath, Raja Ambal Sivaraman
  • Patent number: 11329133
    Abstract: Some embodiments include an integrated assembly having a gate material, an insulative material adjacent the gate material, and a semiconductor oxide adjacent the insulative material. The semiconductor oxide has a channel region proximate the gate material and spaced from the gate material by the insulative material. An electric field along the gate material induces carrier flow within the channel region, with the carrier flow being along a first direction. The semiconductor oxide includes a grain boundary having a portion which extends along a second direction that crosses the first direction of the carrier flow. In some embodiments, the semiconductor oxide has a grain boundary which extends along the first direction and which is offset from the insulative material by an intervening portion of the semiconductor oxide. The carrier flow is within the intervening region and substantially parallel to the grain boundary. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Yi Fang Lee, Isamu Asano, Ramanathan Gandhi, Scott E. Sills