Abstract: A display substrate includes: a base substrate; a light-emitting unit in each pixel region and including a first electrode, an organic light-emitting layer, and a second electrode sequentially disposed in a direction away from the base substrate; an auxiliary conductive layer between the light-emitting unit and the base substrate; a pixel circuit in each pixel region and including a driving transistor. The auxiliary conductive layer is on a side of the pixel circuit away from the base substrate, the second electrode has a portion extending out of the pixel region and coupling to the auxiliary conductive layer through a via hole not overlapping the pixel region, the auxiliary conductive layer is insulated and spaced apart from the first electrode and has a mesh or chain shape, and a material of the auxiliary conductive layer is the same as a material of the first and second electrodes of the driving transistor.

Abstract: In a static electricity protection circuit, an N+ embedded region is provided, extending over an upper surface of a P-type P semiconductor substrate. One N?-semiconductor region, another N?-semiconductor region, and an N? common impurity region are provided in an upward direction from the N+ embedded region. The one N?-semiconductor region and the other N?-semiconductor region are coupled together via the N? common impurity region. A P? impurity region is provided in the upward direction from the one N?-semiconductor region. Another P? impurity region is provided in the upward direction from the other N?-semiconductor region. A diode formed by the one P? impurity region and the one N?-semiconductor region and a diode formed by the other P? impurity region and the other N?-semiconductor region are coupled in opposite directions to each other via the N? common impurity region.

Abstract: The present disclosure is directed toward carbon based diodes, carbon based resistive change memory elements, resistive change memory having resistive change memory elements and carbon based diodes, methods of making carbon based diodes, methods of making resistive change memory elements having carbon based diodes, and methods of making resistive change memory having resistive change memory elements having carbons based diodes. The carbon based diodes can be any suitable type of diode that can be formed using carbon allotropes, such as semiconducting single wall carbon nanotubes (s-SWCNT), semiconducting Buckminsterfullerenes (such as C60 Buckyballs), or semiconducting graphitic layers (layered graphene). The carbon based diodes can be pn junction diodes, Schottky diodes, other any other type of diode formed using a carbon allotrope. The carbon based diodes can be placed at any level of integration in a three dimensional (3D) electronic device such as integrated with components or wiring layers.

Abstract: A method of manufacturing a group III nitride semiconductor substrate may comprise introducing group III element vacancies to a first region of the group III nitride semiconductor substrate. The method may comprise introducing an acceptor element to a second region of the group III nitride semiconductor substrate. The second region may contact the first region at least in part. The method may comprise performing annealing to activate the acceptor element in the second region.

Abstract: This invention provides an electroluminescence device comprising an indirect bandgap semiconductor layer, such as silicon or germanium, having a local conduction-band minimum at the ?-point in an E-k diagram for using as a light emitting layer, and a direct bandgap semiconductor layer formed by a heterojunction on the indirect bandgap semiconductor layer for using as an electron supply means transporting electrons from a ?-valley to a ?-valley when a forward-biased voltage is applied, wherein a light emission is occurred by recombining the electrons transported to the ?-valley of the indirect bandgap semiconductor layer with holes located at a valance band maximum of the indirect bandgap semiconductor layer.

Abstract: A method of forming a stacked low temperature diode and related devices. At least some of the illustrative embodiments are methods comprising forming a metal interconnect disposed within an inter-layer dielectric. The metal interconnect is electrically coupled to at least one underlying integrated circuit device. A barrier layer is deposited on the metal interconnect and the inter-layer dielectric. A semiconductor layer is deposited on the barrier layer. A metal layer is deposited on the semiconductor layer. The barrier layer, the semiconductor layer, and the metal layer are patterned. A low-temperature anneal is performed to induce a reaction between the patterned metal layer and the patterned semiconductor layer. The reaction forms a silicided layer within the patterned semiconductor layer. Moreover, the reaction forms a P-N junction diode.

Abstract: Disclosed is a stacked chip module and associated method with integrated circuit (IC) chips having integratable built-in self-maintenance blocks. The module comprises a stack of chips and each chip comprises a self-maintenance block with first and second controllers. The first controller controls wafer-level and module-level servicing (e.g., self-testing or self-repairing) of an on-chip functional block. The second controller provides an interface between an off-chip tester and the first controller during wafer-level servicing. Each chip further comprises a plurality of interconnect structures (e.g., multiplexers and through-substrate-vias) that integrate the self-maintenance blocks of adjacent chips in the stack so that, during module-level servicing, a single second controller on a single one of the chips in the stack (e.g., the bottom chip) provides the only interface between the off-chip tester and all of the first controllers.

Abstract: A micro light emitting diode (LED) and a method of forming an array of micro LEDs for transfer to a receiving substrate are described. The micro LED structure may include a micro p-n diode and a metallization layer, with the metallization layer between the micro p-n diode and a bonding layer. A conformal dielectric barrier layer may span sidewalls of the micro p-n diode. The micro LED structure and micro LED array may be picked up and transferred to a receiving substrate.

Abstract: A power semiconductor device includes an active device region disposed in a semiconductor substrate, an edge termination region disposed in the semiconductor substrate between the active device region and a lateral edge of the semiconductor substrate and a trench disposed in the edge termination region which extends from a first surface of the semiconductor substrate toward a second opposing surface of the semiconductor substrate. The trench has an inner sidewall, an outer sidewall and a bottom. The inner sidewall is spaced further from the lateral edge of the semiconductor substrate than the outer sidewall, and an upper portion of the outer sidewall is doped opposite as the inner sidewall and bottom of the trench to increase the blocking voltage capacity. Other structures can be provided which yield a high blocking voltage capacity such as a second trench or a region of chalcogen dopant atoms disposed in the edge termination region.

Abstract: An organic EL device includes a first substrate including a cathode layer and a smoothing layer, an organic layer formed on the cathode layer, an anode layer formed on the organic layer, and a second substrate joined to the anode layer. In a region of a peripheral portion of the first substrate, the organic layer is not formed. The anode layer is provided on the cathode layer through an insulating layer in a portion of the region so as to extend to an outer peripheral side, the extended anode layer is folded back to a side opposite to the second substrate to constitute an anode taking-out portion, and a portion of the cathode layer of the first substrate is folded back to constitute a cathode taking-out portion.

Abstract: A semiconductor device having a semiconductor die is provided. The semiconductor die includes a main horizontal surface, an outer edge, an active area, and a peripheral area. The peripheral area includes a dielectric structure surrounding the active area and extending from the main horizontal surface into the semiconductor die. The dielectric structure includes, in a horizontal cross-section, at least one substantially L-shaped portion that is inclined against the outer edge. Further, a method for forming a semiconductor device is provided.

Abstract: A semiconductor device includes a channel region; a gate dielectric over the channel region; a gate electrode over the gate dielectric; and a first source/drain region adjacent the gate dielectric. The first source/drain region is of a first conductivity type. At least one of the channel region and the first source/drain region includes a superlattice structure. The semiconductor device further includes a second source/drain region on an opposite side of the channel region than the first source/drain region. The second source/drain region is of a second conductivity type opposite the first conductivity type. At most, one of the first source/drain region and the second source/drain region comprises an additional superlattice structure.

Abstract: A semiconductor device includes a substrate having first main face having rectangular shape, a first electrode provided at the center on first main face of substrate, first electrode is made of conducting material harder than substrate, and a second electrode provided along at least a part of the periphery on first main face so as to surround first electrode, second electrode is integrated with first electrode by the same conducting material as that of the first electrode, and second electrode has a thinner film thickness than that of the first electrode.

Abstract: The generation of a chip identifier supporting at least one integrated circuit, which includes providing a cutout of at least one conductive path by cutting the chip, the position of the cutting line relative to the chip conditioning the identifier.

Abstract: Bacteria in water 9 exposed outdoors are effectively killed with ultraviolet (UV) light by suppressing post-treatment increase in the bacteria population due to photoreactivation. The apparatus shines UV light on the water 9 to kill bacteria and has UV light emitting diodes (LEDs) 1 that emit UVA light with a primary emission peak of 320 nm-400 nm. The antibacterial action of the UVA light emitted by the UV LEDs 1 prevents proliferation of bacteria in the disinfected water 9 due to photoreactivation.

Abstract: A light emitting device is provided. The light emitting device includes a light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, a first dielectric layer over a cavity where a part of the light emitting structure is removed, a second electrode layer over the first dielectric layer, a second dielectric layer over the light emitting structure above the cavity, and a first electrode over the second dielectric layer.

Abstract: Provided is a pixel for picking up an image signal capable of suppressing an occurrence of a cross-talk. The pixel for picking up an image signal includes a substrate surrounded by a trench, a photodiode, and a pass transistor. The photodiode is formed at an upper portion of the substrate and includes a P-type diffusion area and an N-type diffusion area which are joined with each other in a longitudinal direction. The pass transistor is formed at the upper portion of the substrate and includes the one terminal that is the joined P-type diffusion area and the N-type diffusion area, the other terminal that is a floating diffusion area, and a gate terminal disposed between the two terminals. The pixel for picking up an image signal is surrounded by the trench which penetrates the substrate from the upper portion to the lower portion of the substrate, and the trench is filled with an insulator.

Abstract: A surface plasmon-generating apparatus includes an active layer including an n-type region formed on one side and a p-type region formed on the other side, the n-type region and the p-type region being in contact with each other to form a pn junction therebetween; a first barrier layer in contact with a first surface of the active layer; a second barrier layer in contact with a second surface of the active layer, the second surface being opposite the first surface; and a metal body disposed above the pn junction of the active layer with the second barrier layer and an insulating layer therebetween.

Abstract: A phase change memory device having buried conduction lines directly underneath phase change memory cells is presented. The phase change memory device includes buried conduction lines buried in a semiconductor substrate and phase change memory cells arranged on top of the buried conductive lines. By having the buried conduction lines directly underneath the phase change memory cells, the resultant device can realize a considerable reduction in size.

Abstract: The present disclosure provides systems and methods for configuring and constructing a single photo detector or array of photo detectors with all fabrications circuitry on a single side of the device. Both the anode and the cathode contacts of the diode are placed on a single side, while a layer of laser treated semiconductor is placed on the opposite side for enhanced cost-effectiveness, photon detection, and fill factor.

Abstract: In a pn junction diode having a conductivity modulating element provided on a first principal surface of a semiconductor substrate, when an impurity concentration of a p type impurity region is lowered to shorten a reverse recovery time, hole injection is suppressed, thereby causing a problem that a forward voltage value is increased at a certain current point. Moreover, introduction of a life time killer to shorten the reverse recovery time leads to a problem of increased leak current. On an n? type semiconductor layer that is a single crystal silicon layer, a p type polycrystalline silicon layer (p type polysilicon layer) is provided. Since the polysilicon layer has more grain boundaries than the single crystal silicon layer, an amount of holes injected into the n? type semiconductor layer from the p type polysilicon layer in forward voltage application can be suppressed.

Abstract: A phase change memory device having buried conduction lines directly underneath phase change memory cells is presented. The phase change memory device includes buried conduction lines buried in a semiconductor substrate and phase change memory cells arranged on top of the buried conductive lines. By having the buried conduction lines directly underneath the phase change memory cells, the resultant device can realize a considerable reduction in size.

Abstract: The present invention is directed to novel front side illuminated, back side contact photodiodes and arrays thereof. In one embodiment, the photodiode has a substrate with at least a first and a second side and a plurality of electrical contacts physically confined to the second side. The electrical contacts are in electrical communication with the first side through a doped region of a first type and a doped region of a second type, each of the regions substantially extending from the first side through to the second side. In another embodiment, the photodiode comprises a wafer with at least a first and a second side; and a plurality of electrical contacts physically confined to the second side, where the electrical contacts are in electrical communication with the first side through a diffusion of a p+ region through the wafer and a diffusion of an n+ region through the wafer.

Abstract: A semiconductor device which includes a passivation structure formed with a conductive strip of resistive material that crosses itself once around the active region of the device to form a first closed loop, a continuous strip that loops around the first closed loop without crossing itself which crosses itself a second time to form a second closed loop.

Abstract: A semiconductor device including polysilicon (poly-Si) and method of manufacturing the same are provided. The semiconductor device includes a TaNx material layer and a poly-Si layer formed on the TaNx material layer. The semiconductor device including poly-Si may be manufactured by forming a TaNx material layer and forming a poly-Si layer by depositing silicon formed on the TaNx material layer and annealing silicon.

Abstract: An ESD protection structure includes a structure to be protected disposed in a semiconductor body. A region of a first conductivity type is disposed within the semiconductor body and a channel is disposed in the semiconductor body and extends through the region of the first conductivity type. A semiconductor of a second conductivity type is disposed within the channel adjacent the region of the first conductivity type such that the region of the first conductivity type and the semiconductor of the second conductivity type form a diode. At least one of the region of the first conductivity type and the semiconductor of the second conductivity type is electrically coupled to the structure to be protected.

Abstract: Process variation-tolerant diodes and diode-connected thin film transistors (TFTs), printed or patterned structures (e.g., circuitry) containing such diodes and TFTs, methods of making the same, and applications of the same for identification tags and sensors are disclosed. A patterned structure comprising a complementary pair of diodes or diode-connected TFTs in series can stabilize the threshold voltage (Vt) of a diode manufactured using printing or laser writing techniques. The present invention advantageously utilizes the separation between the Vt of an NMOS TFT (Vtn) and the Vt of a PMOS TFT (Vtp) to establish and/or improve stability of a forward voltage drop across a printed or laser-written diode. Further applications of the present invention relate to reference voltage generators, voltage clamp circuits, methods of controlling voltages on related or differential signal transmission lines, and RFID and EAS tags and sensors.

Abstract: The present invention, in one embodiment, provides a method of producing a PN junction the method including providing a single crystal substrate; forming an insulating layer on the single crystal substrate; forming a via through the insulating layer to provide an exposed portion of the single crystal substrate; forming amorphous Si on at least the exposed portion of the single crystal substrate; converting at least a portion of the amorphous Si into single crystal Si; and forming dopant regions in the single crystal Si. In one embodiment the diode of the present invention is integrated with a memory device.

Abstract: An inclined surface having an inclination angle ? is formed in an edge portion which forms an opening portion of an inter-layer insulating film, thereby reducing a stress by the inclined surface.

Abstract: A semiconductor structure includes an interconnect region and a semiconductor stack bonded to the interconnect region through a bonding region. The stack includes at least two semiconductor layers having different electrical properties. The stack also includes single crystalline semiconductor material. The stack can be processed to form a mesa structure and the mesa structure can be processed to from a vertically oriented semiconductor device.

Abstract: A phase change memory device that has a diode with an enlarged, i.e., bulging, PN interfacial junction and a corresponding fabrication method are presented. The phase change memory device includes a semiconductor substrate, an insulation layer, a diode, and a phase change memory cell. The insulation layer is placed on the semiconductor substrate and has a contact hole which is wider in a middle portion than the lower and upper portions of the contact hole. The diode is formed within the contact hole and PN interfacial junction at the wider middle portion of the diode within the contact hole. The phase change memory cell is formed on top of the diode.

Abstract: An apparatus and method for making it. Some embodiments include a light-emitting device having a light-emitting active region; a tunneling-barrier (TB) structure facing adjacent the active region; a TB grown-epitaxial-metal-mirror (TB-GEMM) structure facing adjacent the TB structure, wherein the TB-GEMM structure includes at least one metal is substantially lattice matched to the active region; and a conductivity-type III-nitride crystal structure adjacent facing the active region opposite the TB structure. In some embodiments, the active region includes an MQW structure. In some embodiments, the TB-GEMM includes an alloy composition such that metal current injectors have a Fermi energy potential substantially equal to the sub-band minimum energy potential of the MQW. Some embodiments further include a second mirror (optionally a GEMM) to form an optical cavity between the second mirror and the TB-GEMM structure.

Abstract: A negative differential resistance (NDR) device, and methods of making and using the NDR device. The NDR device includes a substrate comprising a conductor material or a semi-conductor material and a self-assembled monolayer (SAM) that includes a first electroactive moiety and a spacer moiety disposed on the substrate that defines a barrier between the electroactive moiety and the substrate, wherein the NDR device exhibits negative differential resistance in the presence of a varying applied voltage. Also provided are NDR in multilayers in which the peak to valley ratio of the NDR response can be controlled by the number of layers; modulation of NDR using binding groups to one of the electrical contacts or to the electroactive moiety itself; and NDR devices that display multiple peaks in the current-voltage curve that contain electroactive moieties that have multiple low potential electrochemical oxidations and/or reductions.

Abstract: A semiconductor component includes a semiconductor body and a second semiconductor zone of a first conductivity type that serves as a rear side emitter. The second semiconductor zone is preceded by a plurality of third semiconductor zones of a second conductivity type that is opposite to the first conductivity type. The third semiconductor zones are spaced apart from one another in a lateral direction. In addition, provided within the semiconductor body is a field stop zone spaced apart from the second semiconductor zone, thereby reducing an electric field in the direction toward the second semiconductor zone.

Abstract: A memory allowing reduction of a memory cell size is obtained. This memory comprises a first conductive type first impurity region formed on the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell and a word line, a plurality of second conductive type second impurity regions formed on the surface of the first impurity region at a prescribed interval, each functioning as a second electrode of the diode, a bit line formed on the semiconductor substrate and connected to the second impurity regions and a wire provided above the bit line and connected to the first impurity region every prescribed interval.

Abstract: Nanostructures with 0, 1, 2 and 3 dimensions, with negative differential resistance and method for making these nanostructures. A nanostructure according to the invention may notably be used in nanoelectronics. It comprises at least one structure (32) or at least one plurality of said at least one structure, at the surface of a silicon carbide substrate (30), the structure being selected from quantum dots, atomic segments, atomic lines and clusters, and at least one metal deposit (34), this metal deposit covering at least the structure or at least the plurality of said at least one structure, or of the combination of two or more of these nanostructures with 0, 1, 2 or 3 dimensions.

Abstract: An indirect connection to and across a photodiode array. The backside contact is used as one portion which connects to a capacitor. The capacitor forms a shunt across the bulk substrate, thus shunting across the series resistance of the substrate, and reducing the series resistance.

Abstract: A semiconductor device includes a semiconductor region wherein the semiconductor region is a forced or non-forced Near Natural breakdown region, which is completely depleted when a predetermined voltage having a magnitude less than or equal to the breakdown voltage of a non-Natural breakdown (for example, Zener breakdown and Avalanche breakdown) is applied across the device.

Abstract: A thermionic or thermotunneling gap diode device consisting of two silicon electrodes maintained at a desired distance from one another by means of spacers. These spacers are formed by oxidizing one electrode, protecting certain oxidized areas and removing the remainder of the oxidized layer. The protected oxidized areas remain as spacers. These spacers have the effect of maintaining the electrodes at a desired distance without the need for active elements, thus greatly reducing costs.

Abstract: An arrangement of pillar shaped p-i-n diodes having a high aspect ration are formed on a semiconductor substrate. Each device is formed by an intrinsic or lightly doped region (i-region) positioned between a P+ region and an N+ region at each end of the pillar. The arrangement of pillar p-i-n diodes is embedded in an optical transparent medium. For a given surface area, more light energy is absorbed by the pillar arrangement of p-i-n diodes than by conventional planar p-i-n diodes. The pillar p-i-n diodes are preferably configured in an array formation to enable photons reflected from one pillar p-i-n diode to be captured and absorbed by another p-i-n diode adjacent to the first one, thereby optimizing the efficiency of energy conversion.

Abstract: A p-type semiconductor carbon nanotube and a method of manufacturing the same are provided. The p-type semiconductor carbon nanotube includes a carbon nanotube; and a halogen element that is attached to an inner wall of the carbon nanotube and accepts electrons from the carbon nanotube to achieve p-type doping of the carbon nanotube. The p-type semiconductor carbon nanotube is stable at high temperatures and can maintain intrinsic good electrical conductivity of the carbon nanotube. The p-type semiconductor carbon nanotube can be relatively easily obtained using a conventional method of manufacturing a carbon nanotube, thereby significantly broadening the range of application of the carbon nanotube to electronic devices.

Abstract: A nano tube cell and a memory device using the same features a cross point cell using a capacitor and a PNPN nano tube switch to reduce the whole memory size. In the memory device, the unit nano tube cell comprising a capacitor and a PNPN nano tube switch which does not an additional gate control signal is located where a word line and a bit line are crossed, so that a cross point cell array is embodied. As a result, the whole chip size is reduced, and read and write operations are effectively improved.

Abstract: A rectifying contact to an n-type oxide material and/or a substantially insulating oxide material includes a p-type oxide material. The p-type oxide material includes a copper species and a metal species, each of which are present in an amount ranging from about 10 atomic % to about 90 atomic % of total metal in the p-type oxide material. The metal species is selected from tin, zinc, and combinations thereof.

Abstract: The present invention discloses a nano tube cell, and a semiconductor device having the nano tube cell and a double bit line sensing structure. The cell array circuit includes a plurality of top sub cell arrays, a plurality of bottom sub cell arrays, a main bit line sense amp and a word line driving unit. Especially, the top and bottom sub cell arrays have a double bit line sensing structure for inducing a sensing voltage of a main bit line by controlling a volume of a current supplied from a power voltage to the main bit line according to a sensing voltage of a sub bit line receiving a cell data. Each of the sub cell arrays includes a capacitor, and a PNPN nano tube cell having a PNPN diode switch selectively turned on/off according to a voltage difference between one side terminal of the capacitor and the sub bit line, to decrease a cell size and improve operational characteristics of the circuit.

Abstract: A semiconductor device includes a semiconductor region wherein the semiconductor region is a forced or non-forced Near Natural breakdown region, which is completely depleted when a predetermined voltage having a magnitude less than or equal to the breakdown voltage of a non-Natural breakdown (for example, Zener breakdown and Avalanche breakdown) is applied across the device.

Abstract: A pixel sensor cell structure and method of manufacture. The pixel cell comprises a doped layer formed adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinning layer is reduced.

Abstract: A nonvolatile memory device features a serial diode cell as a cross-point cell using a nonvolatile ferroelectric capacitor and a serial diode chain. The serial diode cell comprises a ferroelectric capacitor and a serial diode switch. The ferroelectric capacitor, located where a word line and a bit line are crossed, stores values of logic data. The serial diode switch is connected between the ferroelectric capacitor and the bit line and selectively switched depending on voltages applied to the word line. The nonvolatile memory device using a serial diode cell comprises a plurality of serial diode cell arrays, a plurality of word line driving units and a plurality of sense amplifiers. Each of the plurality of serial diode cell arrays each includes a single serial diode cell where a word line and a bit line are crossed. The plurality of word line driving units selectively drive the word line. The plurality of sense amplifiers sense and amplify data transmitted through the bit line.

Abstract: A diode is provided which includes a first-conductivity-type cathode layer, a first-conductivity-type drift layer placed on the cathode region and having a lower concentration than the cathode layer, a generally ring-like second-conductivity-type ring region formed in the drift layer, second-conductivity-type anode region formed in the drift layer located inside the ring region, a cathode electrode formed in contact with the cathode layer, and an anode electrode formed in contact with the anode region, wherein the lowest resistivity of the second-conductivity-type anode region is at least 1/100 of the resistivity of the drift layer, and the thickness of the anode region is smaller than the diffusion depth of the ring region.

Abstract: A vertical geometry light emitting diode is disclosed that is capable of emitting light in the red, green, blue, violet and ultraviolet portions of the electromagnetic spectrum. The light emitting diode includes a conductive silicon carbide substrate, an InGaN quantum well, a conductive buffer layer between the substrate and the quantum well, a respective undoped gallium nitride layer on each surface of the quantum well, and ohmic contacts in a vertical geometry orientation.

Abstract: A vertical geometry light emitting diode is disclosed that is capable of emitting light in the red, green, blue, violet and ultraviolet portions of the electromagnetic spectrum. The light emitting diode includes a conductive silicon carbide substrate, an InGaN quantum well, a conductive buffer layer between the substrate and the quantum well, a respective undoped gallium nitride layer on each surface of the quantum well, and ohmic contacts in a vertical geometry orientation.