Abstract: The present invention relates to a semiconductor heat treatment member for holding a semiconductor wafer, including a base member a surface of which is covered with an oxide film, the base member including a silicon carbide, in which a surface of a wafer holding portion to be in contact with a semiconductor wafer has an arithmetic average roughness Ra of smaller than or equal to 0.3 ?m and an element average length RSm of shorter than or equal to 40 ?m.

Abstract: An organic light-emitting device is provided That includes: a first electrode; a second electrode facing the first electrode; m number of emission units disposed between the first electrode and the second electrode, the emission units each including at least one emission layer. m?1 charge generation layers are disposed between two adjacent emission units and each includes an n-type charge generation layer and a p-type charge generation layer. Maximum emission wavelengths of light emitted by two emission units may be different.

Abstract: A device configured to transfer a micro element includes: a pick-up head array configured to selectively pick up or release the micro element, and including a plurality of pick-up heads; and a test circuit having a plurality of sub-test circuits, each sub-test circuit corresponding to one pick-up head among the plurality of pick-up heads, and having at least two test electrodes for simultaneous testing of photoelectric parameters of the micro element when the transfer device transfers the micro element.

Abstract: A transfer device for micro element with a test circuit can test the micro element during transfer. The transfer device for micro elements includes: a base substrate, having two surfaces opposite to each other; a pick-up head array, formed over the first surface of the base substrate for picking up or releasing the micro element; a test circuit set inside or/on the surface of the base substrate, which has a series of sub-test circuits, each sub-test circuit at least having two test electrodes for simultaneous test of photoelectric parameters of the micro element when the transfer device transfers the micro element.

Abstract: A light emitting device includes: a light emitting layered structure; an electrode unit connected to the light emitting layered structure and including a transparent electrode layer of a primary metal oxide which is stacked on the light emitting layered structure along a stacking direction; and a total-internal-reflection suppression material dispersed in the transparent electrode layer and containing a secondary metal oxide that is different from the primary metal oxide. The secondary metal oxide has a concentration gradient within the transparent electrode layer along the stacking direction. The light output power of the light emitting device may be increased by about 44% as compared to a conventional light emitting device.

Abstract: A semiconductor apparatus includes: a semiconductor apparatus includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; and a third semiconductor layer of the first conductivity type, wherein: the second semiconductor layer is formed between the first and third semiconductor layers, and the first and second semiconductor layers are in contact with each other; and a first energy level at a bottom edge of a conduction band of the first semiconductor layer is lower than a second energy level at a top edge of a valence band of the second semiconductor layer, and the second energy level at the top edge of the valence band of the second semiconductor layer is substantially the same as a third energy level at a bottom edge of a conduction band of the third semiconductor layer.

Abstract: A method includes implanting recombination center atoms via a first surface into a semiconductor body and causing the implanted recombination center atoms to diffuse in the semiconductor body in a first diffusion process.

Abstract: A resistive switching memory device is provided with first to third electrodes. The first electrode forms a Schottky barrier which can develop a rectifying property and resistance change characteristics at an interface between the first electrode and an oxide semiconductor. The third electrode is made of a material which provides an ohmic contact with the oxide semiconductor. A control voltage is applied between the first and second electrodes, and a driving voltage is applied between the first and third electrodes.

Abstract: Exemplary embodiments provide materials and methods of forming high-quality semiconductor devices using lattice-mismatched materials. In one embodiment, a composite film including one or more substantially-single-particle-thick nanoparticle layers can be deposited over a substrate as a nanoscale selective growth mask for epitaxially growing lattice-mismatched materials over the substrate.

Abstract: The present invention aims at providing an organic EL device that emits light by an alternating current, has a simple structure and provides little increase of production processes, while downsizing an overall configuration and a simplifying a method for producing said organic EL device. The organic EL device includes a power feeding part and an organic-EL-element forming part. The organic-EL-element forming part includes a plurality of unit EL elements formed on a substrate. There is provided a plurality of series-connected parts each formed by a plurality of the unit EL elements that are electrically connected in series in a forward direction. A plurality of the series-connected parts are electrically connected to the power feeding part in parallel. The series-connected parts that are connected in parallel include a series-connected part that is connected to the power feeding part so as to have a reverse polarity.

Abstract: An embodiment of a semiconductor device includes a gallium nitride (GaN) substrate having a first surface and a second surface. The second surface is substantially opposite the first surface, at least one device layer is coupled to the first surface, and a backside metal is coupled to the second surface. A top metal stack is coupled to the at least one device layer. The top metal stack includes a contact metal coupled to a surface of the at least one device layer, a protection layer coupled to the contact metal, a diffusion barrier coupled to the protection layer, and a pad metal coupled to the diffusion barrier. The semiconductor device is configured to conduct electricity between the top metal stack and the backside metal.

Abstract: A micro light emitting diode (LED) and a method of forming an array of micro LEDs for transfer to a receiving substrate are described. The micro LED structure may include a micro p-n diode and a metallization layer, with the metallization layer between the micro p-n diode and a bonding layer. A conformal dielectric barrier layer may span sidewalls of the micro p-n diode. The micro LED structure and micro LED array may be picked up and transferred to a receiving substrate.

Abstract: A nonvolatile memory device includes a substrate and a first insulating layer on the substrate. The first insulating layer includes a first opening therein. A lower electrode is provided in the first opening and protrudes from a surface of the first insulating layer outside the first opening. An electrode passivation pattern is provided on a sidewall of the lower electrode that protrudes from the surface of the first insulating layer. A second insulating layer is provided on the first insulating layer and includes a second opening therein at least partially exposing the lower electrode. A variable resistance material layer extends into the second opening to contact the lower electrode. The electrode passivation layer electrically separates the sidewall of the lower electrode from the variable resistance material layer. The electrode passivation pattern is formed of a material having an etching selectivity to that of the second insulating layer. Related fabrication methods are also discussed.

Abstract: A component and a method for producing a component are disclosed. The component comprises an integrated circuit, a housing body, a wiring device overlapping the integrated circuit and the housing body, and one or more external contact devices in communication with the wiring device.

Abstract: A substrate is provided that has a metallic layer on a substrate surface of a substrate. A film made of a two dimensional (2-D) material, such as graphene, is deposited on a metallic surface of the metallic layer. The metallic layer is dewet and/or removed to provide the film on the substrate surface.

Abstract: A semiconductor device includes: an emitter electrode formed of a silicide film, and provided on a semiconductor layer; an insulating film provided on the emitter electrode; and an electrode pad made of Al, and provided on the insulating film.

Abstract: A fast recovery rectifier structure with the combination of Schottky structure to relieve the minority carriers during the forward bias condition for the further reduction of the reverse recovery time during switching in addition to the lifetime killer such as Pt, Au, and/or irradiation. This fast recovery rectifier uses unpolished substrates and thick impurity diffusion for low cost production. A reduced p-n junction structure with a heavily p-type doped thin film is provided to terminate and shorten the p-n junction space charge region. This reduced p-n junction with less total charge in the p-n junction to further improve the reverse recovery time. This reduced p-n junction can be used alone, with the traditional lifetime killer method, with the Schottky structure and/or with the epitaxial substrate.

Abstract: To provide an electrode for an organic device which can be widely applied to organic devices by having both hole injection function and electron injection function. A carrier injection electrode layer 110 in which a metal for electron injection 112 (a metal having a work function of 4.2 eV or less) and a metal for hole injection 113 (a metal having a work function of more than 4.2 eV) are mixed with one kind of organic compound 111 is provided between a first organic layer 100a and a second organic layer 100b. Thus, carriers are injected into a carrier injection electrode layer 110 in the direction according to voltage application, and seemingly, current flows between an organic layer 100 and a metal electrode 101, or between the first organic layer 100a and the second organic layer 100b.

Abstract: A semiconductor device includes a substrate having first main face having rectangular shape, a first electrode provided at the center on first main face of substrate, first electrode is made of conducting material harder than substrate, and a second electrode provided along at least a part of the periphery on first main face so as to surround first electrode, second electrode is integrated with first electrode by the same conducting material as that of the first electrode, and second electrode has a thinner film thickness than that of the first electrode.

Abstract: The present invention discloses a method for lift-off of an LED substrate. By eroding the sidewall of a GaN epitaxial layer, cavity structures are formed, which may act in cooperation with a non-fully filled patterned sapphire substrate from epitaxial growth to cause the GaN epitaxial layer to separate from the sapphire substrate. The method according to an embodiment of the present invention can effectively reduce the dislocation density in the growth of a GaN-based epitaxial layer; improve lattice quality, and realize rapid lift-off of an LED substrate, and has the advantages including low cost, no internal damage to the GaN film, elevated performance of the photoelectric device and improved luminous efficiency.

Abstract: This thin-film transistor includes adhesive strength enhancing films between a barrier film and electrode films. Each of the adhesive strength enhancing film is composed of two zones including (a) a pure copper zone that is formed on the electrode film side, and (b) a component concentrated zone that is formed in an interface portion contact with the barrier film, and that includes Cu, Ca, oxygen, and Si as constituents. In concentration distributions of Ca and oxygen in a thickness direction of the component concentrated zone, a maximum content of Ca of a Ca-containing peak is in a range of 5 to 20 at %, and a maximum content of oxygen of an oxygen-containing peak is in a range of 30 to 50 at %, respectively.

Abstract: A method of forming an ohmic contact on a substrate is described. The method includes depositing a set of silicon particles on the substrate surface. The method also includes heating the substrate in a baking ambient to a baking temperature and for a baking time period in order to create a densified film ink pattern. The method further includes exposing the substrate to a dopant source in a diffusion furnace with a deposition ambient, the deposition ambient comprising POCl3, a carrier N2 gas, a main N2 gas, and a reactive O2 gas at a deposition temperature and for a deposition time period, wherein a PSG layer is formed on the substrate surface. The method also includes heating the substrate in a drive-in ambient to a drive-in temperature and for a drive-in time period; and depositing a silicon nitride layer. The method further includes depositing a set of metal contacts on the set of silicon particles; and heating the substrate to a firing temperature and for a firing time period.

Abstract: An active device array substrate including a first patterned conductive layer, a dielectric layer, a second patterned conductive layer, a passivation layer and pixel electrodes is provided. The first patterned conductive layer includes scan lines, common lines, gates and strip floating shielding patterns. The dielectric layer covering the first patterned conductive layer has first contact holes which expose a portion of the common lines, respectively. The second patterned conductive layer includes data lines, sources, drains and strip capacitance electrodes. Each strip capacitance electrode is electrically connected to one of the common lines through one of the first contact holes. A gap is formed between each data line and one strip capacitance electrode, and the strip floating shielding patterns are disposed under the data lines, the gap and the strip capacitance electrodes. Each pixel electrode is electrically connected to one of the drains through one of the second contact holes.

Abstract: An device according to the present invention comprises: graphene; and a metal electrode, the metal electrode and the graphene being electrically connected, the following relationship of Eq. (1) being satisfied: coth ? ( r GP r C ? S ) < 1.3 , Eq . ? ( 1 ) where rGP (in units of ?/?m2) denotes the electrical resistance of a graphene layer per unit area, rC (in units of ??m2) denotes the contact resistance per unit area between the graphene layer and a metal electrode, and S denotes the contact area (in units of ?m2) between the graphene layer and the metal electrode.

Abstract: The invention provides a method for forming an extended gate field effect transistor (EGFET) based sensor, including: (a) providing a substrate; (b) forming a sensing film including titanium dioxide, ruthenium doped titanium dioxide or ruthenium oxide on the substrate; and (c) forming a conductive wire extended from the sensing film for external contact.

Abstract: A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain regions is a field effect source/drain region generated by a fringe field of the gate. The other source/drain region is a PN-junction source/drain region having different impurity fields and different conductivity than the substrate. At least one of the source/drain regions is a field effect source/drain region. Accordingly, a short channel effect is reduced or eliminated in the device.

Abstract: The switching element of the present invention includes an ion conduction layer (40) capable of conducting metal ions, a first electrode (21) and a second electrode (31) provided in contact with the ion conduction layer (40), and a third electrode (35) provided in contact with the ion conduction layer (40) and capable of supplying metal ions, and is of a configuration in which the area over which the first electrode (21) contacts the ion conduction layer (40) is smaller than the area over which the second electrode (31) contacts the ion conduction layer (40). The use of this configuration decreases the leak current in the OFF state.

Abstract: A lower electrode layer 2, an upper electrode layer 4 formed above the lower electrode layer 2, and a metal oxide thin film layer 3 formed between the lower electrode layer 2 and the upper electrode layer 4 are provided. The metal oxide thin film layer 3 includes a first region 3a whose value of resistance increases or decreases by an electric pulse that is applied between the lower electrode layer 2 and the upper electrode layer 4 and a second region 3b arranged around the first region 3a and having a larger content of oxygen than the first region 3a, wherein the lower and upper electrode layers 2 and 4 and at least a part of the first region 3a are arranged so as to overlap as viewed from the direction of the thickness of the first region 3a.

Abstract: The present invention, in one embodiment, provides a method of producing a PN junction the method including providing a single crystal substrate; forming an insulating layer on the single crystal substrate; forming a via through the insulating layer to provide an exposed portion of the single crystal substrate; forming amorphous Si on at least the exposed portion of the single crystal substrate; converting at least a portion of the amorphous Si into single crystal Si; and forming dopant regions in the single crystal Si. In one embodiment the diode of the present invention is integrated with a memory device.

Abstract: A fast recovery rectifier structure with the combination of Schottky structure to relieve the minority carriers during the forward bias condition for the further reduction of the reverse recovery time during switching in addition to the lifetime killer such as Pt, Au, and/or irradiation. This fast recovery rectifier uses unpolished substrates and thick impurity diffusion for low cost production. A reduced p-n junction structure with a heavily doped film is provided to terminate and shorten the p-n junction space charge region. This reduced p-n junction with less total charge in the p-n junction to further improve the reverse recovery time. This reduced p-n junction can be used alone, with the traditional lifetime killer method, with the Schottky structure and/or with the epitaxial substrate.

Abstract: A nonvolatile semiconductor memory apparatus 25 comprises a semiconductor substrate 11, a lower-layer wire 12 formed on the semiconductor substrate 11, an upper-layer wire 20 formed above the lower-layer wire 12 to cross the lower-layer wire 12, an interlayer insulating film 13 provided between the lower-layer wire 12 and the upper-layer wire 20, and a resistance variable layer 15 which is embedded in a contact hole 14 formed in the interlayer insulating film 13 and is electrically connected to the lower-layer wire 12 and the upper-layer wire 20. The upper-layer wire 20 includes at least two layers which are a lowermost layer 21 made of an electrically-conductive material having a hydrogen barrier property and an electric conductor layer 22 having a specific resistance which is lower than a specific resistance of the lowermost layer 21.

Abstract: One embodiment of the present invention provides a semiconductor light-emitting device. The semiconductor light-emitting device includes a substrate, a p-type doped InGaAIN layer, an n-type doped InGaAIN layer, and an active layer situated between the p-type doped and n-type doped InGaAIN layers. The semiconductor light-emitting device further includes an n-side Ohmic-contact layer coupled to an N-polar surface of the n-type doped InGaAIN layer. The Ohmic-contact layer comprises at least one of Au, Ni, and Pt, and at least one of group IV elements.

Abstract: A method for forming a contact to a substrate is disclosed. The method includes providing a substrate, the substrate being doped with a first dopant; and diffusing a second dopant into at least a first side of the substrate to form a second dopant region, the first side further including a first side surface area. The method also includes forming a dielectric layer on the first side of the substrate. The method further includes forming a set of composite layer regions on the dielectric layer, wherein each composite layer region of the set of composite layer regions further includes a set of Group IV semiconductor nanoparticles and a set of metal particles. The method also includes heating the set of composite layer regions to a first temperature, wherein at least some composite layer regions of the set of composite layer regions etch through the dielectric layer and form a set of contacts with the second dopant region.

Abstract: A lower electrode layer 2, an upper electrode layer 4 formed above the lower electrode layer 2, and a metal oxide thin film layer 3 formed between the lower electrode layer 2 and the upper electrode layer 4 are provided. The metal oxide thin film layer 3 includes a first region 3a whose value of resistance increases or decreases by an electric pulse that is applied between the lower electrode layer 2 and the upper electrode layer 4 and a second region 3b arranged around the first region 3a and having a larger content of oxygen than the first region 3a, wherein the lower and upper electrode layers 2 and 4 and at least a part of the first region 3a are arranged so as to overlap as viewed from the direction of the thickness of the first region 3a.

Abstract: Nanostructures with 0, 1, 2 and 3 dimensions, with negative differential resistance and method for making these nanostructures. A nanostructure according to the invention may notably be used in nanoelectronics. It comprises at least one structure (32) or at least one plurality of said at least one structure, at the surface of a silicon carbide substrate (30), the structure being selected from quantum dots, atomic segments, atomic lines and clusters, and at least one metal deposit (34), this metal deposit covering at least the structure or at least the plurality of said at least one structure, or of the combination of two or more of these nanostructures with 0, 1, 2 or 3 dimensions.

Abstract: A high-frequency noise isolation structure and a method for forming the same are provided. The noise isolation structure isolates a first device region and a second device region over a semiconductor substrate. The noise isolation structure preferably includes a sinker region substantially encircling a first device region, a buried layer underlying the first device region and joining the sinker region, a deep guard ring substantially encircling the sinker region, and a deep trench oxide region substantially encircling the sinker region. The isolation structure further includes a wide guard ring between the first and the second device regions. The sinker region and the buried region preferably have a high impurity concentration. Integrated circuits to be noise decoupled are preferably formed in the respective first and second device regions.

Abstract: A phase change memory device and a method of fabricating the same are disclosed. The phase change memory device includes a first conductor pattern having a first conductivity type and a sidewall. A second conductor pattern is connected to the sidewall of the first conductor pattern to form a diode. A phase change layer is electrically connected to the second conductor pattern and a top electrode is connected to the phase change layer.

Abstract: A p-type semiconductor carbon nanotube and a method of manufacturing the same are provided. The p-type semiconductor carbon nanotube includes a carbon nanotube; and a halogen element that is attached to an inner wall of the carbon nanotube and accepts electrons from the carbon nanotube to achieve p-type doping of the carbon nanotube. The p-type semiconductor carbon nanotube is stable at high temperatures and can maintain intrinsic good electrical conductivity of the carbon nanotube. The p-type semiconductor carbon nanotube can be relatively easily obtained using a conventional method of manufacturing a carbon nanotube, thereby significantly broadening the range of application of the carbon nanotube to electronic devices.

Abstract: A method of forming and a device including an interconnect structure having a unidirectional electrical conductive material is described. The unidirectional conductive material may overlie interconnect materials, and/or may surround interconnect materials, such as by lining the walls and base of a trench and via. The unidirectional conductive material may be configured to conduct electricity in a direction corresponding to a projection to or from a contact point and conductive material overlying the unidirectional conductive material, but have no substantial electrical conductivity in other directions. Moreover, the unidirectional conductive material may be electrically conductive in a direction normal to a surface over which it is formed or in directions along or across a plane, but have no substantial electrical conductivity in other directions.

Abstract: A method of fabricating a CoSb3-based thermoelectric device is disclosed. The method includes providing a high-temperature electrode, providing a buffer layer on the high-temperature electrode, forming composite n-type and p-type layers, attaching the buffer layer to the composite n-type and p-type layers, providing a low-temperature electrode on the composite n-type and p-type layers and separating the composite n-type and p-type layers from each other to define n-type and p-type legs between the high-temperature electrode and the low-temperature electrode.

Abstract: A method for forming a metal wiring of a semiconductor device, includes forming a first metal layer on a wafer, partially etching a portion of the first metal layer where a metal wiring is to be formed, sequentially forming a first copper barrier layer, a copper seed layer, and a copper layer on the first metal layer, annealing the copper layer, polishing the resulting structure until the first metal layer is exposed, patterning the first metal layer and the first copper barrier layer to form a portion of a metal wiring, forming a second copper barrier layer, forming a second metal layer, and patterning the second metal layer and the second copper barrier layer to form the metal wiring.

Abstract: A fast recovery rectifier structure with the combination of Schottky structure to relief the minority carriers during the forward bias condition for the further reduction of the reverse recovery time during switching in addition to the lifetime killer such as Pt, Au, and/or irradiation. This fast recovery rectifier uses unpolished substrates and thick impurity diffusion for low cost production. A reduced p-n junction structure with a heavily doped film is provided to terminate and shorten the p-n junction space charge region. This reduced p-n junction with less total charge in the p-n junction to further improve the reverse recovery time. This reduced p-n junction can be used alone, with the traditional lifetime killer method, with the Schottky structure and/or with the epitaxial substrate.

Abstract: This invention concerns a process for producing integrated circuits containing at least one layer of elemental metal which during the processing of the integrated circuit is at least partly in the form of metal oxide, and the use of an organic compound containing certain functional groups for the reduction of a metal oxide layer formed during the production of an integrated circuit. According to the present process the metal oxide layer is at least partly reduced to elemental metal with a reducing agent selected from organic compounds containing one or more of the following functional groups: alcohol (—OH), aldehyde (—CHO), and carboxylic acid (—COOH).

Abstract: Processes for effecting thermal transfer of electroactive organic material are disclosed wherein unwanted portions of a layer of electroactive organic material supported by a donor element are removed or transferred from the layer by thermal transfer, particularly laser-induced thermal transfer, leaving a desired pattern of the electroactive organic material on the donor element. The electroactive organic material may be an organic material exhibiting electroluminescence, charge transport, charge injection, electrical conductivity, semiconductivity and/or exciton blocking. The layer of electroactive organic material may comprise more than one layer of different types of electroactive organic material. The exposure pattern is a negative image of the desired pattern. The electroactive organic material of the desired pattern is not, therefore, exposed to the heat which can cause decomposition.

Abstract: A particle, includes a semiconductor nanocrystal. The nanocrystal is doped.

Abstract: In a semiconductor module, twenty five semiconductor devices having light receiving properties, for example, are arranged in five by five matrices using a conductor mechanism formed from six lead frames Each column of semiconductor devices is connected in series and each row of semiconductor devices is connected in parallel. These are embedded in a light transmitting member formed from a transparent synthetic resin, and a positive electrode terminal and a negative electrode terminal are disposed. The semiconductor devices are formed with first and second flat surfaces, and negative electrodes and positive electrodes are disposed.

Abstract: A plurality of buried conductors and/or buried plate patterns formed within a monocrystalline substrate is disclosed. A plurality of empty-spaced buried patterns are formed by drilling holes in the monocrystalline substrate and annealing the monocrystalline substrate to form empty-spaced patterns of various geometries. The empty-spaced patterns are then connected through vias with surfaces of the monocrystalline substrate. The empty-spaced patterns and their respective vias are subsequently filled with conductive materials.

Abstract: Provided is a light emitting device and a method of manufacturing the same. The light emitting device comprises a transparent substrate, an n-type compound semiconductor layer formed on the transparent substrate, an active layer, a p-type compound semiconductor layer, and a p-type electrode sequentially formed on a first region of the n-type compound semiconductor layer, and an n-type electrode formed on a second region separated from the first region of the n-type compound semiconductor layer, wherein the p-type electrode comprises first and second electrodes, each electrode having different resistance and reflectance.

Abstract: With a solar ball 10 serving as a light-receiving semiconductor apparatus, the outer surface of a spherical solar cell 1 is covered with a light-transmitting outer shell member 11, and electrode members 14, 15 are connected to electrodes 6, 7 of the solar cell 1. The outer shell member 11 comprises a capsule 12 produced by bonding together two halves, and a filler 13 that is packed inside this capsule and cured. A solar panel can be configured such that a plurality of the solar balls 10 are arrayed in a matrix and connected in parallel and in series, or a solar panel can be configured such that a multiplicity of spherical solar cells 1 are arrayed in a matrix and covered with a transparent outer shell member. A solar string in the form of a rod or cord can be configured such that a plurality of the solar cells 1 are arrayed in columns and connected in parallel, and then covered with a transparent outer shell member.

Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.