Test Or Calibration Structure Patents (Class 257/48)
  • Patent number: 10845846
    Abstract: A portable electronic device that can operate even when electric power supplied through contactless charge by electromagnetic induction is low is provided. The portable electronic device includes a reflective liquid crystal display which includes a transistor including an oxide semiconductor, a power source portion which includes a rechargeable battery capable of charge by contactless charge, and a signal processing portion which includes a nonvolatile semiconductor memory device. In the portable electronic device, electric power stored in the rechargeable battery is used in the reflective liquid crystal display and the signal processing portion.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: November 24, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 10823683
    Abstract: A method for detecting defects in deep features like channel holes, via holes or trenches based on laser-enhanced electron tunneling effect. A substrate having thereon a film stack is provided. First and second deep features are formed in the film stack. The first deep feature has a sacrificial oxide layer disposed at its bottom. The second deep feature comprises an under-etch defect. The sacrificial oxide layer has a thickness of less than 50 angstroms. The substrate is subjected to a laser-enhanced electron beam inspection process. The substrate is scanned by an electron beam and illuminated by a laser beam. The laser beam induces electron tunneling across the sacrificial protection layer, thereby capturing a bright voltage contrast (BVC) signal corresponding to the first deep feature, and detecting a dark voltage contrast (DVC) signal corresponding to the second deep feature.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: November 3, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Sheng Chao Nie, Jin Xing Chen, Junqi Ren
  • Patent number: 10812089
    Abstract: Apparatus and associated methods relating to reducing lock time include pre-calibrating and storing phase-locked loop (PLL) and/or injection-locked oscillator (ILO) adaptation values during startup and loading the pre-calibrated values during rate change. In an illustrative example, an integrated circuit may include a controllable frequency circuit operable at frequencies within each of a plurality of frequency bands. A data store may store operational settings associated with each frequency of the plurality of frequency bands. A state machine may be coupled to the controllable frequency circuit and the data store configured to select a predetermined frequency band in response to a command signal, retrieve, from the data store, operational settings associated with the predetermined frequency band, and, apply the retrieved operational settings to the controllable frequency circuit.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: October 20, 2020
    Assignee: XILINX, INC.
    Inventors: Caleb S. Leung, Edward Lee, Alan C. Wong, Christopher J. Borrelli, Yohan Frans
  • Patent number: 10811362
    Abstract: An overlay mark structure includes a plurality of first patterns of a previous layer and a plurality of second patterns of a current layer. Each of the second patterns includes a first section and a second section. The first section is disposed corresponding to one of the first patterns in a vertical direction. The first section partially overlaps the first pattern corresponding to the first section in the vertical direction. The second section is separated from the first section in an elongation direction of the second pattern. A part of the first pattern corresponding to the first section is disposed between the first section and the second section in the elongation direction of the second pattern. A measurement method of the overlay mark structure includes performing a diffraction-based overlay measurement between each of the first sections and the first pattern overlapping the first section.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: October 20, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Wei Cheng, Bo-Jou Lu, Chun-Chi Yu
  • Patent number: 10804678
    Abstract: An example method of manufacturing a semiconductor device. A first wafer may be provided that includes a first layer that contains quantum dots. A second wafer may be provided that includes a buried dielectric layer and a second layer on the buried dielectric layer. An interface layer may be formed on at least one of the first layer and the second layer, where the interface layer may be an insulator, a transparent electrical conductor, or a polymer. The first wafer may be bonded to the second wafer by way of the interface layer.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: October 13, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Di Liang, Geza Kurczveil, Raymond G. Beausoleil, Marco Fiorentino
  • Patent number: 10796973
    Abstract: Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a device-under-testing that has one or more source/drain regions and a first metallization level arranged over the device-under-testing. The first metallization level includes one or more first interconnect lines. The structure further includes a contact level having one or more first contacts arranged between the first metallization level and the device-under-testing. The one or more first contacts directly connect the one or more first interconnect lines with the one or more source/drain regions. The structure further includes a second metallization level arranged over the first metallization level. The second metallization level has a first test pad and one or more second interconnect lines connecting the one or more first interconnect lines with the first test pad.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: October 6, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mankyu Yang, Vara Govindeswara Reddy Vakada, Edward Maciejewski, Brian Greene, Atsushi Ogino, Vikrant Chauhan, Prianka Sengupta
  • Patent number: 10788525
    Abstract: Provided is a semiconductor device, a measurement device, a measurement method, and a semiconductor system that enable accurate measurement of the plasma induced damage (PID) effect on a small scale. The semiconductor device includes an NMOSFET whose gate is connected to an antenna part that functions as an antenna in a plasma process and a PMOSFET that controls the connection between the NMOSFET and a ring oscillator. The semiconductor device is provided with a test element group (TEG) that includes an NMOSFET whose gate is connected to an antenna part that functions as an antenna in a plasma process and a PMOSFET that controls the connection between the NMOSFET and a ring oscillator.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: September 29, 2020
    Assignee: SONY CORPORATION
    Inventors: Yohei Hiura, Hidetoshi Oishi, Shigetaka Mori
  • Patent number: 10790204
    Abstract: Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a test pad, a device-under-testing having one or more source/drain regions, and a metallization level arranged over the device-under-testing. The metallization level includes one or more interconnect lines that are connected with the test pad. One or more contacts, which are arranged between the metallization level and the device-under-testing, directly connect the one or more interconnect lines with the one or more source/drain regions.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: September 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mankyu Yang, Vara Govindeswara Reddy Vakada, Edward Maciejewski, Brian Greene, Atsushi Ogino, Vikrant Chauhan, Prianka Sengupta
  • Patent number: 10779416
    Abstract: Disclosed herein may be an apparatus and method for detecting ion migration. The apparatus may include: a first printed circuit board (PCB) pad coupled with a ground; a second PCB pad disposed at a position spaced apart from the first PCB pad; a power supply unit configured to supply power to the second PCB pad; a voltage detection unit configured to detect a voltage of an output terminal of the first PCB pad; and a control unit configured to determine whether ion migration has occurred between the first PCB pad and the second PCB pad using the voltage detected by the voltage detection unit.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: September 15, 2020
    Assignee: HYUNDAI MOBIS CO., LTD.
    Inventor: Jae Hyun Park
  • Patent number: 10777472
    Abstract: An IC includes a contiguous standard cell area with first, second, and third TS-GATE-short-configured test area geometries disposed therein. In some embodiments, the contiguous standard cell area may further include: fourth and fifth TS-GATE-short-configured test area geometries, and/or other test area geometries, such as tip-to-tip-short, tip-to-side-short, diagonal-short, corner-short, interlayer-overlap-short, via-chamfer-short, merged-via-short, snake-open, stitch-open, via-open, or metal-island-open.
    Type: Grant
    Filed: September 29, 2018
    Date of Patent: September 15, 2020
    Assignee: PDF Solutions, Inc.
    Inventors: Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama
  • Patent number: 10770406
    Abstract: An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: September 8, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ricky Alan Jackson, Erika Lynn Mazotti, Sudtida Lavangkul
  • Patent number: 10770124
    Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: September 8, 2020
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Lawrence Lai, Fan Ho, David A. Secker, Wayne S. Richardson, Akash Bansal, Brian S. Leibowitz, Kyung Suk Oh
  • Patent number: 10771268
    Abstract: Provided is an apparatus for generating digital values to provide a random digital value. The apparatus may generate the digital value based on a semiconductor process variation. The apparatus may include a generating unit to generate a plurality of digital values, based on the semiconductor process variation, and a processing unit to process the digital values and to provide a first digital value. The generating unit may include a plurality of physically unclonable functions (PUFs). A parameter may be differently applied to the PUFs, and the PUFs may generate the digital values.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: September 8, 2020
    Assignee: ICTK HOLDINGS CO., LTD
    Inventors: Dong Kyue Kim, Byong Deok Choi
  • Patent number: 10763180
    Abstract: A base substrate include a first substrate (110) having a first principal surface (110a) and a second principal surface (110b), and a first wiring member placed over the first or second principal surface. A pixel substrate includes a second substrate (201) having a third principal surface (201a) and a fourth principal surface (201b), a plurality of light-emitting elements (202) mounted over the third principal surface, a driver IC (205) mounted over the third principal surface, an external connection terminal mounted over the third principal surface, and a second wiring member (206) placed on the third or fourth principal surface. The driver IC drives the plurality of light-emitting elements. The external connection terminal receives an input signal that is supplied from outside the pixel substrate. The second substrate (201) is disposed to be stacked on top of the first substrate (110) so that the first principal surface and the fourth principal surface face each other.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: September 1, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Katsuji Iguchi
  • Patent number: 10748793
    Abstract: A method of micro-transfer printing comprises providing a component source wafer and components disposed in, on, or over the component source wafer. A destination substrate and a stamp for transferring the components from the component source wafer to the destination substrate is provided. The component source wafer has an attribute or structure that varies across the component source wafer that affects the structure, operation, appearance, or performance of the components. A first array of components is transferred from the component source wafer to the destination substrate with a first orientation. A second array of components is transferred from the component source wafer to the destination substrate with a second orientation different from the first orientation. Components can be transferred by micro-transfer printing and different orientations can be a different rotation, overlap, interlacing, or offset.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: August 18, 2020
    Assignee: X Display Company Technology Limited
    Inventors: Andrew Tyler Pearson, Erich Radauscher, Christopher Michael Verreen, Matthew Alexander Meitl, Christopher Andrew Bower, Ronald S. Cok
  • Patent number: 10746787
    Abstract: A testing architecture for integrated circuits on a wafer includes at least one first circuit of a structure test element group (TEG) realized in a scribe line providing separation between first and second integrated circuits. At least one pad is shared by a second circuit inside at least one of the first and second integrated circuits and the first circuit. Switching circuitry is coupled to the at least one pad and to the first and second circuits.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: August 18, 2020
    Assignee: STMicroelectronics S.r.l.
    Inventor: Alberto Pagani
  • Patent number: 10748852
    Abstract: Disclosed is a multi-chip module (MCM) with redundant chip-to-chip communication connection(s) to minimize the need to discard a chip-mounting layer due to defective signal traces. The MCM includes at least first and second chips mounted on the chip-mounting layer. The chip-mounting layer includes signal traces that are electrically connected between first and second links on the first and second chips, respectively, to form communication connections including at least one redundant communication connection. Instead of being directly connected to the chip-to-chip communication connections, first and second interfaces on the first and second chips are connected via first and second multiplexors, respectively, to selected ones of multiple chip-to-chip communication connections. By employing the multiplexors and the redundant chip-to-chip communication connection(s), chip-to-chip communication connection(s) with defective signal trace(s) can be bypassed.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: August 18, 2020
    Assignee: Marvell International Ltd.
    Inventors: Wolfgang Sauter, Mark W. Kuemerle, Edmund Blackshear
  • Patent number: 10741737
    Abstract: A light emitting device package includes a package substrate and a submount on the package substrate. An upper surface of the submount includes a central region, first and second base regions spaced from the package substrate, relative to the central region, and a sloped region between the central region and the first and second base regions. A light emitting device chip is in the central region. A first electrode layer is between the central region and the light emitting device chip and extends onto the sloped region and the first base region. A second electrode layer is between the central region and the light emitting device chip, extends onto the sloped region and the second base region, and is spaced apart from the first electrode layer. First and second reflective layers are on the first and second electrode layers, respectively, and overlap the sloped region.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: August 11, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mi Hyun Kim, Young Hwan Park, Sam Mook Kang, Joo Sung Kim, Jong Uk Seo, Young Jo Tak
  • Patent number: 10741537
    Abstract: A method of manufacturing a semiconductor structure includes forming a redistribution layer (RDL); forming a conductive member over the RDL; performing a first electrical test through the conductive member; disposing a first die over the RDL; performing a second electrical test through the conductive member; and disposing a second die over the first die and the conductive member.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COOMPANY LTD.
    Inventors: Hsiang-Tai Lu, Shuo-Mao Chen, Mill-Jer Wang, Feng-Cheng Hsu, Chao-Hsiang Yang, Shin-Puu Jeng, Cheng-Yi Hong, Chih-Hsien Lin, Dai-Jang Chen, Chen-Hua Lin
  • Patent number: 10734296
    Abstract: An electrical device includes a substrate orientated parallel to a first plane and a first integrated circuit die disposed above the substrate. The first integrated circuit die includes pads that are electrically coupled to at least some of the pads at the top surface of the substrate. The electrical device has a packaging material disposed above the first integrated circuit die. The electrical device includes one or more test pads that are orientated parallel to the first plane and disposed above the first integrated circuit die in the vertical direction. The one or more test pads are electrically coupled to the first integrated circuit die and encased within the packaging material such that the one or more test pads are not exposed external to the electrical device.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: August 4, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Joseph A. De La Cerda
  • Patent number: 10725385
    Abstract: A method may include, but is not limited to, receiving a measurement including a metrology parameter for a layer of a metrology target and an alignment mark from an overlay metrology tool prior to a lithography process; deriving a merit figure from the metrology parameter and the alignment mark; deriving a correction factor from the merit figure; providing the correction factor to the lithography process via a feed forward process; receiving an additional measurement including an additional metrology parameter for the layer and an additional layer from an additional overlay metrology tool after the lithography process; deriving an adjustment from the additional metrology parameter; and providing the adjustment to the lithography process via a feedback process.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: July 28, 2020
    Assignee: KLA-Tencor Corporation
    Inventors: Tsachy Holovinger, Liran Yerushalmi, David Tien, DongSub Choi
  • Patent number: 10727214
    Abstract: A method for manufacturing an integrated circuit (IC) device. A first IC wafer is diced to obtain a first superdie including a plurality of first die. A second IC wafer is diced to obtain a second superdie including a plurality of second die. The first superdie and the second superdie are placed on an interposer substrate to form at least part of a composite IC wafer, wherein each of the first die is aligned with a respective one of the second die in the composite IC wafer. The composite IC wafer is diced to obtain a plurality of IC devices, where each of the IC devices includes a respective one of the first die and the second die with which it is aligned.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: July 28, 2020
    Assignee: Synaptics Incorporated
    Inventor: Stephen L. Morein
  • Patent number: 10720465
    Abstract: A first circuit layer including a first semiconductor substrate with photoelectric conversion unit that photoelectrically converts incident light and generates charge, and a first wiring layer with wiring that reads out signal based upon charge generated by the photoelectric conversion unit; second circuit layer including a second wiring layer with wiring connected to the wiring of the first wiring layer, and a second semiconductor substrate with a through electrode connected to the wiring of the second wiring layer; third circuit layer including a third semiconductor substrate with a through electrode connected to the through electrode of the second circuit layer, and third wiring layer with wiring connected to the through electrode of the third semiconductor substrate; and a fourth circuit layer including a fourth wiring layer with wiring connected to the wiring of the third wiring layer, and fourth semiconductor substrate connected to the wiring of the fourth wiring layer.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: July 21, 2020
    Assignee: NIKON CORPORATION
    Inventors: Shigeru Matsumoto, Toru Takagi
  • Patent number: 10707341
    Abstract: A semiconductor device includes: a plurality of semiconductor switching elements that are a plurality of MOSFETs each including a Schottky barrier diode; a first ohmic electrode disposed above a first region of a well region and electrically connected to the first region, the first region being on the opposite side from a predefined region; a first Schottky electrode disposed on a semiconductor layer exposed at the first region of the well region; and a line electrically connected to the first ohmic electrode, the first Schottky electrode, and a source electrode. The device enables reduction of a breakdown in a gate insulating film.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: July 7, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yukiyasu Nakao, Kohei Ebihara, Shiro Hino
  • Patent number: 10707288
    Abstract: The present disclosure provides a TFT array substrate and an OLED display panel. The TFT array substrate includes a display area, a non-display area around the display area, a COF bonding area and a test area. The COF bonding area and the test area are arranged in the non-display area. The test area includes several test pads spaced apart. According to the present disclosure, the test pads are arranged on the TFT array substrate. Thus, during testing, it is not necessary to cut off the connection wire between the test pads and the TFT array substrate. Therefore, the problem of uncovered metal residue after the cut-off of the connection wire may be avoided. Moreover, when the test of the TFT array substrate is finished, the test pads will be covered by insulating material such that the problem of uncovered metal residue of the test pads can be avoided.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: July 7, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Xue Li
  • Patent number: 10698021
    Abstract: A device includes a leadframe having a diepad and leads, a compound semiconductor chip arranged over a first surface of the diepad and including gate, source electrode and drain electrodes, and an encapsulation material covering the compound semiconductor chip and diepad. A second surface of the diepad opposite the first surface is exposed from the encapsulation material. The device also includes a first lead of the leadframe electrically coupled to the gate electrode, a second lead of the leadframe electrically coupled to the source electrode, a third lead of the leadframe electrically coupled to the source electrode, and a fourth lead of the leadframe electrically coupled to the drain electrode. The third lead is configured to provide a sensing signal representing an electrical potential of the source electrode to a gate driver circuit. The gate driver circuit is configured to drive the gate electrode based on the sensing signal.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: June 30, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Klaus Schiess
  • Patent number: 10692841
    Abstract: Semiconductor devices having through-stack interconnects for facilitating connectivity testing, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a stack of semiconductor dies and a plurality of through-stack interconnects extending through the stack to electrically couple the semiconductor dies. The interconnects include functional interconnects and at least one test interconnect. The test interconnect is positioned in a portion of the stack more prone to connectivity defects than the functional interconnects. Accordingly, testing the connectivity of the test interconnect can provide an indication of the connectivity of the functional interconnects.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: June 23, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Christian N. Mohr, Scott E. Smith
  • Patent number: 10685923
    Abstract: An electronic chip including a plurality of buried doped bars and a circuit for detecting an anomaly of an electric characteristic of the bars.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: June 16, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Alexandre Sarafianos, Jimmy Fort, Thierry Soude
  • Patent number: 10685937
    Abstract: A package and a method of forming the same are provided. A method includes forming a first die structure. The first die structure includes a die stack and a stacked dummy structure bonded to a carrier. A second die structure is formed. The second die structure includes a first integrated circuit die. The first die structure is bonded to the second die structure by bonding a topmost integrated circuit die of the die stack to the first integrated circuit die. The topmost integrated circuit die of the die stack is a farthest integrated circuit die of the die stack from the carrier. A singulation process is performed on the first die structure to form a plurality of individual die structures. The singulation process singulates the stacked dummy structure into a plurality of individual stacked dummy structures.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen, Chen-Hua Yu
  • Patent number: 10679912
    Abstract: A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: June 9, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Akihiro Horibe, Yasuteru Kohda, Seiji Munetoh, Chitra Subramanian, Kuniaki Sueoka
  • Patent number: 10680031
    Abstract: A first circuit layer including a first semiconductor substrate with photoelectric conversion unit that photoelectrically converts incident light and generates charge, and a first wiring layer with wiring that reads out signal based upon charge generated by the photoelectric conversion unit; second circuit layer including a second wiring layer with wiring connected to the wiring of the first wiring layer, and a second semiconductor substrate with a through electrode connected to the wiring of the second wiring layer; third circuit layer including a third semiconductor substrate with a through electrode connected to the through electrode of the second circuit layer, and third wiring layer with wiring connected to the through electrode of the third semiconductor substrate; and a fourth circuit layer including a fourth wiring layer with wiring connected to the wiring of the third wiring layer, and fourth semiconductor substrate connected to the wiring of the fourth wiring layer.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: June 9, 2020
    Assignee: NIKON CORPORATION
    Inventors: Shigeru Matsumoto, Toru Takagi
  • Patent number: 10679721
    Abstract: Embodiments of structures and methods for testing three-dimensional (3D) memory devices are disclosed. In one example, a 3D memory device includes a memory array structure, a peripheral device structure, and an interconnect layer in contact with a front side of the memory array structure and a front side of the peripheral device structure, and a conductive pad at a back side of the memory array structure and that overlaps the memory array structure. The memory array structure includes a memory array stack, a through array contact (TAC) extending vertically through at least part of the memory array stack, and a memory array contact. The peripheral device structure includes a test circuit. The interconnect layer includes an interconnect structure. The conductive pad, the TAC, the interconnect structure, and at least one of the test circuit and the memory array contact are electrically connected.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 9, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jong Jun Kim, Feng Pan, Jong Seuk Lee, Zhenyu Lu, Yongna Li, Lidong Song, Youn Cheul Kim, Steve Weiyi Yang, Simon Shi-Ning Yang
  • Patent number: 10663513
    Abstract: Apparatuses including test segment circuits and methods for testing the same are disclosed. An example apparatus includes a plurality of segment lines configured to form a ring around a die and a plurality of test segment circuits, each test segment circuit coupled to at least two segment lines of the plurality of segment lines. Each test segment circuit is coupled to a portion of a first signal line, a portion of a second signal line, and a portion of a third signal line and each test segment circuit is configured to control an operation performed on at least one segment line of the plurality of segment lines.
    Type: Grant
    Filed: May 19, 2019
    Date of Patent: May 26, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kevin G. Werhane, Nathaniel J. Meier, Bin Liu
  • Patent number: 10665746
    Abstract: A manufacturing method of a light-emitting device including the following steps is provided. A test trace and a first signal trace are formed on a first substrate. A light-emitting element electrically connected to the test trace and the first signal trace is formed. A test procedure is performed on the light-emitting element via the test trace and the first signal trace. An encapsulation layer is formed on the first substrate to cover the light-emitting element. The test trace is removed, and then a driving unit electrically connected to light-emitting element is formed.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: May 26, 2020
    Assignee: Au Optronics Corporation
    Inventors: Yung-Chih Chen, Tsung-Ying Ke, Li-Chih Hsu, Keh-Long Hwu, Wan-Tsang Wang, Chun-Hsin Liu
  • Patent number: 10643735
    Abstract: An apparatus and method for testing two-terminal memory elements organized as a cross-point memory array. The apparatus allows functional testing of two-terminal memory elements organized as a cross-point memory array, and built in a short flow manufacturing process. The proposed apparatus substantially eliminates the use of any type of additional active or passive switches, selectors, or decoders. A large number of memory elements of various memory types including planar (two dimensional) or three dimensional memory structures can be tested without the need of manufacturing selectors or running the full flow process.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: May 5, 2020
    Assignee: PDF Solutions, Inc.
    Inventors: Tomasz Brozek, Christopher Hess, Rakesh Vallishayee, Meindert Lunenborg, Hendrik Schneider, Yuan Yu, Amit Joag, SiewHoon Ng
  • Patent number: 10643911
    Abstract: A scribe line structure including a semiconductor substrate, a pad and a first patterned metal layer is provided. The semiconductor substrate has a die region, a die sealing region located outside the die region and a dicing region located outside the die sealing region. The pad is disposed in the dicing region. The first patterned metal layer is disposed in the dicing region, right below and connected to the pad, wherein the first patterned metal layer has a plurality of first patterns directly connected to each other.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: May 5, 2020
    Assignee: UNITED MICROELECTRIC CORP.
    Inventor: Kuang-Hui Tang
  • Patent number: 10636711
    Abstract: A flexible display device can include a flexible substrate including a display area including a plurality of pixels, a first non-display area extended from the display area, a bending area extended from the first non-display area, a second non-display area extended from the bending area, and a pad area extended from the second non-display area and including a plurality of pads; a plurality of data lines configured to transmit a data voltage to the plurality of pixels; a plurality of link lines extending through the first non-display area, the bending area, the second non-display area, and the pad area to connect the plurality of data lines with the plurality of pads; and a plurality of inspection transistors arranged in the pad area, each of the plurality of inspection transistors including a first electrode connected to one of the plurality of link lines.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: April 28, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Miso Kim, SungJin Park
  • Patent number: 10636750
    Abstract: A semiconductor device which includes a substrate having integrated circuits; and metallization layers on the substrate, the metallization layers having a peripheral region adjacent to a kerf region of the semiconductor device and containing a crack stop structure. The crack stop structure includes a bottom portion containing a plurality of the metallization layers connected by vias with each metallization layer decreasing in width in a step pyramid structure from a bottom of the bottom portion to a top of the bottom portion; and a top portion containing a top metallization layer of the metallization layers connected to the bottom portion, the top metallization layer being wider than a top-most metallization layer of the bottom portion and having a segment that extends toward the kerf region so as to create an overhang with respect to the bottom portion.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: April 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shidong Li, Kirk D. Peterson, Nicolas Pizzuti, Thomas M. Shaw, Thomas A. Wassick
  • Patent number: 10629509
    Abstract: Redistribution circuit structures and methods of forming the same are disclosed. One of the redistribution circuit structures includes a first conductive structure, a dielectric layer and a second conductive structure. The dielectric layer is disposed over and exposes a portion of the first conductive structure. The second conductive structure is disposed in the dielectric layer to electrically connect to the first conductive structure, and includes a first conductive layer and a second conductive layer disposed on and electrically connected to the first conductive layer. The first conductive layer includes a main portion and a conductive protrusion, the conductive protrusion is disposed on an entire edge of an upper surface of the main portion, and a top of the conductive protrusion is higher than the upper surface of the main portion.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Yun Tu, Ching-Wen Hsiao, Sheng-Yu Wu, Ching-Hui Chen
  • Patent number: 10613136
    Abstract: An apparatus comprising: a substrate; an integrated circuit region formed in the substrate; a seal ring disposed in the substrate to form a ring around the integrated circuit region, the seal ring configured to provide for protection against one or more of moisture ingress and ion ingress to the integrated circuit region and crack propagation through the substrate; and a defect sensor comprising a conductive track formed of at least one conductive layer in the substrate, the conductive track disposed outwardly of the seal ring and arranged to at least partially surround the integrated circuit region and seal ring, the conductive track having a first end terminal and a second end terminal to receive a detection signal therebetween to pass through the conductive track to detect a break in the conductive track and thereby a defect in the substrate.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: April 7, 2020
    Assignee: NXP B.V.
    Inventors: Leo Van Gemert, Peter Drummen
  • Patent number: 10607865
    Abstract: A method for processing a plate-shaped workpiece having a division line and a metal member formed on the division line or in an area corresponding to the division line includes a holding step of holding the plate-shaped workpiece on a chuck table where the metal member is exposed, a first cutting step of cutting the plate-shaped workpiece along the division line by using a first cutting blade after performing the holding step, thereby forming a first cut groove dividing the metal member, and a second cutting step of cutting the plate-shaped workpiece along the first cut groove by using a second cutting blade after performing the first cutting step, thereby forming a second cut groove fully cutting the plate-shaped workpiece. The first cutting step includes the step of supplying a cutting fluid containing an organic acid and an oxidizing agent to the plate-shaped workpiece.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: March 31, 2020
    Assignee: DISCO CORPORATION
    Inventor: Kenji Takenouchi
  • Patent number: 10607948
    Abstract: A method of individualizing a semiconductor chip of a batch of semiconductor chips with respective individualization data of the semiconductor chip, the method comprising, applying a plurality of circuit layouts to the semiconductor chip to form a plurality of circuits on the semiconductor chip, wherein for each circuit layout, said circuit layout is arranged such that, (a) the corresponding circuit, when triggered, falls into any one of two or more respective triggered states, and (b) one of the two or more respective triggered states is a respective preferred state defined by said circuit layout, wherein the plurality of respective preferred states of the circuits in the plurality of circuits encode the individualization data, and wherein each individualized semiconductor chip of the batch of semiconductor chips comprises a generic circuit.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: March 31, 2020
    Assignee: IRDETO B.V.
    Inventor: Gerard Johan Dekker
  • Patent number: 10593405
    Abstract: According to one embodiment, a semiconductor memory device includes: a word line; a first memory cell; a first circuit; and a second circuit. The first memory cell is connected to the word line. The first circuit generates a first voltage having a waveform including a first time period during which a voltage value increases with time and a second time period during which the voltage value decreases with time, and applies the generated first voltage to the word line. The second circuit measures first time from a first timing when a state of the first memory cell changes according to the first voltage to a second timing when the state of the first memory cell changes according to the first voltage after the first timing. The second circuit determines first data stored in the first memory cell on the basis of the measured first time.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: March 17, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Ryuichi Fujimoto, Kan Shimizu, Shigehito Saigusa, Motoki Nagata, Yumi Takada, Hitoshi Shiga, Makoto Morimoto
  • Patent number: 10586777
    Abstract: To improve the reliability of a semiconductor device. The semiconductor device includes a plurality of wiring layers formed on a semiconductor substrate, a pad formed on an uppermost wiring layer of the plurality of wiring layers, a surface protection film which includes an opening on the pad and is made of an inorganic insulating film, a rewiring formed on the surface protection film; a pad electrode formed on the rewiring, and a wire connected to the pad electrode. The rewiring includes a pad electrode mounting portion on which the pad electrode is mounted, a connection portion which is connected to the pad, and an extended wiring portion which couples the pad electrode mounting portion and the connection portion, and the pad electrode mounting portion has a rectangular shape when seen in a plan view.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: March 10, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kentaro Yamada, Shigeki Tomaru, Taketoshi Fukushima
  • Patent number: 10586843
    Abstract: A method of forming an integrated circuit device having a nanosheet resistor includes forming a nanosheet structure having alternating sheets of silicon and silicon germanium. An ion implantation is performed on the nanosheet structure. A thermal anneal is performed on the nanosheet structure. A dielectric oxide is placed around the nanosheet structure. A first contact and a second contact are coupled to the nanosheet structure to form a resistor between the first contact and the second contact. Other embodiments are also described herein.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Wei Wang, Zheng Xu
  • Patent number: 10580474
    Abstract: A semiconductor device may include a refresh control circuit which may generate test addresses that are counted based on a refresh signal and a detection clock signal and may senses logic levels of internal data corresponding to the test addresses to generate a sense signal. The semiconductor device may include a memory circuit may include a plurality of word lines which are selected by the test addresses and may output the internal data stored in memory cells connected to the word lines. The semiconductor device may include an address storage circuit may divide each of the test addresses into a main group and a sub-group to store the main groups and the sub-groups of the test addresses. The address storage circuit may store the sub-groups which are inputted at a point of time that the sense signal is generated, regarding the stored main groups having the same level combination.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: March 3, 2020
    Assignee: SK hynix Inc.
    Inventors: Sang Ah Hyun, Yunyoung Lee, Seok Bo Shim, Sang Ho Lee
  • Patent number: 10580811
    Abstract: An image pickup element package according to an embodiment of the present technology includes a solid-state image pickup element, a circuit board, a translucent substrate, and a support. The solid-state image pickup element includes a light-receiving surface, and a back surface on a side opposite to the light-receiving surface. The circuit board supports the back surface of the solid-state image pickup element. The translucent substrate is opposed to the light-receiving surface. The support includes a resin frame portion and a conductor portion and is disposed between the circuit board and the translucent substrate. The resin frame portion includes a hollow portion that houses the solid-state image pickup element, and a fixation portion that is fixed to a casing portion of an image-pickup device. The conductor portion is integrally provided in the resin frame portion and provides thermal connection between the circuit board and the fixation portion.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: March 3, 2020
    Assignee: SONY CORPORATION
    Inventor: Keiki Fukuda
  • Patent number: 10574639
    Abstract: An authentication apparatus includes: a combination information generator that generates first combination information indicating a combination of physical characteristics of at least two of first elements included in a first semiconductor device; a group identification information generator that generates first group identification information based on the combination of the physical characteristics of the at least two of the first elements, the first group identification information being for identifying the first semiconductor device as belonging to a same group as another semiconductor device manufactured in a same process; a transmitter that transmits the first combination information to an authentication partner; a receiver that receives second group identification information that the authentication partner generates in accordance with the first combination information; and an information verifier that compares the first group identification information with the second group identification information.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: February 25, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Yoshikazu Katoh
  • Patent number: 10572616
    Abstract: A test pattern includes first line patterns disposed at a first level, having discontinuous regions spaced apart by a first space, having a first width, and extending in a first direction. The test pattern includes a connection line pattern disposed at a second level and extending in the first direction, second line patterns disposed at the second level, branching from the connection line pattern, having a second width, and extending in a second direction perpendicular to the first direction. The test pattern includes via patterns disposed at a third level, having a third width, and formed around an intersection region having the first width of the first line pattern and the second width of the second line pattern. First pads are connected with the first line patterns. A second pad is connected with the connection line pattern.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: February 25, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Wook Hwang, Jong-Hyun Lee, Min-Soo Kang
  • Patent number: 10565921
    Abstract: A display panel and a display device having the display panel are provided. The display panel includes two or more signal lines arranged in a column direction in a display area, two or more link lines arranged in a non-display area to be electrically connected to the two or more signal lines or to extend from the two or more signal lines, and two or more pads arranged in the non-display area to be electrically connected to the two or more link lines, and at least one of the two or more link lines extends in a diagonal direction in a pad area in which the two or more pads are located. Accordingly, it is possible to decrease the size of the non-display area to enable a narrow bezel design.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: February 18, 2020
    Assignee: LG Display Co., Ltd.
    Inventor: Euncheol Eom