Test Or Calibration Structure Patents (Class 257/48)
  • Patent number: 11215661
    Abstract: Embodiments of the disclosure provide a crack detecting and monitoring system, including: a plurality of electrically conductive structures extending about a protective barrier formed in an inactive region of an integrated circuit (IC), wherein an active region of the IC is enclosed within the protective barrier; and a plurality of stages of sensing circuits connected in series for sensing a change in an electrical characteristic of each of the plurality of structures and for receiving an enable signal, wherein each sensing circuit is coupled to a respective structure of the plurality of structures, the change in the electrical characteristic indicating damage to the respective structure, wherein each sensing circuit includes a circuit for selectively generating the enable signal for a next sensing circuit in the plurality of stages of sensing circuits.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: January 4, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Nicholas A. Polomoff, Dewei Xu, Eric D. Hunt-Schroeder
  • Patent number: 11217128
    Abstract: A display panel includes: a substrate including a display area and a non-display area around the display area; a plurality of scan lines and a plurality of data lines crossing each other on the substrate at the display area; a plurality of pixels connected to the plurality of scan lines and the plurality of data lines; and a test circuit portion on the substrate at the non-display area, the test circuit portion connected to the plurality of data lines. The test circuit portion includes: a lighting test signal line which applies a lighting signal to each of the plurality of data lines; and a crack detection circuit line connected between the plurality of data lines and the lighting test signal line. The crack detection circuit line includes a plurality of signal lines connected to different data lines among the plurality of data lines.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: January 4, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kwangchul Jung, Jaeyoon Jung, Joungpyo Park, Boogyo Shin, Hyunsuk Yang
  • Patent number: 11192988
    Abstract: The present invention fills a long-felt need for an improved phenol-furan resin composition used as a chimney liner with reduced combustibility, and for the preparation of pre-impregnated fiber-reinforced composite material and its use. The invention shows a higher tolerance for certain conditions that are damaging to other resin compositions including higher heat tolerance and higher tolerance for flue gases and other compounds.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: December 7, 2021
    Inventors: István Kovácsay, Lídia Kecskeméthy, Norbert Piukovics
  • Patent number: 11189578
    Abstract: The disclosure concerns an electronic chip including a resistive region and a first switch of selection of a first area in contact with the resistive region.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: November 30, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Alexandre Sarafianos, Bruno Nicolas, Daniele Fronte
  • Patent number: 11164801
    Abstract: An extension of conventional IC fabrication processes to include some of the concepts of flip-chip assemblies while producing a final “non-flip chip” circuit structure suitable for conventional packaging or for direct usage by customers. Multiple IC dies are fabricated on a semiconductor wafer in a conventional fashion, solder bumped or the like, and singulated. The singulated dies, which may be of different sizes and functionality, are then flip-chip assembled onto a single tile substrate of thin-film material which has been patterned with vias, peripheral connection pads, and one or more ground planes. Once dies are flip-chip mounted to the thin-film tile, all of the dies on the entire tile may be probed using automated testing equipment. Sets of dies of different functionality may be tested as a system or subsystem. Once test probing is complete, the dies (or sets of dies) and tile are singulated into die/tile assemblies.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: November 2, 2021
    Assignee: pSemi Corporation
    Inventors: Mark Moffat, Andrew Christie, Duncan Pilgrim, Ronald Eugene Reedy
  • Patent number: 11158550
    Abstract: A semiconductor package includes a frame having a first surface, a second surface opposite the first surface, and a through-hole, a first semiconductor chip in the through-hole of the frame, a second semiconductor chip on the frame, a first connection structure on the first surface of the frame and including a first redistribution structure electrically connected to the first semiconductor chip and having a third surface contacting the first surface of the frame, the first redistribution structure including a first redistribution layer and a first redistribution via, a first pad on a center portion of a fourth surface of the first redistribution structure opposite the third surface, a second pad on an edge portion of the fourth surface, a second connection structure on the second surface and comprising a second redistribution structure electrically connected to the second semiconductor chip and including a second redistribution layer and a second redistribution via, and an electrical connection metal on the f
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: October 26, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jeongjoon Oh
  • Patent number: 11150202
    Abstract: An X-ray imaging system includes the following. An X-ray Talbot imaging apparatus includes an X-ray source, a plurality of gratings, and an X-ray detector. An X-ray is irradiated from the X-ray source through the examined target which is an object and the plurality of gratings and to the X-ray detector to obtain a moire image necessary to generate the reconstructed image of the examined target. A first database shows, for each name or type of material, a correlation between information regarding a signal strength in the reconstructed image generated based on the moire image and quality information of the material included in the examined target. A controller estimates as the evaluation index the quality information in the examined target from the reconstructed image based on information regarding the input name or the type of material and input shape information and the first database.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: October 19, 2021
    Assignee: KONICA MINOLTA, INC.
    Inventors: Yasunori Tsuboi, Hiromichi Shindou
  • Patent number: 11145561
    Abstract: The present disclosure provides a display panel and a method for manufacturing the same. The method includes providing a substrate including a display area and a non-display area. A chip on film (COF) and a testing structure are disposed in the non-display area. A testing circuit includes a signal trace including a non-metal trace and a metal trace connecting to each other. A cutting line is disposed on the signal trace. The method further includes testing the display area of the substrate by the testing structure, and removing a test pad.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: October 12, 2021
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Xing Ming, Caiqin Chen, Yiyi Wang
  • Patent number: 11145605
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate and a first crack-detecting structure positioned in the substrate and comprising a first capacitor unit. The first capacitor unit comprises a first bottom conductive layer positioned in the substrate, a first capacitor insulating layer surrounding the first bottom conductive layer, and a first buried plate surrounding the first capacitor insulating layer.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: October 12, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Jar-Ming Ho
  • Patent number: 11145643
    Abstract: The present disclosure relates to a semiconductor device, a method for manufacturing a semiconductor device, and a plasma-induced damage (PID) protection device capable of, without increasing a chip area, releasing a large PID with high efficiency and protecting an element to be protected from the PID with higher accuracy. There are provided a protection metal-oxide-semiconductor field-effect transistor (MOSFET) that includes a drain connected to a gate electrode of a MOSFET to be protected and a grounded source and protects the MOSFET to be protected from a plasma-induced damage (PID), and a dummy antenna connected to a gate electrode of the protection MOSFET, the dummy antenna turning on the protection MOSFET prior to the MOSFET to be protected due to PID charge. The present disclosure can be applied to a semiconductor device.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: October 12, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Yohei Hiura
  • Patent number: 11139273
    Abstract: A semiconductor die includes one or more semiconductor devices (e.g., memory array, processors), first and second banks of I/O ports arranged along one or more sides of the die, and a multiplexing circuit. The multiplexing circuit can be changed between a first state and a second state. In the first state the first bank of I/O ports is coupled to the semiconductor device(s) and the second bank of I/O ports is not coupled to the semiconductor device(s), and in the second state the first bank of I/O ports is not coupled to the semiconductor device(s) and the second bank of I/O ports is coupled to the semiconductor device(s). The state of the multiplexing circuit can be set, for example, by an on-die fuse circuit or an externally accessible select line. The semiconductor die can be included in a chip package, which can be included on a printed circuit board.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventor: Michael D. Nelson
  • Patent number: 11127713
    Abstract: High bandwidth memories and systems including the same may include a buffer die, a plurality of memory dies stacked on the buffer die, a plurality of dummy bump groups in edge regions of the buffer die and the plurality of memory dies, and a plurality of signal line groups. Each of the plurality of dummy bump groups includes dummy bumps spaced apart from each other between each pair of adjacent dies and configured to connect the two adjacent dies to each other. Each of the signal line groups includes a plurality of signal lines configured to transmit a corresponding signal among an input signal and a plurality of bump crack detection signals applied to an input dummy bump of each of the plurality of dummy bump groups via sequential transmission through the plurality of dummy bumps to an output dummy bump during a bump crack test operation.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: September 21, 2021
    Inventors: Youngcheon Kwon, Kyomin Sohn, Jaeyoun Youn
  • Patent number: 11121083
    Abstract: A semiconductor device includes a substrate; an insulating layer positioned above the substrate, wherein the insulating layer has two ends; a first doped region formed in the substrate and positioned at one end of the two ends of the insulating layer; a second doped region formed in the substrate and positioned at the other end of the two ends of the insulating layer, wherein the second doped region is opposite to the first doped region; a control terminal positioned above the insulating layer; a first fuse head positioned above the control terminal and electrically coupled to the first doped region; a second fuse head positioned above the first fuse head; and a fuse area positioned between the first fuse head and the second fuse head.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: September 14, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chin-Ling Huang
  • Patent number: 11121047
    Abstract: A semiconductor structure includes a substrate, a device, a contact via, a metal/dielectric layer, and a test structure. The device is over the substrate. The contact via is connected to the device. The metal/dielectric layer is over the contact via. The metal/dielectric layer includes a first portion and a second portion. The first portion of the metal/dielectric layer has a metallization pattern connected to the contact via. The second portion of the metal/dielectric layer is void of metal. The test structure is over the second portion of the metal/dielectric layer.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: September 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Bo Shu, Tsung-Hua Yang, Chung-Jen Huang
  • Patent number: 11121056
    Abstract: A semiconductor device includes a semiconductive substrate, a dielectric stack disposed over the semiconductive substrate, a probe pad formed on the dielectric stack, a test key embedded in the semiconductor device and a single via string stacking extending along a direction from a level of the probe pad to the semiconductive substrate and electrically connecting the periphery of the probe pad to the test key. A semiconductor device includes a semiconductive substrate, a dielectric stack, a probe pad, a test key, an extension segment electrically connected to the periphery of the probe pad and laterally extending from the probe pad from a top view, and a single via string stacking extending along a direction from the probe pad to the semiconductive substrate and electrically connecting the extension segment to the test key. The single via string stacking and the probe pad are laterally offset from a top view.
    Type: Grant
    Filed: January 27, 2019
    Date of Patent: September 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chien-Mao Chen
  • Patent number: 11114352
    Abstract: A process monitor circuitry is described that can measure the electron mobility (?), oxide capacitance (Cox) and threshold voltage (Vth) of an integrated circuit.
    Type: Grant
    Filed: August 25, 2019
    Date of Patent: September 7, 2021
    Assignee: Birad—Research & Development Company Ltd.
    Inventors: Joseph Shor, Liron Lisha
  • Patent number: 11099230
    Abstract: An electromigration (EM) test structure for localizing EM-induced voids is provided. The EM test structure includes an EM test element, a via, and a stress line. The EM test element includes a first force pad and a first sense pad. The via electrically connects the EM test element to the stress line. A second end portion of the stress line includes a second force pad and a second sense pad. The second force pad defines, at least in part, a conductive pathway between the first and second force pads. The second sense pad defines, at least in part, a conductive pathway between the first and second sense pads to facilitate four-terminal resistance measurements. A first end portion of the stress line includes a third sense pad that defines, at least in part, a conductive pathway between the first and third sense pads to facilitate four-terminal resistance measurements.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: August 24, 2021
    Assignee: International Business Machines Corporation
    Inventors: Baozhen Li, Chih-Chao Yang
  • Patent number: 11101206
    Abstract: The lower surface of the wiring substrate includes a first region overlapping with the semiconductor chip mounted on the upper surface, and a second region surrounding the first region and not overlapping with the semiconductor chip. The first region includes a third region in which the plurality of external terminals is not arranged, and a fourth region surrounding the third region in which the plurality of external terminals is arranged. The plurality of external terminals includes a plurality of terminals arranged in the fourth region of the first region and a plurality of terminals arranged in the second region. The plurality of terminals includes a plurality of power supply terminals for supplying a power supply potential to the core circuit of the semiconductor chip, and a plurality of reference terminals for supplying a reference potential to the core circuit of the semiconductor chip.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: August 24, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshitaka Okayasu, Shuuichi Kariyazaki
  • Patent number: 11094601
    Abstract: A semiconductor element includes an element body and a test electrode. The element body has a principal surface facing in a thickness direction and a first side surface facing in a direction orthogonal to the principal surface and connected to the principal surface. The test electrode is disposed on the principal surface and is adjacent to the boundary between the principal surface and the first side surface. The element body is provided with a plurality of dents that straddle the boundary and are recessed from both the principal surface and the first side surface. The plurality of dents are arranged along the boundary.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: August 17, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Motoharu Haga
  • Patent number: 11088108
    Abstract: A method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first ring-like structure over a chip. The first ring-like structure surrounds the first conductive bump, the first ring-like structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring-like structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate through the first conductive bump.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Yao Yang, Ling-Wei Li, Yu-Jui Wu, Cheng-Lin Huang, Chien-Chen Li, Lieh-Chuan Chen, Che-Jung Chu, Kuo-Chio Liu
  • Patent number: 11088038
    Abstract: A semiconductor package includes a base including a first bonding structure; and a first semiconductor chip, including a second bonding structure, the second bonding structure being coupled to the first bonding structure of the base, wherein the first bonding structure includes: a test pad; a first pad being electrically connected to the test pad; and a first insulating layer, wherein the second bonding structure includes: a second pad being electrically connected to the first pad; and a second insulating layer being in contact with the first insulating layer, and wherein at least a portion of the test pad is in contact with the second insulating layer.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: August 10, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyuek Jae Lee, Tae Hun Kim, Ji Hwan Hwang, Ji Hoon Kim, Ji Seok Hong
  • Patent number: 11075770
    Abstract: A semiconductor device is provided. The semiconductor device includes a unique-information generation portion, a detection portion, a memory portion, and a readout portion. The unique-information generation portion operates in a plurality of operation environments to generate unique information. The unique information includes stable information and unstable information. The stable information is constant in the plurality of operation environments, and the unstable information is different in at least two of the plurality of operation environments. The detection portion detects the unstable information. The memory portion stores the unique information and identification information for identifying the unstable information. The readout portion reads out the unique information and the identification information and outputs the unique information and the identification information to an external portion.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: July 27, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Masaru Yano
  • Patent number: 11075181
    Abstract: A semiconductor device includes a semiconductor substrate including a chip region and an edge region around the chip region, a lower insulating layer on the semiconductor substrate, a chip pad on the lower insulating layer on the chip region, an upper insulating layer provided on the lower insulating layer to cover the chip pad, the upper and different insulating layers including different materials, and a redistribution chip pad on the chip region and connected to the chip pad. The upper insulating layer includes a first portion on the chip region having a first thickness, a second portion on the edge region having a second thickness, and a third portion on the edge region, the third portion extending from the second portion, spaced from the first portion, and having a decreasing thickness away from the second portion. The second thickness is smaller than the first thickness.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: July 27, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Hoon Han, Dong-Wan Kim, Dongho Kim, Jaewon Seo
  • Patent number: 11069695
    Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device, as well as a method for forming the IC. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A memory cell structure is disposed on the memory region, and logic device is disposed on the logic region. A memory test structure is disposed at a periphery of the memory cell structure. The memory test structure includes a pair of dummy control gates respectively separated from the substrate by a pair of dummy floating gates and a pair of dummy select gate electrodes disposed on opposite sides of the pair of dummy control gates. The memory test structure further includes a pair of conductive floating gate test contact vias respectively extending through the pair of dummy control gate and reaching on the dummy floating gate.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Ling Shih, Yong-Shiuan Tsair
  • Patent number: 11067620
    Abstract: A method includes applying a DC stress condition to a transistor for a predetermined stress time, measuring an impedance of the transistor after the predetermined stress time, and repeating the application of the DC stress condition and the measurement of the impedance until the measured impedance exceeds an impedance threshold or a total stress time exceeds a time threshold, where the DC stress condition includes applying a non-zero drain voltage signal to a drain terminal of the transistor, applying a gate voltage signal to a gate terminal of the transistor, and applying a non-zero source current signal to a source terminal of the transistor.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: July 20, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Dong Seup Lee, Jungwoo Joh, Pinghai Hao, Sameer Pendharkar
  • Patent number: 11070384
    Abstract: A semiconductor device is provided. The semiconductor device includes a unique-information generation portion, a detection portion, a memory portion, and a readout portion. The unique-information generation portion operates in a plurality of operation environments to generate unique information. The unique information includes stable information and unstable information. The stable information is constant in the plurality of operation environments, and the unstable information is different in at least two of the plurality of operation environments. The detection portion detects the unstable information. The memory portion stores the unique information and identification information for identifying the unstable information. The readout portion reads out the unique information and the identification information and outputs the unique information and the identification information to an external portion.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: July 20, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Masaru Yano
  • Patent number: 11056435
    Abstract: At least some embodiments of the present disclosure relate to a substrate for packaging a semiconductor device package. The substrate comprises a dielectric layer, a first conductive element adjacent to the dielectric layer, a second conductive element adjacent to the dielectric layer, and a third conductive element adjacent to the dielectric layer. The first conductive element has a first central axis in a first direction and a second central axis in a second direction. The first conductive element comprises a first chamfer and a second chamfer adjacent to the first chamfer. The second conductive element has a first central axis in the first direction and a second central axis in the second direction. The third conductive element has a first central axis in the first direction and a second central axis in the second direction. The first central axes of the first, second, and third conductive elements are substantially parallel to one another in the first direction and are misaligned from one another.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: July 6, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Lin Ho, Chung Chieh Chang, Ya Fang Chan, Chih-Cheng Lee
  • Patent number: 11043524
    Abstract: A device-bonded body includes: a first device where a plated bump is disposed; a second device where a bonding electrode bonded to the plated bump is disposed; and a sealing layer made of NCF or NCP, the sealing layer being disposed between the first device and the second device and including filler particles made of inorganic material; wherein a surface of the plated bump includes a first area and a second area higher than the first area; and at least a part of a side surface of an outer circumferential portion of the second area intersects with a surface of the first area.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: June 22, 2021
    Assignee: OLYMPUS CORPORATION
    Inventor: Takashi Nakayama
  • Patent number: 11043550
    Abstract: A display device includes a substrate, a display area disposed on the substrate and including a plurality of pixels and data lines, a peripheral area disposed outside the display area of the substrate, a pad portion disposed in the peripheral area, an encapsulation layer disposed in the peripheral area and the display area, and disposed on the plurality of pixels of the display area, a crack detection circuit disposed in the peripheral area, and a first crack detection line connected with the pad portion and the crack detection circuit. The first crack detection line is disposed on the encapsulation layer.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: June 22, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kyong Tae Park, Chul-Hwan Park, Sun-Kyo Jung, Sung Ho Cho
  • Patent number: 11042682
    Abstract: Methods for generating a cell set for an analog design tool are disclosed. A method comprises receiving, at a cell generator, one or more electronic files of a process-specific architectural cell (AP_Cell) having wiring for power and ground, FILL, wherein the AP_Cell is configured according to a first manufacturing process. The method further includes receiving, at the cell generator, one or more electronic files of a schematic cell (S_Cell) having internal wiring between circuit elements to provide a function for the S_Cell. The method also includes merging data from the one or more electronic files of the AP_Cell and the one or more electronic files of the S_Cell to generate a process-specific schematic cell (SP_Cell) used as a building block for a physical layout of an analog IC, wherein the process-specific schematic cell comprises one or more electronic files. Related devices are also described herein.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: June 22, 2021
    Assignee: Silicon Technologies, Inc.
    Inventors: Kent F. Smith, Thomas L. Wolf, Tracy L. Johancsik, Thomas G. Wolf, Kyler C. Fillerup
  • Patent number: 11037840
    Abstract: A plurality of semiconductor devices (5) are formed on a semiconductor wafer (1). A film thickness measurement wiring pattern (3,4) is formed on a dicing line (6,7) defining the plurality of semiconductor devices (5). An SOG film (10) is formed on the semiconductor devices (5) and the film thickness measurement wiring pattern (3,4). A film thickness of the SOG film (10) at a central part of the film thickness measurement wiring pattern (3,4) is measured. The film thickness measurement wiring pattern (3,4) is a rectangular pattern having long sides parallel to the dicing line (3,4).
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: June 15, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yuji Kawasaki
  • Patent number: 11037842
    Abstract: A semiconductor device includes a first normal pattern which is disposed in an active area of a semiconductor chip, wherein the first normal pattern has a particular shape and the active area includes circuitry for operating the semiconductor chip, and includes a first defective pattern and a second normal pattern which are disposed in a dummy area of the semiconductor chip, wherein the dummy area of the semiconductor chip is an area that does not perform functions for operating the semiconductor chip. The second normal pattern has the same shape as the first normal pattern and the first defective pattern has the same shape as the first normal pattern except for a first defect. The first normal pattern is disposed at a first level layer of the semiconductor chip.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: June 15, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jong Doo Kim
  • Patent number: 11024604
    Abstract: A packaged semiconductor device includes a substrate with first and second opposing major surfaces. A stacked semiconductor device structure is connected to the first major surface and includes a plurality of semiconductor die having terminals. Conductive interconnect structures electrically connect the terminals of the semiconductor dies together. The semiconductor dies are stacked together so that the terminals are exposed, and the stacked semiconductor device structure comprises a stepped profile. The conductive interconnect structures comprise a conformal layer that substantially follows the stepped profile.
    Type: Grant
    Filed: August 10, 2019
    Date of Patent: June 1, 2021
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Shaun Bowers, Ramakanth Alapati
  • Patent number: 11016554
    Abstract: A semiconductor apparatus includes a plurality of chips and a first bypass switch. The chips are coupled in series between a power end and a reference ground end. The first bypass switch is coupled in series between a first end and a second end of a first chip among the chips, wherein the first end is coupled to the power end and the second end is coupled to the reference ground end. The first bypass switch is turned on according to a first control signal when an operational efficiency of the first chip is less than a threshold value and the first chip is determined to be damaged.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: May 25, 2021
    Assignee: DigWise Technology Corporation, LTD
    Inventors: JingJie Wu, Shih-Hao Chen, Wen-Pin Hsieh, Chih-Wen Yang
  • Patent number: 11016398
    Abstract: Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tseng Chin Lo, Bo-Sen Chang, Yueh-Yi Chen, Chih-Ting Sun, Ying-Jung Chen, Kung-Cheng Lin, Meng Lin Chang
  • Patent number: 11004829
    Abstract: A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level. These die pairs are formed using wafer-to-wafer bonding technology, where the wafers may be bonded to each other when they are of full thickness. Once bonded, respective inactive surfaces of the wafers may be thinned and then the die pairs diced from the wafers to form a completed memory module. When the wafers are bonded face to face, they compensate each other, mechanically resulting in the die pair having a minimum warpage.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: May 11, 2021
    Assignee: SanDisk Technologies LLC
    Inventor: Nagesh Vodrahalli
  • Patent number: 11006193
    Abstract: An electro-optical apparatus having an ASIC electrically linked, by way of a multistage SerDes, to an array of optical data transmitters and receivers. In an example embodiment, a first SerDes stage is connected to the ASIC by a plurality of relatively wide, short electrical buses and further connected to a second SerDes stage by a plurality of narrower, longer electrical buses. The second SerDes stage is located in close proximity to the transmitter/receiver array to enable the signals transmitted therebetween to be switched at a high frequency rate, e.g., higher than 500 MHz. The width and length of said narrower, longer electrical buses are selected such as to support a high overall data throughput for the corresponding electrical data links between the ASIC and the transmitter/receiver array while being able to afford acceptable levels of signal integrity, power usage, and timing skews in these links.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: May 11, 2021
    Assignee: NOKIA SOLUTIONS AND NETWORKS OY
    Inventors: Ariel Leonardo Vera Villarroel, Michael Noll
  • Patent number: 11005668
    Abstract: Embodiments of the invention provide an electronic system for generating secret information comprising a Physically Unclonable Function (PUF) circuit, the PUF circuit being configured to provide a difference between two values of a physical variable of the PUF in response to a challenge applied to the PUF circuit. The system is configured to apply a set of challenges during an enrolment phase, and measure the physical variable difference provided by the PUF in response to each challenge. The system further comprises: A helper data generator (2) configured to generate a helper data comprising a set of bits, a bit of the helper data being generated in association with each applied challenge, the helper data generator being configured to generate each helper data bit from the physical variable difference provided by the PUF in response to the application of the associated challenge, the system further comprising a secret information generator (3) for extracting secret information from the helper data.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: May 11, 2021
    Inventors: Jean-Luc Danger, Philippe Nguyen
  • Patent number: 11003389
    Abstract: An operating method of a memory device includes: instructing, by a master chip, a first memory chip and a second memory chip to perform a read operation; transferring, by the first memory chip, data stored in the first memory chip to the master chip through a first through-chip channel in response to the read operation instruction, and transferring, by the second memory chip, data stored in the second memory chip to the master chip through a second through-chip channel in response to the read operation instruction; comparing, by the master chip, a phase of the data transferred through the first through-chip channel with a phase of the data transferred through the second through-chip channel; and adjusting a delay value of a data transmission channel of at least one of the first memory chip and the second memory chip based on a result of the comparing.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: May 11, 2021
    Assignee: SK hynix Inc.
    Inventor: Yun-Gi Hong
  • Patent number: 10998079
    Abstract: Embodiments of methods for testing three-dimensional memory devices are disclosed. The method can include: applying an input signal to a first conductive pad of the memory device by a first probe of a probe card; transmitting the input signal through the first conductive pad, a first TAC, a first interconnect structure passing through a bonding interface of the memory device, at least one of a memory array contact and a test circuit to a test structure; receiving an output signal through a second interconnect structure passing through the bonding interface, a second TAC, at least one of the memory array contact and the test circuit from the test structure; measuring the output signal from a second conductive pad of the memory device by a second probe of the probe card; and determining a characteristic of the test structure based on the input signal and the output signal.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: May 4, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jong Jun Kim, Feng Pan, Jong Seuk Lee, Zhenyu Lu, Yongna Li, Lidong Song, Youn Cheul Kim, Steve Weiyi Yang, Simon Shi-Ning Yang
  • Patent number: 10991646
    Abstract: A flexible circuit board for a display, having a chip-on-film structure, is disclosed. A connection pattern which is selected as a first connection pattern among connection patterns connected to panel contact pads does not reach a cutting line and is confined within a product region. As a consequence, the connection pattern selected as the first connection pattern may be prevented from being exposed on a cutting section along the cutting line, and thus, may be prevented from being changed in its electrical property due to penetration of moisture.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: April 27, 2021
    Assignee: Silicon Works Co., Ltd.
    Inventors: Kyung Jik Min, Ju Young Shin, Ji Hyun Hwang, Jung Bae Yun
  • Patent number: 10971410
    Abstract: A base substrate include a first substrate (110) having a first principal surface (110a) and a second principal surface (110b), and a first wiring member placed over the first or second principal surface. A pixel substrate includes a second substrate (201) having a third principal surface (201a) and a fourth principal surface (201b), a plurality of light-emitting elements (202) mounted over the third principal surface, a driver IC (205) mounted over the third principal surface, an external connection terminal mounted over the third principal surface, and a second wiring member (206) placed on the third or fourth principal surface. The driver IC drives the plurality of light-emitting elements. The external connection terminal receives an input signal that is supplied from outside the pixel substrate. The second substrate (201) is disposed to be stacked on top of the first substrate (110) so that the first principal surface and the fourth principal surface face each other.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: April 6, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Katsuji Iguchi
  • Patent number: 10971631
    Abstract: The present application provides a thin film transistor (TFT) and a method of fabricating the same, a display substrate and a method of fabricating the same, and a display device. The TFT includes a substrate, and a source electrode, a drain electrode and an active layer on the substrate. The active layer includes first and second active layers, the first active layer has a carrier mobility greater than that of the second active layer, and the second active layer is closer to the source electrode and the drain electrode than the first active layer. An orthographic projection of the source electrode on the substrate and an orthographic projection of the drain electrode on the substrate at least partially overlap with an orthographic projection of the second active layer on the substrate, respectively, and the first active layer is separated from the source electrode and the drain electrode.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: April 6, 2021
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Binbin Cao
  • Patent number: 10962591
    Abstract: A wafer surface test preprocessing device includes a chamber; a supporting component disposed in the chamber; an atomizer connected to a lateral side of the chamber; a cooling component connected to a bottom of the chamber; and a lid disposed on a top of the chamber. With the wafer surface test preprocessing device having the cooling component to thereby dispense with a ventilation device and collect hydrofluoric acid residues in the chamber at the bottom of the chamber, thereby saving costs and time effectively.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: March 30, 2021
    Inventor: Te-Ming Chiang
  • Patent number: 10966313
    Abstract: Provided is a method of manufacturing a printed circuit board having test points in which test points and pads are formed on the printed circuit board and then are electrically connected to each other, so that it is possible to form the pads having a pitch interval smaller than that in the related art. This may contribute to miniaturization of the printed circuit board by mounting a connector smaller than that in the related art on the printed circuit board, and may enable the preformed test points to be used as they are even after the connector used is removed from the printed circuit board. Also provided is a printed circuit board manufactured thereby.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: March 30, 2021
    Inventor: Jeong Wan Kim
  • Patent number: 10942215
    Abstract: The various technologies presented herein relate to measuring a signal generated by a die-based test circuit incorporated into an IC and utilizing the measured signal to authenticate the IC. The signal can be based upon a sensor response generated by the test circuit fabricated into the die, wherein the sensor response is based upon a property of the die material. The signal can be compared with a reference value obtained from one or more test circuit(s) respectively located on one or more reference dies, wherein the reference dies are respectively cut from different wafers, and the location at which the reference dies were cut is known. If the measured signal matches the reference value, the die is deemed to be from the same cut location as the dies from which the reference value was obtained. If the measured signal does not match the reference value, the die is not authenticated.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: March 9, 2021
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: William A. Zortman, Ryan Helinski, Jason Hamlet
  • Patent number: 10935676
    Abstract: A sensor for detecting particles is presented comprises a silicon wafer substrate and a charge detection layer mounted on the silicon wafer substrate, wherein the charge detection layer comprises a plurality of discrete pixel sensors. The sensor further comprises a converter material, wherein the converter material is operable to interact with a first type of particle to generate a reaction, wherein the reaction produces charged particles, wherein the charge detection layer is configured to detect the charged particles produced by the reaction. Further, the sensor comprises a substrate layer operable to filter a second type of particle, wherein the converter material is coated on an underside of the substrate layer such that the converter material faces the charge detection layer and an air gap is formed between the converter material and the charge detection layer.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: March 2, 2021
    Assignee: RHOMBUS HOLDINGS LLC
    Inventor: Anshuman Roy
  • Patent number: 10930571
    Abstract: A method for detecting overlay misalignment of a semiconductor device uses a test structure that includes a sensor structure and a via-chain structure. The sensor structure is disposed in a first layer on a semiconductor substrate and includes a plurality of first conductive lines extending in a first direction. Each first conductive line is separated from an adjacent first conductive line in a second direction by a first space. The via-chain structure is in a second layer above the first layer and between the first layer and the second layer. The via-chain structure includes at least one second conductive line disposed in the second layer and at least one via electrically connected to each second conductive line and extending toward the first layer. The at least one via is disposed in the first space between the adjacent first conductive lines of the sensor structure.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: February 23, 2021
    Inventors: Ki-Don Lee, Zack Tran Mai
  • Patent number: 10906457
    Abstract: A light guide body is held in a more compact holder. In a lighting device (10A) including a light emitter (20), an optical fiber (30), and a holder (40) configured to hold the optical fiber (30) with the optical fiber (30) facing the light emitter (20), the holder (40) includes two sandwiching portions (44, 45) configured to engage with each other in a state in which a holding target portion (31) of the optical fiber (30) held by the holder (40) is sandwiched in a first direction crossing an extending direction of the holding target portion (31). Two sandwiching portions (44, 45) engage with each other at positions adjacent to the holding target portion (31) in a second direction crossing both of the extending direction and the first direction.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: February 2, 2021
    Assignee: TS TECH CO., LTD.
    Inventor: Masanori Suzuki
  • Patent number: 10908212
    Abstract: A semiconductor memory device includes first bumps positioned along a first direction; second bumps positioned in parallel to the first bumps along the first direction; first registers connected with the first bumps; and second registers connected with the second bumps. The first registers and the second registers are sequentially connected and form a shift register.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: February 2, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyunui Lee, Hye-Seung Yu, Won-Joo Yun