Abstract: An antenna system includes N integrated passive components (IPCs). A first end of each IPC of the N IPCs is directly configured to couple to an antenna for receiving signals of a band corresponding to the IPC and filtering signals of bands corresponding to other IPCs of the N IPCs. The antenna system can prevent signals of various bands from interfering with each other, reduces parasitic capacitance effect, and further improves nonlinear distortion.

Abstract: Some embodiments include a high voltage nonlinear transmission line that includes a high voltage input configured to receive electrical pulses having a first peak voltage that is greater than 5 kV having a first rise time; a plurality of circuit elements electrically coupled with ground, each of the plurality of circuit elements includes a resistor and a nonlinear semiconductor junction capacitance device; a plurality of inductors, at least one of the plurality of inductors is electrically coupled between two circuit elements of the plurality of circuit elements; and a high voltage output providing a second peak voltage with a second rise time that is faster than the first rise time.

Abstract: A semiconductor device and an operating method for the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region, a fourth doped region and a first gate structure. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The first doped region is surrounded by the second doped region. The third doped region has the first type conductivity. The fourth doped region has the second type conductivity. The first gate structure is on the second doped region. The third doped region and the fourth doped region are in the second doped region and the first doped region on opposing sides of the first gate structure respectively.

Abstract: A method for forming a back-side illuminated image sensor, including the steps of: a) forming, from the front surface, doped polysilicon regions, of a conductivity type opposite to that of the substrate, extending in depth orthogonally to the front surface and emerging into the first layer; b) thinning the substrate from its rear surface to reach the polysilicon regions, while keeping a strip of the first layer; c) depositing, on the rear surface of the thinned substrate, a doped amorphous silicon layer, of a conductivity type opposite to that of the substrate; and d) annealing at a temperature capable of transforming the amorphous silicon layer into a crystallized layer.

Abstract: Various embodiments are provided for graphite and/or graphene based semiconductor devices. In one embodiment, a semiconductor device includes a semiconductor layer and a semimetal stack. In another embodiment, the semiconductor device includes a semiconductor layer and a zero gap semiconductor layer. The semimetal stack/zero gap semiconductor layer is formed on the semiconductor layer, which forms a Schottky barrier. In another embodiment, a semiconductor device includes first and second semiconductor layers and a semimetal stack. In another embodiment, a semiconductor device includes first and second semiconductor layers and a zero gap semiconductor layer. The first semiconductor layer includes a first semiconducting material and the second semi conductor layer includes a second semiconducting material formed on the first semiconductor layer. The semimetal stack/zero gap semiconductor layer is formed on the second semiconductor layer, which forms a Schottky barrier.

Abstract: A variable-resistance material memory (VRMM) device includes a container conductor disposed over an epitaxial semiconductive prominence that is coupled to a VRMM. A VRMM device may also include a conductive plug in a recess that is coupled to a VRMM. A VRMM array may also include a conductive plug in a surrounding recess that is coupled to a VRMM. Apparatuses include the VRMM with one of the diode constructions.

Abstract: A varactor diode includes a contact layer having a first conductivity type, a voltage blocking layer having the first conductivity and a first net doping concentration on the contact layer, a blocking junction on the voltage blocking layer, and a plurality of discrete doped regions in the voltage blocking layer and spaced apart from the carrier injection junction. The plurality of discrete doped regions have the first conductivity type and a second net doping concentration that is higher than the first net doping concentration, and the plurality of discrete doped regions are configured to modulate the capacitance of the varactor diode as a depletion region of the varactor diode expands in response to a reverse bias voltage applied to the blocking junction. Related methods of forming a varactor diode are also disclosed.

Abstract: Apparatus and methods for a MOS varactor structure are disclosed. An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed.

Abstract: A PFC module includes: a diode bridge having first and second diodes in the upper arm, and third and fourth diodes in the lower arm; and first and second switching elements for power factor correction. The first and second diodes are Schottky barrier diodes formed by using a wide bandgap semiconductor. The third and fourth diodes, and the first and second switching elements are diodes and switching elements respectively formed by using silicon.

Abstract: Disclosed is a semiconductor structure, which includes a non-planar varactor having a geometrically designed depletion zone with a taper, as to provide improved Cmax/Cmin with low series resistance. Because of the taper, the narrowest portion of the depletion zone can be designed to be fully depleted, while the remainder of the depletion zone is only partially depleted. The fabrication of semiconductor structure may follow that of standard FinFET process, with a few additional or different steps. These additional or different steps may include formation of a doped trapezoidal (or triangular) shaped silicon mesa, growing/depositing a gate dielectric, forming a gate electrode over a portion of the mesa, and forming a highly doped contact region in the mesa where it is not covered by the gate electrode.

Abstract: In a first aspect, a method of forming a metal-insulator-metal (“MIM”) stack is provided, the method including: (1) forming a dielectric material having an opening and a first conductive carbon layer within the opening; (2) forming a spacer in the opening; (3) forming a carbon-based switching material on a sidewall of the spacer; and (4) forming a second conductive carbon layer above the carbon-based switching material. A ratio of a cross sectional area of the opening in the dielectric material to a cross sectional area of the carbon-based switching material on the sidewall of the spacer is at least 5. Numerous other aspects are provided.

Abstract: Apparatus and methods for a MOS varactor structure are disclosed An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed.

Abstract: Provided is a pixel for picking up an image signal capable of suppressing an occurrence of a cross-talk. The pixel for picking up an image signal includes a substrate surrounded by a trench, a photodiode, and a pass transistor. The photodiode is formed at an upper portion of the substrate and includes a P-type diffusion area and an N-type diffusion area which are joined with each other in a longitudinal direction. The pass transistor is formed at the upper portion of the substrate and includes the one terminal that is the joined P-type diffusion area and the N-type diffusion area, the other terminal that is a floating diffusion area, and a gate terminal disposed between the two terminals. The pixel for picking up an image signal is surrounded by the trench which penetrates the substrate from the upper portion to the lower portion of the substrate, and the trench is filled with an insulator.

Abstract: Disclosed are semiconductor devices with breakdown voltages that are more controlled and stable after repeated exposure to breakdown conditions than prior art devices. The disclosed devices can be used to provide secondary circuit functions not previously contemplated by the prior art.

Abstract: A variable-resistance material memory (VRMM) device includes a container conductor disposed over an epitaxial semiconductive prominence that is coupled to a VRMM. A VRMM device may also include a conductive plug in a recess that is coupled to a VRMM. A VRMM array may also include a conductive plug in a surrounding recess that is coupled to a VRMM. Apparatuses include the VRMM with one of the diode constructions.

Abstract: A semiconductor device made of a group-III nitride semiconductor having excellent properties is provided. The semiconductor device has a horizontal diode structure of Schottky type or P-N junction type, or combined type thereof having a main conduction pathway in the horizontal direction in a conductive layer with unit anode portions and unit cathode electrodes being integrated adjacently to each other in the horizontal direction. The conductive layer is preferably formed by depositing a group-III nitride layer and generating a two-dimensional electron gas layer on the interface. Forming the conductive layer of the group-III nitride having high breakdown field allows the breakdown voltage to be kept high while the gap between electrodes is narrow, which achieves a semiconductor device having high output current per chip area.

Abstract: This invention discloses a bottom-anode Schottky (BAS) diode that includes an anode electrode disposed on a bottom surface of a semiconductor substrate. The bottom-anode Schottky diode further includes a sinker dopant region disposed at a depth in the semiconductor substrate extending substantially to the anode electrode disposed on the bottom surface of the semiconductor and the sinker dopant region covered by a buried Schottky barrier metal functioning as a Schottky anode.

Abstract: The invention relates to noise isolation in semiconductor devices, and a design structure on which a subject circuit resides. A design structure is embodied in a machine readable medium used in a design process. The design structure includes a deep sub-collector located in a first epitaxial layer, and a doped region located in a second epitaxial layer, which is above the first epitaxial layer. The design structure further includes a reach-through structure penetrating from a surface of the device through the first and second epitaxial layers to the deep sub-collector, and a trench isolation structure penetrating from a surface of the device and surrounding the doped region.

Abstract: The present invention relates to embodiments of TPV cell structures based on carbon nanotube and nanowire materials. One embodiment according to the present invention is a p-n junction carbon nanotube/nanowire TPV cell, which is formed by p-n junction wires. A second embodiment according to the present invention is a carbon nanotube/nanowire used as a p-type (or n-type), and using bulk material as the other complementary type to a form p-n junction TPV cell. A third embodiment according to the present invention uses a controllable Schottky barrier height between a one-dimensional nanowire and a metal contact to form the built-in potential of the TPV cells.

Abstract: A junction barrier Schottky diode has an N-type well having surface and a first impurity concentration; a p-type anode region in the surface of the well, and having a second impurity concentration; and an N-type cathode region in the surface of the well and horizontally abutting the anode region, and having a third impurity concentration. A first N-type region vertically abuts the anode and cathode regions, and has a fourth impurity concentration. An ohmic contact is made to the anode and a Schottky contact is made to the cathode. The fourth impurity concentration is less than the first, second and third impurity concentrations.

Abstract: Methods and heterostructure barrier varactor (HBV) diodes optimized for application with frequency multipliers at providing outputs at submillimeter wave frequencies and above. The HBV diodes include a silicon-containing substrate, an electrode over the silicon-containing substrate, and one or more heterojunction quantum wells of alternating layers of Si and SiGe of one or more electrodes of the diode. Each SiGe quantum well preferably has a floating SiGe layer between adjacent SiGe gradients followed by adjacent Si layers, such that, a single homogeneous structure is provided characterized by having no distinct separations. The plurality of Si/SiGe heterojunction quantum wells may be symmetric or asymmetric.

Abstract: A varactor diode includes a contact layer having a first conductivity type, a voltage blocking layer having the first conductivity and a first net doping concentration on the contact layer, a blocking junction on the voltage blocking layer, and a plurality of discrete doped regions in the voltage blocking layer and spaced apart from the carrier injection junction. The plurality of discrete doped regions have the first conductivity type and a second net doping concentration that is higher than the first net doping concentration, and the plurality of discrete doped regions are configured to modulate the capacitance of the varactor diode as a depletion region of the varactor diode expands in response to a reverse bias voltage applied to the blocking junction. Related methods of forming a varactor diode are also disclosed.

Abstract: An integrated circuit structure in which a plurality of Schottky diodes and a capacitor are integrally formed. The integrated circuit structure includes a substrate including an N-type semiconductor doped with N-type impurities and a P-type semiconductor doped with P-type impurities; a first conductive layer laminated on the substrate so that the first conductive layer is electrically connected to the N-type semiconductor and the P-type semiconductor; a dielectric layer laminated on an upper surface of the first conductive layer; and a second conductive layer laminated on an upper surface of the dielectric layer so that the second conductive layer forms a capacitor together with the first conductive layer and the dielectric layer. Accordingly, when the integrated circuit structure is used in a rectification circuit, the size of an entire circuit can be reduced.

Abstract: A Schottky barrier diode includes a first semiconductor layer and a second semiconductor layer successively formed above a semiconductor substrate with a buffer layer formed between the first and second semiconductor layers and the semiconductor substrate. A Schottky electrode and an ohmic electrode spaced from each other are formed on the second semiconductor layer, and a back face electrode is formed on the back face of the semiconductor substrate. The Schottky electrode or the ohmic electrode is electrically connected to the back face electrode through a via penetrating through at least the buffer layer.

Abstract: The present invention relates to dielectric actuators or sensors of the kind wherein electrostatic attraction between two electrodes located on an elastomeric body leads to a compression of the body in a first direction and a corresponding extension of the body in a second direction. The dielectric actuator/sensor structure comprises a first sheet of elastomeric material having at least one smooth surface and a second surface and a second sheet of elastomeric material having at least one smooth surface and a second surface. The sheets are laminated together with their second surfaces exposed, and there is provided a first electrode on the second surface of the first sheet and second electrode on the second surface of the second sheet.

Abstract: Disclosed is a semiconductor structure, which includes a non-planar varactor having a geometrically designed depletion zone with a taper, as to provide improved Cmax/Cmin with low series resistance. Because of the taper, the narrowest portion of the depletion zone can be designed to be fully depleted, while the remainder of the depletion zone is only partially depleted. The fabrication of semiconductor structure may follow that of standard FinFET process, with a few additional or different steps. These additional or different steps may include formation of a doped trapezoidal (or triangular) shaped silicon mesa, growing/depositing a gate dielectric, forming a gate electrode over a portion of the mesa, and forming a highly doped contact region in the mesa where it is not covered by the gate electrode.

Abstract: A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n? doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n? doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts.

Abstract: A voltage controlled oscillator (VCO), suitable for use in a frequency shift keying (FSK) system. The VCO device comprises a switching varactor unit, having a first terminal and a second terminal, wherein the switching varactor unit produces a capacitance, according to a frequency-selection voltage. A VCO core has a first output terminal, a second output terminal complementary to the first output terminal, and an input terminal. Wherein, the switching varactor unit is coupled in parallel with the VCO core at the first output terminal and the second output terminal to produce a capacitance effect with respect to the capacitance, so as to adjust a frequency constant ?{square root over (LC)} of the VCO core.

Abstract: A structure and method comprises a deep sub-collector located in a first epitaxial layer and a doped region located in a second epitaxial layer, which is above the first epitaxial layer. The device further comprises a reach-through structure penetrating from a surface of the device through the first and second epitaxial layers to the deep sub-collector, and a trench isolation structure penetrating from a surface of the device and surrounding the doped region.

Abstract: A semiconductor film is formed on a substrate. Subsequently, a resist film is formed on the semiconductor film, and dry etching is performed to the semiconductor film using the resist film as a mask. Due to the dry etching, the edge portion of the semiconductor film protrudes from the resist film. Next, the p-type impurities are introduced into the edge portion of the semiconductor film using the resist film as a mask. The volume density of the p-type impurities in a channel edge portion of the semiconductor film is two to five times the volume density of the p-type impurities in a channel center section. Subsequently, the resist film is removed to form a gate insulating film and a gate electrode.

Abstract: An integrally packaged optronic integrated circuit device (310) including an integrated circuit die (322) containing at least one of a radiation emitter and radiation receiver and having top and bottom surfaces formed of electrically insulative and mechanically protective material, at least one of the surfaces (317) being transparent to radiation, and electrically insulative edge surfaces (314) having pads.

Abstract: Schottky barrier diodes use a dielectric separation region to bound an active region. The dielectric separation region permits the elimination of a guard ring in at least one dimension. Further, using a dielectric separation region in an active portion of the integrated circuit device may reduce or eliminate parasitic capacitance by eliminating this guard ring.

Abstract: A method for fabricating a Schottky diode using a shallow trench contact to reduce leakage current in the fabrication of an integrated circuit device is described. An insulating layer is deposited over a thermal oxide layer provided overlying a silicon semiconductor substrate. A contact opening is etched through the insulating layer and the thermal oxide layer to the silicon substrate. The contact opening is overetched whereby a shallow trench is formed within the silicon substrate underlying the contact opening wherein the shallow trench has a bottom and sidewalls comprising the silicon substrate. A first metal layer is deposited over the insulating layer and within the contact opening and within the shallow trench.

Abstract: Electron-hole production at a Schottky barrier has recently been observed experimentally as a result of chemical processes. This conversion of chemical energy to electronic energy may serve as a basic link between chemistry and electronics and offers the potential for generation of unique electronic signatures for chemical reactions and the creation of a new class of solide state chemical sensors. Detection of the following chemical species was established: hydrogen, deuterium, carbon monoxide, molecular oxygen. The detector (1b) consists of a Schottky diode between an Si layer and an ultrathin metal layer with zero force electrical contacts.

Abstract: In one embodiment, a varactor includes a first node and a second node. The varactor includes: at least one first varactor element including a source, a drain, and a p-type doped gate; at least one second varactor element including a source, a drain, and an n-type doped gate; and at least one third varactor element including a source, a drain, and an intermediately doped gate, the intermediately doped gate having doping characteristics intermediate to doping characteristics of the p-type and n-type gates. The varactor includes one or more wells in a substrate region underlying the first, second, and third varactor elements. The first, second, and third varactor elements are coupled in parallel between the first and second nodes.

Abstract: A semiconductor diode with hydrogen detection capability includes a semiconductor substrate, a doped semiconductor active layer formed on the substrate and made from a compound having the formula XYZ, in which X is a Group III element, Y is another Group III element different from X, and Z is a Group V element, a semiconductor contact-enhancing layer formed on the active layer and made from a compound having the formula MN, in which M is a Group III element, and N is a Group V element, an ohmic contact layer formed on the semiconductor contact-enhancing layer, and a Schottky barrier contact layer formed on the active layer. The Schottky barrier contact layer is made from a metal that is capable of dissociating a hydrogen molecule into hydrogen atoms.

Abstract: A semiconductor device, such as a pin diode, includes a first drift layer, a second drift layer, an anode layer on the first drift layer, and a buffer layer formed between the first and second drift layers. The shortest distance from the pn-junction between the anode layer and the buffer layer, and the thickness of the buffer layer are set at the respective values at which a high breakdown voltage is obtained, while reducing the tradeoff relation between the soft recovery and the fast and low-loss reverse recovery.

Abstract: A semiconductor device includes a plurality of barrier layers and a plurality of quantum well layers which are alternately interleaved with each other and disposed on a substrate of semiconductor material so as to form a multiple-heterojunction varactor diode. The barrier layers and quantum well layers are doped with impurities. The varactor diode includes an ohmic contact which is electrically connected to a heavily doped embedded region and a Schottky contact which is electrically connected to a depletion region of the diode. The ohmic contact and the Schottky contact enable an external voltage source to be applied to the contacts so as to provide a bias voltage to the varactor diode. A variable capacitance is produced as a result of the depletion region varying with a variation in the bias voltage. The varactor diode also provides a constant series resistance.

Abstract: An integrated Schottky barrier diode chip includes a compound semiconductor substrate, a plurality of Schottky barrier diodes formed on the substrate and an insulating region formed on the substrate by an on implantation. The insulating region electrically separates a portion of a diode at a cathode voltage from a portion of the diode at an anode voltage. Because of the absence of a polyimide layer and trench structures, this planar device configuration results in simpler manufacturing method and improved device characteristics.

Abstract: A Semiconductor component, such as an IGBT, a thyristor, a GTO or a diode, and especially a Schottky diode is provided that is capable of blocking for producing a termination portion of a semiconductor component. An insulator profile of an insulator portion includes a curved surface, which is free of steps and is produced by gray-tone lithography in the termination portion of an anode. The device also includes a substrate that is covered with an insulating layer having a thickness of between 0.5 &mgr;m and 15 &mgr;m, an insulator layer having a thickness is covered with a photosensitive layer (photoresist layer) where the photoresist layer is exposed through a mask, which changes in its gray-tone value in accordance with the course of curvature of the surface of at least one insulator profile, and is subsequently structured to form at least one resist remainder.

Abstract: A method and apparatus is provided to identify defective laminate objects or package substrates having mounting sites for integrated circuit dies during the package substrate fabrication process. A hole is drilled or punched within the boundary of an individual package substrate contained within a larger laminate substrate and covered with a material layer coating composed of an opaque material such as a resist. The coating may then be selectively applied or removed at a later point during the fabrication process dependent upon whether the package substrate has been classified as defective or non-defective. After specific package substrates have been marked as defective, a light source and light collector are supplied to the fabrication process on opposite sides of the wafer. By shining the light source on the laminate substrate, defective package substrates can be identified by the passage of light through the hole which is no longer covered with resist.

Abstract: A varactor includes a semiconductor substrate of a first conductivity type, a high-concentration buried collector region of a second conductivity type formed in an upper portion of the semiconductor substrate, a collector region of the second conductivity type formed on a first surface of the high-concentration buried collector region, a high-concentration collector contact region of the second conductivity type formed on a second surface of the high-concentration buried collector region, a high-concentration silicon-germanium base region of the first conductivity type formed on the collector region, a metal silicide layer formed on the silicon-germanium base region, a first electrode layer formed to contact the metal silicide layer, and a second electrode layer formed to be electrically connected to the collector contact region.

Abstract: The subject invention relates to a metal-semiconductor diode clamped semiconductor device and method for producing such device. A specific embodiment of the subject invention utilizes one or more Schottky barriers at, for example, the drain and/or source of at least one transistor of a field effect transistor integrated circuit. The use of one or more Schottky barriers is useful for reducing the susceptibility of latch-up for circuits having two opposite type transistors, i.e., two opposite polarity carriers, in which the two transistors are in close enough proximity to experience latch-up. This can allow the spacing between n- and p-type transistors to be reduced, thus reducing the area of the circuit. The subject invention can also allow the elimination of a metal contact by utilizing the metal layer used to form the metal-semiconductor junction in a complementary IGFET structure, to further reduce the circuit area. The subject invention is applicable to complementary metal oxide silicon (CMOS) devices.

Abstract: The present invention provides a varactor diode for frequency multipliers at submillimeter wave frequencies and above. Functionally the new diode replaces the conventional heterostructure barrier varactor diode. Two important features of the antimony-based quantum well heterostructure barrier varactor are; first: an aluminum antimnide/aluminum-arsenic-antimnide heterostructure barrier and second: a bandgap-engineered, triangular quantum well cathode and anode.

Abstract: A semiconductor device which can prevent an operation thereof from being uncontrollable to obtain a high reliability, and can be manufactured easily and can reduce a manufacturing cost. A p-type impurity layer containing a p-type impurity in a relatively high concentration is provided as an operation region of a diode in one of main surfaces of a silicon substrate containing an n-type impurity in a relatively low concentration and a plurality of ring-shaped Schottky metal layers are concentrically provided on the main surface of the silicon substrate around the p-type impurity layer with a space formed therebetween to surround the p-type impurity layer. A silicon oxide film is provided on the main surface of the silicon substrate around the p-type impurity layer and an anode electrode is provided on the p-type impurity layer.

Abstract: A receiver for radio or television signals provided with a high-frequency circuit having a discrete semiconductor component which includes a planar variable capacitance diode and an integrated series resistor formed on a common semiconductor or substrate. The receiver has lower parasitic capacitance and improved data reception, resulting in an increase of the Q factor of the variable capacitance diode and an increase in the circuit performance. The overall circuit loss is also reduced.

Abstract: An object of this invention is to provide a pn-varactor having a small resistance and capable of coinciding with incorporation of a circuit employing LC resonance into an integrated circuit. A dummy gate pattern 4 is formed over a n-well 1 in a semiconductor wafer and then p+ diffusion regions 2, 3 are formed on both sides with the dummy gate pattern 4 as inhibition mask. For the purpose, a control voltage VT higher than potentials of the p+ diffusion regions 2, 3 is applied to the n-well 1. Consequently, both the pn-junction between the n-well 1 and the p+ diffusion region 2 and the pn-junction between the n-well 1 and the p+ diffusion region 3 act as a pn-varactor whose capacity is changed by the control voltage VT. If an end dummy pattern is provided on both sides or around the p+ diffusion regions 2, 3, imbalance in capacity due to deflection in position is prevented.

Abstract: A Schottky barrier diode has a Schottky contact region formed in an n epitaxial layer disposed on a GaAs substrate and an ohmic electrode surrounding the Schottky contact region. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. An insulating region is formed through the n epitaxial layer so that an anode bonding pad is isolated form other elements of the device at a cathode voltage. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.

Abstract: The package size of a diode is made smaller. On the element forming face of a semiconductor substrate having a p−-type conductive type, after a hyper-abrupt p+n+ junction of a p+-type diffusion layer, an n+-type hyper-abrupt layer, an n−-epitaxial layer, an n-type low resistance layer and an n+-type diffusion layer is formed, an anode electrode is formed on the top of the p+-type diffusion layer and a cathode electrode is formed on the top of the n+-type diffusion layer. Thereafter, electrode bumps are formed on the top of the anode electrode and the cathode electrode to thereby manufacture a small diode that can be facedown bonded onto a mounting board.

Abstract: A varactor circuit having an increased tuning range comprises a first varactor in series with a second varactor between first and second terminals. A resistor is connected between the first and second terminals. A tap of the resistor is connected to a junction of the first and second varactors. This circuit effectively doubles tuning range compared to a single varactor.