Schottky Barrier Patents (Class 257/471)
  • Patent number: 11164979
    Abstract: A semiconductor device includes a semiconductor substrate, a Schottky layer, a plurality of first doped regions, a plurality of second doped regions, a first conductive layer and a second conductive layer. The semiconductor substrate includes a first conductive type, and the Schottky layer is disposed on the semiconductor substrate. The first doped regions and the second doped regions include a second conductive type, and which are disposed within the semiconductor substrate. The first doped regions are in parallel and extended along a first direction, and the second doped regions are in parallel and extended along a second direction to cross the first doped regions, thereby to define a plurality of grid areas. The first conductive layer is disposed on the Schottky layer, and the second conductive layer is disposed under the semiconductor substrate.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: November 2, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang Huang, Kai-Chieh Hsu, Chun-Chih Chen, Li-Fan Chen, Ching-Ho Li, Ting-You Lin, Gong-Kai Lin, Yeh-Ning Jou, Chien-Hsien Song, Hsiao-Ying Yang, Chien-Chi Hsu, Fu-Chun Tseng
  • Patent number: 10985241
    Abstract: A semiconductor device includes a semiconductor substrate, which includes an element region and an outer-periphery voltage withstanding region. The outer-periphery voltage withstanding region includes a plurality of p-type guard rings surrounding the element region in a multiple manner. Each of the guard rings includes a high concentration region and a low concentration region. A low concentration region of an outermost guard ring includes a first part positioned on an outer peripheral side of its high concentration region. Respective low concentration regions of the guard rings include respective second parts, each positioned in a range sandwiched between corresponding two adjacent high concentration regions among a plurality of concentration regions. A width of the first part on a front surface is wider than widths of the second parts on the front surface.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: April 20, 2021
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Hiromichi Kinpara, Yusuke Yamashita, Yasushi Urakami
  • Patent number: 10923603
    Abstract: A semiconductor device includes a first N-type deep well region and a second N-type deep well region formed in a substrate, an N-type diffused well region formed between the first N-type deep well region and the second N-type deep well region, wherein a concentration of the N-type diffused well region is less than a concentration of the first N-type deep well region or the second N-type deep well region, a first P-type well region formed in the first N-type deep well region, a second P-type well region formed in the N-type diffused well region, an insulating film formed to be in contact with the first P-type well region, and a silicide formed on the N-type diffused well region, such that a Schottky barrier diode is formed between the silicide and the N-type diffused well.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: February 16, 2021
    Assignee: Key Foundry Co., Ltd.
    Inventors: Yon Sup Pang, Hyun Kwang Shin, Tae Hoon Lee
  • Patent number: 10916644
    Abstract: A semiconductor device includes a first electrode, a second electrode disposed at a position opposing the first electrode, and a semiconductor body provided between the first electrode and the second electrode. The semiconductor body includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type and a third semiconductor layer of the second conductivity type; the second semiconductor layer is provided between the first semiconductor layer and the first electrode; and the third semiconductor layer is selectively provided inside the first semiconductor layer and disposed at a position separated from the second semiconductor layer. The first electrode is electrically connected to the second semiconductor layer and includes an extension portion; and the extension portion pierces the second semiconductor layer, extends in a first direction toward the second electrode, and is connected to the third semiconductor layer.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: February 9, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Keiko Kawamura, Tsuneo Ogura
  • Patent number: 10916626
    Abstract: A silicon carbide diode that contains a silicon carbide substrate, a silicon carbide layer on top of the silicon carbide substrate, two first lower barrier metal portions disposed on the silicon carbide layer and separated from each other along a top surface of the silicon carbide layer, and a first higher barrier metal portion connected to the two lower barrier metal portions. The silicon carbide layer is thinner and having lower doping than the silicon carbide substrate. The first higher barrier metal portion is located between the two first lower barrier metal portions on the silicon carbide layer along a direction of the top surface of the silicon carbide layer. By reducing the leakage current at the junction barrier, the reverse breakdown voltage of the silicon carbide diode is significantly improved.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: February 9, 2021
    Assignee: Hong Kong Applied Science and Technology Research Institute Co., Ltd.
    Inventors: Shu Kin Yau, Siu Wai Wong
  • Patent number: 10896953
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high voltage diode structures and methods of manufacture. The structure includes: a diode structure composed of first well of a first dopant type in a substrate; and a well ring structure of the first dopant type in the substrate which completely surrounds the first well of the first dopant type, and spaced a distance “x” from the first well to cut a leakage path to a shallower second well of a second dopant type.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: January 19, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jagar Singh, Shiv Kumar Mishra
  • Patent number: 10896981
    Abstract: Aspects generally relate to a P-N junction varactor that can be integrated with high electron mobility transistor (HEMT) in a single device or die. The varactor and HEMT are fabricated with the same materials forming various layers of the varactor and HEMT. Using the same material stack-up to form the varactor and HEMT can reduce the number of processing steps during the fabrication of the integrated varactor and HEMT device. The integrated varactor and HEMT device may be used for RF circuits, such as radio frequency front end (RFFE) devices for use in 5G.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: January 19, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Gengming Tao, Xia Li, Bin Yang
  • Patent number: 10886266
    Abstract: Aspects generally relate to a P?N junction varactor that can be integrated with high electron mobility transistor (HEMT) in a single device or die. The varactor and HEMT are fabricated with different materials forming various layers of the varactor and HEMT. Using different material stack-up to form the varactor and HEMT allows characteristics of the varactor and HEMT to be varied for improved performance in different operating scenarios. The integrated varactor and HEMT device may be used for RF circuits, such as radio frequency front end (RFFE) devices for use in 5G.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: January 5, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Gengming Tao, Bin Yang, Xia Li
  • Patent number: 10680119
    Abstract: A Schottky diode includes an insulating substrate and at least one Schottky diode unit. The at least one Schottky diode unit is located on a surface of the insulating substrate. The at least one Schottky diode unit includes a first electrode, a semiconductor structure and a second electrode. The semiconductor structure comprising a first end and a second end. The first end is laid on the first electrode; the second end is located on the surface of the insulating substrate. The semiconducting structure is nano-scale semiconductor structure. The second electrode is located on the second end.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: June 9, 2020
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Dan Zhao, Xiao-Yang Xiao, Ying-Cheng Wang, Yuan-Hao Jin, Tian-Fu Zhang, Qun-Qing Li
  • Patent number: 10629747
    Abstract: A thin film transistor, a manufacturing method of the thin film transistor, an array substrate and a manufacturing method of the array substrate are provided. The thin film transistor includes a base substrate, a metal light-shielding layer and a first active layer which are on the base substrate, and a spacer layer between the first active layer and the metal light-shielding layer; the first active layer includes a channel region, and the spacer layer is between the channel region and the metal light-shielding layer.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: April 21, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Cuili Gai, Ling Wang, Baoxia Zhang
  • Patent number: 10580769
    Abstract: A semiconductor device with an embedded schottky diode and a manufacturing method thereof are provided. A semiconductor device having a schottky diode include: an epilayer of a first conductivity type, a body layer of a second conductivity type, and a source layer of the first conductivity type arranged in that order; a gate trench that extends from the source layer to a part of the epilayer; a body trench formed a predetermined distance from the gate trench and extends from the source layer to a part of the epilayer; and a guard ring of the second conductivity type that contacts an outer wall of the body trench and formed in the epilayer.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: March 3, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Francois Hebert
  • Patent number: 10566465
    Abstract: A semiconductor device includes a first N-type deep well region and a second N-type deep well region formed in a substrate, an N-type diffused well region formed between the first N-type deep well region and the second N-type deep well region, wherein a concentration of the N-type diffused well region is less than a concentration of the first N-type deep well region or the second N-type deep well region, a first P-type well region formed in the first N-type deep well region, a second P-type well region formed in the N-type diffused well region, an insulating film formed to be in contact with the first P-type well region, and a silicide formed on the N-type diffused well region, such that a Schottky barrier diode is formed between the silicide and the N-type diffused well.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: February 18, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Yon Sup Pang, Hyun Kwang Shin, Tae Hoon Lee
  • Patent number: 10510905
    Abstract: A Schottky diode includes a drift region, a channel in an upper portion of the drift region, and first and second adjacent blocking junctions in the upper portion of the drift region that define the channel therebetween. The drift region and channel are doped with dopants having a first conductivity type, and the first and second blocking junctions doped with dopants having a second conductivity type that is opposite the first conductivity type. The blocking junctions extend at least one micron into the upper portion of the drift region and are spaced apart from each other by less than 3.0 microns.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: December 17, 2019
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Edward R. Van Brunt, Brett Hull, Scott Thomas Allen
  • Patent number: 10411108
    Abstract: A vertical Schottky diode includes an ohmic contact, a first epitaxial N-type gallium nitride layer physically contacting the ohmic contact and having a first doping concentration, and a second epitaxial N-type gallium nitride layer physically contacting the first epitaxial N-type gallium nitride layer and having a second doping concentration that is lower than the first doping concentration. The vertical Schottky diode further includes a first edge termination region and a second edge termination region coupled to the second epitaxial N-type gallium nitride layer and separated from each other by a portion of the second epitaxial N-type gallium nitride layer, and a Schottky contact coupled to the portion of the second epitaxial N-type gallium nitride layer, and to the first edge termination region and the second edge termination region.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: September 10, 2019
    Assignee: Qromis, Inc.
    Inventors: Vladimir Odnoblyudov, Ozgur Aktas
  • Patent number: 10347714
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type, an impurity region of a second conductivity type formed in a surface layer portion of the semiconductor layer, a terminal region of the second conductivity type that is formed in the surface layer portion of the semiconductor layer along a peripheral edge of the impurity region and that has a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the impurity region, and a surface electrode that is formed on the semiconductor layer and that has a connection portion connected to the impurity region and to the terminal region.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: July 9, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Jun Takaoka
  • Patent number: 10297696
    Abstract: A Schottky diode includes an insulating substrate and at least one Schottky diode unit. The at least one Schottky diode unit is located on a surface of the insulating substrate. The at least one Schottky diode unit includes a first electrode, a semiconductor structure and a second electrode. The semiconductor structure comprising a first end and a second end. The first end is laid on the first electrode, the second end is located on the surface of the insulating substrate. The semiconducting structure is nano-scale semiconductor structure. The second electrode is located on the second end.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: May 21, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Dan Zhao, Xiao-Yang Xiao, Ying-Cheng Wang, Yuan-Hao Jin, Tian-Fu Zhang, Qun-Qing Li
  • Patent number: 10294581
    Abstract: A method of plating a substrate, such as a wafer, by applying a voltage between the substrate and an anode is disclosed. The plating method includes: preparing a substrate having a recess formed in a surface thereof, a conductive layer being formed in at least a part of the recess; placing an insoluble anode and the substrate in contact with a copper sulfate plating solution containing an additive; applying a predetermined plating voltage between the substrate and the insoluble anode by a plating power source to plate the substrate; and shutting off a reverse electric current, which flows from the insoluble anode to the substrate via the plating power source, by a diode disposed between the insoluble anode and the substrate when the predetermined plating voltage is not applied.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: May 21, 2019
    Assignee: EBARA CORPORATION
    Inventors: Shingo Yasuda, Akira Owatari
  • Patent number: 10233535
    Abstract: A plasma processing apparatus includes a first electrode, a second electrode disposed to face the first electrode, a chamber, a first high-frequency power supply, a direct-current power supply, and a gas supply source. The plasma processing apparatus generates first plasma to form a film of a reaction product on the second electrode by causing the first high-frequency power supply to supply first high-frequency power to the second electrode and causing the gas supply source to supply a first gas into the chamber; and generates second plasma to sputter the film of the reaction product by causing the first high-frequency power supply to supply the first high-frequency power to the second electrode, causing the direct-current power supply to supply direct-current power to the second electrode, and causing the gas supply source to supply a second gas into the chamber.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: March 19, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Yoshihide Kihara, Masanobu Honda, Toru Hisamatsu
  • Patent number: 10229970
    Abstract: For enhancing a reverse-recovery immunity of a diode element, a semiconductor device includes a first conductivity-type drift layer, a second conductivity-type anode region provided in an upper portion of the drift layer, an insulating film provided on the drift layer, an anode electrode having an ohmic contact portion ohmically contacted to the anode region through a contact hole penetrating the insulating film, and a Schottky electrode Schottky-contacted to a peripheral portion of the anode region.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: March 12, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Eri Ogawa, Akio Nakagawa
  • Patent number: 10199514
    Abstract: An embodiment of a method of manufacturing a semiconductor device includes providing a semiconductor material that comprises SiC and forming an electrically conductive contact layer on the semiconductor material. A non-ohmic contact is formed between the semiconductor material and the electrically conductive contact layer. The electrically conductive contact layer comprises a metal nitride with a nitrogen content between 10 to 50 atomic %. Additional embodiments of manufacturing a semiconductor device are described.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: February 5, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Jens Peter Konrath, Ronny Kern, Stefan Krivec, Ulrich Schmid, Laura Stoeber
  • Patent number: 10199454
    Abstract: For enhancing a reverse-recovery immunity of a diode element, a semiconductor device includes a first conductivity-type drift layer, a second conductivity-type anode region provided in an upper portion of the drift layer, an insulating film provided on the drift layer, an anode electrode having an ohmic contact portion ohmically contacted to the anode region through a contact hole penetrating the insulating film, and a Schottky electrode Schottky-contacted to a peripheral portion of the anode region.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: February 5, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Eri Ogawa, Akio Nakagawa
  • Patent number: 10157980
    Abstract: The present disclosure provides a method of manufacturing a Schottky diode. A substrate is provided. A first well region of a first conductive type is formed in the substrate. A first ion implantation of a second conductive type is performed on a first portion of the first well region while keeping a second portion of the first well region from being implanted. A first doped region is formed by heating the substrate to cause dopant diffusion between the first portion and the second portion. A metal-containing layer is formed on the first doped region to obtain a Schottky barrier interface.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Shun Lo, Yu-Chi Chang, Felix Ying-Kit Tsui
  • Patent number: 10134727
    Abstract: III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: November 20, 2018
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Sansaptak Dasgupta, Gerhard Schrom, Valluri R. Rao, Robert S. Chau
  • Patent number: 10134851
    Abstract: A diode includes: a semiconductor substrate; a cathode metal layer contacting a bottom of the substrate; a semiconductor drift layer on the substrate; a graded aluminum gallium nitride (AlGaN) semiconductor barrier layer on the drift layer and having a larger bandgap than the drift layer, the barrier layer having a top surface and a bottom surface between the drift layer and the top surface, the barrier layer having an increasing aluminum composition from the bottom surface to the top surface; and an anode metal layer directly contacting the top surface of the barrier layer.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: November 20, 2018
    Assignee: HRL Laboratories, LLC
    Inventors: Rongming Chu, Yu Cao, Zijian “Ray” Li, Adam J. Williams
  • Patent number: 10062746
    Abstract: A semiconductor rectifying device includes a substrate of a first conductivity type, an epitaxial layer of the first conductivity type, a filling structure, an upper electrode, a guard ring, and a guard layer. The epitaxial layer defines a plurality of trenches thereon. The filling structure includes an insulating material formed on the inner surface of the trench and a conductive material filled in the trench. A doped region of a second conductivity type is formed in the surface of the epitaxial layer between the filling structures. A method of manufacturing a semiconductor rectifying device includes forming an epitaxial layer of a first conductivity type on a substrate of the first conductivity type, defining a plurality of trenches on the epitaxial layer, forming a plurality of filling structures in the plurality of trenches, and forming a doped region in the epitaxial layer between the filling structures.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: August 28, 2018
    Assignee: CSMC TECHNOLOGIES FAB1 CO., LTD.
    Inventors: Shengrong Zhong, Xiaoshe Deng, Dongfei Zhou
  • Patent number: 9972725
    Abstract: There is provided a semiconductor device configured to include a plurality of semiconductor units formed in a semiconductor layer. Each of the semiconductor units comprises a mesa portion; a Schottky electrode formed on the mesa portion; an insulating film formed continuously on another portion of the Schottky electrode that is nearer to an edge of an upper face of the mesa portion than one portion of the Schottky electrode, on a side face of the mesa portion, and on a surface of the semiconductor layer other than the mesa portion; and a wiring electrode formed on the Schottky electrode and the insulating film. An angle between the side face of the mesa portion and the surface of the semiconductor layer is 90 degrees. A part of the wiring electrode is placed between the insulating films formed on opposed side faces of adjacent mesa portions.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: May 15, 2018
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Kazuya Hasegawa, Tohru Oka, Nariaki Tanaka
  • Patent number: 9899482
    Abstract: A diode includes: a semiconductor substrate; a cathode metal layer contacting a bottom of the substrate; a semiconductor drift layer on the substrate; a graded aluminum gallium nitride (AlGaN) semiconductor barrier layer on the drift layer and having a larger bandgap than the drift layer, the barrier layer having a top surface and a bottom surface between the drift layer and the top surface, the barrier layer having an increasing aluminum composition from the bottom surface to the top surface; and an anode metal layer directly contacting the top surface of the barrier layer.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: February 20, 2018
    Assignee: HRL Laboratories, LLC
    Inventors: Rongming Chu, Yu Cao, Zijian Li, Adam J. Williams
  • Patent number: 9876011
    Abstract: A semiconductor device comprising: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on the first semiconductor region; an insulating portion provided on the first semiconductor region; a third semiconductor region of the second conductivity type provided on the second semiconductor region and having a higher carrier concentration of the second conductivity type than that of the second semiconductor region; and a first electrode provided on the insulating portion and the third semiconductor region, the first electrode having a portion which is aligned with the second semiconductor region in a second direction perpendicular to a first direction being from the first semiconductor region to the second semiconductor region, and the first electrode being in contact with the second semiconductor region and the third semiconductor region.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: January 23, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Matsushita, Kazutoshi Nakamura
  • Patent number: 9865750
    Abstract: The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the drift layer. The metal for the Schottky layer and the semiconductor material for the drift layer are selected to provide a low barrier height Schottky junction between the drift layer and the Schottky layer.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: January 9, 2018
    Assignee: Cree, Inc.
    Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Kumar Agarwal, John Williams Palmour, Scott Allen
  • Patent number: 9799732
    Abstract: A P+ type region, a p-type region, and a P? type region are disposed in a surface layer of a silicon carbide substrate base and are disposed in a breakdown voltage structure portion surrounding an active region to make up an element structure of Schottky junction. The p? type region surrounds the P+ type region and the p-type region to form a junction termination structure. A Schottky electrode forms a Schottky junction with an n-type silicon carbide epitaxial layer. The Schottky electrode and an electrode pad have end portions positioned on the P+ type region and the end portion of the Schottky electrode is exposed from the end portion of the electrode pad. As a result, the region of the breakdown voltage structure portion can be made smaller while the active region can be made larger, and a semiconductor device is easily fabricated.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: October 24, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi Tsuji, Noriyuki Iwamuro, Kenji Fukuda
  • Patent number: 9768230
    Abstract: Devices and methods for forming a device are disclosed. The device includes a substrate and a selector diode disposed over the substrate. The diode includes first and second terminals. The first terminal is disposed between the second terminal and the substrate. The diode includes a Schottky Barrier (SB) disposed at about an interface of the first and second terminals. The SB includes a tunable SB height defined by a SB region having segregated dopants. The device includes a memory element disposed over and coupled to the selector diode.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: September 19, 2017
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Yuan Sun, Eng Huat Toh
  • Patent number: 9741849
    Abstract: Integrated circuits and methods of producing such integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a heavily doped source area having conductivity determining impurities at a heavily doped source concentration and a lightly doped drain area having conductivity determining impurities at a lightly doped drain concentration less than the heavily doped source concentration. A drain conductor directly contacts the lightly doped drain area, and a channel is positioned between the heavily doped source area and the lightly doped drain area. A gate overlies the channel.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: August 22, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Chien-Hsin Lee, Mahadeva Iyer Natarajan, Xiangxiang Lu, Tsung-Che Tsai, Manjunatha Prabhu
  • Patent number: 9728654
    Abstract: A semiconductor device includes: a first conductive type semiconductor device; a first conductive type drift region formed by epitaxial growth on the semiconductor substrate; a plurality of first conductive type vertical implantation regions formed by multistage ion implantation in the drift region, the vertical implantation regions having a prescribed vertical implantation width and a prescribed drift region width; an anode electrode disposed on the front surface of the drift region opposite to the semiconductor substrate, the anode electrode being in Schottky contact with the drift region and in ohmic contact with the first conductive type vertical implantation regions; and a cathode electrode disposed on the rear surface of the semiconductor substrate opposite to the drift region, the cathode electrode being in ohmic contact with the semiconductor substrate.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: August 8, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Syoji Higashida
  • Patent number: 9722042
    Abstract: The present invention discloses a group-III nitride semiconductor device, which comprises a substrate, a buffer layer, a semiconductor stack structure, and a passivation film. The buffer layer is disposed on the substrate. The semiconductor stack structure is disposed on the buffer layer and comprises a gate, a source, and a drain. In addition, a gate insulating layer is disposed between the gate and the semiconductor stack structure for forming a HEMT. The passivation film covers the HEMT and includes a plurality of openings corresponding to the gate, the source, and the drain, respectively. The material of the passivation film is silicon oxynitride.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: August 1, 2017
    Inventor: Wen-Jang Jiang
  • Patent number: 9698137
    Abstract: Electrostatic Discharge (ESD) protection using lateral surface Schottky diodes is disclosed. In one embodiment, a Metal-Insulator-Metal (MIM) capacitor with ESD protection comprises a group III-V substrate, a first metal layer contacting the substrate, an insulation layer formed over the first metal layer, and a second metal layer formed over the insulation layer and also contacting the substrate. A MIM capacitor is formed by overlapping portions of the first metal layer, the insulation layer, and the second metal layer. First and second Schottky diodes are formed where the first and second metal layers, respectively, contact the substrate, such that the cathodes of the Schottky diodes are electrically connected to one another and the anodes of the Schottky diodes are electrically connected to the respective overlapping portions of the first and second metal layers.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: July 4, 2017
    Assignee: Qorvo US, Inc.
    Inventors: Peter J. Zampardi, Brian G. Moser, Michael Meeder, Venkata Chivukula
  • Patent number: 9691911
    Abstract: A semiconductor device include a substrate, a first well region formed in the substrate, a first isolation structure formed in the first well region, a Schottky barrier structure formed on the first well region, and a plurality of assist structures formed on the first well region. The substrate includes a first conductivity type, the first well region includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. The assist structures physically contact the first well region.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: June 27, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Yin Hsiao, Ching-Chung Yang
  • Patent number: 9607944
    Abstract: A semiconductor device includes a plurality of first wires and second wires, a first conductive layer, and a second conductive layer. Each of the first wires forms a closed polygon and surrounds a center, and each of the second wires forms the closed polygon and surrounds the center. The first and second wires are interlaced, and none of the first and second wires are coupled to each other. The first conductive layer, having an entire surface structure, is disposed on the first and second wires and coupled to the first wires. The second conductive layer, having an entire surface structure, is disposed on the first and second wires and coupled to the second wires. The first conductive layer is disposed between the second conductive layer and the first and second wires, and the first and second conductive layers are not coupled to each other.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: March 28, 2017
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Pei-Heng Hung, Hsiung-Shih Chang, Manoj Kumar, Yen-Ni Lee, Teng-Shao Su
  • Patent number: 9608056
    Abstract: In one general aspect, a power rectifier device can include a drift layer including silicon carbide of n-type conductivity, and a Schottky electrode disposed on the drift layer where the Schottky electrode and a surface of the drift layer can provide a Schottky contact. The power rectifier device can also include an array of p-type regions disposed underneath the Schottky electrode.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: March 28, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Andrei Konstantinov
  • Patent number: 9577118
    Abstract: The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage Vth of 0.3 V to 0.7 V and a leakage current Jr of 1×10?9 A/cm2 to 1×10?4 A/cm2 in a rated voltage VR.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: February 21, 2017
    Assignee: ROHM CO., LTD.
    Inventors: Masatoshi Aketa, Yuta Yokotsuji
  • Patent number: 9496366
    Abstract: A method for manufacturing a semiconductor device includes forming a thermal oxide film on one surface of an SiC substrate by thermal oxidation at a temperature of 1150° C. or above in a gas atmosphere including nitrogen and oxygen, and introducing highly-concentrated nitrogen to one surface of the SiC substrate while forming the thermal oxide film; forming a highly-concentrated n-type SiC layer on one surface of the SiC substrate such that the thermal oxide film is removed from one surface of the SiC substrate by etching and, thereafter, one surface of the SiC substrate is exposed to radicals so that Si—N bonded bodies and C—N bonded bodies on one surface of the SiC substrate are removed while leaving nitrogen introduced into a lattice of SiC out of highly-concentrated nitrogen introduced into one surface of the SiC substrate; and forming an ohmic electrode layer on one surface of the SiC substrate.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: November 15, 2016
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Yusuke Maeyama, Yoshiyuki Watanabe, Shunichi Nakamura
  • Patent number: 9490134
    Abstract: A termination structure of a semiconductor device is provided. The semiconductor device includes an active area and a termination area adjacent to the active area, in which the termination area has the termination structure. The termination structure includes a substrate, an epitaxy layer, a dielectric layer, a conductive material layer and a conductive layer. The epitaxy layer is disposed on the substrate and has a voltage-sustaining region. The voltage-sustaining region has trenches parallel to each other. The dielectric layer is disposed in the trenches and on a portion of the epitaxy layer. The conductive material layer is disposed on the dielectric layer in the trenches. The conductive layer covers the trenches, and is in contact with the conductive material layer and a portion of the epitaxy layer, and is electrically connected between the active area and the termination area. A method for manufacturing the termination structure is also provided.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: November 8, 2016
    Assignee: SUPER GROUP SEMICONDUCTOR CO., LTD.
    Inventors: Chun-Ying Yeh, Yuan-Ming Lee
  • Patent number: 9455326
    Abstract: A wide bandgap semiconductor device includes a first conductive type high-concentration wide bandgap semiconductor substrate, a first conductive type low-concentration wide bandgap semiconductor deposited film which is formed on the semiconductor substrate, a metal film which is formed on the semiconductor deposited film so that a Schottoky interface region is formed between the metal film and the semiconductor deposited film, and a second conductive type region which is formed in a region of the semiconductor deposited film corresponding to a peripheral portion of the metal film, wherein the Schottoky interface region in the semiconductor deposited film is surrounded by the second conductive type region so that periodic island regions are formed in the Schottoky interface region.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: September 27, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Akimasa Kinoshita, Noriyuki Iwamuro
  • Patent number: 9412737
    Abstract: When an IGBT has a barrier layer 10 that separates an upper body region 8a from a lower body region 8b, conductivity modulation is enhanced and on-resistance decreases. When the IGBT also has a Schottky contact region 6 that extends to reach the barrier layer 10, a diode structure can be obtained. In this case, however, a saturation current increases as well as short circuit resistance decreases. The Schottky contact region 6 is separated from the emitter region 4 by the upper body region 8a. By selecting an impurity concentration in the region 8a, an increase in a saturation current can be avoided. Alternatively, a block structure that prevents a depletion layer extending from the region 6 into the region 8a from joining a depletion layer extending from the region 4 into the region 8a may be provided in an area separating the region 6 from the region 4.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: August 9, 2016
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Jun Saito, Satoru Machida, Yusuke Yamashita
  • Patent number: 9397231
    Abstract: A semiconductor device having a wide depletion region for increasing the breakdown voltage of the device includes an epitaxial layer of a first conductive type. An anode electrode and a cathode electrode are arranged on the epitaxial layer to be separated from each other. A first drift layer of the first conductive type formed in the epitaxial layer. A Schottky contact area is at a region of contact between the anode electrode and the first drift layer. An impurity region of a second conductive type is different from the first conductive type at the epitaxial layer. An insular impurity region is formed below the Schottky contact area.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: July 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Ju Kim, Jae-June Jang, Hoon Chang, Jae-Ho Kim, Kyu-Heon Cho
  • Patent number: 9385186
    Abstract: A high voltage device with composite structure comprises a high voltage power MOS transistor HVNMOS and a JFET. The high voltage power MOS transistor HVNMOS comprises a drain, a source, a gate and a substrate, and a P-type well region Pwell as a conducting channel which is arranged between the source and the drain. The JFET comprises the drain, the source, the gate and the substrate, and an N-type well region Nwell as a conducting channel which is arranged between the source and the drain. The high voltage power MOS transistor HVNMOS and the JFET share the same drain, and the drain is processed by using N-type double diffusion process. The embodiment of the present invention further presents a starting circuit using the high voltage device with composite structure.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: July 5, 2016
    Assignee: Shenzhen Sunmoon Microelectronics Co., Ltd.
    Inventor: Zhaohua Li
  • Patent number: 9379181
    Abstract: A semiconductor device is provided with a semiconductor substrate in which a power semiconductor element part and a temperature sensing diode part are provided. The temperature sensing diode part includes a first semiconductor region, a second semiconductor region, a first base region, and a first drift region. In the semiconductor substrate, an isolation trench is formed, which passes through the first base region, extends to the first drift region, and surrounds an outer periphery of the temperature sensing diode part. At least a part of one of side walls of the isolation trench is in contact with the power semiconductor element part, and the other side wall of the isolation trench is in contact with the temperature sensing diode part.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: June 28, 2016
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventor: Masahiro Sugimoto
  • Patent number: 9355937
    Abstract: A semiconductor device includes a semiconductor substrate, a first metal layer, a barrier metal layer, and a second metal layer. The semiconductor substrate includes a front surface and a back surface. A semiconductor element and an electrode of the semiconductor element are located on the front surface. An opening in the back surface reaches a lower surface of the electrode, and the opening is defined by a side surface and a bottom surface. The first metal layer covers the side surface and the bottom surface. The barrier metal layer covers the first metal layer in the opening. The second metal layer is in contact with solder in the opening and is closer to the electrode than parts of the barrier metal layer. The second metal layer is laminated on the barrier metal layer and covers at least a part of the barrier metal layer in the opening.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: May 31, 2016
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Hidetoshi Koyama
  • Patent number: 9312408
    Abstract: The disclosure relates to an image sensor comprising a substrate region in a semiconductor material; an active layer in contact with the substrate region; and a photodiode array formed in the active layer. The substrate region has a doping level such that the resistivity of the substrate region is less than 6 mOhm·cm.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: April 12, 2016
    Assignee: STMicroelectronics SA
    Inventor: Didier Dutartre
  • Patent number: 9306005
    Abstract: According to example embodiments, an electronic device includes: a semiconductor layer; a graphene directly contacting a desired (and/or alternatively predetermined) area of the semiconductor layer; and a metal layer on the graphene. The desired (and/or alternatively predetermined) area of the semiconductor layer include one of: a constant doping density, a doping density that is equal to or less than 1019 cm?3, and a depletion width of less than or equal to 3 nm.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: April 5, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-eun Byun, Seong-jun Park, David Seo, Hyun-jae Song, Jae-ho Lee, Hyun-jong Chung, Jin-seong Heo
  • Patent number: 9263599
    Abstract: A semiconductor system having a trench MOS barrier Schottky diode is described, including an n-type epitaxial layer, in which at least two etched trenches are located in a two-dimensional manner of presentation on an n+-type substrate which acts as the cathode zone. An electrically floating, p-type layer, which acts as the anode zone of the p-n type diode, is located in the n-type epitaxial layer, at least in a location below the trench bottom. An oxide layer is located between a metal layer and the surface of the trenches. The n-type epitaxial layer may include two n-type layers of different doping concentrations.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: February 16, 2016
    Assignee: ROBERT BOSCH GMBH
    Inventors: Ning Qu, Alfred Goerlach