Abstract: A method of manufacturing a semiconductor device includes forming a cell chip including a first substrate, a source layer on the first substrate, a stacked structure on the source layer, and a channel layer passing through the stacked structure and coupled to the source layer, flipping the cell chip, exposing a rear surface of the source layer by removing the first substrate from the cell chip, performing surface treatment on the rear surface of the source layer to reduce a resistance of the source layer, forming a peripheral circuit chip including a second substrate and a circuit on the second substrate, and bonding the cell chip including the source layer with a reduced resistance to the peripheral circuit chip.

Abstract: A semiconductor device includes a semiconductor body, a first electrode on a back surface of the semiconductor body, second and third electrodes provided on a front surface of the semiconductor body, a first film linking the second electrode and the third electrode, and a second film between the semiconductor body and the first film. The first film has a higher resistivity than the first semiconductor body, and the second film is insulative. The second film includes a first-film-thickness portion and a second-film-thickness portion. The first-film-thickness portion has a first film thickness along a first direction directed from the first electrode toward the second electrode. The second-film-thickness portion has a second film thickness along the first direction thicker than the first film thickness. The first-film-thickness portion and the second-film-thickness portion surround the second electrode.

Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminals and including a drift region with dopants of a first conductivity type. An active region has at least one power cell extending at least partially into the semiconductor body, is electrically connected with the first load terminal and includes a part of the drift region. Each power cell includes a section of the drift region and is configured to conduct a load current between the terminals and to block a blocking voltage applied between the terminals. A chip edge laterally terminates the semiconductor body. A non-active termination structure arranged in between the chip edge and active region includes an ohmic layer. The ohmic layer is arranged above a surface of the semiconductor body, forms an ohmic connection between electrical potentials of the first and second load terminals, and is laterally structured along the ohmic connection.

Abstract: An electronic device including a substrate, a semiconductor element disposed on the substrate, and a plurality of guard rings at least partially surrounding the semiconductor element, wherein adjacent guard rings are spaced apart by a substantially uniform distance as measured along an entire length of the guard rings, and at least one of the plurality of guard rings has a flared portion. In an embodiment, at least one of the plurality of guard rings electrically floats. In another embodiment, the plurality of guard rings are disposed at least partially below a primary surface of the substrate. In an embodiment, the electronic device is a high voltage MOSFET or an IGBT.

Abstract: A resistive field plate including a spiral resistive element and meander resistive element is provided in an edge termination structure portion. The spiral resistive element is formed in a spiral planar layout, surrounding the periphery of a high-potential-side region to span from the high-potential-side region to a low-potential-side region. A spiral wire of the spiral resistive element includes a conductive film layer and a thin-film resistive layer connected to each other. The meander resistive element has ends positioned in the high-potential-side region and the low-potential-side region, and is provided in a meandering planar layout. The meander resistive element is provided at a same level as that of the thin-film resistive layer, and faces in the depth direction the conductive film layer of the spiral resistive element, sandwiching an interlayer insulating film therebetween. The conductive film layer of the spiral resistive element and the meander resistive element constitute a field plate.

Abstract: A power semiconductor device is disclosed. In one example, the device comprises: a semiconductor body comprising a drift region, the drift region having dopants of a first conductivity type; an active region having at least one power cell; least partially into the semiconductor body; the at least one power cell being configured to conduct a load current between said terminals and to block a blocking voltage applied between said terminals; an edge that laterally terminates the semiconductor body; and a non-active termination structure arranged in between the edge and the active region. The termination structure comprises: at least one doped semiconductor region implemented in the semiconductor body; a conductor structure, and an ohmic path that electrically couples the conductor structure with an electrical potential of the first load terminal.

Abstract: A 3D semiconductor device, including: a first layer including first transistors; a second layer overlying the first transistors and including second transistors; wherein the second layer includes a through layer via with a diameter of less than 150 nm; and a Phase-Lock-Loop (PLL) circuit, where the Phase-Lock-Loop (PLL) circuit is connected to at least one input structure, and where the least one input structure is designed to connect an input to the device from external devices.

Abstract: A power diode is disclosed wherein it is possible to lower on-voltage by expanding a conducting region at an on time. By applying negative voltage to a plate electrode when turning on a power diode, an inversion layer is formed in a front surface layer of an n drift region sandwiched between a p guard ring region and a p anode region, and the p guard ring region and p anode region are connected by the inversion layer, thereby causing one portion or all of the p guard ring region to function as an active region together with the anode region, and expanding an energization region, thus lowering on-voltage.

Abstract: Radio-frequency (RF) switch circuits are disclosed having transistor gate voltage compensation to provide improved switching performance. RF switch circuits include a plurality of field-effect transistors (FETs) connected in series between first and second nodes, each FET having a gate. A compensation network including a coupling circuit couples the gates of each pair of neighboring FETs.

Abstract: Provided is a high voltage semiconductor device. The semiconductor device includes a doped well located in a substrate that is oppositely doped. The semiconductor device includes a dielectric structure located on the doped well. A portion of the doped well adjacent the dielectric structure has a higher doping concentration than a remaining portion of the doped well. The semiconductor device includes an elongate polysilicon structure located on the dielectric structure. The elongate polysilicon structure has a length L. The portion of the doped well adjacent the dielectric structure is electrically coupled to a segment of the elongate polysilicon structure that is located away from a midpoint of the elongate polysilicon structure by a predetermined distance that is measured along the elongate polysilicon structure. The predetermined distance is in a range from about 0*L to about 0.1*L.

Abstract: A semiconductor structure comprising a substrate, an active device, a field oxide layer and a poly-silicon resistor is disclosed. The active device is formed in a surface area of the substrate. The active device has a first doped area, a second doped area and a third doped area. The second doped area is disposed on the first doped area. The first doped area is between the second and the third doped areas. The first doped area has a first type conductivity. The third doped area has a second type conductivity. The first and the second type conductivities are different. The field oxide layer is disposed on a part of the third doped area. The poly-silicon resistor is disposed on the field oxide layer and is electrically connected to the third doped area.

Abstract: A semiconductor includes an N-type impurity region provided in a substrate. A P-type RESURF layer is provided at a top face of the substrate in the N-type impurity region. A P-well has an impurity concentration higher than that of the P-type RESURF layer, and makes contact with the P-type RESURF layer at the top face of the substrate in the N-type impurity region. A first high-voltage-side plate is electrically connected to the N-type impurity region, and a low-voltage-side plate is electrically connected to a P-type impurity region. A lower field plate is capable of generating a lower capacitive coupling with the substrate. An upper field plate is located at a position farther from the substrate than the lower field plate, and is capable of generating an upper capacitive coupling with the lower field plate whose capacitance is greater than the capacitance of the lower capacitive coupling.

Abstract: A semiconductor structure with a high voltage area and a low voltage area includes a substrate of a first conductivity type accommodating the high voltage area and the low voltage area. A resistor is on the substrate, connecting the high voltage area and the low voltage area, and the resistor resides substantially in the high voltage area. The structure further includes a first doped region of the first conductivity type in the substrate between the high voltage area and the low voltage area, and a second doped region of a second conductivity type between the substrate and the first doped region. Moreover, an insulating layer is formed between the resistor and the first doped region.

Abstract: An integrated circuit containing a voltage divider having an upper resistor of unsilicided gate material over field oxide around a central opening and a drift layer under the upper resistor, an input terminal coupled to an input node of the upper resistor adjacent to the central opening in the field oxide and coupled to the drift layer through the central opening, a sense terminal coupled to a sense node on the upper resistor opposite from the input node, a lower resistor with a sense node coupled to the sense terminal and a reference node, and a reference terminal coupled to the reference node. A process of forming the integrated circuit containing the voltage divider.

Abstract: An integrated circuit containing a gate controlled voltage divider having an upper resistor on field oxide in series with a transistor switch in series with a lower resistor. A resistor drift layer is disposed under the upper resistor, and the transistor switch includes a switch drift layer adjacent to the resistor drift layer, separated by a region which prevents breakdown between the drift layers. The switch drift layer provides an extended drain or collector for the transistor switch. A sense terminal of the voltage divider is coupled to a source or emitter node of the transistor and to the lower resistor. An input terminal is coupled to the upper resistor and the resistor drift layer. A process of forming the integrated circuit containing the gate controlled voltage divider.

Abstract: In one general aspect, a semiconductor processing method can include forming an N-type silicon region disposed within a P-type silicon substrate. The method can also include forming a field oxide (FOX) layer in the P-type silicon substrate where the FOX layer includes an opening exposing at least a portion of the N-type silicon region. The method can further include forming a reduced surface field (RESURF) oxide (ROX) layer having a first portion disposed on the exposed N-type silicon region and a second portion disposed on the FOX layer where the ROX layer includes a first dielectric layer in contact with the exposed N-type silicon region and a second dielectric layer disposed on the first dielectric layer. The method can further include forming a doped polysilicon layer having a first portion disposed on the first portion of the ROX layer and a second portion disposed on the second portion of the ROX layer.

Abstract: An improved die seal ring is described which includes at least one break. In the region of the break in the die seal ring, the doping is modified so that the impedance of the electrical path across the break through the substrate is increased. Offsets in the break may also be used and the offset may be within a break in a track and/or between breaks in different tracks, where the die seal ring includes more than one track.

Abstract: Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.

Abstract: A method of forming a non-volatile resistive oxide memory array includes forming a plurality of one of conductive word lines or conductive bit lines over a substrate. Metal oxide-comprising material is formed over the plurality of said one of the word lines or bit lines. A series of elongated trenches is provided over the plurality of said one of the word lines or bit lines. A plurality of self-assembled block copolymer lines is formed within individual of the trenches in registered alignment with and between the trench sidewalls. A plurality of the other of conductive word lines or conductive bit lines is provided from said plurality of self-assembled block copolymer lines to form individually programmable junctions comprising said metal oxide-comprising material where the word lines and bit lines cross one another.

Abstract: A method for fabricating edge termination structures in gallium nitride (GaN) materials includes providing a n-type GaN substrate having a first surface and a second surface, forming an n-type GaN epitaxial layer coupled to the first surface of the n-type GaN substrate, and forming a growth mask coupled to the n-type GaN epitaxial layer. The method further includes patterning the growth mask to expose at least a portion of the n-type GaN epitaxial layer, and forming at least one p-type GaN epitaxial structure coupled to the at least a portion of the n-type GaN epitaxial layer. The at least one p-type GaN epitaxial structure comprises at least one portion of an edge termination structure. The method additionally includes forming a first metal structure electrically coupled to the second surface of the n-type GaN substrate.

Abstract: A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.

Abstract: A semiconductor device includes a semiconductor body including a first surface, an inner region and an edge region, a first doped device region of a first doping type in the inner region and the edge region, a second device region forming a device junction in the inner region with the first device region, and a plurality of at least two dielectric regions extending from the first surface into the semiconductor body. Two dielectric regions that are adjacent in a lateral direction of the semiconductor body are separated by a semiconductor mesa region. The semiconductor device further includes a resistive layer connected to the second device region and connected to at least one semiconductor mesa region.

Abstract: In a semiconductor device in which a first electrode and a second electrode are disposed on a surface of a first conductivity-type semiconductor layer of a semiconductor substrate and a lateral element is formed to cause an electric current between the first electrode and the second electrode, a scroll-shaped resistive field plate is disposed on the semiconductor layer across an insulation film. The resistive field plate extends toward the second electrode while surrounding a periphery of the first electrode in a scroll shape. A resistance value of a total resistance of the resistive field plate is in a range between 90 k? and 90 M?.

Abstract: A method of forming a non-volatile resistive oxide memory array includes forming a plurality of one of conductive word lines or conductive bit lines over a substrate. Metal oxide-comprising material is formed over the plurality of said one of the word lines or bit lines. A series of elongated trenches is provided over the plurality of said one of the word lines or bit lines. A plurality of self-assembled block copolymer lines is formed within individual of the trenches in registered alignment with and between the trench sidewalls. A plurality of the other of conductive word lines or conductive bit lines is provided from said plurality of self-assembled block copolymer lines to form individually programmable junctions comprising said metal oxide-comprising material where the word lines and bit lines cross one another.

Abstract: A Semiconductor component having a space saving edge structure is disclosed. One embodiment provides a first side, a second side, an inner region, an edge region adjoining the inner region in a lateral direction of the semiconductor body, and a first semiconductor layer extending across the inner region and the edge region and having a basic doping of a first conductivity type. At least one active component zone of a second conductivity type, which is complementary to the first conductivity type, is disposed in the inner region in the first semiconductor layer. An edge structure is disposed in the edge region and includes at least one trench extending from the first side into the semiconductor body. An edge electrode is disposed in the trench, a dielectric layer is disposed in the trench between the edge electrode and the semiconductor body, a first edge zone of the second conductivity type adjoin the trench and are at least partially disposed below the trench.

Abstract: A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Insulative material is deposited over the first electrode. An opening is formed into the insulative material over the first electrode. The opening includes sidewalls and a base. The opening sidewalls and base are lined with a multi-resistive state layer comprising multi-resistive state metal oxide-comprising material which less than fills the opening. A second conductive electrode of the memory cell is formed within the opening laterally inward of the multi-resistive state layer lining the sidewalls and elevationally over the multi-resistive state layer lining the base. Other aspects and implementations are contemplated.

Abstract: A semiconductor die has devices such as MOSgated devices, diodes and the like formed into the top and bottom surfaces of the die. One terminal of each of the devices terminal in the interior center of the die and a common contact is made to the interior center of the die at one edge of the die. Various packages for the die having a reduced foot print on a support substrate are disclosed.

Abstract: An integrated circuit resistor is provided that comprises a mesa 14 between electrical contacts 16 and 18. The electrical resistance between electrical contacts 16 and 18 is selectively increased through the formation of recesses 20 and 22 in the mesa 14. The size of recesses 20and 22 can be used to tune the value of the electrical resistance between contacts 16 and 18.

Abstract: A magnetic random access memory structure comprising an anti-ferromagnetic layer structure, a crystalline ferromagnetic structure physically coupled to the anti-ferromagnetic layer structure and a ferromagnetic free layer structure physically coupled to the crystalline ferromagnetic structure.

Abstract: In an embodiment of the invention, an integrated circuit having a cell is provided. The cell may include a field effect transistor structure which includes a gate stack and a resistivity changing material structure disposed above the gate stack, wherein the resistivity changing material structure includes a resistivity changing material which is configured to change its resistivity in response to the application of an electrical voltage to the resistivity changing material structure.

Abstract: A method for fabricating a vertical channel transistor in a semiconductor device includes forming a plurality of pillars arranged in a first direction and a second direction crossing the first direction over a substrate, wherein each of the pillars includes a hard mask pattern thereon, forming a bit line region in the substrate between the pillars, forming a first sidewall insulation layer on a sidewall of each of the pillars, forming an insulation layer for filling a space between the pillars, forming a mask pattern for exposing the substrate between lines of the pillars arranged in the first direction over a resulting structure including the insulation layer, etching the insulation layer and the substrate using the mask pattern as an etch barrier to form a trench for defining a bit line in the substrate, and forming a second sidewall insulation layer over a resulting structure including the trench.

Abstract: A semiconductor component has a semiconductor body (100) having a basic doping and a first and second side, an inner region (103) arranged between the first and second sides, and an edge region (104) adjacent to the inner region in a lateral direction, at least one active component zone (12) which is arranged in the inner region (103) in the region of the first side (101) and is doped complementarily to the basic doping, and a channel stop zone (20), which is arranged in the edge region (104) in the region of the first side (101), is of the same conduction type as the basic doping and is doped more heavily than the basic doping, the doping concentration in the channel stop zone (20) decreasing continuously at least in sections in a lateral direction in the direction of the active component zone (12) at least over a distance (d1) of 10 ?m.

Abstract: A bipolar high voltage/power semiconductor device has a drift region having adjacent its ends regions of different conductivity types respectively. High and low voltage terminals are provided. A first insulated gate terminal and a second insulated gate terminal are also provided. One or more drive circuits provide appropriate voltages to the first and second insulated gate terminals so as to allow current conduction in a first direction or in a second direction that is opposite the first direction.

Abstract: A technique to enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple gate-coupled effect and a PMOSFET triggering source with this technique, low-voltage triggered NMOS fingers have also been developed in power and I/O ESD protection, respectively. A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps.

Abstract: According to one embodiment of the present invention, a CBRAM cell includes a solid electrolyte block having at least three solid electrolyte contacting areas, electrodes electrically connected to the solid electrolyte contacting areas, wherein conductive paths are formable, erasable or detectable within the solid electrolyte block by applying voltages between the solid electrolyte contacting areas using the electrodes as voltage suppliers, and wherein the contacting areas are spatially separated from each other such that conductive paths starting from different solid electrolyte contacting areas or ending at different solid electrolyte contacting areas do not overlap each other.

Abstract: Disclosed are a variety of junction termination structures for high voltage semiconductor power devices. The structures are specifically aimed at providing a high breakdown voltage while being constructed with a minimal number of process steps. The combination of an RIE etch and/or implantation and anneal process with a finely patterned mesh provides the desired radial gradient for maximum breakdown voltage. The structures provide control of both the conductivity and charge density within the region. These structures can beneficially be applied to all high voltage semiconductor device structures, but are of particular interest for wide bandgap devices as they tend to have very high breakdown fields and scaled dimensions of the depletion layer width.

Abstract: A power semiconductor device that includes a plurality of gate structure each having a gate insulation of a first thickness, and a termination region, the termination including a field insulation body surrounding the active region and having a recess that includes a bottom insulation thicker than the first thickness.

Abstract: A manufacturing method of a field effect transistor in which, a patterned gate electrode is provided on a substrate, and a gate insulator is provided on the substrate and the gate electrode, a source electrode and a drain electrode are spaced apart from each other on the gate insulator, a region to be a channel between the source electrode and the drain electrode is provided, a boundary between the region and either one of the source electrode and the drain electrode is linear, a boundary between the region and either one of the drain electrode and the source electrode is non-linear, the boundary has a continuous or discontinuous shape, and the boundary part has a plurality of recess parts, the surface of the region has hydrophilicity and a peripheral region of the region prepares a member having water-repellency, and a solution including semiconductor organic molecules is supplied to the region, and the solution is dried.

Abstract: A semiconductor device which includes a passivation structure formed with a conductive strip of resistive material that crosses itself once around the active region of the device to form a first closed loop, a continuous strip that loops around the first closed loop without crossing itself which crosses itself a second time to form a second closed loop.

Abstract: An insulated gate type semiconductor device comprised of a semiconductor layer serving as an active region isolated from a semiconductor substrate by a substrate isolation insulating film and a T-shaped gate electrode comprised of a trunk-shaped main gate electrode and a crosspiece-shaped conductor pattern provided on the semiconductor layer, wherein the thickness of the gate insulating film directly under the crosspiece-shaped conductor pattern is made greater than the thickness of the gate insulating film directly under the main gate electrode, whereby it is possible to prevent short-circuits between electrodes, prevent short-circuits between separators, and prevent an increase of the parasitic capacitance.

Abstract: A semiconductor device disclosed herein comprises: a first base region which is of a first conductivity type; a second base region which is of a second conductivity type and which is selectively formed on a major surface of the first base region; a stopper region which is of a first conductivity type and which is formed on the major surface of the first base region, the stopper region being a predetermined distance away from the second base region and surrounding the second base region; and a ring region which is of a second conductivity type which is formed on the major surface of the first base region between the second base region and the stopper region, the ring region being spirally around the second base region and electrically connected to the second base region and the stopper region.

Abstract: Magnetic tunnel junction (“MTJ”) element structures and methods for fabricating MTJ element structures are provided. An MTJ element structure may comprise a crystalline pinned layer, an amorphous fixed layer, and a coupling layer disposed between the crystalline pinned layer and the amorphous fixed layer. The amorphous fixed layer is antiferromagnetically coupled to the crystalline pinned layer. The MTJ element further comprises a free layer and a tunnel barrier layer disposed between the amorphous fixed layer and the free layer. Another MTJ element structure may comprise a pinned layer, a fixed layer and a non-magnetic coupling layer disposed therebetween. A tunnel barrier layer is disposed between the fixed layer and a free layer. An interface layer is disposed adjacent the tunnel barrier layer and a layer of amorphous material. The first interface layer comprises a material having a spin polarization that is higher than that of the amorphous material.

Abstract: A semiconductor device with a load resistor is manufactured such that a contact is formed at both ends of the load resistor, and at least one contact is formed between the contacts, in order to prevent impurities from being generated within each contact while the contacts are being generated by etching an insulation layer phenomena of electric charge build up from occurring when an etching process fabricates an insulation layer to generate the contact in a long load resistor located under the insulation layer and insulated electrically and physically.

Abstract: A compound semiconductor device is comprising a compound semiconductor substrate (219) having a ground plane (205); an active element (201) disposed on the substrate; a passive element (211) disposed on the substrate and electrically coupled to the active element; and an insulating layer (202) adjacent the substrate and interposed between the passive device and ground surface such that there is no resistive ground path from the passive device to the ground surface.

Abstract: According to the present invention, there is provided a semiconductor device having, a semiconductor substrate having a surface on which an insulating layer is formed, a first-conductivity-type first semiconductor layer formed on the insulating layer and having a first impurity concentration, a first-conductivity-type second semiconductor region formed in the first semiconductor layer from a surface of the first semiconductor layer to a surface of the insulating layer, and having a concentration higher than the first impurity concentration, a second-conductivity-type third semiconductor region formed in the first semiconductor layer from the surface of the first semiconductor layer to the surface of the insulating layer with a predetermined distance between the second and third semiconductor regions, and having a second impurity concentration, a second-conductivity-type fourth semiconductor region formed in a surface portion of the second semiconductor region, and having a concentration higher than the second

Abstract: A high withstand voltage semiconductor device, comprises: a substrate, a semiconductor layer formed on an upper surface of the substrate, a lateral semiconductor device formed in a surface region of the semiconductor layer and having a first principal electrode in its inner location and a second principal electrode in its outer location so as to let primary current flow between the first and second principal electrodes, a field insulation film formed inside from the second principal electrode in an upper surface of the semiconductor layer to surround the first principal electrode, a resistive field plate formed on an upper surface of the field insulation film to surround the first principal electrode and sectioned in a plurality of circular field plates in an approximate circular arrangement orbiting gradually from the vicinity of the first principal electrode toward the second principal electrode, the innermost one of the circular field plates being electrically connected to the first principal electrode whi

Abstract: A chip resistor comprising a substrate having opposite parallel symmetrical first and second surfaces, a central longitudinal plane of symmetry, separate and spaced first and second resistive layers on the first and second surfaces. The resistive layers are electrically connected in parallel to each other and the first and second surfaces of the substrate are symmetrically located with respect to and equidistant from a central longitudinal plane. Thus, when electrical current passes through the resistive layers, a temperature distribution within the substrate will be substantially symmetrical about the central longitudinal plane of the substrate for eliminating thermal bending thereof. The splitting of the surge current between two resistive layers results in the lower temperature in each resistive layer when compared with the temperature in the single resistive layer of the prior art chip resistor loaded by the same current.

Abstract: A method for controlling silver doping of a chalcogenide glass in a resistance variable memory element is disclosed herein. The method includes forming a thin metal containing layer having a thickness of less than about 250 Angstroms over a second chalcogenide glass layer, formed over a first metal containing layer, formed over a first chalcogenide glass layer. The thin metal containing layer preferably is a silver layer. An electrode may be formed over the thin silver layer. The electrode preferably does not contain silver.

Abstract: An amorphous layer of a cobalt iron-based (CoFe-based) magnetic alloy suitable for use in magnetoelectronic devices is disclosed. In the most preferred embodiments of the present invention, at least one amorphous layer is provided in an MTJ stack to increase the smoothness of the various layers in the MTJ stack while also enhancing the magnetic performance of the resulting device. Additionally, the alloys of the present invention are also useful in cladding applications to provide electrical flux containment for signal lines in magnetoelectronic devices and as a material for fabricating write heads.

Abstract: A high-voltage semiconductor device includes: a drain region; a metal electrode electrically connected to the drain region; and electrically floating plate electrodes formed on a field insulating film over a semiconductor regionm. Parts of the metal electrodes are extended onto the interlevel dielectric film and located over the respective plate electrodes. Each part of the metal electrode is capacitively coupled to associated one of the plate electrodes.