With Means To Increase Breakdown Voltage Threshold Patents (Class 257/487)
  • Patent number: 11891554
    Abstract: A phosphor having a favorable emission peak wavelength, narrow full width at half maximum, and/or high emission intensity is provided. Additionally, a light-emitting device, an illumination device, an image display device, and/or an indicator lamp for a vehicle having favorable color rendering, color reproducibility and/or favorable conversion efficiency are provided. The present invention relates to a phosphor including a crystal phase having a composition represented by a specific formula, and having a minimum reflectance of 20% or more in a specific wavelength region, in which the specific wavelength region is from the emission peak wavelength of the phosphor to 800 nm, and a light-emitting device comprising the phosphor.
    Type: Grant
    Filed: March 29, 2023
    Date of Patent: February 6, 2024
    Assignees: Mitsubishi Chemical Corporation, NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Tomoyuki Kurushima, Yuhei Inata, Naoto Hirosaki
  • Patent number: 11891555
    Abstract: A phosphor having a favorable emission peak wavelength, narrow full width at half maximum, and/or high emission intensity is provided. Additionally, a light-emitting device, an illumination device, an image display device, and/or an indicator lamp for a vehicle having favorable color rendering, color reproducibility and/or favorable conversion efficiency are provided. The present invention relates to a phosphor including a crystal phase having a composition represented by a specific formula, and having a minimum reflectance of 20% or more in a specific wavelength region, in which the specific wavelength region is from the emission peak wavelength of the phosphor to 800 nm, and a light-emitting device comprising the phosphor.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: February 6, 2024
    Assignees: Mitsubishi Chemical Corporation, NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Tomoyuki Kurushima, Yuhei Inata, Naoto Hirosaki
  • Patent number: 11884857
    Abstract: A phosphor having a favorable emission peak wavelength, narrow full width at half maximum, and/or high emission intensity is provided. Additionally, a light-emitting device, an illumination device, an image display device, and/or an indicator lamp for a vehicle having favorable color rendering, color reproducibility and/or favorable conversion efficiency are provided. The present invention relates to a phosphor including a crystal phase having a composition represented by a specific formula, and when, in a powder X-ray diffraction spectrum of the phosphor, the intensity of a peak that appears in a region where 2?=38-39° is designated as Ix and the intensity of a peak that appears in a region where 2?=37-38° is designated as Iy, the relative intensity Ix/Iy of Ix to Iy is 0.140 or less, and a light-emitting device comprising the phosphor.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: January 30, 2024
    Assignees: Mitsubishi Chemical Corporation, National Institute for Materials Science
    Inventors: Tomoyuki Kurushima, Yuhei Inata, Naoto Hirosaki
  • Patent number: 11884856
    Abstract: A phosphor having a favorable emission peak wavelength, narrow full width at half maximum, and/or high emission intensity is provided. Additionally, a light-emitting device, an illumination device, an image display device, and/or an indicator lamp for a vehicle having favorable color rendering, color reproducibility and/or favorable conversion efficiency are provided. The present invention relates to a phosphor including a crystal phase having a composition represented by a specific formula, and when, in a powder X-ray diffraction spectrum of the phosphor, the intensity of a peak that appears in a region where 2?=38-39° is designated as Ix and the intensity of a peak that appears in a region where 2?=37-38° is designated as Iy, the relative intensity Ix/Iy of Ix to Iy is 0.140 or less, and a light-emitting device comprising the phosphor.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: January 30, 2024
    Assignees: Mitsubishi Chemical Corporation, NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Tomoyuki Kurushima, Yuhei Inata, Naoto Hirosaki
  • Patent number: 11670712
    Abstract: A semiconductor device structure can include: (i) a first semiconductor layer having dopants of a first type; (ii) a second semiconductor layer having the dopants of the first type on the first semiconductor layer, where the second semiconductor layer is lightly-doped relative to the first semiconductor layer; (iii) first and second column regions spaced from each other in the second semiconductor layer, where the second column region is arranged between two of the first column regions; and (iv) first and second first sub-column regions laterally arranged in the second column region, where a doping concentration of the first sub-column region decreases in a direction from the first column region to the second sub-column region, and where a doping concentration of the second sub-column region decreases in a direction from the first column region to the first sub-column region.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: June 6, 2023
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventor: Zhongping Liao
  • Patent number: 11557646
    Abstract: Devices, methods and techniques are disclosed to suppress electrical discharge and breakdown in insulating or encapsulation material(s) applied to solid-state devices. In one example aspect, a multi-layer encapsulation film includes a first layer of a first dielectric material and a second layer of a second dielectric material. An interface between the first layer and the second layer is configured to include molecular bonds to prevent charge carriers from crossing between the first layer and the second layer. The multi-layer encapsulation configuration is structured to allow an electrical contact and a substrate of the solid-state device to be at least partially surrounded by the multi-layer encapsulation configuration.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: January 17, 2023
    Assignees: LAWRENCE LIVERMORE NATIONAL SECURITY, LLC, OPCONDYS, INC.
    Inventors: Stephen Sampayan, Kristin Cortella Sampayan
  • Patent number: 11038022
    Abstract: A superjunction power semiconductor device includes a termination region with superjunction structures having higher breakdown voltage than the breakdown voltage of the active cell region. In one embodiment, the termination region includes superjunction structures having lower column charge as compared to the superjunction structures formed in the active cell region. In other embodiments, a superjunction power semiconductor device incorporating superjunction structures with slanted sidewalls where the grading of the superjunction columns in the termination region is reduced as compared to the column grading in the active cell region. The power semiconductor device is made more robust by ensuring any breakdown occurs in the core region as opposed to the termination region. Furthermore, the manufacturing process window for the power semiconductor device is enhanced to improve the manufacturing yield of the power semiconductor device.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: June 15, 2021
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Madhur Bobde, Karthik Padmanabhan, Lingpeng Guan
  • Patent number: 10971632
    Abstract: A semiconductor device may include a Silicon on Insulator (SOI) substrate, and a diode formed on the SOI substrate, the diode including a cathode region and an anode region. The semiconductor device may include at least one breakdown voltage trench disposed at an edge of the cathode region, and between the cathode region and the anode region.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: April 6, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jaroslav Pjencak, Moshe Agam, Johan Camiel Julia Janssens
  • Patent number: 10957803
    Abstract: A bidirectional Zener diode includes a substrate, a first conductivity type base region formed at a front surface portion of the substrate, a second conductivity type first impurity region formed at the base region, a second conductivity type second impurity region formed at the base region away from the first impurity region, an insulating layer formed on a front surface of the substrate, a first electrode film formed on the insulating layer and electrically connected to the first impurity region, and a second electrode film formed on the insulating layer and electrically connected to the second impurity region, and a first region formed on the insulating layer, the first region being sandwiched between the first electrode film and the second electrode film, and the first region including a portion having an aspect ratio of 1 or larger.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: March 23, 2021
    Assignee: ROHM CO., LTD.
    Inventors: Takahiro Arakawa, Junya Yamagami
  • Patent number: 10943899
    Abstract: A semiconductor device includes a guard active area formed in a substrate, a plurality of transistors disposed in an element area adjacent to the guard active area, each of the transistors including an active area and a gate structure crossing the active area, and a diode transistor disposed between a first transistor and a second transistor among the transistors, and having a diode gate structure connected to the guard active area, a first active area connected to a gate structure of the first transistor, and a second active area connected to a gate structure of the second transistor.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: March 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Su Jeong Kim, In Mo Kim
  • Patent number: 10811305
    Abstract: A multi-layer wafer and method of manufacturing such wafer are provided. The method comprises applying a stress compensating oxide layer to each of two heterogeneous wafers, applying at least one bonding oxide layer to at least one of the two heterogeneous wafers, chemical-mechanical polishing the at least one bonding oxide layer, and low temperature bonding the two heterogeneous wafers to form a multi-layer wafer pair. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafers having a stress compensating oxide layer and at least one bonding oxide layer applied to at least one of the two heterogeneous wafers. The two heterogeneous wafers are low temperature bonded together to form the multi-layer wafer.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: October 20, 2020
    Assignee: International Business Machines Corporation
    Inventors: Li-Wen Hung, John U. Knickerbocker, Leathen Shi, Cornelia Tsang Yang, Bucknell C. Webb
  • Patent number: 10720330
    Abstract: A semiconductor device includes: a first-conductivity-type drift layer including a first-conductivity-type impurity, vacancy-oxygen-hydrogen complex defects each caused by a vacancy, an oxygen atom, and a hydrogen atom, divacancy-and-vacancy-phosphorus complex defects, having a trap density level lower than a trap density level of the vacancy-oxygen-hydrogen complex defect, and third complex defects; a plurality of donor layers provided at different depths in a depth direction of the first-conductivity-type drift layer, wherein each of the plurality of donor layers includes donors caused by the vacancy-oxygen-hydrogen complex defects, and each of the plurality of donor layers has an impurity concentration distribution that includes a first portion with a maximum impurity concentration and a second portion with a concentration gradient in which the impurity concentration is reduced from the first portion to both main surfaces of the first-conductivity-type drift layer; and a second-conductivity-type semiconduc
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: July 21, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tomonori Mizushima, Yusuke Kobayashi
  • Patent number: 10707321
    Abstract: A power device, which has a Field Stop (FS) layer based on a semiconductor substrate between a collector region and a drift region in an FS-IGBT structure. The FS layer includes multiple implants for improved functionality of the power device.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: July 7, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Kyu-hyun Lee, Se-kyeong Lee, Doo-seok Yoon, Soo-hyun Kang, Young-chul Choi
  • Patent number: 10658504
    Abstract: A p?-type isolation region is provided at a part between a p-type ground region and a circuit region (a high potential region and an intermediate potential region) in an n-type well region. The p?-type isolation region is electrically connected with a H-VDD pad and an n+-type drain region of a HVNMOS. The p?-type isolation region has between n+-type pickup connect regions and between n+-type drain regions of two of the HVNMOSs, a protruding part (a T-shaped part, an L-shaped part, a partial U-shaped part) or an additional part that protrudes toward a p-ground region.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: May 19, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masaharu Yamaji
  • Patent number: 10566463
    Abstract: In a power semiconductor device of the application a total number n of floating field rings (10_1 to 10_n) formed in a termination area is at least 10. For any integer i in a range from i=2 to i=n, a ring-to-ring separation di,i?i between an i-th floating field ring and a directly adjacent (i?1)-th floating field ring, when counting the floating field rings (10_1 to 10_n) along a straight line starting from a main pn-junction and extending in a lateral direction away from the main pn-junction, is given by the following formula: di,i?1=d1,0+?j=1j=i?1 ?j for i=2 to n, wherein d1,0 is a distance between the innermost floating field ring (10_1) closest to the main pn-junction and the main pn-junction, and wherein: ?zone1?0.05·?zone2<?j<?zone1+0.05·?zone2 for j=1 to I?2, 2·?zone2<|?j|<10·?zone2. for j=I?1, 0.95·?zone2<?j<1.05·?zone2 for j=I to n?1, ?zone2>0.1 ?m, and ??zone2/2<?zone1<?zone2/2, wherein I is an integer, for which 3?l?n/2.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: February 18, 2020
    Assignee: ABB Schweiz
    Inventors: Friedhelm Bauer, Umamaheswara Vemulapati, Marco Bellini
  • Patent number: 10559658
    Abstract: A Schottky barrier diode includes a first semiconductor layer having depressions on a top surface thereof, and having a guard ring extending from the top surface to an inner position of the first semiconductor layer, the guard ring including portions arranged with the depressions interposed therebetween when viewed in a direction perpendicular to the top surface; the diode further includes an insulation layer having portions arranged with the depressions interposed therebetween when viewed in the perpendicular direction, a first metal layer extending as bridging inside and outside of the depressions and the insulation layer, the first metal layer having a first end on the insulation layer, and a second metal layer formed on the first metal layer and having a second end on the insulation layer, the second end being flush with the first end.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: February 11, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Yoshiteru Nagai, Kohei Makita
  • Patent number: 10546836
    Abstract: A multi-layer wafer and method of manufacturing such wafer are provided. The method includes creating under bump metallization (UMB) pads on each of the two heterogeneous wafers; applying a conductive means above the UMB pads on at least one of the two heterogeneous wafers; and low temperature bonding the two heterogeneous wafers to adhere the UMB pads together via the conductive means. At least one stress compensating polymer layer may be applied to at least one of two heterogeneous wafers. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafer having UMB pads and at least one of the heterogeneous wafers having a stress compensating polymer layer and a conductive means applied above the UMB pads on at least one of the two heterogeneous wafers. The two heterogeneous wafers low temperature bonded together to adhere the UMB pads together via the conductive means.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bing Dang, Li-Wen Hung, John U. Knickerbocker, Jae-Woong Nah
  • Patent number: 10381477
    Abstract: A semiconductor device in a semiconductor substrate having a first main surface includes a transistor array and a termination region. The transistor array includes a source region, a drain region, a body region, a drift zone, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel in the body region. The body region and the drift zone are disposed along a first horizontal direction between the source region and the drain region. The transistor array further includes first field plate trenches in the drift zone. A longitudinal axis of the first field plate trenches extends in the first horizontal direction. The semiconductor device further includes a second field plate trench, a longitudinal axis of the second field plate trench extending in a second horizontal direction perpendicular to the first direction.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: August 13, 2019
    Assignee: Infineon Technologies AG
    Inventors: Andreas Peter Meiser, Till Schloesser
  • Patent number: 10256234
    Abstract: A semiconductor device includes a semiconductor substrate provided with an IGBT cell having a collector region and a diode cell having a cathode region, a first defect layer and a second defect layer in a drift region. A region present in the drift region and surrounded by an interface between the IGBT cell and the diode cell orthogonal to a first principal plane, and a plane passing through a boundary between the collector region and the cathode region on a boundary line along an interface between the collector region and the drift region and crossing the first principal plane at an angle of 45 degrees is referred to as a boundary region. The diode cell satisfies a relationship of SD1>S, in which S is an area occupied by the boundary region and SD1 is an area occupied by the diode cell in a surface of the drift region.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: April 9, 2019
    Assignee: DENSO CORPORATION
    Inventors: Hiromitsu Tanabe, Kenji Kouno
  • Patent number: 10242935
    Abstract: A packaged semiconductor device includes a die attached to a die flag of a lead frame wherein the die includes a first, second, third, and fourth minor side, wherein the first and second minor sides are opposite each other and the third and fourth minor sides are opposite each other. The device includes an outer-most lead of the lead frame extending outwardly from the first minor side of the die and closest to the third minor side, wherein the outer-most lead includes a thinned region located between the die and a full thickness portion of the outer-most lead. The device includes an electrical connection between the die and the outer-most lead, and an encapsulant surrounding the die, the electrical connection, and surrounding at least a portion of an outer edge of the thinned portion of the outer-most lead such that the full thickness portion of the outer-most lead extends beyond the encapsulant.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: March 26, 2019
    Assignee: NXP USA, Inc.
    Inventors: Burton Jesse Carpenter, Leo M. Higgins, III
  • Patent number: 10229979
    Abstract: A structure includes a laterally diffused (LD) MOSFET with an n-type drift region disposed on a surface of a substrate and a p-type body region contained in the drift region. The structure further includes an n-type source region contained in the p-type body region; an n-type drain region contained in the n-type drift region; a gate electrode disposed on a gate dielectric overlying a portion of the p-type body region and the n-type drift region and an electrically conductive field shield member disposed within the n-type drift region at least partially beneath the p-type body region and generally parallel to the gate electrode. The electrically conductive buried field shield member is contained within and surrounded by a layer of buried field shield oxide and is common to both a first LD MOSFET and a second LD MOSFET that are connected in parallel. Methods to fabricate the structure are also disclosed.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventor: Tak H. Ning
  • Patent number: 10170333
    Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Fang Cheng, Chen-Chih Wu, Chien-Yuan Lee, Yen-Lin Liu
  • Patent number: 10170568
    Abstract: A structure includes a laterally diffused (LD) MOSFET with an n-type drift region disposed on a surface of a substrate and a p-type body region contained in the drift region. The structure further includes an n-type source region contained in the p-type body region; an n-type drain region contained in the n-type drift region; a gate electrode disposed on a gate dielectric overlying a portion of the p-type body region and the n-type drift region and an electrically conductive field shield member disposed within the n-type drift region at least partially beneath the p-type body region and generally parallel to the gate electrode. The electrically conductive buried field shield member is contained within and surrounded by a layer of buried field shield oxide and is common to both a first LD MOSFET and a second LD MOSFET that are connected in parallel. Methods to fabricate the structure are also disclosed.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventor: Tak H. Ning
  • Patent number: 10109719
    Abstract: In one general aspect, a method of fabricating a power device can include preparing a semiconductor substrate of a first conductivity type, and forming a first Field Stop (FS) layer and a second FS layer.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: October 23, 2018
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Kyu-hyun Lee, Se-kyeong Lee, Doo-seok Yoon, Soo-hyun Kang, Young-chul Choi
  • Patent number: 9972707
    Abstract: A semiconductor device includes a main IGBT region in which an IGBT is provided, a main diode region in which a diode is provided, a sense IGBT region in which an IGBT is provided, and a sense diode region in which a diode is provided. A clearance between the body region and the anode region is longer than a product of electron mobility and electron lifetime in the n-type region between the body region and the anode region. A clearance between an end of the collector region on a sense diode region side and the body region is longer than a product of electron mobility and electron lifetime in the n-type region between the end and the body region.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: May 15, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Keisuke Kimura, Satoru Kameyama
  • Patent number: 9960250
    Abstract: Provided are a power device having an improved field stop layer and a method of manufacturing the same. The method can include performing a first ion implant process by implanting impurity ions of a first conductive type into a front surface of a semiconductor substrate to form an implanted field stop layer where the semiconductor substrate is the first conductive type. The method can include performing a second ion implant process by implanting impurity ions of the first conductive type into a first part of the implanted field stop layer such that an impurity concentration of the first part of the implanted field stop layer is higher than an impurity concentration of a second part of the implanted field stop layer.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: May 1, 2018
    Assignee: Semiconductor Components Industries LLC
    Inventors: Kyu-hyun Lee, Young-chul Kim, Kyeong-seok Park, Bong-yong Lee, Young-chul Choi
  • Patent number: 9954086
    Abstract: A semiconductor device of the present invention is structured such that in a surface layer of a first principal surface of a semiconductor substrate, an n-type drift layer, a p-type base layer, a p-type floating layer, an n-type emitter layer, an emitter electrode, and a trench in which a gate electrode is embedded with a gate insulating film is disposed therebetween are formed from a front surface side. Further, in a surface layer of a second principal surface of the semiconductor substrate, a p-type collector layer and a collector electrode contacting the-type collector layer are formed, and in a direction from the p-type collector layer toward a surface, an n-type selenium-doped field stop layer and an n-type proton doped field stop layer are formed, whereby IGBT turn OFF oscillation, oscillation at diode reverse recovery, and increases in leak voltage can be suppressed, and electrical loss can be reduced.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: April 24, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yuichi Onozawa
  • Patent number: 9911869
    Abstract: A diode comprising a semiconductor body delimited by a front surface and including: a first semiconductor region having a first type of conductivity, facing at least in part the front surface; and a second semiconductor region having a second type of conductivity, the second semiconductor region facing at least in part the front surface and surrounding, at a distance, at least part of the first semiconductor region. The diode further includes: a trench, which extends in the semiconductor body starting from the front surface, for surrounding at least part of the second semiconductor region; and a lateral insulation region, which is arranged within the trench, is formed by dielectric material and contacts at least in part the second semiconductor region.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: March 6, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Marco Sambi, Dario Ripamonti, Davide Ugo Ghisu, Dario Bianchi
  • Patent number: 9825187
    Abstract: A bidirectional Zener diode of the present invention includes a semiconductor substrate of a first conductivity type, a first electrode and a second electrode which are defined on the semiconductor substrate, and a plurality of diffusion regions of a second conductivity type, which are defined at intervals from one another on a surface portion of the semiconductor substrate, to define p-n junctions with the semiconductor substrate, and the plurality of diffusion regions include diode regions which are electrically connected to the first electrode and the second electrode, and pseudo-diode regions which are electrically isolated from the first electrode and the second electrode.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: November 21, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Hiroki Yamamoto
  • Patent number: 9799762
    Abstract: A semiconductor device comprises a transistor formed in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode being adjacent to the channel region. The gate electrode is configured to control a conductivity of a channel formed in the channel region, the channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a first ridge extending along the first direction, and the transistor includes a first field plate arranged adjacent to the drift zone.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: October 24, 2017
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Till Schloesser
  • Patent number: 9768164
    Abstract: A high voltage semiconductor device, particularly a device including a number of high breakdown voltage transistors having a common drain, first well, and insulating structure between the gate and the drain as well as method for using the same is provided in this disclosure. The high breakdown voltage transistors in the device together are in an elliptical shape. A second well region, gate structure, and a source region are partially overlapping discontinuous elliptical rings having at least two discontinuities or openings in a top view. The respective discontinuities or openings define each of the high breakdown voltage transistors.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jam-Wem Lee
  • Patent number: 9711600
    Abstract: In a semiconductor device having a silicon carbide device, a technique capable of suppressing variation in a breakdown voltage and achieving reduction in an area of a termination structure is provided. In order to solve the above-described problem, in the present invention, in a semiconductor device having a silicon carbide device, a p-type first region and a p-type second region provided to be closer to an outer peripheral side than the first region are provided in a junction termination portion, a first concentration gradient is provided in the first region, and a second concentration gradient larger than the first concentration gradient is provided in the second region.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: July 18, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiro Mochizuki, Norifumi Kameshiro
  • Patent number: 9704952
    Abstract: An object is to provide a technique that suppresses decrease in the breakdown voltage of a protective element. There is provided a semiconductor device that comprises a vertical MOS transistor and a protective element. A first nitride semiconductor layer has a convex that is protruded toward a second nitride semiconductor layer. The convex has a top face placed at a position to overlap with at least part of an ohmic electrode of a second conductive type when viewed from a stacking direction of a stacked body. The thickness of the second nitride semiconductor layer in a portion which a bottom face of a trench is in contact with is greater than the thickness of the second nitride semiconductor layer in a portion which the top face of the convex is in contact with.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: July 11, 2017
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Takaki Niwa, Masayoshi Kosaki, Takahiro Fujii, Tohru Oka, Yukihisa Ueno
  • Patent number: 9653620
    Abstract: A semiconductor device including a p or p+ doped portion and an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion. The device further includes an insulating portion provided adjacent the drift portion and at least one of the doped portions in a region where the drift portion and the at least one doped portion meet. The device further includes at least one additional portion, wherein the at least one additional portion is located such that, when the doped portions and the at least one additional portion are biased, the electrical potential lines leave the semiconductor drift portion homogeneously.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: May 16, 2017
    Assignee: X-FAB SEMICONDUCTOR FOUNDRIES AG
    Inventors: Alexander Dietrich Hölke, Deb Kumar Pal, Kia Yaw Kee, Yang Hao
  • Patent number: 9646964
    Abstract: The invention provides a semiconductor device. The semiconductor device includes a buried oxide layer disposed on a substrate. A semiconductor layer having a first conduction type is disposed on the buried oxide layer. A first well doped region having a second conduction type is disposed in the semiconductor layer. A cathode doped region having the second conduction type is disposed in the first well doped region. A first anode doped region having the first conduction type is disposed in the first well doped region, separated from the cathode doped region. A first distance from a bottom boundary of the first anode doped region to a top surface of the semiconductor layer is greater than a second distance from the bottom boundary to an interface between the semiconductor layer and the buried oxide layer.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: May 9, 2017
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Manoj Kumar, Pei-Heng Hung, Hsiung-Shih Chang, Chia-Hao Lee, Jui-Chun Chang
  • Patent number: 9525057
    Abstract: A source region of a MOSFET includes: a source contact region connected to a source pad; a source extension region adjacent to a channel region in a well region; and a source resistance control region arranged between the source extension region and the source contact region. The source resistance control region is different in an impurity concentration from the source extension region and the source contact region. These three regions are connected in series between the source pad and the channel region in the well region.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: December 20, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naruhisa Miura, Shiro Hino, Akihiko Furukawa, Yuji Abe, Shuhei Nakata, Masayuki Imaizumi, Yasuhiro Kagawa
  • Patent number: 9520464
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: December 13, 2016
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Madhur Bobde, Lingpeng Guan, Anup Bhalla, Hamza Yilmaz
  • Patent number: 9520367
    Abstract: A device includes a semiconductor substrate having a surface with a trench, first and second conduction terminals supported by the semiconductor substrate, a control electrode supported by the semiconductor substrate between the first and second conduction terminals and configured to control flow of charge carriers during operation between the first and second conduction terminals, and a Faraday shield supported by the semiconductor substrate and disposed between the control electrode and the second conduction terminal. At least a portion of the Faraday shield is disposed in the trench.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: December 13, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Zihao M. Gao, David C. Burdeaux, Wayne R. Burger, Robert A. Pryor, Philippe Renaud
  • Patent number: 9455328
    Abstract: A low-temperature oxide method is used for manufacturing backside field stop layer of IGBT and first fabricates front elements and front metal layer on a first face of a first conductive type substrate. A multiple-recesses structure is formed on a back side of the first conductive type substrate. Each of the recess in the multiple-recesses structure has first conductive type implanted patterns on exterior sides thereof and the multiple-recesses structure has a first conductive type implanted layer on bottom thereof. A plurality of first conductive type polysilicon layers are deposited into the multiple-recesses structure and respectively corresponding to the first conductive type implanted patterns. A second conductive type impurity layer is formed on the bottom of the first conductive type substrate and laser annealing is conducted to form backside field stop layer for IGBT.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: September 27, 2016
    Assignee: PFC DEVICE HOLDINGS LIMITED
    Inventors: Kuan-Yu Chen, Mei-Ling Chen
  • Patent number: 9385707
    Abstract: A high voltage semiconductor device, particularly a device including a number of high breakdown voltage transistors having a common drain, first well, and insulating structure between the gate and the drain as well as method for using the same is provided in this disclosure. The high breakdown voltage transistors in the device together are in an elliptical shape. A second well region, gate structure, and a source region are partially overlapping discontinuous elliptical rings having at least two discontinuities or openings in a top view. The respective discontinuities or openings define each of the high breakdown voltage transistors.
    Type: Grant
    Filed: January 19, 2015
    Date of Patent: July 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jam-Wem Lee
  • Patent number: 9305913
    Abstract: An ESD protection structure includes a first conductive type substrate; first and second well regions of a first conductive type; a third well region of a second conductive type located between the first and second well regions; a first doped region of the first conductive type and a second doped region of the second conductive type disposed in the first well region; a third doped region of the first conductive type and a fourth doped region of the second conductive type disposed in the second well region; and fifth and sixth doped regions disposed at an interface of the first and third well regions or an interface of the second and third well regions. The fifth doped region of the first conductive type is located in the first or second well region, and the sixth doped region of the second conductive type is located in the third well region.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: April 5, 2016
    Assignee: Episil Technologies Inc.
    Inventors: Jing-Sheng Deng, Te-Kun Liu
  • Patent number: 9231050
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: January 5, 2016
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Madhur Bobde, Lingping Guan, Anup Bhalla, Hamza Yilmaz
  • Patent number: 9219060
    Abstract: According to one embodiment, a semiconductor device includes first, second, and third electrodes, first, second, third, fourth, fifth, sixth, and seventh semiconductor regions. The first semiconductor region is provided between the first and second electrodes. The second semiconductor region is provided between the first electrode and the first semiconductor region. The third and fourth semiconductor regions are provided between the first electrode and the second semiconductor region. The fifth semiconductor region is positioned between the third semiconductor region and the second electrode, and is provided between the first semiconductor region and the second electrode. The sixth semiconductor region is positioned between the fourth semiconductor region and the second electrode, and is provided between the first semiconductor region and the second electrode. The seventh semiconductor region is provided between the fifth semiconductor region and the second electrode.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: December 22, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tsuneo Ogura
  • Patent number: 9202910
    Abstract: A lateral power semiconductor device includes a semiconductor body having a first surface and a second opposite surface, a first main electrode, a second main electrode, a plurality of switchable semiconductor cells and at least one curved semiconductor portion. The first main electrode includes at least two sections and is arranged on the first surface. The second main electrode is arranged on the first surface and between the two sections of the first main electrode. The plurality of switchable semiconductor cells is arranged between a respective one of the two sections of the first main electrode and the second main electrode and is configured to provide a controllable conductive path between the first main electrode and the second main electrode. The curved semiconductor portion is between the first main electrode and the second main electrode and has increasing doping concentration from the first main electrode to the second main electrode.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: December 1, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Norbert Thyssen, Rolf Weis
  • Patent number: 9165921
    Abstract: One embodiment of a semiconductor device includes a dense trench transistor cell array. The dense trench transistor cell array includes a plurality of transistor cells in a semiconductor body. A width w3 of a transistor mesa region of each of the plurality of transistor cells and a width w1 of a first trench of each of the plurality of transistor cells satisfy the following relationship: w3<1.5×w1. The semiconductor device further includes semiconductor diodes. At least one of the semiconductor diodes is arranged between first and second parts of the plurality of transistor cells and includes a diode mesa region adjoining opposing walls of second trenches. A depth d1 of the first trench and a depth d2 of the second trenches differ by at least 20%.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: October 20, 2015
    Assignee: Infineon Technology AG
    Inventors: Peter Nelle, Markus Zundel
  • Patent number: 9136362
    Abstract: A semiconductor device with a lateral element includes a semiconductor substrate, first and second electrodes on the substrate, and a resistive field plate extending from the first electrode to the second electrode. The lateral element passes a current between the first and second electrodes. A voltage applied to the second electrode is less than a voltage applied to the first electrode. The resistive field plate has a first end portion and a second end portion opposite to the first end portion. The second end portion is located closer to the second electrode than the first end portion. An impurity concentration in the second end portion is equal to or greater than 1×1018 cm?3.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 15, 2015
    Assignee: DENSO CORPORATION
    Inventors: Takeshi Sakai, Akira Yamada, Shigeki Takahashi, Youichi Ashida, Satoshi Shiraki
  • Patent number: 9117901
    Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a substrate, having an isolation structure for defining a device region; a drift region located in the device region, wherein from top view, the drift region includes multiple sub-regions separated from one another but are electrically connected with one another; a source and a drain in the device region; and a gate on the surface of the substrate and between the source and drain in the device region.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: August 25, 2015
    Assignee: RICHTEK TECHNOLOGY CORPORATION, R.O.C.
    Inventors: Tsung-Yi Huang, Chien-Hao Huang
  • Patent number: 9035415
    Abstract: A technology for a vertical semiconductor device having a RESURF structure, which is capable of preventing the drop of the withstand voltage when the adhesion of external electric charges occurs is provided. The vertical semiconductor device disclosed in the present specification has a cell region and a non-cell region disposed outside the cell region. This vertical semiconductor device has a diffusion layer disposed in at least part of the non-cell region. When the vertical semiconductor device is viewed in a plane, the diffusion layer has an impurity surface density higher than that satisfying a RESURF condition at an end part close to the cell region, and an impurity surface density lower than that satisfying the RESURF condition at an end part far from the cell region.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: May 19, 2015
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Masaru Senoo
  • Patent number: 9035434
    Abstract: A semiconductor device having first and second portions with opposite conductivity types. There are first through fourth layers in the semiconductor device. A peak value of the impurity concentration of the fourth layer is higher than the peak value of the impurity concentration of the second layer and lower than the peak value of the impurity concentration of a first portion of the third layer. The fourth layer includes a third portion located on the first portion and a fourth portion which is located on the second portion. The semiconductor device allows a decrease in the forward voltage drop and also allows an improvement of the safe operating area tolerance. Thus, it is possible to decrease the forward voltage drop, improve the maximum reverse voltage, and suppress oscillations at the time of recovery.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: May 19, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Nakamura
  • Patent number: 9035379
    Abstract: A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ker Hsiao Huo, Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng