With Means To Increase Breakdown Voltage Threshold Patents (Class 257/487)
  • Patent number: 10381477
    Abstract: A semiconductor device in a semiconductor substrate having a first main surface includes a transistor array and a termination region. The transistor array includes a source region, a drain region, a body region, a drift zone, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel in the body region. The body region and the drift zone are disposed along a first horizontal direction between the source region and the drain region. The transistor array further includes first field plate trenches in the drift zone. A longitudinal axis of the first field plate trenches extends in the first horizontal direction. The semiconductor device further includes a second field plate trench, a longitudinal axis of the second field plate trench extending in a second horizontal direction perpendicular to the first direction.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: August 13, 2019
    Assignee: Infineon Technologies AG
    Inventors: Andreas Peter Meiser, Till Schloesser
  • Patent number: 10256234
    Abstract: A semiconductor device includes a semiconductor substrate provided with an IGBT cell having a collector region and a diode cell having a cathode region, a first defect layer and a second defect layer in a drift region. A region present in the drift region and surrounded by an interface between the IGBT cell and the diode cell orthogonal to a first principal plane, and a plane passing through a boundary between the collector region and the cathode region on a boundary line along an interface between the collector region and the drift region and crossing the first principal plane at an angle of 45 degrees is referred to as a boundary region. The diode cell satisfies a relationship of SD1>S, in which S is an area occupied by the boundary region and SD1 is an area occupied by the diode cell in a surface of the drift region.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: April 9, 2019
    Assignee: DENSO CORPORATION
    Inventors: Hiromitsu Tanabe, Kenji Kouno
  • Patent number: 10242935
    Abstract: A packaged semiconductor device includes a die attached to a die flag of a lead frame wherein the die includes a first, second, third, and fourth minor side, wherein the first and second minor sides are opposite each other and the third and fourth minor sides are opposite each other. The device includes an outer-most lead of the lead frame extending outwardly from the first minor side of the die and closest to the third minor side, wherein the outer-most lead includes a thinned region located between the die and a full thickness portion of the outer-most lead. The device includes an electrical connection between the die and the outer-most lead, and an encapsulant surrounding the die, the electrical connection, and surrounding at least a portion of an outer edge of the thinned portion of the outer-most lead such that the full thickness portion of the outer-most lead extends beyond the encapsulant.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: March 26, 2019
    Assignee: NXP USA, Inc.
    Inventors: Burton Jesse Carpenter, Leo M. Higgins, III
  • Patent number: 10229979
    Abstract: A structure includes a laterally diffused (LD) MOSFET with an n-type drift region disposed on a surface of a substrate and a p-type body region contained in the drift region. The structure further includes an n-type source region contained in the p-type body region; an n-type drain region contained in the n-type drift region; a gate electrode disposed on a gate dielectric overlying a portion of the p-type body region and the n-type drift region and an electrically conductive field shield member disposed within the n-type drift region at least partially beneath the p-type body region and generally parallel to the gate electrode. The electrically conductive buried field shield member is contained within and surrounded by a layer of buried field shield oxide and is common to both a first LD MOSFET and a second LD MOSFET that are connected in parallel. Methods to fabricate the structure are also disclosed.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventor: Tak H. Ning
  • Patent number: 10170568
    Abstract: A structure includes a laterally diffused (LD) MOSFET with an n-type drift region disposed on a surface of a substrate and a p-type body region contained in the drift region. The structure further includes an n-type source region contained in the p-type body region; an n-type drain region contained in the n-type drift region; a gate electrode disposed on a gate dielectric overlying a portion of the p-type body region and the n-type drift region and an electrically conductive field shield member disposed within the n-type drift region at least partially beneath the p-type body region and generally parallel to the gate electrode. The electrically conductive buried field shield member is contained within and surrounded by a layer of buried field shield oxide and is common to both a first LD MOSFET and a second LD MOSFET that are connected in parallel. Methods to fabricate the structure are also disclosed.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventor: Tak H. Ning
  • Patent number: 10170333
    Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Fang Cheng, Chen-Chih Wu, Chien-Yuan Lee, Yen-Lin Liu
  • Patent number: 10109719
    Abstract: In one general aspect, a method of fabricating a power device can include preparing a semiconductor substrate of a first conductivity type, and forming a first Field Stop (FS) layer and a second FS layer.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: October 23, 2018
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Kyu-hyun Lee, Se-kyeong Lee, Doo-seok Yoon, Soo-hyun Kang, Young-chul Choi
  • Patent number: 9972707
    Abstract: A semiconductor device includes a main IGBT region in which an IGBT is provided, a main diode region in which a diode is provided, a sense IGBT region in which an IGBT is provided, and a sense diode region in which a diode is provided. A clearance between the body region and the anode region is longer than a product of electron mobility and electron lifetime in the n-type region between the body region and the anode region. A clearance between an end of the collector region on a sense diode region side and the body region is longer than a product of electron mobility and electron lifetime in the n-type region between the end and the body region.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: May 15, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Keisuke Kimura, Satoru Kameyama
  • Patent number: 9960250
    Abstract: Provided are a power device having an improved field stop layer and a method of manufacturing the same. The method can include performing a first ion implant process by implanting impurity ions of a first conductive type into a front surface of a semiconductor substrate to form an implanted field stop layer where the semiconductor substrate is the first conductive type. The method can include performing a second ion implant process by implanting impurity ions of the first conductive type into a first part of the implanted field stop layer such that an impurity concentration of the first part of the implanted field stop layer is higher than an impurity concentration of a second part of the implanted field stop layer.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: May 1, 2018
    Assignee: Semiconductor Components Industries LLC
    Inventors: Kyu-hyun Lee, Young-chul Kim, Kyeong-seok Park, Bong-yong Lee, Young-chul Choi
  • Patent number: 9954086
    Abstract: A semiconductor device of the present invention is structured such that in a surface layer of a first principal surface of a semiconductor substrate, an n-type drift layer, a p-type base layer, a p-type floating layer, an n-type emitter layer, an emitter electrode, and a trench in which a gate electrode is embedded with a gate insulating film is disposed therebetween are formed from a front surface side. Further, in a surface layer of a second principal surface of the semiconductor substrate, a p-type collector layer and a collector electrode contacting the-type collector layer are formed, and in a direction from the p-type collector layer toward a surface, an n-type selenium-doped field stop layer and an n-type proton doped field stop layer are formed, whereby IGBT turn OFF oscillation, oscillation at diode reverse recovery, and increases in leak voltage can be suppressed, and electrical loss can be reduced.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: April 24, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yuichi Onozawa
  • Patent number: 9911869
    Abstract: A diode comprising a semiconductor body delimited by a front surface and including: a first semiconductor region having a first type of conductivity, facing at least in part the front surface; and a second semiconductor region having a second type of conductivity, the second semiconductor region facing at least in part the front surface and surrounding, at a distance, at least part of the first semiconductor region. The diode further includes: a trench, which extends in the semiconductor body starting from the front surface, for surrounding at least part of the second semiconductor region; and a lateral insulation region, which is arranged within the trench, is formed by dielectric material and contacts at least in part the second semiconductor region.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: March 6, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Marco Sambi, Dario Ripamonti, Davide Ugo Ghisu, Dario Bianchi
  • Patent number: 9825187
    Abstract: A bidirectional Zener diode of the present invention includes a semiconductor substrate of a first conductivity type, a first electrode and a second electrode which are defined on the semiconductor substrate, and a plurality of diffusion regions of a second conductivity type, which are defined at intervals from one another on a surface portion of the semiconductor substrate, to define p-n junctions with the semiconductor substrate, and the plurality of diffusion regions include diode regions which are electrically connected to the first electrode and the second electrode, and pseudo-diode regions which are electrically isolated from the first electrode and the second electrode.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: November 21, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Hiroki Yamamoto
  • Patent number: 9799762
    Abstract: A semiconductor device comprises a transistor formed in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode being adjacent to the channel region. The gate electrode is configured to control a conductivity of a channel formed in the channel region, the channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a first ridge extending along the first direction, and the transistor includes a first field plate arranged adjacent to the drift zone.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: October 24, 2017
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Till Schloesser
  • Patent number: 9768164
    Abstract: A high voltage semiconductor device, particularly a device including a number of high breakdown voltage transistors having a common drain, first well, and insulating structure between the gate and the drain as well as method for using the same is provided in this disclosure. The high breakdown voltage transistors in the device together are in an elliptical shape. A second well region, gate structure, and a source region are partially overlapping discontinuous elliptical rings having at least two discontinuities or openings in a top view. The respective discontinuities or openings define each of the high breakdown voltage transistors.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jam-Wem Lee
  • Patent number: 9711600
    Abstract: In a semiconductor device having a silicon carbide device, a technique capable of suppressing variation in a breakdown voltage and achieving reduction in an area of a termination structure is provided. In order to solve the above-described problem, in the present invention, in a semiconductor device having a silicon carbide device, a p-type first region and a p-type second region provided to be closer to an outer peripheral side than the first region are provided in a junction termination portion, a first concentration gradient is provided in the first region, and a second concentration gradient larger than the first concentration gradient is provided in the second region.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: July 18, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiro Mochizuki, Norifumi Kameshiro
  • Patent number: 9704952
    Abstract: An object is to provide a technique that suppresses decrease in the breakdown voltage of a protective element. There is provided a semiconductor device that comprises a vertical MOS transistor and a protective element. A first nitride semiconductor layer has a convex that is protruded toward a second nitride semiconductor layer. The convex has a top face placed at a position to overlap with at least part of an ohmic electrode of a second conductive type when viewed from a stacking direction of a stacked body. The thickness of the second nitride semiconductor layer in a portion which a bottom face of a trench is in contact with is greater than the thickness of the second nitride semiconductor layer in a portion which the top face of the convex is in contact with.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: July 11, 2017
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Takaki Niwa, Masayoshi Kosaki, Takahiro Fujii, Tohru Oka, Yukihisa Ueno
  • Patent number: 9653620
    Abstract: A semiconductor device including a p or p+ doped portion and an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion. The device further includes an insulating portion provided adjacent the drift portion and at least one of the doped portions in a region where the drift portion and the at least one doped portion meet. The device further includes at least one additional portion, wherein the at least one additional portion is located such that, when the doped portions and the at least one additional portion are biased, the electrical potential lines leave the semiconductor drift portion homogeneously.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: May 16, 2017
    Assignee: X-FAB SEMICONDUCTOR FOUNDRIES AG
    Inventors: Alexander Dietrich Hölke, Deb Kumar Pal, Kia Yaw Kee, Yang Hao
  • Patent number: 9646964
    Abstract: The invention provides a semiconductor device. The semiconductor device includes a buried oxide layer disposed on a substrate. A semiconductor layer having a first conduction type is disposed on the buried oxide layer. A first well doped region having a second conduction type is disposed in the semiconductor layer. A cathode doped region having the second conduction type is disposed in the first well doped region. A first anode doped region having the first conduction type is disposed in the first well doped region, separated from the cathode doped region. A first distance from a bottom boundary of the first anode doped region to a top surface of the semiconductor layer is greater than a second distance from the bottom boundary to an interface between the semiconductor layer and the buried oxide layer.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: May 9, 2017
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Manoj Kumar, Pei-Heng Hung, Hsiung-Shih Chang, Chia-Hao Lee, Jui-Chun Chang
  • Patent number: 9525057
    Abstract: A source region of a MOSFET includes: a source contact region connected to a source pad; a source extension region adjacent to a channel region in a well region; and a source resistance control region arranged between the source extension region and the source contact region. The source resistance control region is different in an impurity concentration from the source extension region and the source contact region. These three regions are connected in series between the source pad and the channel region in the well region.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: December 20, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naruhisa Miura, Shiro Hino, Akihiko Furukawa, Yuji Abe, Shuhei Nakata, Masayuki Imaizumi, Yasuhiro Kagawa
  • Patent number: 9520464
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: December 13, 2016
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Madhur Bobde, Lingpeng Guan, Anup Bhalla, Hamza Yilmaz
  • Patent number: 9520367
    Abstract: A device includes a semiconductor substrate having a surface with a trench, first and second conduction terminals supported by the semiconductor substrate, a control electrode supported by the semiconductor substrate between the first and second conduction terminals and configured to control flow of charge carriers during operation between the first and second conduction terminals, and a Faraday shield supported by the semiconductor substrate and disposed between the control electrode and the second conduction terminal. At least a portion of the Faraday shield is disposed in the trench.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: December 13, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Zihao M. Gao, David C. Burdeaux, Wayne R. Burger, Robert A. Pryor, Philippe Renaud
  • Patent number: 9455328
    Abstract: A low-temperature oxide method is used for manufacturing backside field stop layer of IGBT and first fabricates front elements and front metal layer on a first face of a first conductive type substrate. A multiple-recesses structure is formed on a back side of the first conductive type substrate. Each of the recess in the multiple-recesses structure has first conductive type implanted patterns on exterior sides thereof and the multiple-recesses structure has a first conductive type implanted layer on bottom thereof. A plurality of first conductive type polysilicon layers are deposited into the multiple-recesses structure and respectively corresponding to the first conductive type implanted patterns. A second conductive type impurity layer is formed on the bottom of the first conductive type substrate and laser annealing is conducted to form backside field stop layer for IGBT.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: September 27, 2016
    Assignee: PFC DEVICE HOLDINGS LIMITED
    Inventors: Kuan-Yu Chen, Mei-Ling Chen
  • Patent number: 9385707
    Abstract: A high voltage semiconductor device, particularly a device including a number of high breakdown voltage transistors having a common drain, first well, and insulating structure between the gate and the drain as well as method for using the same is provided in this disclosure. The high breakdown voltage transistors in the device together are in an elliptical shape. A second well region, gate structure, and a source region are partially overlapping discontinuous elliptical rings having at least two discontinuities or openings in a top view. The respective discontinuities or openings define each of the high breakdown voltage transistors.
    Type: Grant
    Filed: January 19, 2015
    Date of Patent: July 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jam-Wem Lee
  • Patent number: 9305913
    Abstract: An ESD protection structure includes a first conductive type substrate; first and second well regions of a first conductive type; a third well region of a second conductive type located between the first and second well regions; a first doped region of the first conductive type and a second doped region of the second conductive type disposed in the first well region; a third doped region of the first conductive type and a fourth doped region of the second conductive type disposed in the second well region; and fifth and sixth doped regions disposed at an interface of the first and third well regions or an interface of the second and third well regions. The fifth doped region of the first conductive type is located in the first or second well region, and the sixth doped region of the second conductive type is located in the third well region.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: April 5, 2016
    Assignee: Episil Technologies Inc.
    Inventors: Jing-Sheng Deng, Te-Kun Liu
  • Patent number: 9231050
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: January 5, 2016
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Madhur Bobde, Lingping Guan, Anup Bhalla, Hamza Yilmaz
  • Patent number: 9219060
    Abstract: According to one embodiment, a semiconductor device includes first, second, and third electrodes, first, second, third, fourth, fifth, sixth, and seventh semiconductor regions. The first semiconductor region is provided between the first and second electrodes. The second semiconductor region is provided between the first electrode and the first semiconductor region. The third and fourth semiconductor regions are provided between the first electrode and the second semiconductor region. The fifth semiconductor region is positioned between the third semiconductor region and the second electrode, and is provided between the first semiconductor region and the second electrode. The sixth semiconductor region is positioned between the fourth semiconductor region and the second electrode, and is provided between the first semiconductor region and the second electrode. The seventh semiconductor region is provided between the fifth semiconductor region and the second electrode.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: December 22, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tsuneo Ogura
  • Patent number: 9202910
    Abstract: A lateral power semiconductor device includes a semiconductor body having a first surface and a second opposite surface, a first main electrode, a second main electrode, a plurality of switchable semiconductor cells and at least one curved semiconductor portion. The first main electrode includes at least two sections and is arranged on the first surface. The second main electrode is arranged on the first surface and between the two sections of the first main electrode. The plurality of switchable semiconductor cells is arranged between a respective one of the two sections of the first main electrode and the second main electrode and is configured to provide a controllable conductive path between the first main electrode and the second main electrode. The curved semiconductor portion is between the first main electrode and the second main electrode and has increasing doping concentration from the first main electrode to the second main electrode.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: December 1, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Norbert Thyssen, Rolf Weis
  • Patent number: 9165921
    Abstract: One embodiment of a semiconductor device includes a dense trench transistor cell array. The dense trench transistor cell array includes a plurality of transistor cells in a semiconductor body. A width w3 of a transistor mesa region of each of the plurality of transistor cells and a width w1 of a first trench of each of the plurality of transistor cells satisfy the following relationship: w3<1.5×w1. The semiconductor device further includes semiconductor diodes. At least one of the semiconductor diodes is arranged between first and second parts of the plurality of transistor cells and includes a diode mesa region adjoining opposing walls of second trenches. A depth d1 of the first trench and a depth d2 of the second trenches differ by at least 20%.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: October 20, 2015
    Assignee: Infineon Technology AG
    Inventors: Peter Nelle, Markus Zundel
  • Patent number: 9136362
    Abstract: A semiconductor device with a lateral element includes a semiconductor substrate, first and second electrodes on the substrate, and a resistive field plate extending from the first electrode to the second electrode. The lateral element passes a current between the first and second electrodes. A voltage applied to the second electrode is less than a voltage applied to the first electrode. The resistive field plate has a first end portion and a second end portion opposite to the first end portion. The second end portion is located closer to the second electrode than the first end portion. An impurity concentration in the second end portion is equal to or greater than 1×1018 cm?3.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 15, 2015
    Assignee: DENSO CORPORATION
    Inventors: Takeshi Sakai, Akira Yamada, Shigeki Takahashi, Youichi Ashida, Satoshi Shiraki
  • Patent number: 9117901
    Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a substrate, having an isolation structure for defining a device region; a drift region located in the device region, wherein from top view, the drift region includes multiple sub-regions separated from one another but are electrically connected with one another; a source and a drain in the device region; and a gate on the surface of the substrate and between the source and drain in the device region.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: August 25, 2015
    Assignee: RICHTEK TECHNOLOGY CORPORATION, R.O.C.
    Inventors: Tsung-Yi Huang, Chien-Hao Huang
  • Patent number: 9035415
    Abstract: A technology for a vertical semiconductor device having a RESURF structure, which is capable of preventing the drop of the withstand voltage when the adhesion of external electric charges occurs is provided. The vertical semiconductor device disclosed in the present specification has a cell region and a non-cell region disposed outside the cell region. This vertical semiconductor device has a diffusion layer disposed in at least part of the non-cell region. When the vertical semiconductor device is viewed in a plane, the diffusion layer has an impurity surface density higher than that satisfying a RESURF condition at an end part close to the cell region, and an impurity surface density lower than that satisfying the RESURF condition at an end part far from the cell region.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: May 19, 2015
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Masaru Senoo
  • Patent number: 9035378
    Abstract: A trench power MOSFET structure and fabrication method thereof is provided. The fabrication method comprises following process. First, form an isolating trench. Then, form at least two doped regions around the isolating trench. The doped regions are adjacent and the doping concentrations of two doped regions are different. Form an isolating structure in the isolating trench. Wherein, the junction profiles of the two doped regions are made by on implantation method for moderate the electric field distribution and decreasing the conduction loss.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: May 19, 2015
    Assignee: SUPER GROUP SEMICONDUCTOR CO., LTD.
    Inventors: Hsiu-Wen Hsu, Chun-Ying Yeh, Yuan-Ming Lee
  • Patent number: 9034717
    Abstract: Methods for forming a layer of semiconductor material and a semiconductor-on-insulator structure are provided. A substrate including one or more devices or features formed therein is provided. A seed layer is bonded to the substrate, where the seed layer includes a crystalline semiconductor structure. A first portion of the seed layer that is adjacent to an interface between the seed layer and the substrate is amorphized. A second portion of the seed layer that is not adjacent to the interface is not amorphized and maintains the crystalline semiconductor structure. Dopant implantation is performed to form an N-type conductivity region or a P-type conductivity region in the first portion of the seed layer. A solid-phase epitaxial growth process is performed to crystallize the first portion of the seed layer. The SPE growth process uses the crystalline semiconductor structure of the second portion of the seed layer as a crystal template.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Jean-Pierre Colinge
  • Patent number: 9035379
    Abstract: A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ker Hsiao Huo, Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng
  • Patent number: 9035434
    Abstract: A semiconductor device having first and second portions with opposite conductivity types. There are first through fourth layers in the semiconductor device. A peak value of the impurity concentration of the fourth layer is higher than the peak value of the impurity concentration of the second layer and lower than the peak value of the impurity concentration of a first portion of the third layer. The fourth layer includes a third portion located on the first portion and a fourth portion which is located on the second portion. The semiconductor device allows a decrease in the forward voltage drop and also allows an improvement of the safe operating area tolerance. Thus, it is possible to decrease the forward voltage drop, improve the maximum reverse voltage, and suppress oscillations at the time of recovery.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: May 19, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Nakamura
  • Publication number: 20150123236
    Abstract: An embodiment of a diode includes a semiconductor substrate, a first contact region having a first conductivity type, a second contact region laterally spaced from the first contact region, and having a second conductivity type, an intermediate region disposed in the semiconductor substrate between the first and second contact regions, electrically connected with the first contact region, and having the first conductivity type, and a buried region disposed in the semiconductor substrate, having the second conductivity type, and electrically connected with the second contact region. The buried region extends laterally across the first contact region and the intermediate region to establish first and second junctions, respectively. The first junction has a lower breakdown voltage than the second junction.
    Type: Application
    Filed: November 5, 2013
    Publication date: May 7, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Xin Lin, Hongning Yang, Jiang-Kai Zuo
  • Publication number: 20150115390
    Abstract: A transient voltage suppressor and its manufacturing method are provided, which can easily control voltage withstanding characteristics of a Zener diode by analogizing growth of a buried layer by forming a portion of the buried layer by performing ion implantation on a first epitaxial layer and then forming the other portion of the buried layer while depositing a second epitaxial layer having the same impurity concentration with the first epitaxial layer, and which can improve a current distribution characteristic by forming a doping region in a ring shape to increase a current pass region by increasing a PN junction area of a Zener diode in a small area.
    Type: Application
    Filed: October 1, 2014
    Publication date: April 30, 2015
    Inventors: Hyun Sik Kim, Hee Won Jang
  • Publication number: 20150091104
    Abstract: The invention provides a semiconductor structure and a semiconductor device having such semiconductor structure. The semiconductor structure includes: a substrate; a first well having a first conductivity type, which is provided on the substrate; a second well having a second conductivity type and contacting the first well at a boundary in between in a lateral direction; and a plurality of mitigation regions having the first conductivity type or the second conductivity type, provided in the first well and being close to the boundary in a lateral direction and penetrating the first well in a vertical direction.
    Type: Application
    Filed: September 30, 2013
    Publication date: April 2, 2015
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Tsung-Yi Huang
  • Patent number: 8994141
    Abstract: A semiconductor includes an N-type impurity region provided in a substrate. A P-type RESURF layer is provided at a top face of the substrate in the N-type impurity region. A P-well has an impurity concentration higher than that of the P-type RESURF layer, and makes contact with the P-type RESURF layer at the top face of the substrate in the N-type impurity region. A first high-voltage-side plate is electrically connected to the N-type impurity region, and a low-voltage-side plate is electrically connected to a P-type impurity region. A lower field plate is capable of generating a lower capacitive coupling with the substrate. An upper field plate is located at a position farther from the substrate than the lower field plate, and is capable of generating an upper capacitive coupling with the lower field plate whose capacitance is greater than the capacitance of the lower capacitive coupling.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: March 31, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Takahashi, Takami Otsuki
  • Publication number: 20150076652
    Abstract: There is provided a power semiconductor device, including: a first semiconductor layer of a first conductive type having a thickness of t1 so as to withstand a reverse voltage of 600V; and a second semiconductor layer of a second conductive type formed inside an upper portion of the first semiconductor layer and having a thickness of t2, wherein t1/t2 is 15 to 18.
    Type: Application
    Filed: December 9, 2013
    Publication date: March 19, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Chang Su JANG, Kee Ju UM, In Hyuk SONG, Jaehoon PARK, Dong Soo SEO
  • Patent number: 8969928
    Abstract: Transistors having a dielectric over a semiconductor, a control gate over the dielectric at a particular level, and one or more conductive structures over the dielectric at the particular level facilitate control of device characteristics of the transistor. The one or more conductive structures are between the control gate and at least one source/drain region of the transistor. The one or more conductive structures are electrically isolated from the control gate.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: March 3, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Mike Smith, Henry Jim Fulford
  • Publication number: 20150054117
    Abstract: Semiconductor devices with guard rings are described. The semiconductor devices may be, e.g., transistors and diodes designed for high-voltage applications. A guard ring is a floating electrode formed of electrically conducting material above a semiconductor material layer. A portion of an insulating layer is between at least a portion of the guard ring and the semiconductor material layer. A guard ring may be located, for example, on a transistor between a gate and a drain electrode. A semiconductor device may have one or more guard rings.
    Type: Application
    Filed: October 31, 2014
    Publication date: February 26, 2015
    Inventors: Umesh Mishra, Srabanti Chowdhury, Yuvaraj Dora
  • Patent number: 8946817
    Abstract: A semiconductor device includes a semiconductor body including an inner region, and an edge region, a first doped device region of a first doping type in the inner region and the edge region and coupled to a first terminal, and at least one second doped device region of a second doping type complementary to the first doping type in the inner region and coupled to a second terminal. Further, the semiconductor device includes a minority carrier converter structure in the edge region. The minority carrier converter structure includes a first trap region of the second doping type adjoining the first doped device region, and a conductor electrically coupling the first trap region to the first doped device region.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: February 3, 2015
    Assignee: Infineon Technologies Austria AG
    Inventor: Franz Hirler
  • Publication number: 20150021713
    Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.
    Type: Application
    Filed: July 14, 2014
    Publication date: January 22, 2015
    Inventors: Sheng-Fang Cheng, Yen-Lin Liu, Chen-Chih Wu, Chien-Yuan Lee
  • Patent number: 8937352
    Abstract: A layout pattern of an implant layer includes at least a linear region and at least a non-linear region. The linear region includes a plurality of first patterns to accommodate first dopants and the non-linear region includes a plurality of second patterns to accommodate the first dopants. The linear region abuts the non-linear region. Furthermore, a pattern density of the first patterns in the linear region is smaller than a pattern density of the second patterns in the non-linear region.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: January 20, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Ming-Tsung Lee, Cheng-Hua Yang, Wen-Fang Lee, Chih-Chung Wang, Chih-Wei Hsu, Po-Ching Chuang
  • Patent number: 8937364
    Abstract: A high voltage semiconductor device, particularly a device including a number of high breakdown voltage transistors having a common drain, first well, and insulating structure between the gate and the drain as well as method for using the same is provided in this disclosure. The high breakdown voltage transistors in the device together are in an elliptical shape. A second well region, gate structure, and a source region are partially overlapping discontinuous elliptical rings having at least two discontinuities or openings in a top view. The respective discontinuities or openings define each of the high breakdown voltage transistors.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: January 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jam-Wem Lee
  • Patent number: 8921943
    Abstract: Methods and apparatus for ESD structures. A semiconductor device includes a first active area containing an ESD cell coupled to a first terminal and disposed in a well; a second active area in the semiconductor substrate, the second active area comprising a first diffusion of the first conductivity type for making a bulk contact to the well; and a third active area in the semiconductor substrate, separated from the first and second active areas by another isolation region, a portion of the third active area comprising an implant diffusion of the first conductivity type within a first diffusion of the second conductivity type and adjacent a boundary with the well of the first conductivity type; wherein the third active area comprises a diode coupled to the terminal and reverse biased with respect to the well of the first conductivity type.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Ying Hsu, Tzu-Heng Chang, Jen-Chou Tseng, Ming-Hsiang Song, Johannes Van Zwol, Taede Smedes
  • Patent number: 8895418
    Abstract: One embodiment describes a method of manufacturing a semiconductor device. Here, impurities are implanted into a semiconductor body via a first side of the semiconductor body. Thereafter, a drift zone layer on the first side of the semiconductor body is formed. The following is an ablation of the semiconductor body from a second side of the semiconductor body and up to pn junction defined by impurities.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: November 25, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Peter Irsigler, Thomas Neidhart, Guenter Schagerl, Hans-Joachim Schulze
  • Patent number: 8890293
    Abstract: A guard ring for a through via, and a method of manufacture thereof, is provided. The guard ring comprises one or more rings around a through via, wherein the rings may be, for example, circular, rectangular, octagon, elliptical, square, or the like. The guard ring may be formed from a contact through an inter-layer dielectric layer and interconnect structures (e.g., vias and lines) extending through the inter-metal dielectric layers. The guard ring may contact a well formed in the substrate.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: November 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hung Lu, Song-Bor Lee, Ching-Chen Hao
  • Publication number: 20140332919
    Abstract: A termination structure for a semiconductor power device includes a plurality of termination groups formed in a lightly doped epitaxial layer of a first conductivity type over a heavily doped semiconductor substrate of a second conductivity type. Each termination group includes a trench formed in the lightly doped epitaxial layer of the first conductivity type. All sidewalls of the trench are covered by a plurality of epitaxial layers of alternating conductivity types disposed on two opposite sides and substantially symmetrical with respect to a central gap-filler layer disposed between two innermost epitaxial layers of an innermost conductivity type as the first conductivity type.
    Type: Application
    Filed: July 28, 2014
    Publication date: November 13, 2014
    Inventors: Lingpeng Guan, Madhur Bobde, Hamza Yilmaz, Karthik Padmanabhan