Abstract: A semiconductor device comprises a substrate, a semiconductor layer formed on the substrate; and a high-voltage termination. The high-voltage termination includes a plurality of floating field rings, a deep trench and a dielectric material is disposed within the deep trench. The plurality of floating field rings are formed in the semiconductor layer and respectively disposed around a region of the semiconductor layer. The deep trench is formed in the semiconductor layer and concentrically disposed around an outermost floating field ring of the plurality of floating field rings. The high-voltage termination may also include a field plate disposed over the floating field rings, the deep trench, or both.

Abstract: A semiconductor device includes at least one transistor, a shallow well region, a guard ring, and a plurality of first and second doped regions. The transistor is on a substrate and includes a source structure, a gate structure, and a drain structure. The shallow well region surrounds the transistor. The shallow well region has a first conductivity type. The guard ring surrounds the shallow well region. The guard ring has the first conductivity type. The first and second doped regions are disposed on the guard ring and surround the well region. The first doped regions and the second doped regions are alternately arranged in a shape of a loop. Each of the first doped regions and each of the second doped regions have opposite conductivity types.

Abstract: A semiconductor device includes an active region provided in an n+-type silicon carbide substrate and through which main current flows, a termination region that surrounds a periphery of the active region, and a p-type silicon carbide layer provided on a front surface of the n+-type silicon carbide substrate and extending into the termination region. A region of the p-type silicon carbide layer extending into the termination region includes one or more step portions that progressively reduce a thickness of the p-type silicon carbide layer as the p-type silicon carbide layer becomes farther outward from the active region.

Abstract: In one embodiment, electrostatic discharge (ESD) devices are disclosed.

Abstract: A semiconductor device includes: an interlayer insulating film covering: a cathode region and an anode region to form a pn junction with each other; a cathode electrode provided on the interlayer insulating film and connected to the cathode region through a first contact hole; and an anode electrode provided on the interlayer insulating film and connected to the anode region through a second contact hole. Among current paths in the cathode and anode regions, the current path in one of the cathode and anode regions that has a larger sheet resistance is shorter than the other current path, the current path in the cathode region extending from an interface of the pn junction to an end of the first contact hole closest to the interface, the current path in the anode region extending from the interface to an end of the second contact hole closest to the interface.

Abstract: The embodiments described herein provide a die crack detector and method that use a conductive trace arranged to at least substantially extend around a perimeter of an integrated circuit die. A one-time programmable element, such as a fuse, is coupled in series with the conductive trace, and a package lead is electrically coupled to both the fuse and another operational element on the integrated circuit die. With the fuse intact the package lead can thus be used to determine a measurement of the conductivity of the conductive trace, with the measurement of conductivity indicative of the presence of a crack on the die. After such testing the fuse can be electrically opened, and the package lead used for normal operation of the device on the packaged die without the conductive trace interfering with this operation.

Abstract: The invention relates to semiconductor devices for conversion of the ionizing radiation into an electrical signal enabling determination of the radiation level and absorbed dose of gamma, proton, electronic and alpha radiations being measured. The ionizing radiation sensor is a p-i-n structure fabricated by the planar technology. The sensor contains a high-resistance silicon substrate of n-type conductivity, on whose front side there are p-regions; layer from SiO2; aluminum metallization; and a passivating layer. P-region, located in the central part of the substrate and occupying the most surface area, forms the active region of the sensor. At least two p-regions in the form of circular elements are located in the inactive region on the perimeter of the substrate around the central p-region and ensure a decrease in the surface current value and smooth voltage drop from the active region to the device perimeter.

Abstract: A semiconductor device including field insulating films and having first corner portions, provided on a P-type epitaxial growth layer; an N?-type cathode that is provided in the P-type epitaxial growth layer and is located on the inner sides of the field insulating films; and a P?-type anode that is formed on the cathode so as to be in contact with the cathode and covers the first corner portions provided on the inner sides of the field insulating films, wherein the junction between the cathode and the anode serves as a PN junction of the diode, and the PN junction is spaced apart from the first corner portions.

Abstract: A semiconductor includes an N-type impurity region provided in a substrate. A P-type RESURF layer is provided at a top face of the substrate in the N-type impurity region. A P-well has an impurity concentration higher than that of the P-type RESURF layer, and makes contact with the P-type RESURF layer at the top face of the substrate in the N-type impurity region. A first high-voltage-side plate is electrically connected to the N-type impurity region, and a low-voltage-side plate is electrically connected to a P-type impurity region. A lower field plate is capable of generating a lower capacitive coupling with the substrate. An upper field plate is located at a position farther from the substrate than the lower field plate, and is capable of generating an upper capacitive coupling with the lower field plate whose capacitance is greater than the capacitance of the lower capacitive coupling.

Abstract: A super junction structure having implanted column regions surrounding an N epitaxial layer in a deep trench is disclosed to overcome charge imbalance problem and to further reduce Rds. The inventive super junction can be used for MOSFET and Schottky rectifier.

Abstract: A method or an auxiliary method to implement Optimum Variation Lateral Electric Displacement uses an insulator film(s) containing conductive particles covering on the semiconductor surface. This film(s) is capable of transmitting electric displacement into or extracting it from the semiconductor surface, or even capable of extracting some electric displacement from a part of the semiconductor surface and then transmitting it to another part of the surface. Optimum Variation Lateral Electric Displacement can be used to fabricate lateral high voltage devices, or as the edge termination for vertical high voltage devices, or to make capacitance. It can be further used to prevent strong field at the boundaries of semiconductor regions of different types of conductivity types.

Abstract: Methods and apparatus for ESD structures. A semiconductor device includes a first active area containing an ESD cell coupled to a first terminal and disposed in a well; a second active area in the semiconductor substrate, the second active area comprising a first diffusion of the first conductivity type for making a bulk contact to the well; and a third active area in the semiconductor substrate, separated from the first and second active areas by another isolation region, a portion of the third active area comprising an implant diffusion of the first conductivity type within a first diffusion of the second conductivity type and adjacent a boundary with the well of the first conductivity type; wherein the third active area comprises a diode coupled to the terminal and reverse biased with respect to the well of the first conductivity type.

Abstract: An N type layer made of an N type epitaxial layer in which an N+ type drain layer etc are formed is surrounded by a P type drain isolation layer extending from the front surface of the N type epitaxial layer to an N+ type buried layer. A P type collector layer is formed in an N type layer made of the N type epitaxial layer surrounded by the P type drain isolation layer and a P type element isolation layer, extending from the front surface to the inside of the N type layer. A parasitic bipolar transistor that uses the first conductive type drain isolation layer as the emitter, the second conductive type N type layer as the base, and the collector layer as the collector is thus formed so as to flow a surge current into a ground line.

Abstract: In aspects of the invention, SiC reverse blocking MOSFET includes an active region including a MOS gate structure and a breakdown voltage structure portion surrounding the outer circumference of the active region, which are provided on the surface side of a SiC-n? drift layer that is grown on one main surface of a p+ SiC substrate. A p-type isolation region is provided on the side surface of the SiC-n? drift layer so as to surround the outer circumference of the breakdown voltage structure portion and to extend from the front surface of the SiC-n? drift layer to the p+ SiC substrate. A concave portion which reaches the SiC-n? drift layer through the p+ SiC substrate and has a bottom area corresponding to the area of the active region is provided in a region of the other main surface of the p+ SiC substrate which is opposite to the active region.

Abstract: A guard ring for a through via, and a method of manufacture thereof, is provided. The guard ring comprises one or more rings around a through via, wherein the rings may be, for example, circular, rectangular, octagon, elliptical, square, or the like. The guard ring may be formed from a contact through an inter-layer dielectric layer and interconnect structures (e.g., vias and lines) extending through the inter-metal dielectric layers. The guard ring may contact a well formed in the substrate.

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a first electrode, and a second electrode. The semiconductor substrate is of a first conductivity type. The first semiconductor layer is of a second conductivity type, provided on the semiconductor substrate. The second semiconductor layer is of a first conductivity type, reaches the semiconductor substrate from a surface of the first semiconductor layer, and surrounds the first semiconductor layer. The third semiconductor layer is of a second conductivity type, separated from the second semiconductor layer, surrounded by the second semiconductor layer, and has a higher concentration of second-conductivity-type impurities than the first semiconductor layer.

Abstract: A super junction semiconductor device includes a substrate layer of a first conductivity type and an epitaxial layer adjoining the substrate layer and including first columns of the first conductivity type and second columns of a second conductivity type. The first and second columns extend along a main crystal direction into the epitaxial layer and have vertical dopant profiles perpendicular to the first surface. The vertical dopant profile of at least one of the first and second columns includes first portions separated by second portions. In each of the first portions a dopant concentration varies by at most 30% of a maximum value within the respective first portion. In the second portions the dopant concentration is lower than in the adjoining first portions. A ratio of a total length of the first portions to a total length of the first and second portions is at least 50%.

Abstract: A super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode.

Abstract: In a semiconductor device including a low lifetime region of a depth within a range on both sides sandwiching a p-n junction of a p-type semiconductor region bottom portion, the low lifetime region includes a central region that has a portion coinciding with the semiconductor region as seen from one main surface side and is selectively formed as far as the position of a contact end portion of a region of the coinciding portion with which the semiconductor region and a metal electrode are in contact, a peripheral region wherein the central region extends as far as the position of an outer peripheral end of the semiconductor region, and an expanded end portion region wherein the peripheral region extends as far as an outer peripheral end of the innermost of guard rings. Because of this, it is possible to reduce leakage current while maintaining high reverse recovery current resistance.

Abstract: In a semiconductor device having a pn-junction diode structure that includes anode diffusion region including edge area, anode electrode on anode diffusion region, and insulator film on edge area of anode diffusion region, the area of anode electrode above anode diffusion region with insulator film interposed between anode electrode and anode diffusion region is narrower than the area of insulator film on edge area of anode diffusion region.

Abstract: Provided is a power semiconductor device including a guard ring region to protect control devices. The power semiconductor device includes a semiconductor body layer extending over a semiconductor substrate of a first conductivity type. The semiconductor body layer has a second conductivity type opposite the first conductivity type. A well of the first conductivity type extends in the semiconductor body layer and is configured to be electrically insulated from the semiconductor substrate. At least one control device is formed in the well, where the control device comprises at least one of PN junction. A guard ring region of the first conductivity type is laterally spaced from but surrounds the well. The guard ring region together with the semiconductor substrate and the semiconductor body layer form a parasitic bipolar transistor, and the guard ring region functions as a collector of the parasitic bipolar transistor.

Abstract: Provided is an electronic device that generates an output signal corresponding to an input signal, comprising a signal processing section that receives the input signal and outputs the output signal corresponding to the input signal, and a floating electrode that accumulates a charge by being irradiated by an electron beam. The signal processing section adjusts electric characteristics of the output signal according to a charge amount accumulated in the floating electrode, and includes a transistor formed on the semiconductor substrate between an input terminal that receives the input signal and an output terminal that outputs the output signal. The floating electrode is formed between a gate electrode of the transistor and the semiconductor substrate.

Abstract: A semiconductor chip having a current source coupled between a first potential and an electrical node, a detection circuit having an input coupled to the electrical node, and a first active component coupled in series with the current source and further coupled between the electrical node and a second potential, wherein the first active component is coupled to the electrical node via a first conductive interconnect.

Abstract: A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.

Abstract: A multi-trench termination structure for semiconductor device is disclosed, where the semiconductor device includes a semiconductor substrate and an active structure region. The multi-trench termination structure includes multiple trenches defined on an exposed face of the semiconductor substrate, a first mask layer formed on a partial exposed surface of the semiconductor substrate and corresponding to a termination structure region of the semiconductor device, a gate insulation layer formed in the trenches, a conductive layer formed on the gate insulation layer and protruding out of the exposed surface of the semiconductor substrate, and a metal layer formed over the first mask layer and conductive layer on the termination structure region of the semiconductor device.

Abstract: A high voltage ESD protection diode wherein the p-n junction is defined by a p-well and an n-well and includes a RESURF region, the diode including a field oxide layer formed on top of the p-well and n-well, wherein the parameters of the diode are adjustable by controlling one or more of the junction width, the length of the RESURF region, or the length of the field oxide layer.

Abstract: A method or an auxiliary method to implement Optimum Variation Lateral Electric Displacement uses an insulator film(s) containing conductive particles covering on the semiconductor surface. This film(s) is capable of transmitting electric displacement into or extracting it from the semiconductor surface, or even capable of extracting some electric displacement from a part of the semiconductor surface and then transmitting it to another part of the surface. Optimum Variation Lateral Electric Displacement can be used to fabricate lateral high voltage devices, or as the edge termination for vertical high voltage devices, or to make capacitance. It can be further used to prevent strong field at the boundaries of semiconductor regions of different types of conductivity types.

Abstract: A semiconductor device includes a semiconductor substrate of a first electroconductive type, a first principal electrode arranged on a first side of the semiconductor substrate, a first semiconductor layer of a second electroconductive type arranged on a second side of the semiconductor substrate and at a certain distance from an edge of the semiconductor substrate, plural second semiconductor layer portions of the second electroconductive type arranged on the second side of the semiconductor substrate and positioned selectively in between the edge and the first semiconductor layer, an insulating film arranged to cover a portion of the first semiconductor layer from the edge, an electroconductive film arranged to cover portions of the insulating film and the first semiconductor layer, and a second principal electrode arranged in contact with the first semiconductor layer and the electroconductive film.

Abstract: A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.

Abstract: A semiconductor wafer includes semiconductor chip areas on a semiconductor substrate, the semiconductor chip areas having thereon semiconductor circuit patterns and inner guard ring patterns surrounding the semiconductor circuit patterns; and scribe lanes on the semiconductor substrate between the semiconductor chip areas, the scribe lanes having thereon outer guard ring patterns surrounding the inner guard ring patterns and a process monitoring pattern between the outer guard ring patterns, the outer guard ring patterns and the process monitoring pattern being merged with each other.

Abstract: A semiconductor device for protecting against an electro static discharge is disclosed. In one embodiment, the semiconductor device includes a first low doped region disposed in a substrate, a first heavily doped region disposed within the first low doped region, the first heavily doped region comprising a first conductivity type, and the first low doped region comprising a second conductivity type, the first and the second conductivity types being opposite, the first heavily doped region being coupled to a node to be protected. The semiconductor device further includes a second heavily doped region coupled to a first power supply potential node, the second heavily doped region being separated from the first heavily doped region by a portion of the first low doped region, and a second low doped region disposed adjacent the first low doped region, the second low doped region comprising the first conductivity type.

Abstract: In a semiconductor device having a pn-junction diode structure that includes anode diffusion region including edge area, anode electrode on anode diffusion region, and insulator film on edge area of anode diffusion region, the area of anode electrode above anode diffusion region with insulator film interposed between anode electrode and anode diffusion region is narrower than the area of insulator film on edge area of anode diffusion region.

Abstract: A semiconductor structure. The semiconductor structure includes a semiconductor substrate, a first transistor on the semiconductor substrate, and a guard ring on the semiconductor substrate. The semiconductor substrate includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface. The guard ring includes a semiconductor material doped with a doping polarity. A first doping profile of a first doped transistor region of the first transistor in the reference direction and a second doping profile of a first doped guard-ring region of the guard ring in the reference direction are essentially a same doping profile. The guard ring forms a closed loop around the first transistor.

Abstract: A Semiconductor component having a space saving edge structure is disclosed. One embodiment provides a first side, a second side, an inner region, an edge region adjoining the inner region in a lateral direction of the semiconductor body, and a first semiconductor layer extending across the inner region and the edge region and having a basic doping of a first conductivity type. At least one active component zone of a second conductivity type, which is complementary to the first conductivity type, is disposed in the inner region in the first semiconductor layer. An edge structure is disposed in the edge region and includes at least one trench extending from the first side into the semiconductor body. An edge electrode is disposed in the trench, a dielectric layer is disposed in the trench between the edge electrode and the semiconductor body, a first edge zone of the second conductivity type adjoin the trench and are at least partially disposed below the trench.

Abstract: A semiconductor layer of a vertical diode is divided into a center region and a surrounding region. An anode electrode contacts a surface of the center region in the semiconductor layer. An insulation layer contacts a surface of the surrounding region in the semiconductor layer. Ring-shaped FLR regions are formed in the surface of the surrounding region in the semiconductor layer. The innermost FLR region extends from an inside to an outside of a boundary between the anode electrode and the insulation layer, and extends along the boundary. A shoulder portion is formed in the surface of the semiconductor layer in a manner such that a portion that contacts the insulation layer is higher than a portion that contacts the anode electrode. Flows of holes directed toward the anode electrode pass through a plurality of positions in the shoulder portion.

Abstract: In a conventional semiconductor device, there has been a problem that, in a region where a wiring layer to which a high electric potential is applied traverses a top surface of an isolation region, the withstand voltage is deteriorated. In a semiconductor device of the present invention, an epitaxial layer is deposited on a substrate, and an LDMOSFET is formed in one region divided by an isolation region. In a region where a wiring layer connected to a drain electrode traverses a top surface of the isolation region, a conductive plate having a ground electric potential and another conductive plate in a floating state are formed under the wiring layer. With this structure, electric field is reduced in the vicinity of the isolation region under the wiring layer, whereby a withstand voltage of the LDMOSFET is increased.

Abstract: An integrated circuit (IC) is disclosed to include a central area of the IC that is partitioned into a first section containing at least one digital circuit and a second section containing at least one analog circuit; and a guard strip (or shield) that is within the central area and that is positioned within between the digital circuit and the analog circuit. The shield or guard strip comprises of n-well and p-tap regions that separate digital and analog circuits.

Abstract: A diode, includes a semiconductor substrate, a first region doped with a first dopant type in the substrate, a second region doped with a second dopant type in the substrate, a first well of the first dopant type in the substrate and surrounding the first region and the second region, and a second well of the second dopant type in the substrate connecting the first region and the second region. The first dopant type is opposite the second dopant type.

Abstract: The invention relates to an integrated circuit having a semiconductor component (10) comprising a first p-type region (12) and a first n-type region (11) adjoining the first p-type region (12), which together form a first pn junction having a breakdown voltage. According to the invention, a further n-type region adjoining the first p-type region or a further p-type region (13) adjoining the first n-type region (11) is provided, the first p-type or n-type region (11) and the further n-type or p-type region (13) adjoining the latter together forming a further pn junction having a further breakdown voltage, the first pn junction and the further pn junction being connected or connectable to one another in such a way that, in the case of an overloading of the semiconductor component, on account of a current loading of the first pn junction, first of all the further pn junction breaks down.

Abstract: A high-voltage termination structure includes a peripheral voltage-spreading network. One or more trench structures are connected at least partly in series between first and second power supply voltages. The trench structures include first and second current-limiting structures connected in series with a semiconductor material, and also includes permanent charge in a trench-wall dielectric. The current-limiting structures in the trench structures are jointly connected in a series-parallel ladder configuration. The current-limiting structures, in combination with the semiconductor material, provide a voltage distribution between the core portion and the edge portion.

Abstract: A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance.

Abstract: A rectifier for high temperature application includes a conductive semiconductor layer, a conductive epitaxial layer, and a plurality of conductive doped regions within the conductive epitaxial layer. A fringe conductive doped region is formed surrounding the conductive doped region, and an outer fringe conductive doped region is formed further surrounding the fringe conductive doped region. A first metal layer is formed on the upper surface of the conductive semiconductor substrate covering the entire conductive doped regions, and contacting at least a portion of the fringe conductive doped region. A second metal layer is formed on the lower surface of the conductive semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type having a top surface and a bottom surface, a semiconductor layer of a first conductivity type formed on the top surface of the semiconductor substrate, and having an active region and an edge termination region surrounding the active region, a first semiconductor region of a second conductivity type formed in the edge termination region adjacent to an edge of the active region, a second semiconductor region of a second conductivity type buried in the edge termination region in a sheet shape or a mesh shape substantially in parallel with a surface of the semiconductor layer, a first electrode formed on the active region of the semiconductor layer and a part of the first semiconductor region, and a second electrode formed on the bottom surface of the semiconductor substrate.

Abstract: The invention relates to a semiconductor component comprising a buried temporarily n-doped area (9), which is effective only in the event of turn-off from the conducting to the blocking state of the semiconductor component and prevents chopping of the tail current in order thus to improve the turn-off softness. Said temporarily effective area is created by implantation of K centers (10).

Abstract: A vertical rectifying and protection power diode, formed in a lightly-doped semiconductor layer of a first conductivity type, resting on a heavily-doped substrate of the first conductivity type, having a first ring-shaped region, of the first conductivity type more heavily-doped than the layer and more lightly doped than the substrate, surrounding an area of the layer and extending to the substrate; and a second ring-shaped region, doped of the second conductivity type, extending at the surface of the first region and on either side thereof; a first electrode having a thin layer of a material capable of forming a Schottky diode with the layer, resting on the area of the layer and on at least a portion of the second ring-shaped region with which it forms an ohmic contact.

Abstract: Wiring is routed to assure insulation between wiring traces in a semiconductor integrated circuit device. The device includes a first wiring trace to which a prescribed voltage is supplied; a second wiring trace that takes on a voltage that exceeds the prescribed voltage; and a third wiring trace that only takes on a voltage less than the prescribed voltage. Alternatively, the device includes a first wiring trace to which a prescribed voltage is supplied; a second wiring trace that takes on a voltage less than the prescribed voltage; and a third wiring trace that takes on a voltage equal to or greater than the prescribed voltage. The wiring traces are routed at a certain wiring space in such a manner that the first wiring trace is interposed between the second and third wiring traces. The first wiring trace for which the potential difference is known to be small beforehand is routed so as to always be adjacent to the second wiring trace.

Abstract: In various embodiments, circuits and semiconductor devices and structures and methods to manufacture these structures and devices are disclosed. In one embodiment, a bidirectional polarity, voltage transient protection device is disclosed. The voltage transient protection device may include a bipolar PNP transistor having a turn-on voltage of VBE1, a bipolar NPN transistor having a turn-on voltage of VBE2, and a field effect transistor (FET) having a threshold voltage of VTH, wherein a turn-on voltage VTO of the voltage transient protection device is approximately equal to the sum of VBE1, VBE2, and VTH, that is, VTO?VBE1+VBE2+VTH. Other embodiments are described and claimed.

Abstract: In a semiconductor device having a pn-junction diode structure that includes anode diffusion region including edge area, anode electrode on anode diffusion region, and insulator film on edge area of anode diffusion region, the area of anode electrode above anode diffusion region with insulator film interposed between anode electrode and anode diffusion region is narrower than the area of insulator film on edge area of anode diffusion region.

Abstract: A production method for a semiconductor device, including the steps of: forming a semiconductor layer of the first conductivity on the semiconductor substrate; forming a trench in the semiconductor layer, the trench penetrating through the semiconductor layer to reach the semiconductor substrate; filling a filling material in a predetermined bottom portion of the trench, so that a filling material portion is provided in the bottom portion of the trench up to a predetermined upper surface position which is shallower than an interface between the semiconductor substrate and the semiconductor layer; and, after the filling step, introducing an impurity of the second conductivity into a portion of the semiconductor layer exposed to an interior side wall of the trench.

Abstract: A high-voltage termination structure includes a peripheral voltage-spreading network. One or more trench structures are connected at least partly in series between first and second power supply voltages. The trench structures include first and second current-limiting structures connected in series with a semiconductor material, and also includes permanent charge in a trench-wall dielectric. The current-limiting structures in the trench structures are jointly connected in a series-parallel ladder configuration. The current-limiting structures, in combination with the semiconductor material, provide a voltage distribution between the core portion and the edge portion.