Abstract: The invention relates to a ground-compatible inhibit circuit structure and method, for circuits integrated in a semiconductor substrate which is unrelated to ground potential. The circuit structure is integrated in the same substrate as an associated circuit to be inhibited, and the substrate is covered with an epitaxial layer accommodating the components of the inhibit circuit structure. It includes a stable internal voltage reference and a circuit portion for comparing this reference with an inhibit signal in order to block the associated circuit upon a predetermined threshold value being exceeded, even in a condition of the signal potential being higher than the supply potential to the circuit. Advantageously, the epitaxial layer of each well is always at a potential higher than or equal to that of the substrate.

Abstract: A semiconductor apparatus substrate according to the present invention has a substrate, a piece-substrate that has been punched out of the substrate and pushed back to the original position, an opening unit formed in a region of the substrate that substantially surrounds the piece-substrate, and a support unit installed inside the opening unit. As a result of this configuration, in transporting the semiconductor apparatus substrate after the piece-substrate has been pushed back, the piece-substrate is prevented from falling off the semiconductor apparatus substrate.

Abstract: A Gunn diode which is formed by sequentially laminating a first semiconductor layer, an active layer and a second semiconductor layer onto a semiconductor substrate. The Gunn diode comprises first and second electrodes arranged on the second semiconductor layer for impressing voltage on the active layer, and a concave portion which is cut from around the first electrode in a direction of the second semiconductor layer and the active layer and which subdivides the second semiconductor layer and the active layer to which the first electrode is connected as a region which functions as a Gunn diode. Since etching for defining a region that is to function as a Gunn diode is performed by self-alignment dry etching utilizing electrode layers formed above this region as masks, variations in characteristics are restricted.

Abstract: A MOSFET die and a Schottky diode die are mounted on a common lead frame pad and their drain and cathode, respectively, are connected together at the pad. The pad has a plurality of pins extending from one side thereof. The lead frame has insulated pins on its opposite side which are connected to the FET source, the FET gate and the Schottky diode anode respectively by wire bonds. The lead frame and die are molded in an insulated housing and the lead frame pins are bent downwardly to define a surface-mount package.

Abstract: A nonvolatile semiconductor memory device includes an n-type region which is in contact with n+ drain diffusion region at a surface of p-type silicon substrate and covers the periphery thereof. The device also includes a p-type impurity region which is in contact with n-type region and covers the periphery thereof. The n+ drain diffusion region, n-type region and p+ impurity region extend to region located immediately under the floating gate electrode. Thereby, the nonvolatile semiconductor memory device has a structure which can promote injection of high energy electrons along a gate electrode direction.

Abstract: A MOSFET die and a Schottky diode die are mounted on a common lead frame pad and their drain and cathode, respectively, are connected together at the pad. The pad has a plurality of pins extending from one side thereof. The lead frame has insulated pins on its opposite side which are connected to the FET source, the FET gate and the Schottky diode anode respectively by wire bonds. The lead frame and die are molded in an insulated housing and the lead frame pins are bent downwardly to define a surface-mount package.

Abstract: The invention relates to a so-called punch-through diode comprising a stack of, for example, an n++, p−, p+, n++ region (1, 2, 3, 4). In the known diode, these regions (1, 2, 3, 4) are arranged on a substrate (11) in said order. The diode is provided with connection conductors (5, 6). Such a diode does not have a steep I-V characteristic and hence is less suitable as a TVSD (=Transient Voltage Suppression Device). Particularly at voltages below 5 volts, a punch-through diode could form an attractive alternative for use as a TVSD.

Abstract: A lateral semiconductor structure having a punch-through diode for forming a temperature-compensated voltage limitation in which the space charge resistance is reduced through a lateral arrangement of preferably annular regions around a base trough. This is achieved in that the preferably annular regions are arranged with a specific doping as well as a specific separation from the base trough. By using the punch-through and avalanche effects, a higher breakdown voltage is achieved since the space charge resistance is reduced by the chosen arrangement.

Abstract: A MOS transistor that includes: a semiconductor substrate; a well region formed in the semiconductor substrate, where a trench region is defined in the well region; an isolator formed on a corner of the trench region, where the trench region is filled with polysilicon; a gate conductor formed over the trench region; and source/drain regions formed within the well region laterally aligned to the gate conductor. A suitable method to form the MOS transistor includes the acts of: forming a well region in a semiconductor substrate; forming a trench region in the well region; forming an isolator in a corner of the trench region; filling the trench region with polysilicon; forming a gate conductor formed over the trench region; and forming source/drain regions within the well region on opposite sides of the gate conductor.

Abstract: A method of forming integrated isolation regions and active regions includes first forming a plurality of dielectric layers upon a semiconductor substrate. Then, a patterned mask is applied to define portions of the dielectric layers that will remain to form isolation regions and to define portions of the dielectric layers that will be removed in an etch step to create voids to the surface of the semiconductor substrate. Subsequently, epitaxially growth is employed to form active regions within the voids that were previously formed. Transistors are then formed in and on the active regions and are subsequently interconnected to form an integrated circuit.

Abstract: An integrated circuit includes a plurality of transistors formed to include insulative punchthrough regions. Each of the plurality of transistors includes a channel formed upon a substrate, an insulative punchthrough region formed below the channel, a source formed upon the insulative punchthrough region residing adjacent a first end of the channel, a drain formed upon the insulative punchthrough region residing adjacent a second end of the channel, a gate oxide formed above the channel and a gate conductor formed above the gate oxide. Isolation regions may also be formed in the substrate that have an etch stop defination that was formed upon formation of the insulative punchthrough region. A voltage threshold region may be formed between the gate oxide and the channel and lightly doped regions may be formed adjacent the channel. The insulative punchthrough region may be and oxide layer formed within the substrate in an oxygen implant step that also formed the etch stop defination.

Abstract: A punch-through diode transient suppression device has a base region of varying doping concentration to improve leakage and clamping characteristics. The punch-through diode includes a first region comprising an n+ region, a second region comprising a p- region abutting the first region, a third region comprising a p+ region abutting the second region, and a fourth region comprising an n+ region abutting the third region. The peak dopant concentration of the n+ layers should be about 1.5E18 cm.sup.-3, the peak dopant concentration of the p+ layer should be between about 1 to about 5 times the peak concentration of the n+ layer, and the dopant concentration of the p- layer should be between about 0.5E14 cm.sup.-3 and about 1.OE17 cm.sup.-3. The junction depth of the fourth (n+) region should be greater than about 0.3 .mu.m. The thickness of the third (p+) region should be between about 0.3 .mu.m and about 2.0 .mu.m, and the thickness of the second (p-) region should be between about 0.5 .mu.m and about 5.0 .

Abstract: The present invention relates to an assembly of two pairs of diodes in a single semiconductor substrate of a first type of conductivity, the first pair including a first diode in series with a second diode, the second pair including a third diode in series with a fourth diode, the two pairs of diodes being arranged in parallel. Each of the first and third diodes includes neighboring regions of distinct types of conductivity formed in a lightly-doped well of the second type of conductivity, these wells being separated; each of the second and fourth diodes includes separated regions of distinct types of conductivity; and metallizations connect the electrodes of the diodes to form the desired series-to-parallel assembly.

Abstract: The present invention includes a substrate of a first conductivity type having a top surface including at least two intersecting trenches disposed therein with an insulating layer lining the trenches and a conductive material filling the trenches. The transistor also includes a source region of the first conductivity type extending from the top surface of the substrate adjacent to the trenches toward the substrate. The transistor further has a body region of a second conductivity type of opposite polarity from the first conductivity type, the body region extends from the top surface adjacent from the trenches to the substrate and surrounding the source region.

Abstract: A semiconductor device having an oxygen-rich punchthrough region under the channel region, and a process for fabricating such a device are disclosed. In accordance with one embodiment, a semiconductor device is formed by forming an oxygen-rich punchthrough region in a substrate, and forming a channel region over the oxygen-rich punchthrough region. The use of an oxygen-rich punchthrough region may, for example, inhibit the diffusion of dopants used in forming the channel region.

Abstract: A semiconductor device includes a semiconductor substrate having an element region on the main surface thereof, an element isolation region formed to surround the element region on the main surface of the semiconductor substrate, a gate electrode formed over the element region with a gate insulating film disposed therebetween, a first and a second impurity diffusion region formed on a surface of the element region on both sides of at least part of the gate electrode, a first channel region formed in the surface of the element region below the gate electrode between the first and the second impurity diffusion region when a first preset voltage is applied to the gate electrode, and a first tunnel diode formed in a first interface region between the first impurity diffusion region and the first channel region when the first preset voltage is applied to the gate electrode, wherein the first interface region in which the first tunnel diode is formed is formed in position separated from the element isolation region

Abstract: A punch-through diode includes a first and second gate forming first and second junctions respectively with and spaced from each other by a first region. The junctions may be PN junction or Schottky barrier junctions with the first region. The diode may be the top gate-channel-bottom gate junctions of an FET or the collector-base-emitter junctions of a bipolar transistor. In either case, the channel or the base is depleted and currents flow between the top and bottom gate or the emitter and collector respectively. The punch-through diode is used as a voltage reference element and can be structured for Kelvin connection.

Abstract: A punch-through diode includes a first and second gate forming first and second junctions respectively with and spaced from each other by a first region. The junctions may be PN junction or Schottky barrier junctions with the first region. The diode may be the top gate-channel-bottom gate junctions of an FET or the collector-base-emitter junctions of a bipolar transistor. In either case, the channel or the base is depleted and currents flow between the top and bottom gate or the emitter and collector respectively. The punch-through diode is used as a voltage reference element and can be structured for Kelvin connection.

Abstract: A punch-through diode transient suppression device has a base region of varying doping concentration to improve leakage and clamping characteristics. The punch-through diode includes a first region comprising an n+ region, a second region comprising a p- region abutting the first region, a third region comprising a p+ region abutting the second region, and a fourth region comprising an n+ region abutting the third region. The peak dopant concentration of the n+ layers should be about 1.5E18 cm.sup.-3, the peak dopant concentration of the p+ layer should be between about 1 to about 5 times the peak concentration of the n+ layer, and the dopant concentration of the p- layer should be between about 0.5E14 cm.sup.-3 and about 1.0E17 cm.sup.-3. The junction depth of the fourth (n+) region should be greater than about 0.3 um. The thickness of the third (p+) region should be between about 0.3 um and about 2.0 um, and the thickness of the second (p-) region should be between about 0.5 um and about 5.0 um.

Abstract: In an input protection circuit having an SOI structure for protecting a MOSFET against breaking caused by a high voltage such as static electricity, a trench is provided in an SOI substrate to vertically pass through a silicon layer and a buried oxide film and reach the interior of a P-type silicon substrate. An n.sup.+ polysilicon layer is buried in the trench, to be connected with the silicon substrate by a P-N junction. A wire is connected to the n.sup.+ polysilicon layer. An end of the wire is connected to an input pad, and another end thereof is connected to an internal circuit. An input voltage is limited by an avalanche breakdown at the P-N junction in the interface between the n.sup.+ polysilicon layer and the P-type silicon substrate.

Abstract: A MOSFET die and a Schottky diode die are mounted on a common lead frame pad and their drain and cathode, respectively, are connected together at the pad. The pad has a plurality of pins extending from one side thereof. The lead frame has insulated pins on its opposite side which are connected to the FET source, the FET gate and the Schottky diode anode respectively by wire bonds. The lead frame and die are molded in an insulated housing and the lead frame pins are bent downwardly to define a surface-mount package.

Abstract: A protection circuit structure for an internal semiconductor integrated circuit. The protection circuit structure includes a first protection circuit having at least a first input pin and a first discharge pin, a second protection circuit having at least a second input pin and a second discharge pin and a switching device connecting between the first and second protection circuits. The switching device is biased by a potential difference between the first and second discharge pins. The switching device permits operating one of the first and second protection circuits to accomplish a discharge in replacement of an inoperative first or second discharge pin. The switching device takes the ON state when biased by a predetermined voltage or higher which interrupts the internal semiconductor integrated circuit. The switching device connects between wiring lines which respectively connect to the first and second discharge pins.

Abstract: In a breakover type surge protection device utilizing punch-through that comprises a second semiconductor region forming a first pn junction with a first semiconductor region, a third semiconductor region forming a second pn junction with the second semiconductor region and a fourth semiconductor region forming a third pn junction with the first semiconductor region at a place apart from the second semiconductor region, the second semiconductor region is constituted of a punch-through suppression region portion disposed to cover the corners of the third semiconductor region and a punch-through generation region portion disposed at a place where its thickness can be made uniform. Fabricating surge protection devices according to this configuration reduces variation among their breakover currents and hold currents and increases their surge absorption capacity.

Abstract: An input/output protection device for an integrated circuit is formed using a trench (22). A first electrode region (46) is formed adjacent a first portion of the trench sidewall (24), and a second electrode region (48) is formed adjacent a second portion of the trench sidewall (24). One of the electrode regions is then electrically coupled to an input/output pad, while the other electrode region is electrically coupled to ground. Excessive voltages on the input/output pad are then discharged when the electrode, which is electrically coupled to the input/output pad, punches through to the electrode that is electrically coupled to ground.

Abstract: A voltage controlled thyristor includes an intrinsic layer of material between an anode and a cathode and a gate region between the intrinsic layer and the cathode comprising a lightly doped P type layer with more heavily doped P type regions extending through the lightly doped layer into the intrinsic layer. The more heavily doped P type regions are interspersed among shallower N doped regions of the cathode. In a preferred embodiment, interdigitated ohmic contacts are formed on one surface to the N doped cathode regions and the P doped regions of the control gate. In a preferred embodiment, the anode and cathode emitters have a porous construction in which a lightly doped layer or region has a more heavily doped region or regions therein.

Abstract: Multiple punchthru devices are coupled between multiple metal-two conductors and a metal-one bond pad. Each punchthru device has the capacity to couple its respective metal-two conductor to the bond pad when a predetermined voltage potential exists between the metal-two conductor and the bond pad. A set of metal-one islands, one set associated with each metal-one bond pad cell, resides in a bond pad channel. The positioning of the punchthru devices and the islands minimizing the bond pad cell size and minimizing the spacing between adjacent bond pad cells. The bond pad cell configuration also allows any metal-two conductor to be coupled to the bond pad without having to rearrange punchthru devices or reconfigure the bond pad cell. The multiple punchthru devices associated with each bond pad cell provide redundant overvoltage protection superior to present overvoltage protection circuits.

Abstract: A first region of a first conductivity type is formed in the surface of a semiconductor body, and second and third regions of a second conductivity type are formed on and under, respectively, of the first region. An electrode region formed on a first insulating film formed on the semiconductor body is connected electrically to the first region. The electrode region is defined as having an elongated first part an upper surface of which is connected to an electrode, and having a second, different part which has a substantially constant width and which width is substantially equal to the thickness of the first portion of the electrode region. A metal silicide film is formed over the upper surface of the first portion of the electrode region. The first, second and third regions can be base, emitter and collector regions, respectively, of a bipolar transistor formed in an island region of an epitaxially grown layer on a semiconductor substrate.

Abstract: The invention relates to a controllable, temperature-compensated voltage limiter with a p.sup.+ np.sup.+ (or n.sup.+ pn.sup.+) semiconductor structure in which the width and doping of the central zone is selected such that no avalanche or Zener effect appears when voltage is applied to the two outer layers (punch-through diode). In accordance with the invention, the voltage U.sub.B to be limited is applied between the blocking pn-juncture (B-C). In addition, an adjustable auxiliary voltage (U.sub.H) is applied between the other pn-junction (H-C). The punch-through can be set to a higher defined value via the auxiliary voltage U.sub.H, this value being independent of the temperature to a large extent.