With Polycrystalline Semiconductor Isolation Region In Direct Contact With Single Crystal Active Semiconductor Material Patents (Class 257/505)
  • Patent number: 10680099
    Abstract: A transistor, such as laterally diffused (LD) transistor, having a band region below a drift well is disclosed. The band region and drift well are oppositely doped. The band region is self-aligned to the drift well. The band region reduces the depth of the drift well. A shallower drift well reduces risk of punch-through, improving reliability. In addition, the shallower drift well reduces the drain to body parasitic capacitance which improves performance.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: June 9, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Liming Li, Shaoqiang Zhang, Ruchil Kumar Jain, Raj Verma Purakh
  • Patent number: 10374082
    Abstract: A semiconductor device includes a substrate of a first conductivity type, a gate electrode on the substrate, a first high concentration impurity region of the first conductivity type that is disposed on a first side of the gate electrode, a first well of the first conductivity type that is disposed under the first high concentration impurity region and surrounds the first high concentration impurity region, a second well of a second conductivity type that overlaps with a portion of the gate electrode and is adjacent to the first well, and a first deep well of the second conductivity type that is disposed under the first well and the second well, the first deep well and the first high concentration impurity region being responsive to a first voltage.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: August 6, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong Don Kim, In Jun Hwang, Jung Han Kang
  • Patent number: 9997396
    Abstract: A semiconductor structure having a deep trench isolation structure for improved product yield is disclosed. The semiconductor structure includes a deep trench having a filler material therein. The deep trench is adjacent to field oxide regions in a semiconductor substrate. A high density plasma (HDP) oxide layer, substantially free of thermal oxide, is situated over the filler material in the deep trench. The HDP oxide layer has a substantially co-planar top surface with at least one of the field oxide regions. According to the present disclosure, formation of nodules in the deep trench is prevented.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: June 12, 2018
    Assignee: Newport Fab, LLC
    Inventors: George E. Parker, Dieter Dornisch, Lawrence L. Au
  • Patent number: 9536746
    Abstract: Some embodiments of the present disclosure relate to a semiconductor device configured to mitigate against parasitic coupling while maintaining threshold voltage control for comparatively narrow transistors. In some embodiments, a semiconductor device formed on a semiconductor substrate. The semiconductor device comprises a channel comprising an epitaxial layer that forms an outgrowth above the surface of the semiconductor substrate, and a gate material formed over the epitaxial layer. In some embodiments, a method of forming a semiconductor device is disclosed. The method comprises etching the surface of a semiconductor substrate to form a recess between first and second isolation structures, forming an epitaxial layer within the recess that forms an outgrowth above the surface of the semiconductor substrate, and forming a gate material over the epitaxial layer. Other embodiments are also disclosed.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yeh Hsu, Chia-Wen Liu, Tsung-Hsing Yu, Ken-Ichi Goto, Shih-Syuan Huang
  • Patent number: 9514930
    Abstract: A semiconductor device includes: a compound semiconductor stack structure including a plurality of compound semiconductor layers stacked over a semiconductor substrate; and a first insulating film covering the surface of the compound semiconductor stack structure, the first insulating film being a silicon nitride film including, on the top side, a first region containing nitrogen element in excess of the stoichiometric ratio.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: December 6, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Kozo Makiyama
  • Patent number: 9231083
    Abstract: A multi-region (81, 83) lateral-diffused-metal-oxide-semiconductor (LDMOS) device (40) has a semiconductor-on-insulator (SOI) support structure (21) on or over which are formed a substantially symmetrical, laterally internal, first LDMOS region (81) and a substantially asymmetric, laterally edge-proximate, second LDMOS region (83). A deep-trench isolation (DTI) wall (60) substantially laterally terminates the laterally edge-proximate second LDMOS region (83). Electric field enhancement and lower source-drain breakdown voltages (BVDSS) exhibited by the laterally edge-proximate second LDMOS region (83) associated with the DTI wall (60) are avoided by providing a doped SC buried layer region (86) in the SOI support structure (21) proximate the DTI wall (60), underlying a portion of the laterally edge-proximate second LDMOS region (83) and of opposite conductivity type than a drain region (31) of the laterally edge-proximate second LDMOS region (83).
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: January 5, 2016
    Assignee: FREESCAL SEMICONDUCTOR INC.
    Inventors: Hongning Yang, Daniel J. Blomberg, Jiang-Kai Zuo
  • Publication number: 20150108600
    Abstract: Disclosed are methods and resulting structures which provide an opening for epitaxial growth, the opening having an associated projection for reducing the size of the contact area on a substrate at which growth begins. During growth, the epitaxial material grows vertically from the contact area and laterally over the projection. The projection provides a stress relaxation region for the lateral growth to reduce dislocation and stacking faults at the side edges of the grown epitaxial material.
    Type: Application
    Filed: October 17, 2013
    Publication date: April 23, 2015
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Song Guo, Yushi Hu, Roy Meade, Sanh D. Tang, Michael P. Violette, David H. Wells
  • Patent number: 8975634
    Abstract: An object is to suppress occurrence of oxygen deficiency. An oxide semiconductor film is formed using germanium (Ge) instead of part of or all of gallium (Ga) or tin (Sn). At least one of bonds between a germanium (Ge) atom and oxygen (O) atoms has a bond energy higher than at least one of bonds between a tin (Sn) atom and oxygen (O) atoms or a gallium (Ga) atom and oxygen (O) atoms. Thus, a crystal of an oxide semiconductor formed using germanium (Ge) has a low possibility of occurrence of oxygen deficiency. Accordingly, an oxide semiconductor film is formed using germanium (Ge) in order to suppress occurrence of oxygen deficiency.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: March 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Motoki Nakashima
  • Patent number: 8933533
    Abstract: According to an embodiment, a solid-state bidirectional switch includes a first and a second power field-effect transistor electrically connected anti-serial with each other. Each of the first and second power field-effect transistors includes a source region, a drain region, a body region forming a pn-junction with the source region and having an inversion channel region, a gate terminal, a drift region between the body region and the drain region and having an accumulation channel region, and a drift control region adjacent to the accumulation channel region. The accumulation channel region is controllable through the drift control region. The solid-state bidirectional switch further includes a controller connected with the gate terminals of the first and second power field-effect transistors.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: January 13, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Mario Feldvoss
  • Patent number: 8907429
    Abstract: A semiconductor device includes a silicon substrate; an element isolation region; an element region including a first well; a contact region; a gate electrode extending from the element region to a sub-region of the element isolation region between the element region and the contact region; a source diffusion region; a drain diffusion region; a first insulating region contacting a lower end of the source diffusion region; a second insulating region contacting a lower end of the drain diffusion region; and a via plug configured to electrically connect the gate electrode with the contact region. The first well is disposed below the gate electrode and is electrically connected with the contact region via the silicon substrate under the sub-region. The lower end of the element isolation region except the sub-region is located lower than the lower end of the first well.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: December 9, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Eiji Yoshida, Akihisa Yamaguchi
  • Patent number: 8836074
    Abstract: A semiconductor memory device includes linear patterns disposed between isolation trenches extending in a first direction in a semiconductor device and having a first crystal direction the same as the semiconductor substrate. A bridge pattern connects at least two adjacent linear patterns and includes a semiconductor material having a second crystal direction different from the first crystal direction. A first isolation layer pattern is disposed in at least one of the isolation trenches in a field region of the semiconductor substrate. Memory cells are disposed on at least one of the linear patterns.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: September 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Kwan You, Seung-Woo Paek, Chung-Il Hyun, Jung-Dal Choi
  • Patent number: 8749018
    Abstract: An integrated semiconductor device is provided. The integrated semiconductor device has a first semiconductor region of a second conductivity type, a second semiconductor region of a first conductivity type forming a pn-junction with the first semiconductor region, a non-monocrystalline semiconductor layer of the first conductivity type arranged on the second semiconductor region, a first well and at least one second well of the first conductivity type arranged on the non-monocrystalline semiconductor layer and an insulating structure insulating the first well from the at least one second well and the non-monocrystalline semiconductor layer. Further, a method for forming a semiconductor device is provided.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: June 10, 2014
    Assignee: Infineon Technologies AG
    Inventors: Matthias Stecher, Hans Weber, Lincoln O'Riain, Birgit von Ehrenwall
  • Patent number: 8692266
    Abstract: A circuit substrate structure including a substrate, a dielectric stack layer, a first plating layer and a second plating layer is provided. The substrate has a pad. The dielectric stack layer is disposed on the substrate and has an opening exposing the pad, wherein the dielectric stack layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer located between the first dielectric layer and the second dielectric layer, and there is a gap between the portion of the first dielectric layer surrounding the opening and the portion of the second dielectric layer surrounding the opening. The first plating layer is disposed at the dielectric stack layer. The second plating layer is disposed at the pad, wherein the gap isolates the first plating layer from the second plating layer.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: April 8, 2014
    Assignee: Optromax Electronics Co., Ltd
    Inventor: Kuo-Tso Chen
  • Patent number: 8546249
    Abstract: A method of depositing polycrystalline silicon exclusively on monocrystalline first silicon surface portions of a substrate surface which besides the first surface portions additionally has insulator surface portions, comprising the steps of depositing boron on the first silicon surface portions in an amount which in relation to the first silicon surface portions respectively corresponds to more than a monolayer of boron, and depositing silicon on the first silicon surface portions treated in that way.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: October 1, 2013
    Assignee: IHP GmbH—Innovations for High Performance
    Inventors: Bernd Tillack, Bernd Heinemann, Yuji Yamamoto
  • Patent number: 8531000
    Abstract: An SOI wafer including: a supporting substrate 1; a BOX layer 2 provided above the supporting substrate 1, the BOX layer 2 being formed by a thermal oxidization; a gettering layer 3 provided immediately on the BOX layer 2 and mainly composed of a silicon which contains one or more of oxygen, carbon and nitrogen and contains at least oxygen; and an S layer 4 in which semiconductor devices are to be formed, the S layer 4 being mainly composed of a monocrystalline silicon.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: September 10, 2013
    Assignee: Panasonic Corporation
    Inventor: Kenji Yoneda
  • Patent number: 8399932
    Abstract: A semiconductor device includes a silicon substrate; an element isolation region; an element region including a first well; a contact region; a gate electrode extending from the element region to a sub-region of the element isolation region between the element region and the contact region; a source diffusion region; a drain diffusion region; a first insulating region contacting a lower end of the source diffusion region; a second insulating region contacting a lower end of the drain diffusion region; and a via plug configured to electrically connect the gate electrode with the contact region. The first well is disposed below the gate electrode and is electrically connected with the contact region via the silicon substrate under the sub-region. The lower end of the element isolation region except the sub-region is located lower than the lower end of the first well.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: March 19, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Eiji Yoshida, Akihisa Yamaguchi
  • Patent number: 8389995
    Abstract: A method for producing a solid-state semiconducting structure, includes steps in which: (i) a monocrystalline substrate is provided; (ii) a monocrystalline oxide layer is formed, by epitaxial growth, on the substrate; (iii) a bonding layer is formed by steps in which: (a) the impurities are removed from the surface of the monocrystalline oxide layer; (b) a semiconducting bonding layer is deposited by slow epitaxial growth; and (iv) a monocrystalline semiconducting layer is formed, by epitaxial growth, on the bonding layer so formed. The solid-state semiconducting heterostructures so obtained are also described.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: March 5, 2013
    Assignee: Centre National de la Recherche Scientifique (C.N.R.S.)
    Inventors: Guillaume Saint-Girons, Ludovic Largeau, Gilles Patriarche, Philippe Regreny, Guy Hollinger
  • Patent number: 8334451
    Abstract: A photovoltaic (PV) cell device comprises a first semiconductor substrate; a second semiconductor substrate bonded to the first semiconductor substrate; an insulating layer provided between the first and second substrates to electrically isolate the first substrate from the second substrate; a plurality of PV cells defined on the first substrate, each PV cell including a n-type region and a p-type region; a plurality of vertical trenches provided in the first substrate to separated the PV cells, the vertical trenches terminating at the insulating layer; a plurality of isolation structures provided within the vertical trenches, each isolation structure including a first isolation layer including oxide and a second isolation layer including polysilicon; and an interconnect layer patterned to connect the PV cells to provide X number of PV cells in series and Y number of PV cells in parallel.
    Type: Grant
    Filed: October 4, 2004
    Date of Patent: December 18, 2012
    Assignee: IXYS Corporation
    Inventors: Nestore Polce, Ronald P. Clark, Nathan Zommer
  • Patent number: 8242605
    Abstract: In a semiconductor device having an LDMOSFET, a source electrode is at the back surface thereof. Therefore, to reduce electric resistance between a source contact region in the top surface and the source electrode at the back surface, a poly-silicon buried plug is provided which extends from the upper surface into a P+-type substrate through a P-type epitaxial layer, and is heavily doped with boron. Dislocation occurs in a mono-crystalline silicon region around the poly-silicon buried plug to induce a leakage failure. The semiconductor device has a silicon-based plug extending through the boundary surface between first and second semiconductor layers having different impurity concentrations. At least the inside of the plug is a poly-crystalline region. Of the surface of the poly-crystalline region, the portions located on both sides of the foregoing boundary surface in adjacent relation thereto are each covered with a solid-phase epitaxial region.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: August 14, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroyuki Arie, Nobuaki Umemura, Nobuyoshi Hattori, Nobuto Nakanishi, Kimio Hara, Kyoya Nitta, Makoto Ishikawa
  • Patent number: 8106436
    Abstract: In one embodiment, a semiconductor device is formed having a trench structure. The trench structure includes a single crystalline semiconductor plug formed along exposed upper surfaces of the trench. In one embodiment, the single crystalline semiconductor plug seals the trench to form a sealed core.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: January 31, 2012
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gordon M. Grivna, Gary H. Loechelt, John Michael Parsey, Jr., Mohammed Tanvir Quddus
  • Patent number: 8049296
    Abstract: A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation portion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: November 1, 2011
    Assignee: Honda Motor Co., Ltd.
    Inventors: Nobuaki Miyakawa, Takanori Maebashi, Takahiro Kimura
  • Patent number: 7923807
    Abstract: A semiconductor device comprises a semiconductor substrate of the first conductivity type. A well layer of the first conductivity type is selectively formed on the semiconductor substrate. A first diffused layer of the second conductivity type is selectively formed on the well layer. A second diffused layer of the second conductivity type is formed on the well layer apart from the first diffused layer. A control electrode is formed on an insulating film between the first diffused layer and the second diffused layer. A main electrode is formed on each of the first diffused layer and the second diffused layer. A first trench is formed in the semiconductor substrate surrounding the well layer. A third diffused layer of the second conductivity type is formed contacting to the first trench. The second diffused layer and the third diffused layer are electrically kept at the same potential.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: April 12, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutoshi Nakamura
  • Patent number: 7816264
    Abstract: A wafer processing method having a step of reducing the thickness of a wafer in only a device forming area where semiconductor chips are formed by grinding and etching the back side of the wafer to thereby form a recess on the back side of the wafer. At the same time, an annular projection is formed around the recess to thereby ensure the rigidity of the wafer. Accordingly, handling in shifting the wafer from the back side recess forming step to a subsequent step of forming a back side rewiring layer can be performed safely and easily.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: October 19, 2010
    Assignee: Disco Corporation
    Inventors: Keiichi Kajiyama, Kazuhisa Arai
  • Publication number: 20100252905
    Abstract: A polysilicon-filled isolation trench in a substrate is effective to isolate adjacent semiconductor devices from one another. A silicon nitride cap is provided to protect the polysilicon in the isolation trench from subsequent field oxidation. The cap has lateral boundaries that extend between the side boundaries of the polysilicon and the sidewalls of the trench. Subsequent field oxide regions formed adjacent to the trench establish a gap dimension from the substrate to a top surface of the field oxide regions adjacent to the polysilicon side boundaries that is no less than half of the field oxide thickness.
    Type: Application
    Filed: April 6, 2009
    Publication date: October 7, 2010
    Applicant: POLAR SEMICONDUCTOR, INC.
    Inventor: Noel Hoilien
  • Patent number: 7791161
    Abstract: Structure and method are provided for semiconductor devices. The devices include trenches filled with highly doped polycrystalline semiconductor, extending from the surface into the body of the device for, among other things: (i) reducing substrate current injection, (ii) reducing ON-resistance and/or (iii) reducing thermal impedance to the substrate. For isolated LDMOS devices, the resistance between the lateral isolation wall (tied to the source) and the buried layer is reduced, thereby reducing substrate injection current. When placed in the drain of a lateral device or in the collector of a vertical device, the poly-filled trench effectively enlarges the drain or collector region, thereby lowering the ON-resistance. For devices formed on an oxide isolation layer, the poly-filled trench desirably penetrates this isolation layer thereby improving thermal conduction from the active regions to the substrate. The poly filled trenches are conveniently formed by etch and refill.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: September 7, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ronghua Zhu, Vishnu K. Khemka, Amitava Bose
  • Patent number: 7714318
    Abstract: An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: May 11, 2010
    Assignee: Freescale Semiconductor, Inc
    Inventors: Vance H. Adams, Paul A. Grudowski, Venkat R. Kolagunta, Brian A. Winstead
  • Patent number: 7709925
    Abstract: A semiconductor device, including: a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on the semiconductor substrate; a trench formed in the semiconductor region; a trench diffusion layer of the first conductivity type formed along wall surfaces of the trench; and a buried conductor buried in the trench, wherein an insulation film is further disposed between the wall surfaces of the trench and the buried conductor.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: May 4, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Takahashi, Tomohide Terashima
  • Patent number: 7663173
    Abstract: In a non-volatile memory cell, charge is stored in a fully isolated substrate or floating bulk that forms a storage capacitor with a first poly strip and includes a second poly strip defining a read gate and a poly-filled trench defining a control gate.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: February 16, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Saurabh Desai, Natasha Lavrovskaya, Yuri Mirgorodski, Jeff Babcock
  • Patent number: 7592676
    Abstract: A cell includes a plurality of diffusion region pairs, each of the diffusion region pairs being formed by a first impurity diffusion region which is a constituent of a transistor and a second impurity diffusion region such that the first and second impurity diffusion regions are provided side-by-side in a gate length direction with a device isolation region interposed therebetween. In each of the diffusion region pairs, the first and second impurity diffusion regions have an equal length in the gate width direction and are provided at equal positions in the gate width direction, and a first isolation region portion, which is part of the device isolation region between the first and second impurity diffusion regions, has a constant separation length. In the diffusion region pairs, the first isolation region portions have an equal separation length.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: September 22, 2009
    Assignee: Panasonic Corporation
    Inventor: Kazuyuki Nakanishi
  • Patent number: 7527704
    Abstract: A film structure of a ferroelectric single crystal which can be beneficially used in the fabrication of high-performance electric or electronic parts or devices is prepared by adhering a ferroelectric single crystal plate to a substrate by a conductive adhesive or metal layer, the ferroelectric single crystal plate being polished before or after the adhesion with the substrate.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: May 5, 2009
    Assignee: Ibule Photonics, Inc.
    Inventors: Jaehwan Eun, Sang-Goo Lee, Byungju Choi, Sungmin Rhim
  • Patent number: 7518214
    Abstract: An integrated circuit of a semiconductor device has a line type of pattern that is not prone to serious RC delays. The integrated circuit has a line formed of at least a layer of polycrystalline silicon, a layer of metal having a low sheet resistance, and a layer of a barrier metal interposed between the polycrystalline silicon and the metal having a low sheet resistance, and first spacers disposed on the sides of the line, respectively, and is characterized in that the line has recesses at the sides of the barrier layer and the first spacers fill the recesses. The integrated circuit may constitute a gate line of a semiconductor device. The integrated circuit is formed by forming layers of polycrystalline silicon, metal having a low sheet resistance, and a barrier metal one atop the other, patterning the layers into a line, etching the same to form the recesses, and then forming the first spacers.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: April 14, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-chan Lim, Byung-hee Kim, Tae-ho Cha, Hee-sook Park, Geum-jung Seong
  • Patent number: 7507669
    Abstract: A device includes a top layer having at least two opposing faces, and at least two epitaxially deposited layers, each of the at least two epitaxially deposited layers situated on a respective one of the at least two opposing faces, a combined thickness of the at least two epitaxially deposited layers tuning a gap between the at least two opposing faces.
    Type: Grant
    Filed: August 12, 2004
    Date of Patent: March 24, 2009
    Assignee: Robert Bosch GmbH
    Inventors: Aaron Partridge, Markus Lutz
  • Patent number: 7420258
    Abstract: In one embodiment, a pair of sidewall passivated trench contacts is formed in a substrate to provide electrical contact to a sub-surface feature. A doped region is diffused between the pair of sidewall passivated trenches to provide low resistance contacts.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: September 2, 2008
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gordon M. Grivna, Peter J. Zdebel
  • Patent number: 7420202
    Abstract: An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.
    Type: Grant
    Filed: November 8, 2005
    Date of Patent: September 2, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Vance H. Adams, Paul A. Grudowski, Venkat R. Kolagunta, Brian A. Winstead
  • Patent number: 7382015
    Abstract: A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate are a floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: June 3, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadashi Iguchi, Yoshiaki Himeno, Hiroaki Tsunoda
  • Publication number: 20080105946
    Abstract: Solid state field emission charge storage device is formed by a midgap metal plate and another conductive plate acting as capacitor plates in tunneling relation to a floating charge storage reservoir on a substrate. The plates can be reversibly biased for tunneling of holes or electrons. The devices are tiny islands formed using semiconductor chip fabrication techniques. The islands can form a memory array just as similar islands form a field emitter array for a display screen.
    Type: Application
    Filed: October 24, 2006
    Publication date: May 8, 2008
    Applicant: ATMEL CORPORATION
    Inventor: Bohumil Lojek
  • Patent number: 7291894
    Abstract: In accordance with an embodiment of the present invention, a MOSFET includes at least two insulation-filled trench regions laterally spaced in a first semiconductor region to form a drift region therebetween, and at least one resistive element located along an outer periphery of each of the two insulation-filled trench regions. A ratio of a width of each of the insulation-filled trench regions to a width of the drift region is adjusted so that an output capacitance of the MOSFET is minimized.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: November 6, 2007
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Steven Sapp, Peter H. Wilson
  • Patent number: 7170109
    Abstract: A technique enabling to improve element isolation characteristic of a semiconductor device is provided. An element isolation structure is provided in a semiconductor substrate in which a silicon layer, a compound semiconductor layer and a semiconductor layer are laminated in this order. The element isolation structure is composed of a trench, a semiconductor film, and first and second insulating films. The trench extends through the semiconductor layer and extends to the inside of the compound semiconductor layer. The semiconductor film is provided on the surface of the trench, and the first insulating film is provided on the semiconductor film. The second insulting film is provided on the first insulating film and fills the trench.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: January 30, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Kohei Sugihara, Kazunobu Ota, Hidekazu Oda, Takahashi Hayashi
  • Patent number: 7112850
    Abstract: This invention concerns a non-volatile memory device with a polarizable layer. The apparatus concerns a substrate, a buried oxide layer within the substrate, and a polarizable layer within the substrate. The polarizable layer is formed in a buried oxide layer of a silicon-on-insulator substrate for the fabrication of non-volatile memory. The process of creating the polarizable layer comprises implanting, through the active silicon layer, Si ions into the buried oxide layer at an ion implantation energy selected so that the implanted ion has its peak concentration between 5–50 nm from the silicon/buried oxide interface. The implantation step can occur while externally heating the silicon-on-insulator substrate at a temperature between 25–300 degrees Celsius. An annealing step may be completed to repair any damage the implantation may have created in the silicon-on-insulator substrate.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: September 26, 2006
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Harold L. Hughes, Patrick J. McMarr, Reed K. Lawrence
  • Patent number: 7061069
    Abstract: A first insulation film, a first conductor film, and a cap are sequentially formed on a semiconductor substrate. The first insulation film, the first conductor film, and the cap, and the substrate are etched in the same pattern. A second insulation film is placed in that etched pattern. The cap is removed. A second conductor film is formed on the side face of the second insulation film.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: June 13, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiichi Mori, Mitsuhiro Noguchi
  • Patent number: 7038275
    Abstract: An object of this invention is to provide a buried gate-type semiconductor device in which its gate interval is minimized so as to improve channel concentration thereby realizing low ON-resistance, voltage-resistance depression due to convergence of electrical fields in the vicinity of the bottom of the gate is prevented and further prevention of voltage-resistance depression and OFF characteristic are achieved at the same time. A plurality of gate electrodes 106 each having a rectangular section are disposed in its plan section. The interval 106T between the long sides of the gate electrodes 106 is made shorter than the interval 106S between the short sides thereof. Further, a belt-like contact opening 108 is provided between the short sides of the gate electrode 106, so that P+ source region 100 and N+ source region 104 are in contact with a source electrode. Consequently, the interval 106T between the long sides of the gate electrode 106 can be set up regardless of the width of the contact opening 108.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: May 2, 2006
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Tomoyoshi Kushida
  • Patent number: 7034398
    Abstract: A semiconductor device includes an active element structure that is formed on a semiconductor substrate and has a connection region formed in the surface of the semiconductor substrate. A contact hole extends from a surface of a first insulating film formed on the semiconductor substrate to the connection region. A contact plug is provided in the contact hole. A clearance formed in the contact plug is formed with a buried conductive film consisting of a material different from the contact plug. The buried conductive film has a continuous surface without forming a step with the surface of the contact plug.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: April 25, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Kajita, Kazuyuki Higashi
  • Patent number: 6943426
    Abstract: A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density of the devices can be increased. Also trench constrained doped region diffuse faster and deeper than unconstrained diffusions, thereby reducing the time and temperature needed to complete a desired depth diffusion. The technique may be used for semiconductor devices such as bipolar transistors as well as isolation regions that electrically isolate the devices from each other. In one group of embodiments, a buried layer is formed at an interface between an epitaxial layer and a substrate, at a location generally below the dopant in the mesa.
    Type: Grant
    Filed: August 14, 2002
    Date of Patent: September 13, 2005
    Assignee: Advanced Analogic Technologies, Inc.
    Inventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
  • Patent number: 6885079
    Abstract: An electronic device supported on a semiconductor substrate. The semiconductor device includes a diffusion area in the substrate and a polysilicon layer extending over the substrate and contacting the diffusion area. The electronic device further includes a conductive contact covering and contacting both the polysilicon layer and the diffusion area. Therefore, the semiconductor device disclosed in this invention includes poly-to-diffusion connection for a semiconductor device that has a diffusion are and a polysilicon area. The semiconductor device further includes a contact that covers both the diffusion area and the polysilicon area with a contact filling material forming the connection between these two areas.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: April 26, 2005
    Inventor: Jeng-Jye Shau
  • Patent number: 6878989
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, on which a semiconductor layer having a trench extending in the depth direction toward the semiconductor substrate is formed. A first region of the first conductivity type is formed in the depth direction along one side of the trench in the semiconductor layer and contacts the semiconductor substrate. A second region of the first conductivity type is formed in a surface area of the semiconductor layer and close to the trench and contacts the first region. A third region of the second conductivity type is formed in the surface area of the semiconductor layer. A fourth region of the first conductivity type is formed in a surface area of the third region. A gate insulation film and a gate electrode are provided on the surface of the third region between the second region and the fourth region.
    Type: Grant
    Filed: May 22, 2002
    Date of Patent: April 12, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Izumisawa, Shigeo Kouzuki, Shinichi Hodama
  • Patent number: 6876054
    Abstract: An electronic device, a method of manufacturing an electronic device and an integrated circuit that employs at least one such electronic device to couple first and second circuits together in an isolated fashion. In one embodiment, the electronic device includes a first conductive channel, a second conductive channel and an isolation layer. The isolation layer is formed from and over the first conductive channel, interposing the first conductive channel and the second conductive channel and configured both to isolate the second conductive channel electrically from the first conductive channel and transfer momentum between charge carriers in the first conductive channel and charge carriers in the second conductive channel.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: April 5, 2005
    Assignee: Agere Systems Inc.
    Inventors: Shye Shapira, William B. Wilson, Gerard Zaneski
  • Patent number: 6861326
    Abstract: The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion and at least partially filled with a semiconductive material that comprises at least one atomic percent of an element other than silicon. The mask is removed and a first semiconductor circuit component is formed over the first portion of the substrate. Also, a second semiconductor circuit component is formed over the semiconductive material that at least partially fills the trench. The invention also includes semiconductor constructions.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: March 1, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, Er-Xuan Ping
  • Patent number: 6815799
    Abstract: A semiconductor integrated circuit device with built-in spark killer diodes suitable for output transistor protection has a problem such that a leakage current to the substrate is great and a desirable forward current cannot be obtained. In a semiconductor integrated circuit device of the present invention, P+-type first and second diffusion regions 34 and 32 are formed on the surface of a second epitaxial layer 23 in a partly overlapping manner. And, by a connection to an anode electrode 39 at a part immediately over the P+-type second diffusion region 32, a parasitic resistance R1 is made greater than a parasitic resistance R2. Thus, an operation of a parasitic transistor TR2 that causes a leakage current to a substrate 21 is suppressed, whereby leakage current can be greatly reduced.
    Type: Grant
    Filed: May 14, 2003
    Date of Patent: November 9, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shigeaki Okawa, Koichiro Ogino
  • Patent number: 6762447
    Abstract: A dynamic random access memory (DRAM) formed in a semiconductor body has individual pairs of memory cells that are isolated from one another by a vertical electrical isolation trench and are isolated from support circuitry. The isolation trench has sidewalls and upper and lower portions, and encircles an area of the semiconductor body which contains the memory cells. This electrically isolates pairs of memory cells from each other and from the support circuitry contained within the semiconductor body but not located within the encircled area. The lower portion of the isolation trench is filled with an electrically conductive material that has sidewall portions thereof which are at least partly separated from the sidewalls of the lower portion of the trench by a first electrical insulator, and that has a lower portion that is in electrical contact with the semiconductor body. The upper portion of the isolation trench is filled with a second electrical insulator.
    Type: Grant
    Filed: February 5, 1999
    Date of Patent: July 13, 2004
    Assignees: Infineon Technologies North America Corp., International Business Machines Corporation
    Inventors: Jack A. Mandelman, Rama Divakaruni, Giuseppe Larosa, Ulrike Gruening, Carl Radens
  • Patent number: 6759726
    Abstract: A method of forming an isolating wall in a semiconductor substrate of a first conductivity type, including the steps of boring in the substrate separate recesses according to the desired isolating wall contour; filling the recesses with a material containing a dopant of the second conductivity type; and performing an anneal step so that regions of the second conductivity type diffused from neighboring recesses join. A first series of recesses is formed from the upper surface and a second series of recesses is formed from the lower surface. The recesses have a substantially rectangular section, the large dimension of which is perpendicular to the alignment of the recesses and a depth smaller than or equal to the half-thickness of the substrate.
    Type: Grant
    Filed: October 22, 1999
    Date of Patent: July 6, 2004
    Assignee: STMicroelectronics S.A.
    Inventors: Christine Anceau, Fabien Pierre, Olivier Bonnaud