Integrated Circuit Structure With Electrically Isolated Components Patents (Class 257/499)
  • Patent number: 10997347
    Abstract: In a method, based on an operating condition of a region of an integrated circuit (IC), a first relationship between a temperature and heating power of the region is determined. Based on a cooling capacity of the region, a second relationship between the temperature and cooling power of the region is determined. Based on the first relationship and the second relationship, it is determined whether the region is thermally stable. In response to a determination that the region is thermally unstable, at least one of a structure or the operating condition of the region is changed. At least one of the determination of the first relationship, the determination of the second relationship, the determination of thermally stability of the region, or the change of at least one of the structure or the operating condition of the region is executed by a processor.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wan-Yu Lo, Chung-Hsing Wang, Chin-Shen Lin, Kuo-Nan Yang
  • Patent number: 10978440
    Abstract: A method includes identifying fingers of a first device and fingers of a second device. The method includes grouping the fingers of the first device into a first finger group and a second finger group, wherein the first finger group is electrically connected to the second finger group. The method further includes positioning the first finger group extends across a first doped region. The method further includes positioning the second finger group extends across a second doped region, wherein the second doped region has a same dopant type as the first doped region. The method further includes grouping the fingers of the second device into a third finger group and a fourth finger group, wherein the third finger group is electrically connected to the fourth finger group. The method further includes positioning the third finger group and the fourth finger group extending across the second doped region.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shou-En Liu, Chun-Wei Chang, Bi-Ling Lin, Yung-Sheng Tsai, Jiaw-Ren Shih
  • Patent number: 10964801
    Abstract: A semiconductor device includes a substrate, at least one active semiconductor fin, at least one first dummy semiconductor fin, and at least one second dummy semiconductor fin. The active semiconductor fin is disposed on the substrate. The first dummy semiconductor fin is disposed on the substrate. The second dummy semiconductor fin is disposed on the substrate and between the active semiconductor fin and the first dummy semiconductor fin. A top surface of the first dummy semiconductor fin and a top surface of the second dummy semiconductor fin are curved in different directions.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Sheng Li, Hsin-Chieh Huang, Chi-Wen Liu
  • Patent number: 10937729
    Abstract: Described herein is an integrated circuit device comprising a conductive line structure including a bit line and an insulating capping pattern; and an insulating spacer covering a side wall of the conductive line structure, the insulating spacer including an inner spacer and a char spacer. To form the insulating spacer, a polymer brush pattern may be chemically bonded to the inner spacer to cover a side wall of the conductive line structure; a first insulating spacer film covering the inner spacer and the polymer brush pattern may be formed; and a char spacer may be formed from the polymer brush pattern by pyrolyzing the polymer brush pattern in the absence of oxygen.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: March 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok-han Park
  • Patent number: 10923462
    Abstract: A semiconductor device is disclosed including one or more integrated memory modules. Each integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the first die may be flip-chip bonded to the second die.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: February 16, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Toshiki Hirano, Gokul Kumar, Akio Nishida, Yan Li, Michael Mostovoy
  • Patent number: 10892273
    Abstract: A semiconductor memory device of an embodiment includes a stacked body having a stepped portion in which a plurality of metal layers is stacked via an insulating layer, and end portions of the plurality of metal layers are formed in a stepwise manner, a plurality of columnar portions arranged in steps of the stepped portion and penetrating the stepped portion, and a band portion provided near a leading end portion of the metal layer of a lowermost step of the stepped portion, the band portion extending in a first direction along the leading end portion and dividing the stacked body and a peripheral region of the stacked body, in which a coverage of the columnar portions arranged in the lowermost step is larger than a coverage of the columnar portions arranged in an upper step adjacent to the lowermost step only in a second direction toward a region where memory cells are arranged.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: January 12, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Sachiyo Ito, Ken Furubayashi, Hiroshi Yoshimura
  • Patent number: 10892359
    Abstract: A semiconductor device includes: a semiconductor base 10 in which a first trench 101 is formed in a mesh-like shape in a plan view and a second trench 102 is formed in a mesh opening surrounded by the first trench 101; a first semiconductor element 1 which is formed in the semiconductor base 10 and includes a first gate electrode 81 provided within the first trench 101; and a second semiconductor element 2 which is formed in the semiconductor base 10 and includes a second gate electrode 82 provided within the second trench 102 surrounded by the first gate electrode 81.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: January 12, 2021
    Assignee: SANKEN ELECTRIC CO., LTD.
    Inventors: Shunsuke Fukunaga, Taro Kondo
  • Patent number: 10879235
    Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer includes a first conductive layer and a first dielectric layer formed on the first conductive layer, the first device layer being formed on a substrate. The second device layer includes a second conductive layer, the second device layer being formed on the first device layer. The inter-level connection structure includes one or more conductive materials and configured to electrically connect to the first conductive layer and the second conductive layer, the inter-level connection structure penetrating at least part of the first dielectric layer. The first conductive layer is configured to electrically connect to a first electrode structure of a first semiconductor device within the first device layer.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Tang Lin, Clement Hsingjen Wann, Neng-Kuo Chen
  • Patent number: 10867103
    Abstract: A method of forming an integrated circuit is provided. The method includes several operations. A semiconductor substrate is received, and a conductive grid is disposed over the semiconductor substrate, wherein the conductive grid includes a plurality of non-continuous conductive lines. A plurality of first conductive lines and a plurality of second conductive lines are selected from the plurality of non-continuous conductive lines. The plurality of second conductive lines is replaced by a plurality of third conductive lines respectively, wherein a space between adjacent third conductive lines is greater than a space between adjacent second conductive lines. A system configured to perform the method is also provided.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hiranmay Biswas, Kuo-Nan Yang, Chung-Hsing Wang
  • Patent number: 10867913
    Abstract: A first layer is located over a substrate. The first layer includes a first dielectric component and a first conductive component. A first etching stop layer is located over the first dielectric component. A metal capping layer is located over the first conductive component. A second etching stop layer is located over the first etching stop layer and over the metal capping layer. A second layer is located over the second etching stop layer. The second layer includes a second dielectric component and a second conductive component. A third conductive component electrically interconnects the second conductive component to the first conductive component.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Hsu Wu, Hai-Ching Chen, Jung-Hsun Tsai, Shau-Lin Shue, Tien-I Bao
  • Patent number: 10861965
    Abstract: The present embodiments provide a region of a semiconductor device comprising a plurality of power transistor cells configured as trench MOSFETs in a semiconductor substrate. At least one active power transistor cell further includes a trenched source region wherein a trench bottom surface of the trenched source contact is covered with an insulation layer and layer of a conductive material on top of the insulation layer, to function as an integrated pseudo Schottky barrier diode in the active power transistor cell.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: December 8, 2020
    Assignee: Renesas Electronics America Inc.
    Inventor: Shengling Deng
  • Patent number: 10843637
    Abstract: A vibration device includes: a base substrate which is a first conductivity type semiconductor substrate; a lid substrate; a vibration element disposed between the base substrate and the lid substrate; a wiring disposed on a surface of the base substrate at the lid substrate side; and a coupling member that electrically couples the wiring and the vibration element to each other. The base substrate includes a second conductivity type well, which is different from the first conductivity type, and a first conductivity type first contact area that is disposed in the well and that has a first contact surface which is a part of the surface. The wiring and the coupling member are in contact with the first contact surface, and are electrically coupled to each other via the first contact area.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: November 24, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Koichi Mizugaki
  • Patent number: 10825738
    Abstract: Semiconductor arrangements and methods of manufacturing the same. The semiconductor arrangement may include: a substrate including a base substrate, a first semiconductor layer on the substrate, and a second semiconductor layer on the first semiconductor layer; first and second fin structures formed on the substrate and extending in the same straight line, each of the first and second fin structures including at least portions of the second semiconductor layer; a first isolation part formed around the first and second fin structures on opposite sides of the straight line; first and second FinFETs formed on the substrate based on the first and second fin structures respectively; and a second isolation part between the first and second fin structures and intersecting the first and second fin structures to isolate the first and second fin structures from each other.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: November 3, 2020
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 10825717
    Abstract: A method for reducing transistor sensitivity to shallow trench isolation defects (STI) includes filling a trench formed in a substrate of a semiconductor device, at least partially, with a first oxide, the trench defines an STI and includes a defect extending from the substrate. A mask defines a planar area within the isolation region including a first lateral distance between an edge of the mask and an edge of the isolation region. The first oxide is at least partially removed beneath the planar area with an oxide etch to expose a top portion of the defect. The top portion of the defect is removed with a semiconductor etch. After removing the top portion of the defect, the trench is at least partially filled with a second oxide. A field plate of a split-gate transistor is formed over the STI.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: November 3, 2020
    Assignee: NXP B.V.
    Inventors: Ronghua Zhu, Eric Ooms, Xin Lin
  • Patent number: 10796943
    Abstract: A manufacturing method of a semiconductor structure includes the following steps. A patterned mask layer is formed on a semiconductor substrate. An isolation trench is formed in the semiconductor substrate by removing a part of the semiconductor substrate. A liner layer is conformally formed on an inner sidewall of the isolation trench. An implantation process is performed to the liner layer. The implantation process includes a noble gas implantation process. An isolation structure is at least partially formed in the isolation trench after the implantation process. An etching process is performed to remove the patterned mask layer after forming the isolation structure and expose a top surface of the semiconductor substrate. A part of the liner layer formed on the inner sidewall of the isolation trench is removed by the etching process. The implantation process is configured to modify the etch rate of the liner layer in the etching process.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: October 6, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Liang Ye, Chun-Wei Yu, Yu-Ren Wang, Shi-You Liu, Shao-Hua Hsu
  • Patent number: 10763262
    Abstract: The present disclosure provides a method for preparing a semiconductor structure. The method includes the following steps. A substrate including a conductive layer formed thereon is provided. The conductive layer is patterned to form a plurality of conductive patterns extending along a first direction. A cap layer is conformally formed to cover the plurality of conductive patterns. A patterned hard mask is formed over the cap layer. The plurality of conductive patterns are etched through the patterned hard mask to form a plurality of conductive islands. In some embodiments, the plurality of conductive islands are separated from each other by a plurality of first gaps along the first direction. In some embodiments, the plurality of conductive islands are separated from each other by the cap layer and a plurality of second gaps along a second direction that is different from the first direction.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: September 1, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Patent number: 10741436
    Abstract: A method for making a semiconductor device may include forming first and second spaced apart shallow trench isolation (STI) regions in a semiconductor substrate, and forming a superlattice on the semiconductor substrate and extending between the first and second STI regions. The superlattice may include stacked groups of layers, each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming a first semiconductor stringer comprising a non-monocrystalline body at an interface between a first end of the superlattice and the first STI region, and forming a gate above the superlattice.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: August 11, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Robert John Stephenson, Scott A. Kreps, Robert J. Mears, Kalipatnam Vivek Rao
  • Patent number: 10698022
    Abstract: In accordance with an embodiment of the present invention, a method of testing a plurality of semiconductor devices includes applying a stress voltage having a peak voltage on a shield line disposed over a substrate. The substrate has functional circuitry of a semiconductor device. A fixed voltage is applied to a first metal line disposed above the substrate adjacent the shield line. The first metal line is coupled to the functional circuitry and is configured to be coupled to a high voltage node during operation. The peak voltage is greater than a maximum fixed voltage. The shield line separates the first metal line from an adjacent second metal line configured to be coupled to a low voltage node during operation. The method further includes measuring a current through the shield line in response to the stress voltage, determining the current through the shield line of the semiconductor device, and based on the determination, identifying the semiconductor device as passing the test.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: June 30, 2020
    Assignee: Infineon Technologies AG
    Inventors: Michael Roehner, Stefano Aresu
  • Patent number: 10693845
    Abstract: A computer-implemented method includes receiving download description information for an application from a network using an encrypted communications channel, wherein the download description information includes download address information specifying a network address from which application packages associated with the particular application can be retrieved; and downloading an application package associated with the particular application from the network address specified in the download address information, wherein the application package is downloaded using an unencrypted communications channel.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: June 23, 2020
    Assignee: Alibaba Group Holding Limited
    Inventor: Jiajia Li
  • Patent number: 10658409
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate having a front surface and a back surface facing opposite to the front surface; a filling material extending from the front surface into the semiconductor substrate without penetrating through the semiconductor substrate, the filling material including an upper portion and a lower portion, the upper portion being in contact with the semiconductor substrate; and an epitaxial layer lined between the lower portion of the filling material and the semiconductor substrate. An associated manufacturing method is also disclosed.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. U.
    Inventors: Sheng-Chan Li, I-Nan Chen, Tzu-Hsiang Chen, Yu-Jen Wang, Yen-Ting Chiang, Cheng-Hsien Chou, Cheng-Yuan Tsai
  • Patent number: 10651202
    Abstract: An integrated circuit is provided with several superimposed levels of transistors, the circuit including an upper level provided with transistors having a rear gate electrode laid out on a first semiconducting layer, and a second semiconducting layer, a first transistor among the transistors of the upper level being provided with a contact pad traversing the second semiconducting layer, the contact pad being connected to a connection zone disposed between the first semiconducting layer and the second semiconducting layer, the first transistor being polarised by and connected to at least one power supply line disposed on a side of a front face of the second semiconducting layer that is opposite to the rear face.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: May 12, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Francois Andrieu, Perrine Batude, Maud Vinet
  • Patent number: 10615135
    Abstract: A multi-cell transistor includes a semiconductor structure, a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor extending in a first direction in the semiconductor structure, wherein the unit cell transistors are spaced apart from each other along a second direction, and an isolation structure that is positioned between a first group of the unit cell transistors and a second group of the unit cell transistors and that extends above the semiconductor structure.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: April 7, 2020
    Assignee: Cree, Inc.
    Inventors: Frank Trang, Qianli Mu, Haedong Jang, Zulhazmi Mokhti
  • Patent number: 10593688
    Abstract: A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner. The inter-gate dielectric structure may be disposed between the first gate conductor and the second gate conductor, and may include two or more dielectric films disposed in an alternating manner. The second gate conductor is formed in an L shape such that the second gate has a relatively low aspect ratio, which allows for a reduction in spacing between adjacent gates, while maintaining the required electrical isolation between the gates and contacts that may subsequently be formed.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: March 17, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Scott A. Bell, Chun Chen, Lei Xue, Shenqing Fang, Angela T. Hui
  • Patent number: 10580860
    Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Mark Armstrong, Rafael Rios, Abhijit Jayant Pethe, Willy Rachmady
  • Patent number: 10574150
    Abstract: A power conversion apparatus includes: a board; a first electronic component disposed on a first surface of the board; and a temperature sensor disposed on a second surface of the board which is opposite to the first surface. The power conversion apparatus may further include a first heat conductive member disposed between the first electronic component and the temperature sensor.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: February 25, 2020
    Assignee: KABUSHIKI KAISHA YASKAWA DENKI
    Inventors: Yasunori Yamanaka, Junichi Yokoyama, Satoru Kawano
  • Patent number: 10553603
    Abstract: A semiconductor device according to an embodiment includes a substrate, first to third conductors, and first and second contacts. The first conductor is provided in a first layer above the substrate. The first contact extends in a first direction, and is provided on the first conductor. The second conductor is provided in the first layer and is insulated from the first conductor. The third conductor is provided between the second conductor and the substrate. The second contact extends in the first direction through the second conductor, and is provided on the third conductor. A width of the second contact, as viewed in a second direction, differs between a portion above a boundary face that is included in the first layer and is parallel to the surface of the substrate, and a portion that is below the boundary face.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: February 4, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Tetsuya Yamashita
  • Patent number: 10546810
    Abstract: Described herein is an integrated circuit device comprising a conductive line structure including a bit line and an insulating capping pattern; and an insulating spacer covering a side wall of the conductive line structure, the insulating spacer including an inner spacer and a char spacer. To form the insulating spacer, a polymer brush pattern may be chemically bonded to the inner spacer to cover a side wall of the conductive line structure; a first insulating spacer film covering the inner spacer and the polymer brush pattern may be formed; and a char spacer may be formed from the polymer brush pattern by pyrolyzing the polymer brush pattern in the absence of oxygen.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: January 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok-han Park
  • Patent number: 10541324
    Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate, a buffer layer that includes at least one additional layer formed over the substrate, a channel layer formed over the buffer layer, a barrier layer formed over the channel layer forming a channel, a gate electrode disposed over the substrate electrically coupled to the channel, and an ohmic contact recessed into the barrier layer. A method for fabricating the semiconductor device includes forming a semiconductor substrate that includes a mixed crystal layer, creating an isolation region that defines an active region along an upper surface of the semiconductor substrate, forming a gate electrode over the semiconductor substrate in the active region, and recessing an ohmic contact into the semiconductor substrate.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: January 21, 2020
    Assignee: NXP USA, Inc.
    Inventors: Bruce M. Green, Darrell G. Hill, Karen E. Moore
  • Patent number: 10529664
    Abstract: An electronic device includes a first substrate, a first conductor, a first insulation layer, a second substrate, a second conductor, a second insulation layer. The first substrate has a first surface. The first conductor is disposed on the first surface of the first substrate. The first insulation layer is on the first conductor. The second substrate has a second surface facing toward the first surface of the first substrate. The second conductor is disposed on the second surface of the second substrate. The second insulation layer is on the second conductor. The first insulation layer is in contact with a sidewall of the second conductor. The second insulation layer is in contact with a sidewall of the first conductor. A coefficient of thermal expansion (CTE) of the first insulation layer is greater than a CTE of the first conductor.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: January 7, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 10510765
    Abstract: A memory device and a method for fabricating the same are provided. The memory device includes a semiconductor substrate, well regions, logic transistors, a high-voltage transistor, and a storage transistor. The well regions are disposed in the semiconductor substrate and include logic well regions, a high-voltage well region, and a memory well region. The logic transistors are disposed on the logic well regions. Each the logic transistors includes a high-k metal gate structure. The storage transistor is disposed on the memory well region, and includes a charge storage structure and a high-k metal gate structure. In the method for fabricating the memory device, a high-k first process or high-k last process is used for the formation of the high-k metal gate structures of the memory device. Because all the logic transistors and the storage transistor are formed with the high-k metal gate structure, a number of masks is decreased.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Chi Wu, Chung-Jen Huang
  • Patent number: 10475766
    Abstract: Examples herein include a solid state drive microelectronics package assembly including a substrate and a plurality of microelectronic components coupled to the substrate. The plurality of microelectronic components may be being separated from one another end-to-end by a component gap. The microelectronics package may further include a die package coupled to the substrate, wherein the die package extends across the component gap and is vertically disposed between the plurality of microelectronic components and the substrate. In some examples, the microelectronics components and the die package are each coupled to the substrate by a plurality of connection components (e.g. a solder ball array). The plurality of connection components may be arranged on the microelectronics components to define one or more open areas devoid of any connection components. The die package may be positioned/nested within the one or more open areas to increase overall microelectronic component density of the microelectronics package.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: November 12, 2019
    Assignee: INTEL CORPORATION
    Inventor: Bilal Khalaf
  • Patent number: 10453857
    Abstract: A three-dimensional semiconductor device includes gate electrodes including pad regions sequentially lowered by a first step portion in a first direction and sequentially lowered by a second step portion in a second direction perpendicular to the first direction, the second step portion being lower than the first step portion, wherein a length of a single pad region among pad regions sequentially lowered by the second step portion in the second direction is less than a length of a remainder of the pad regions in the second direction.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: October 22, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Hwan Lee, Jee Yong Kim, Seok Jung Yun, Ji Hyeon Lee
  • Patent number: 10446606
    Abstract: A memory device includes a semiconductor device on a wafer. The semiconductor device includes a gate structure, a first source/drain region, and a second source/drain region. The gate structure is on the first side of the wafer. The first source/drain region is also on the first side of the wafer, and contacts a first end of the gate structure. The second source/drain region is on the second side of the wafer and extends into the first side to contact a second end of the gate structure. The memory device further includes a memory storage element on the second side of the wafer. The memory storage element contacts the second source/drain region.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: October 15, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Arvind Kumar, Joshua M. Rubin
  • Patent number: 10424570
    Abstract: A power conversion apparatus performs power conversion. The power conversion apparatus includes a semiconductor module and a cooler. The semiconductor module includes an insulated-gate bipolar transistor, a metal-oxide-semiconductor field-effect transistor, and a lead frame. The insulated-gate bipolar transistor and the metal-oxide-semiconductor field-effect transistor are connected in parallel to each other and provided on the same lead frame. The cooler has a coolant flow passage. The coolant flow passage extends such that the coolant flow passage and the lead frame of the semiconductor module are opposed to each other. The semiconductor module is configured such that the metal-oxide-semiconductor field-effect transistor is not disposed further downstream than the insulated-gate bipolar transistor in a flow direction of a coolant in the coolant flow passage of the cooler.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: September 24, 2019
    Assignee: DENSO CORPORATION
    Inventors: Mitsunori Kimura, Hiroshi Shimizu, Kengo Mochiki, Yasuyuki Ohkouchi, Yuu Yamahira, Tetsuya Matsuoka, Kazuma Fukushima
  • Patent number: 10381478
    Abstract: A substrate of the silicon on insulator type includes a semi-conducting film disposed on a buried insulating layer which is disposed on an unstressed silicon support substrate. The semi-conducting film includes a first film zone of tensile-stressed silicon and a second film zone of tensile-relaxed silicon. Openings through the buried insulating layer permit access to the unstressed silicon support substrate under the first and second film zones. An N channel transistor is formed from the first film zone and a P channel transistor is formed from the second film zone. The second film zone may comprise germanium enriched silicon forming a compressive-stressed region.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: August 13, 2019
    Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Frederic Boeuf, Olivier Weber
  • Patent number: 10354740
    Abstract: Disclosed is a three-dimensional semiconductor device including a stack structure on a substrate and including electrodes that are vertically stacked on top of each other on a first region of a substrate, a vertical structure penetrating the stack structure and including a first semiconductor pattern, a data storage layer between the first semiconductor pattern and at least one of the electrodes, a transistor on a second region of the substrate, and a first contact coupled to the transistor. The first contact includes a first portion and a second portion on the first portion. Each of the first portion and the second portions has a diameter that increases with an increasing vertical distance from the substrate. A diameter of an upper part of the first portion is greater than a diameter of a lower part of the second portion.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: July 16, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-Ho Kim, Jihwan Yu, Seunghyun Cho
  • Patent number: 10313157
    Abstract: An apparatus includes: a semiconductor die including a first I/O (input/output) pad, a second I/O pad, a switch, and an internal processor, wherein the switch is configured to short the first I/O pad to the second I/O pad when a logical signal is asserted; and a semiconductor package including a first bond pad configured to electrically connect to the first I/O pad, a second bond pad configured to electrically connect to the second I/O pad, a first port configured to electrically connect to a pin of a multi-lane, multi-mode connector, a second port configured to electrically connect to an external processor, a first routing path configured to electrically connect the first port to the first bond pad, and a second routing path configured to electrically connect the second port to the second bond pad, wherein the external processor is configured to process an electrical signal at the second port in accordance with a first protocol when the logical signal is asserted, and the internal processor is configured to
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: June 4, 2019
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chi-Kung Kuan, Chia-Liang (Leon) Lin
  • Patent number: 10297495
    Abstract: A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the first conductive structure, forming a second conductive structure a distance apart from the first conductive structure with the insulation layer therebetween, first removing a portion of the insulation layer by performing a first dry cleaning operation, second removing a reactant product used in the first dry cleaning operation or a first byproduct generated as a result of the first dry cleaning operation by performing a first purge operation, and third removing at least a portion of the remaining insulation layer by performing a second dry cleaning operation to form an air gap between the first and second conductive structures.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: May 21, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mong-sup Lee, Sang-jun Lee, Yoon-ho Son
  • Patent number: 10292264
    Abstract: Provided are an insulating ceramic paste, a ceramic electronic component, and a method for producing the ceramic electronic component that allow prevention of solder shorts between narrow-pitch terminal electrodes and suppression of generation of cracks in an insulator covering a portion of terminal electrodes during a firing step. The ceramic electronic component includes a ceramic multilayer substrate, terminal electrodes formed on a surface of the ceramic multilayer substrate, and an insulating ceramic film formed on the surface of the ceramic multilayer substrate so as to cover a portion of the terminal electrodes. An exposed surface portion (celsian-crystal-rich layer) of the insulating ceramic film has a thermal expansion coefficient that is lower than the thermal expansion coefficient of the ceramic multilayer substrate.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: May 14, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Sumiyo Nakamura, Takahiro Sumi, Takahiro Oka
  • Patent number: 10176287
    Abstract: The invention discloses an STI stress effect modeling method and device of an MOS device, and belongs to the technical field of parameter extraction modeling of devices. The method comprises the following steps: introducing the influence of temperature parameters on the STI stress effect of the MOS device, so as to form a function showing that the STI stress effect of the MOS device changes along with the temperature parameters; extracting the model parameter Model1 of the MOS device at normal temperature; on the basis of the Model1, extracting the parameter Model2 that the STI stress affects the properties of the MOS device at normal temperature; and on the basis of the Model2, extracting fitting parameters of the MOS device in the function so as to acquire final model parameters. The device comprises a first module, a second module, a third module and a fourth module.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: January 8, 2019
    Assignee: The Institute of Microelectronics of Chinese Academy of Science
    Inventors: Jianhui Bu, Shuzhen Li, Jiajun Luo, Zhengsheng Han
  • Patent number: 10135445
    Abstract: A semiconductor integrated circuit device, including a semiconductor layer of a first conductivity type, a first well region of a second conductivity type, a second well region of the second conductivity type, and a third well region of the first conductivity type. The device further includes an isolation region electrically isolating a predetermined region in the first well region, a first high-concentration region of the second conductivity type, disposed outside the isolation region and inside one of the first well region and the second well region, and a second high-concentration region of the second conductivity type, disposed inside the isolation region and inside one of the first well region and the second well region. The first and second high-concentration regions each have an impurity concentration that is higher than that of the first well region.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: November 20, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masaharu Yamaji
  • Patent number: 10134945
    Abstract: A method for wafer to wafer bonding for III-V and CMOS wafers is provided. A silicon carrier wafer is provided having an epitaxial III-V semiconductor region and an oxide region disposed over the wafer top surface, the regions having substantially equal heights. A sidewall of the epitaxial III-V semiconductor region directly contacts a sidewall of the oxide region. A eutectic bonding layer is formed over a top surface of the epitaxial III-V semiconductor region and the oxide region for bonding to the CMOS wafer which contains semiconductor devices. The silicon carrier wafer is removed, and the CMOS wafer is singulated to form a plurality of three-dimensional integrated circuits, each including a CMOS substrate corresponding to a portion of the CMOS wafer and a III-V optical device corresponding to a portion of the III-V epitaxial semiconductor region.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming Chyi Liu, Chen-Hua Yu, Chia-Shiung Tsai, Alexander Kalnitsky, Ru-Liang Lee, Eugene Chen
  • Patent number: 10103165
    Abstract: A memory device includes a gate structure including a plurality of gate electrode layers stacked on an upper surface of a substrate, a plurality of vertical holes extending in a direction perpendicular to the upper surface of the substrate to penetrate through the gate structure, and a plurality of vertical structures in the plurality of vertical holes, respectively, each vertical structure of the plurality of vertical structures including an embedded insulating layer, and a plurality of channel layers separated from each other, the plurality of channel layers being outside the embedded insulating layer.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: October 16, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Hwan Son, Won Chul Jang, Dong Seog Eun, Jae Hoon Jang
  • Patent number: 10103264
    Abstract: A circuit device having differently-strained NMOS and PMOS FinFETs is provided. In an exemplary embodiment, a semiconductor device includes a substrate with a first fin structure and a second fin structure formed thereup. The first fin structure includes opposing source/drain regions disposed above a surface of the substrate; a channel region disposed between the opposing source/drain regions and disposed above the surface of the substrate; and a first buried layer disposed between the channel region and the substrate. The first buried layer includes a compound semiconductor oxide. The second fin structure includes a second buried layer disposed between the substrate and a channel region of the second fin structure, such that the second buried layer is different in composition from the first. For example, the second fin structure may be free of the compound semiconductor oxide.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: October 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Kuo-Cheng Ching
  • Patent number: 10049914
    Abstract: According to various embodiments, a method may include: providing a substrate having a first side and a second side opposite the first side; forming a buried layer at least one of in or over the substrate by processing the first side of the substrate; thinning the substrate from the second side of the substrate, wherein the buried layer includes a solid state compound having a greater resistance to the thinning than the substrate and wherein the thinning stops at the buried layer.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: August 14, 2018
    Assignee: Infineon Technologies AG
    Inventors: Roland Rupp, Hans-Joachim Schulze, Francisco Javier Santos Rodriguez, Iris Moder, Ingo Muri
  • Patent number: 10020316
    Abstract: A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner. The inter-gate dielectric structure may be disposed between the first gate conductor and the second gate conductor, and may include two or more dielectric films disposed in an alternating manner. The second gate conductor is formed in an L shape such that the second gate has a relatively low aspect ratio, which allows for a reduction in spacing between adjacent gates, while maintaining the required electrical isolation between the gates and contacts that may subsequently be formed.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: July 10, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Scott Bell, Chun Chen, Lei Xue, Shenqing Fang, Angela Hui
  • Patent number: 9958348
    Abstract: A micromechanical pressure sensor device and a corresponding manufacturing method. The micromechanical pressure sensor device includes an ASIC wafer having a front side and a rear side, and a rewiring system, formed on the front side of the ASIC wafer, which includes a plurality of stacked strip conductor levels and insulation layers. The pressure sensor device also includes a MEMS wafer having a front side and a rear side, a first micromechanical functional layer which is formed above the front side of the MEMS wafer, and a second micromechanical functional layer which is formed above the first micromechanical functional layer.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: May 1, 2018
    Assignee: ROBERT BOSCH GMBH
    Inventors: Johannes Classen, Jochen Reinmuth, Arnd Kaelberer
  • Patent number: 9960131
    Abstract: In one embodiment, a semiconductor device includes one or more metallizations, such as, e.g., Cu-RDL metallizations, provided on a passivation layer over a dielectric layer. A via is provided through the passivation layer and the dielectric layer in the vicinity of the corners of the metallization. The via may be a “dummy” via without electrical connections to an active device and may be provided at a distance between approximately 1 micron (10?6 m.) and approximately 10 micron (10?5 m.) from each one of said converging sides landing on an underlying metal layer.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: May 1, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Paolo Colpani, Antonella Milani, Lucrezia Guarino, Andrea Paleari
  • Patent number: 9947575
    Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: April 17, 2018
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Yasunori Uchino, Kenichi Watanabe
  • Patent number: RE47629
    Abstract: A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: October 1, 2019
    Assignee: Sony Corporation
    Inventor: Hiromi Ogata