Non-single Crystal, Or Recrystallized, Material Forms Active Junction With Single Crystal Material (e.g., Monocrystal To Polycrystal Pn Junction Or Heterojunction) Patents (Class 257/51)
  • Patent number: 10734490
    Abstract: BJT devices with 3D wrap around emitter are provided. In one aspect, a method of forming a BJT device includes: forming a substrate including a first doped layer having a dopant concentration of from about 1×1020 at. % to about 5×1020 at. % and ranges therebetween, and a second doped layer having a dopant concentration of from about 1×1015 at. % to about 1×1018 at. % and ranges therebetween, wherein the first and second doped layers form a collector; patterning a fin(s) in the substrate; forming bottom spacers at a bottom of the fin(s); forming a base(s) that wraps around the fin(s); forming an emitter(s) that wraps around the base(s); and forming sidewall spacers alongside the emitter(s). A BJT device is also provided.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Injo Ok, Shogo Mochizuki, Soon-Cheon Seo
  • Patent number: 10686093
    Abstract: According to one embodiment, a semiconductor light receiving element is disclosed. The semiconductor light receiving element includes a Si substrate, a Si pn junction, a passivation film, and a compound semiconductor light receiving layer. The Si avalanche multiplication part is provided on the Si substrate. The Si pn junction surrounds the Si avalanche multiplication part, and includes a junction end part at a height different from that of the Si avalanche multiplication part. The passivation film is provided on the junction end part of the Si pn junction. The compound semiconductor light receiving layer is selectively provided inside a region on the Si pn junction.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: June 16, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hideto Furuyama
  • Patent number: 10658027
    Abstract: A method of forming a memory device that includes forming on a substrate, a first insulation layer, a first conductive layer, a second insulation layer, a second conductive layer, a third insulation layer. First trenches are formed through third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer, leaving side portions of the first conductive layer exposed. A fourth insulation layer is formed at the bottom of the first trenches that extends along the exposed portions of the first conductive layer. The first trenches are filled with conductive material. Second trenches are formed through the third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer. Drain regions are formed in the substrate under the second trenches. A pair of memory cells results, with a single continuous channel region extending between drain regions for the pair of memory cells.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: May 19, 2020
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Nhan Do, Xian Liu, Vipin Tiwari, Hieu Van Tran
  • Patent number: 10554018
    Abstract: The invention is directed to a hybrid, vertical current injection electro-optical device, comprising an active region and one or more current blocking layers. The active region includes a stack of III-V semiconductor gain materials designed for optical amplification. The gain materials of the stack are stacked along a stacking direction z, which is perpendicular to a main plane of the stack. The one or more current blocking layers extend perpendicularly to the stacking direction z and laterally on opposite sides of the active region. The one or more current blocking layers each have an effective refractive index n1 that is matched to the effective refractive index n of the active region, i.e., n1=f×n, with f?[0.95; 1.05]. The invention is further directed to a silicon photonics chip comprising such an electro-optical device.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Gustavo Ferreira Villares, Herwig Hahn, Marc Seifried
  • Patent number: 10276500
    Abstract: A semiconductor structure including a first metal line and a second metal line in a dielectric layer, the first metal line and the second metal line are adjacent and within the same dielectric level; an air gap structure in the dielectric layer and between the first metal line and the second metal line, wherein the air gap structure includes an air gap oxide layer and an air gap; and a barrier layer between the air gap structure and the first metal line, wherein the barrier layer is an oxidized metal layer.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Wei Lin, Takeshi Nogami
  • Patent number: 10269943
    Abstract: A semiconductor device that includes a semiconductor structure having a side wall that is non planar and that extends farther outward at an upper portion than at a lower portion of the side wall. The semiconductor structure extends underneath a semiconductor layer wherein a top portion of the structure contacts the semiconductor layer.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: April 23, 2019
    Assignee: NXP USA, INC.
    Inventors: Jay Paul John, Vishal Trivedi, James Albert Kirchgessner
  • Patent number: 10256254
    Abstract: To reduce power consumption and suppress display degradation of a liquid crystal display device. To suppress display degradation due to an external factor such as temperature. A transistor whose channel formation region is formed using an oxide semiconductor layer is used for a transistor provided in each pixel. Note that with the use of a high-purity oxide semiconductor layer, off-state current of the transistor at a room temperature can be 10 aA/?m or less and off-state current at 85° C. can be 100 aA/?m or less. Consequently, power consumption of a liquid crystal display device can be reduced and display degradation can be suppressed. Further, as described above, off-state current of the transistor at a temperature as high as 85° C. can be 100 aA/?m or less. Thus, display degradation of a liquid crystal display device due to an external factor such as temperature can be suppressed.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: April 9, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10193006
    Abstract: A nanowire composite structure is provided. The nanowire composite structure includes a nanowire core, wherein a material of the nanowire core includes Se, Te or a combination thereof. The nanowire composite structure also includes a metal layer covering the nanowire core. A method for forming the nanowire composite structure, a protective structure of a nanowire, a sensing device, and a method for forming a sensing device are also provided.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: January 29, 2019
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Hsueh-Shih Chen, Pin-Ru Chen
  • Patent number: 9929258
    Abstract: A method of controlling formation of junctions in a lateral bipolar junction transistor comprises: providing a starting substrate comprising a bulk silicon material as a handle substrate, a buried oxide layer on the handle substrate, and an intrinsic base semiconductor layer of germanium on the buried oxide layer; forming an extrinsic base layer on the intrinsic base semiconductor layer; etching at least a portion of the base layer; disposing a sidewall spacer on a side of the base layer; disposing a faceted germanium layer adjacent the sidewall spacer; recessing the faceted germanium layer and the intrinsic base semiconductor layer below the sidewall spacer; using a hot angle ion implantation technique to implant ions into a side of the intrinsic base semiconductor layer to form a junction edge/profile; annealing the implanted ions; and epitaxially growing a Si or SiGe layer on the germanium layer and the junction edge/profile.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: March 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Kam-Leung Lee, Tak H. Ning, Jeng-Bang Yau
  • Patent number: 9852912
    Abstract: A method of manufacturing a semiconductor device includes providing a silicon substrate with multiple layers formed on a front side and a backside, wherein at least a dielectric layer is formed on the backside of the silicon substrate; defining isolation regions and active regions at the front side of the silicon substrate, wherein the active regions are separated by the isolation regions; treating the multiple layers formed at the front side and the backside of the silicon substrate, so as to remain the dielectric layer as an outermost layer exposed at the backside of the silicon substrate; and depositing a polysilicon layer on the isolation regions and the active regions at the front side of the silicon substrate.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: December 26, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Sheng Zhang, Liang Yi, Wen-Bo Ding, Chien-Kee Pang, Yu-Yang Chen
  • Patent number: 9625746
    Abstract: Disclosed herein are methods, structures, and devices for a silicon carrier-depletion based modulator with enhanced doping in at least part of slab regions between waveguide core and contact areas. Compared to prior designs, this modulator exhibits lower optical absorption loss and better modulation bandwidth without sacrificing the modulation efficiency when operating at comparable bandwidth settings.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: April 18, 2017
    Assignee: Acacia Communications, Inc.
    Inventors: Long Chen, Christopher Doerr
  • Patent number: 9614148
    Abstract: A lateral bipolar junction transistor (BJT) magnetic field sensor that includes a layout of two or more adjacent lateral BJT devices. Each BJT includes a semiconductor base region of a first conductivity type doping, a semiconductor emitter region of a second conductivity type doping and laterally contacting the base region; and a first semiconductor collector region of a second conductivity type doping contacting said base region on an opposite side thereof. A second collector region of the second conductivity type doping is also formed contacting the base region on the opposite side thereof in spaced apart relation with the first collector region. The first adjacent lateral BJT device includes the emitter, base and first collector region and the second adjacent lateral BJT device includes the emitter, base and second collector region. The sensor induces a detectable difference in collector current amounts in the presence of an external magnetic field transverse to a plane defined by the layout.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: April 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Tak H. Ning, Jeng-Bang Yau
  • Patent number: 9570564
    Abstract: Device structures and fabrication methods for a bipolar junction transistor. A first semiconductor layer is formed on a substrate containing a first terminal. An etch stop layer is formed on the first semiconductor layer, and a second semiconductor layer is formed on the etch stop layer. The second semiconductor layer is etched to define a second terminal at a location of an etch mask on the second semiconductor layer. A first material comprising the etch stop layer and a second material comprising the second semiconductor layer are selected such that the second material of the second semiconductor layer etches at a greater etch rate than the first material of the etch stop layer. The first semiconductor layer may be a base layer that is used to form an intrinsic base and an extrinsic base of the bipolar junction transistor.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: February 14, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Deborah A. Alperstein, David L. Harame, Alvin J. Joseph, Qizhi Liu, Keith J. Machia, Christa R. Willets
  • Patent number: 9550614
    Abstract: A light emitting device includes a semiconductor nanocrystal and a charge transporting layer that includes an inorganic material. The charge transporting layer can be a hole or electron transporting layer. The inorganic material can be an inorganic semiconductor.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: January 24, 2017
    Assignee: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Moungi G. Bawendi, Vladimir Bulovic, Seth Coe-Sullivan, Jean-Michel Caruge, Jonathan Steckel, Jonathan E. Halpert, Alexi Arango
  • Patent number: 9496340
    Abstract: A semiconductor device includes: a laminated body including a channel layer that is configured of a compound semiconductor; and at least one gate electrode that is provided on a top surface side of the laminated body, wherein the laminated body includes a first low-resistance region that is provided on the top surface side of the laminated body, the first low-resistance region facing the at least one gate electrode, and a second low-resistance region that is provided externally of the first low resistance region on the top surface side of the laminated body, the second low-resistance region being continuous with the first low-resistance region.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: November 15, 2016
    Assignee: SONY CORPORATION
    Inventors: Katsuhiko Takeuchi, Satoshi Taniguchi
  • Patent number: 9379175
    Abstract: An integrated circuit includes a first polysilicon region having a first grain size formed on a substrate. The integrated circuit also includes a second polysilicon region, having a second grain size different from the first grain size, formed on the substrate. Furthermore, a method of fabricating an integrated circuit is also provided. The method includes forming a first polysilicon region having an initial grain size on a substrate. The first polysilicon region is implanted with a first dopant of a first conductivity type and a second dopant. After the implantation, the first polysilicon region has a first grain size larger than the initial grain size. Then, a laser rapid thermal annealing process is performed to the first polysilicon region.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: June 28, 2016
    Assignee: MEDIATEK INC.
    Inventors: Yuan-Fu Chung, Chu-Wei Hu, Yuan-Hung Chung
  • Patent number: 9165938
    Abstract: A semiconductor device includes a substrate having a cell region, wherein a contact region, page buffer regions, and a scribe lane region are defined around the cell region; a cell structure located in the cell region, including first conductive layers and first insulating layers which are alternately stacked, and having a non-stepped shape; a contact structure located in the contact region, including second conductive layers and second insulating layers which are alternately stacked, and having a stepped shape; a first dummy structure located in the page buffer region, including first sacrificial layers and third insulating layers which are alternately stacked, and having the non-stepped shape; and a second dummy structure located in the scribe lane region, including second sacrificial layers and fourth insulating layers which are alternately stacked, and having the stepped shape.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: October 20, 2015
    Assignee: SK Hynix Inc.
    Inventors: Won Ki Kim, Jong Man Kim
  • Patent number: 9147793
    Abstract: A method of producing polycrystalline CdTe materials and devices that incorporate the polycrystalline CdTe materials are provided. In particular, a method of producing polycrystalline p-doped CdTe thin films for use in CdTe solar cells in which the CdTe thin films possess enhanced acceptor densities and minority carrier lifetimes, resulting in enhanced efficiency of the solar cells containing the CdTe material are provided.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: September 29, 2015
    Assignee: Alliance For Sustainable Energy, LLC
    Inventors: Timothy A. Gessert, Rommel Noufi, Ramesh G. Dhere, David S. Albin, Teresa Barnes, James Burst, Joel N. Duenow, Matthew Reese
  • Patent number: 9059266
    Abstract: A semiconductor device includes a buffer layer formed with a semiconductor adapted to produce piezoelectric polarization, and a channel layer stacked on the buffer layer, wherein a two-dimensional hole gas, generated in the channel layer by piezoelectric polarization of the buffer layer, is used as a carrier of the channel layer. On a complementary semiconductor device, the semiconductor device described above and an n-type field effect transistor are formed on the same compound semiconductor substrate. Also, a level shift circuit is manufactured by using the semiconductor device. Further, a semiconductor device manufacturing method includes forming a compound semiconductor base portion, forming a buffer layer on the base portion, forming a channel layer on the buffer layer, forming a gate on the channel layer, and forming a drain and source with the gate therebetween on the channel layer.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: June 16, 2015
    Assignee: Sony Corporation
    Inventor: Masahiro Mitsunaga
  • Patent number: 9041202
    Abstract: An object is to provide a semiconductor device with high aperture ratio or a manufacturing method thereof. Another object is to provide semiconductor device with low power consumption or a manufacturing method thereof. A light-transmitting conductive layer which functions as a gate electrode, a gate insulating film formed over the light-transmitting conductive layer, a semiconductor layer formed over the light-transmitting conductive layer which functions as the gate electrode with the gate insulating film interposed therebetween, and a light-transmitting conductive layer which is electrically connected to the semiconductor layer and functions as source and drain electrodes are included.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: May 26, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 9018626
    Abstract: Disclosed herein are a ZnO film structure and a method of forming the same. Dislocation density of a ZnO film grown through epitaxial lateral overgrowth (ELOG) is minimized. In order to block a chemical reaction between the ZnO film and a mask layer at the time of performing the ELOG, a material of the mask layer is AlF3, NaF2, SrF, or MgF2. Therefore, the chemical reaction between ZnO and the mask layer is blocked and a transfer of dislocation from a substrate is also blocked.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: April 28, 2015
    Assignee: Gwangju Institute of Science and Technology
    Inventors: Seong-Ju Park, Yong Seok Choi, Jang-Won Kang, Byeong Hyeok Kim
  • Patent number: 8987780
    Abstract: A graphene capped HEMT device and a method of fabricating same are disclosed. The graphene capped HEMT device includes one or more graphene caps that enhance device performance and/or reliability of an exemplary AlGaN/GaN heterostructure transistor used in high-frequency, high-energy applications, e.g., wireless telecommunications. The HEMT device disclosed makes use of the extraordinary material properties of graphene. One of the graphene caps acts as a heat sink underneath the transistor, while the other graphene cap stabilizes the source, drain, and gate regions of the transistor to prevent cracking during high-power operation. A process flow is disclosed for replacing a three-layer film stack, previously used to prevent cracking, with a one-atom thick layer of graphene, without otherwise degrading device performance. In addition, the HEMT device disclosed includes a hexagonal boron nitride adhesion layer to facilitate deposition of the compound nitride semiconductors onto the graphene.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: March 24, 2015
    Assignee: STMicroelectronics, Inc.
    Inventors: John H Zhang, Cindy Goldberg, Walter Kleemeier
  • Publication number: 20150053982
    Abstract: Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A trench isolation region and a collector are formed in a semiconductor substrate. The collector is coextensive with the trench isolation region. A first semiconductor layer is formed that includes a of single crystal section disposed on the collector and on the trench isolation region. A second semiconductor layer is formed that includes a single crystal section disposed on the single crystal section of the first semiconductor layer and that has an outer edge that overlies the trench isolation region. The section of the first semiconductor layer has a second width greater than a first width of the collector. The section of the second semiconductor layer has a third width greater than the second width. A cavity extends laterally from the outer edge of section of the second semiconductor layer to the section of the first semiconductor layer.
    Type: Application
    Filed: October 30, 2014
    Publication date: February 26, 2015
    Inventors: Renata Camillo-Castillo, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater
  • Publication number: 20150053981
    Abstract: A methodology enabling the formation of steep channel profiles for devices, such as SSRW FETs, having a resultant channel profiles that enables suppression of threshold voltage variation and the resulting device are disclosed. Embodiments include providing STI regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between STI regions; forming a recess in the doped silicon wafer between the STI regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming Si:C on the doped silicon wafer in the recess.
    Type: Application
    Filed: October 10, 2014
    Publication date: February 26, 2015
    Inventors: Vara Govindeswara Reddy VAKADA, Laegu KANG, Michael P. GANZ, Yi QI, Puneet KHANNA, Sri Charan VEMULA, Srikanth SAMAVEDAM
  • Patent number: 8963120
    Abstract: An optoelectronic semiconductor component includes a semiconductor layer sequence having at least one active layer, and a photonic crystal that couples radiation having a peak wavelength out of or into the semiconductor layer sequence, wherein the photonic crystal is at a distance from the active layer and formed by superimposition of at least two lattices having mutually different reciprocal lattice constants normalized to the peak wavelength.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: February 24, 2015
    Assignees: OSRAM Opto Semiconductors GmbH, The University Court of the University of St. Andrews
    Inventors: Krister Bergenek, Christopher Wiesmann, Thomas F. Krauss
  • Publication number: 20150041811
    Abstract: A power transistor includes a number of transistor cells. Each transistor cell includes a source region, a drain region, a body region and a gate electrode. Each source region is arranged in a first semiconductor fin of a semiconductor body. Each drain region is at least partially arranged in a second semiconductor fin of the semiconductor body. The second semiconductor fin is spaced from the first semiconductor fin in a first horizontal direction of the semiconductor body. Each gate electrode is arranged in a trench adjacent the first semiconductor fin, is adjacent the body region, and is dielectrically insulated from the body region by a gate dielectric. Each of the first and second semiconductor fins has a width in the first horizontal direction and a length in a second horizontal direction, wherein the length is larger than the width.
    Type: Application
    Filed: August 7, 2013
    Publication date: February 12, 2015
    Inventor: Stefan Tegen
  • Publication number: 20140361300
    Abstract: Disclosed are bipolar devices, which incorporate an entirely monocrystalline link-up region between the intrinsic and extrinsic base layers, and methods of forming the devices. In the methods, a selective epitaxial deposition process grows monocrystalline semiconductor material for the extrinsic base layer on an exposed edge portion of a monocrystalline section of an intrinsic base layer. This deposition process is continued to intentionally overgrow the monocrystalline semiconductor material until it grows laterally and essentially covers a dielectric landing pad on a center portion of that same monocrystalline section of the intrinsic base layer. Subsequently, an opening is formed through the extrinsic base layer to the dielectric landing pad and the dielectric landing pad is selectively removed, thereby exposing monocrystalline surfaces only of the intrinsic and extrinsic base layers.
    Type: Application
    Filed: June 11, 2013
    Publication date: December 11, 2014
    Inventors: Renata A. Camillo-Castillo, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater
  • Patent number: 8907325
    Abstract: A thin film transistor disposed on a substrate is provided. The thin film transistor includes a gate, a semi-conductive layer, a gate insulator, a source and a drain. The gate insulator is located between the gate and the semi-conductive layer. A light shows a specific color after passing through the gate insulator. The source and the drain are disposed on the semi-conductive layer. A pixel structure and a liquid crystal display panel having the pixel structure are also provided. The liquid crystal display panel can display colorful images without disposing a color filter array additionally so that the manufacturing process of the liquid crystal panel is simple and the manufacturing cost of the liquid crystal panel is low.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: December 9, 2014
    Assignee: Au Optronics Corporation
    Inventors: Chiao-Shun Chuang, Fang-Chung Chen, Han-Ping David Shieh
  • Patent number: 8860025
    Abstract: A semiconductor device includes a semiconductor diode. The semiconductor diode includes a drift region and a first semiconductor region of a first conductivity type formed in or on the drift region. The first semiconductor region is electrically coupled to a first terminal via a first surface of a semiconductor body. The semiconductor diode includes a channel region of a second conductivity type electrically coupled to the first terminal, wherein a bottom of the channel region adjoins the first semiconductor region. A first side of the channel region adjoins the first semiconductor region.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: October 14, 2014
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Franz Hirler, Hans-Peter Felsl, Hans-Joachim Schulze
  • Publication number: 20140291681
    Abstract: Semiconductor devices are disclosed having modified transistor dimensions configured to provide reduced phase noise in certain amplifier applications. Transistor devices having expanded emitter-poly overlap of the emitter window, which serves to separate the external base area from the lateral emitter-base junction, may experience a reduction of free electrons and holes that diffuse into the electric field of the emitter-base junction, thereby reducing phase noise.
    Type: Application
    Filed: March 24, 2014
    Publication date: October 2, 2014
    Inventor: Stephen Joseph KOVACIC
  • Patent number: 8847224
    Abstract: According to one exemplary embodiment, a fin-based bipolar junction transistor (BJT) includes a wide collector situated in a semiconductor substrate. A fin base is disposed over the wide collector. Further, a fin emitter and an epi emitter are disposed over the fin base. A narrow base-emitter junction of the fin-based BJT is formed by the fin base and the fin emitter and the epi emitter provides increased current conduction and reduced resistance for the fin-based BJT. The epi emitter can be epitaxially formed on the fin emitter and can comprise polysilicon. Furthermore, the fin base and the fin emitter can each comprise single crystal silicon.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: September 30, 2014
    Assignee: Broadcom Corporation
    Inventors: Wei Xia, Xiangdong Chen
  • Publication number: 20140264343
    Abstract: A field effect device is disclosed that provides a reduced variation in on-resistance as a function of junction temperature. The field effect device, having a source junction, gate junction and drain junction, includes a resistive thin film adjacent the drain junction wherein the resistive thin film comprises a material having a negative temperature coefficient of resistance. The material is selected from one or more materials from the group consisting of doped polysilicon, amorphous silicon, silicon-chromium and silicon-nickel, where the material properties, such as thickness and doping level, are chosen to create a desired resistance and temperature profile for the field effect device. Temperature variation of on-resistance for the disclosed field effect device is reduced from the temperature variation for a similar field effect device without the resistive thin film.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 18, 2014
    Applicant: D3 SEMICONDUCTOR LLC
    Inventor: Thomas E. Harrington, III
  • Publication number: 20140252358
    Abstract: Methods and apparatus for forming MEMS devices. An apparatus includes at least a portion of a semiconductor substrate having a first thickness and patterned to form a moveable mass; a moving sense electrode forming the first plate of a first capacitance; at least one anchor patterned from the semiconductor substrate and having a portion that forms the second plate of the first capacitance and spaced by a first gap from the first plate; a layer of semiconductor material of a second thickness patterned to form a first electrode forming a first plate of a second capacitance and further patterned to form a second electrode overlying the at least one anchor and forming a second plate spaced by a second gap that is less than the first gap; wherein a total capacitance is formed that is the sum of the first capacitance and the second capacitance. Methods are disclosed.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Inventor: Taiwan Semiconductor Manufacturing Company Ltd.
  • Patent number: 8829519
    Abstract: A PIN diode includes an anode electrode, a P layer, an I layer, an N layer and a cathode electrode. A polysilicon film is formed in a region near the pn junction or n+n junction where the density of carriers implanted in a forward bias state is relatively high, as a predetermined film having a crystal defect serving as a recombination center. The lifetime can thus be controlled precisely.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: September 9, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hidenori Fujii
  • Publication number: 20140246676
    Abstract: A bipolar device with an entirely monocrystalline intrinsic base to extrinsic base link-up region. To form the device, a first extrinsic base layer, which is amorphous or polycrystalline, is deposited such that it contacts an edge portion of a monocrystalline section of an intrinsic base layer through an opening in a dielectric layer. A second extrinsic base layer is deposited on the first. An anneal is performed, either before or after deposition of the second extrinsic base layer, so that the extrinsic base layers are monocrystalline. An opening is formed through the extrinsic base layers to a dielectric landing pad aligned above a center portion of the monocrystalline section of the intrinsic base layer. The dielectric landing pad is removed and a semiconductor layer is grown epitaxially on exposed monocrystalline surfaces of the extrinsic and intrinsic base layers, thereby forming the entirely monocrystalline intrinsic base to extrinsic base link-up region.
    Type: Application
    Filed: March 1, 2013
    Publication date: September 4, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: INTERNATIONAL BUSINESS MACHINES CORPORATION
  • Patent number: 8815625
    Abstract: A pressure sensor having a structure, which includes a supporting body, a circuit arrangement and at least one circuit support. The circuit arrangement includes circuit components, amongst which detection means for generating electrical signals representing a quantity to be detected. The at least one circuit support is connected to the supporting body and has a surface, formed on which is a plurality of said circuit components, amongst which electrically conductive paths, where the circuit support is laminated on the first face of the supporting body.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: August 26, 2014
    Assignee: Metallux SA
    Inventor: Massimo Monichino
  • Patent number: 8809860
    Abstract: The present disclosure reduces and, in some instances, eliminates the density of interface states in III-V compound semiconductor materials by providing a thin crystalline interlayer onto an upper surface of a single crystal III-V compound semiconductor material layer to protect the crystallinity of the single crystal III-V compound semiconductor material layer's surface atoms prior to further processing of the structure.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kuen-Ting Shiu, Dechao Guo, Shu-Jen Han, Edward W. Kiewra, Masaharu Kobayashi
  • Patent number: 8796687
    Abstract: A method of treating a sheet of semiconducting material comprises forming a sinterable first layer over each major surface of a sheet of semiconducting material, forming a second layer over each of the first layers to form a particle-coated semiconductor sheet, placing the particle-coated sheet between end members, heating the particle-coated sheet to a temperature effective to at least partially sinter the first layer and at least partially melt the semiconducting material, and cooling the particle-coated sheet to solidify the semiconducting material and form a treated sheet of semiconducting material.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: August 5, 2014
    Assignee: Corning Incorporated
    Inventors: Glen Bennett Cook, Prantik Mazumder, Mallanagouda Dyamanagouda Patil, Lili Tian, Natesan Venkataraman
  • Patent number: 8779422
    Abstract: A semiconductor device includes an active body having two sidewalls facing each other in a lateral direction, a junction formed in a sidewall of the two sidewalls, a dielectric layer having an open portion to expose the junction and covering the active body, a junction extension portion having a buried region to fill the open portion, and a bit line coupled to the junction extension portion.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 15, 2014
    Assignee: SK Hynix Inc.
    Inventors: Sang-Do Lee, Kyung-Bo Ko, Hae-Jung Lee
  • Patent number: 8772768
    Abstract: A semiconductor device in which fluctuation in electric characteristics due to miniaturization is less likely to be caused is provided. The semiconductor device includes an oxide semiconductor film including a first region, a pair of second regions in contact with side surfaces of the first region, and a pair of third regions in contact with side surfaces of the pair of second regions; a gate insulating film provided over the oxide semiconductor film; and a first electrode that is over the gate insulating film and overlaps with the first region. The first region is a CAAC oxide semiconductor region. The pair of second regions and the pair of third regions are each an amorphous oxide semiconductor region containing a dopant. The dopant concentration of the pair of third regions is higher than the dopant concentration of the pair of second regions.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: July 8, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Publication number: 20140138687
    Abstract: A semiconductor device includes first conductive layers and first interlayer insulating layers stacked alternately with each other, at least one second conductive layer and at least one second interlayer insulating layer formed on the first conductive layers and the first interlayer insulating layers and stacked alternately with each other, a first semiconductor layer passing through the first conductive layers and the first interlayer insulating layers and including polysilicon, and a second semiconductor layer coupled to the first semiconductor layer and passing through the at least one second conductive layer the at least one second interlayer insulating layer, wherein the second semiconductor layer includes silicon germanium.
    Type: Application
    Filed: March 14, 2013
    Publication date: May 22, 2014
    Applicant: SK HYNIX INC.
    Inventors: Ki Hong LEE, Seung Ho PYI, Jin Ho BIN
  • Patent number: 8710500
    Abstract: Methods for fabricating bipolar junction transistors with self-aligned emitter and extrinsic base, bipolar junction transistors made by the methods, and design structures for a BiCMOS integrated circuit. The bipolar junction transistor is fabricated using a sacrificial emitter pedestal that provides a sacrificial mandrel promoting self-alignment between the emitter and the extrinsic base. The sacrificial emitter pedestal is subsequently removed to open an emitter window extending to the intrinsic base. An emitter is formed in the emitter window that lands on the intrinsic base.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: April 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Erik M. Dahlstrom, Peter B. Gray, David L. Harame, Qizhi Liu
  • Publication number: 20140097433
    Abstract: A semiconductor device includes a substrate; a carrier traveling layer formed on the substrate, made of first group III nitride semiconductor, and containing carriers traveling in a direction along a principal surface of the substrate; a barrier layer formed on the carrier traveling layer and made of second group III nitride semiconductor having a wider band gap than the first group III nitride semiconductor; and an electrode formed on the barrier layer. The device further includes a cap layer formed on the barrier layer at a side of the electrode, and made of third group III nitride semiconductor containing a mixture of single crystals and polycrystals.
    Type: Application
    Filed: December 11, 2013
    Publication date: April 10, 2014
    Applicant: Panasonic Corporation
    Inventors: Noboru NEGORO, Hidekazu UMEDA, Nanako HIRASHITA, Tetsuzo UEDA
  • Publication number: 20140061647
    Abstract: According to an embodiment of a field-effect semiconductor device, the field-effect semiconductor device includes a semiconductor body and a source electrode. The semiconductor body includes a drift region, a gate region and a source region of a first semiconductor material having a first band-gap and an anode region of a second semiconductor material having a second band-gap lower than the first band-gap. The drift region is of a first conductivity type. The gate region forms a pn-junction with the drift region. The source region is of the first conductivity type and in resistive electric connection with the drift region and has a higher maximum doping concentration than the drift region. The anode region is of the second conductivity type, forms a heterojunction with the drift region and is spaced apart from the source region. The source metallization is in resistive electric connection with the source region and the anode region.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventor: Wolfgang Werner
  • Patent number: 8659020
    Abstract: It is an object to provide an epitaxial silicon wafer that is provided with an excellent gettering ability in which a polysilicon layer is formed on the rear face side of a silicon crystal substrate into which phosphorus (P) and germanium (Ge) have been doped. A silicon epitaxial layer is grown by a CVD method on the surface of a silicon crystal substrate into which phosphorus and germanium have been doped at a high concentration. After that, a PBS forming step for growing a polysilicon layer is executed on the rear face side of a silicon crystal substrate. By the above steps, the number of LPDs (caused by an SF) that occur on the surface of the epitaxial silicon wafer due to the SF can be greatly reduced.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: February 25, 2014
    Assignee: Sumco Corporation
    Inventors: Tadashi Kawashima, Masahiro Yoshikawa, Akira Inoue, Yoshiya Yoshida
  • Publication number: 20140048805
    Abstract: [Problem] To provide a substrate bonding technique having a wide range of application. [Solution] A silicon thin film is formed on a bonding surface, and the interface with the substrate is surface-treated using energetic particles/metal particles.
    Type: Application
    Filed: January 30, 2012
    Publication date: February 20, 2014
    Applicants: LAN TECHNICAL SERVICE CO., LTD., TAIYO YUDEN CO., LTD., BONDTECH CO., LTD.
    Inventors: Tadatomo Suga, Akira Yamauchi, Ryuichi Kondou
  • Patent number: 8653595
    Abstract: The present invention relates to a semiconductor device including a circuit composed of thin film transistors having a novel GOLD (Gate-Overlapped LDD (Lightly Doped Drain)) structure. The thin film transistor comprises a first gate electrode and a second electrode being in contact with the first gate electrode and a gate insulating film. Further, the LDD is formed by using the first gate electrode as a mask, and source and drain regions are formed by using the second gate electrode as the mask. Then, the LDD overlapping with the second gate electrode is formed. This structure provides the thin film transistor with high reliability.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: February 18, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiroki Adachi
  • Patent number: 8642402
    Abstract: To provide a method for producing a thin film transistor improved in stability, uniformity, reproducibility, heat resistance, durability or the like, a thin film transistor, a thin film transistor substrate, an image display apparatus, an image display apparatus and a semiconductor device. In the semiconductor device, a crystalline oxide is used as an N-type transistor and the electron carrier concentration of the crystalline oxide is less than 2×1017/cm3. Furthermore, the crystalline oxide is a polycrystalline oxide containing In and one or more positive divalent elements selected from Zn, Mg, Cu, Ni, Co and Ca, and the atomic ratio In [In] and the positive divalent element [X][X]/([X]+[In]) is 0.0001 to 0.13.
    Type: Grant
    Filed: February 6, 2008
    Date of Patent: February 4, 2014
    Assignee: Idemitsu Kosan Co., Ltd.
    Inventors: Koki Yano, Kazuyoshi Inoue, Futoshi Utsuno, Masashi Kasami
  • Publication number: 20140021343
    Abstract: An apparatus, method and products thereof provide an accelerated neutral beam derived from an accelerated gas cluster ion beam for processing materials.
    Type: Application
    Filed: March 15, 2013
    Publication date: January 23, 2014
    Applicant: EXOGENESIS CORPORATION
    Inventors: Sean R. Kirkpatrick, Allen R. Kirkpatrick
  • Patent number: 8624321
    Abstract: A thin film transistor is provided, which includes a gate insulating layer covering a gate electrode, a microcrystalline semiconductor layer provided over the gate insulating layer, an amorphous semiconductor layer overlapping the microcrystalline semiconductor layer and the gate insulating layer, and a pair of impurity semiconductor layers which are provided over the amorphous semiconductor layer and to which an impurity element imparting one conductivity type is added to form a source region and a drain region. The gate insulating layer has a step adjacent to a portion in contact with an end portion of the microcrystalline semiconductor layer. A second thickness of the gate insulating layer in a portion outside the microcrystalline semiconductor layer is smaller than a first thickness thereof in a portion in contact with the microcrystalline semiconductor layer.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: January 7, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshiyuki Kurokawa, Hiromichi Godo, Hidekazu Miyairi