Abstract: A method for manufacturing a nitride semiconductor substrate, including: a step of preparing a base substrate; a step of forming a mask layer having a plurality of openings on the main surface of the base substrate; a first step of growing a first layer whose surface is composed only of inclined interfaces; and a second step of epitaxially growing a single crystal of a group III nitride semiconductor on the first layer, making the inclined interfaces disappear, and growing a second layer having a mirror surface, wherein in the first step, at least one valley and a plurality of tops are formed at an upper side of each of the plurality of openings of the mask layer by forming a plurality of concaves on a top surface of the single crystal and making the (0001) plane disappear.

Abstract: Disclosed are a crystalline oxide semiconductor thin film including a crystalline oxide semiconductor including indium, gallium, and tin, the crystalline oxide semiconductor exhibiting a (009) diffraction peak in an X-ray diffraction spectrum, and a method of forming the same, a thin film transistor and a method of manufacturing the same, a display panel, and an electronic device.

Abstract: The present invention relates to an SiC material and an SiC composite material and, more particularly, to an SiC material and an SiC composite material having a diffraction intensity ratio (I) of an X-ray diffraction peak, calculated by formula 1 down below, of less than 1.5. The present invention can provide an SiC material and an SiC composite material which can be etched evenly when exposed to plasma and thereby reduce the occurrence of cracks, holes and so forth. [Formula 1] Diffraction intensity ratio (I)=(peak intensity of plane (200)+peak intensity of plane (220))/peak intensity of plane (111).

Abstract: Provided is a polycrystalline ceramic substrate to be bonded to a compound semiconductor substrate with a bonding layer interposed therebetween, wherein at least one of relational expression (1) 0.7<?1/?2<0.9 and relational expression (2) 0.7<?3/?4<0.9 holds, where ?1 represents a linear expansion coefficient of the polycrystalline ceramic substrate at 30° C. to 300° C. and ?2 represents a linear expansion coefficient of the compound semiconductor substrate at 30° C. to 300° C., and ?3 represents a linear expansion coefficient of the polycrystalline ceramic substrate at 30° C. to 1000° C. and ?4 represents a linear expansion coefficient of the compound semiconductor substrate at 30° C. to 1000° C.

Abstract: A method for producing a transition metal dichalcogenide-graphene heterojunction composite, the method includes: transferring a graphene onto a flexile substrate; depositing a transition metal layer on the flexible substrate onto which the graphene has been transferred; and injecting a gas containing plasma-treated sulfur (S) onto the flexile substrate onto which the transition metal layer has been deposited, is disclosed.

Abstract: Machine assisted systems and methods for use in a solver are described. These systems and methods can use the solver to perform a setup phase, based on left-looking incomplete inverse fast multipole (LL-IFMM) operation on matrix A, and perform a solve phase for calculating a matrix-vector product for the matrix A based on a forward and backward substitution (FBS) method. The parallelization of the setup phase and the solve phase based on an elimination tree method. The parallelization of the setup phase and the solve phase being implemented using hybrid scheduling. The solver, once implemented, can provide timely solutions for ill-conditioned problems, such as circuits with thin conductors. The solver can also enhance a parasitic extractor accuracy when solving problems with a very large number of right-hand sides (RHS).

Abstract: A semiconductor device includes a first layer of first conductivity type and including an element region where semiconductor elements are to be formed, an annular second layer of second conductivity type formed to include a surface of the first layer, and surrounding the element region in a plan view, a third layer of second conductivity type formed in the first layer and separated more from the surface than the second layer, and sandwiching a portion of the first layer between the second and third layers, a fourth layer of second conductivity type and electrically connecting the second and third layers, and an electrode electrically connected to the fourth layer inside the second layer in the plan view. effective concentration of a second conductivity type impurity included in the second layer is higher than that of the first layer, and lower than that of the third layer.

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first heterojunction bipolar transistor includes a first emitter, a first collector, and a first base layer having a portion positioned between the first emitter and the first collector. A second heterojunction bipolar transistor includes a second emitter, a second collector, and a second base layer having a portion positioned between the second emitter and the second collector. The first and second base layers each comprise silicon-germanium, the first base layer includes a first germanium profile, and the second base layer includes a second germanium profile that is identical to the first germanium profile.

Abstract: A semiconductor device including a base region present within a fin semiconductor structure that is present atop a dielectric substrate. An epitaxial emitter region and epitaxial collector region are present on opposing sides and in direct contact with the fin semiconductor structure. An epitaxial extrinsic base region is present on a surface of the fin semiconductor substrate that is opposite the surface of the fin semiconductor structure that is in contact with the dielectric base.

Abstract: BJT devices with 3D wrap around emitter are provided. In one aspect, a method of forming a BJT device includes: forming a substrate including a first doped layer having a dopant concentration of from about 1×1020 at. % to about 5×1020 at. % and ranges therebetween, and a second doped layer having a dopant concentration of from about 1×1015 at. % to about 1×1018 at. % and ranges therebetween, wherein the first and second doped layers form a collector; patterning a fin(s) in the substrate; forming bottom spacers at a bottom of the fin(s); forming a base(s) that wraps around the fin(s); forming an emitter(s) that wraps around the base(s); and forming sidewall spacers alongside the emitter(s). A BJT device is also provided.

Abstract: According to one embodiment, a semiconductor light receiving element is disclosed. The semiconductor light receiving element includes a Si substrate, a Si pn junction, a passivation film, and a compound semiconductor light receiving layer. The Si avalanche multiplication part is provided on the Si substrate. The Si pn junction surrounds the Si avalanche multiplication part, and includes a junction end part at a height different from that of the Si avalanche multiplication part. The passivation film is provided on the junction end part of the Si pn junction. The compound semiconductor light receiving layer is selectively provided inside a region on the Si pn junction.

Abstract: A method of forming a memory device that includes forming on a substrate, a first insulation layer, a first conductive layer, a second insulation layer, a second conductive layer, a third insulation layer. First trenches are formed through third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer, leaving side portions of the first conductive layer exposed. A fourth insulation layer is formed at the bottom of the first trenches that extends along the exposed portions of the first conductive layer. The first trenches are filled with conductive material. Second trenches are formed through the third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer. Drain regions are formed in the substrate under the second trenches. A pair of memory cells results, with a single continuous channel region extending between drain regions for the pair of memory cells.

Abstract: The invention is directed to a hybrid, vertical current injection electro-optical device, comprising an active region and one or more current blocking layers. The active region includes a stack of III-V semiconductor gain materials designed for optical amplification. The gain materials of the stack are stacked along a stacking direction z, which is perpendicular to a main plane of the stack. The one or more current blocking layers extend perpendicularly to the stacking direction z and laterally on opposite sides of the active region. The one or more current blocking layers each have an effective refractive index n1 that is matched to the effective refractive index n of the active region, i.e., n1=f×n, with f?[0.95; 1.05]. The invention is further directed to a silicon photonics chip comprising such an electro-optical device.

Abstract: A semiconductor structure including a first metal line and a second metal line in a dielectric layer, the first metal line and the second metal line are adjacent and within the same dielectric level; an air gap structure in the dielectric layer and between the first metal line and the second metal line, wherein the air gap structure includes an air gap oxide layer and an air gap; and a barrier layer between the air gap structure and the first metal line, wherein the barrier layer is an oxidized metal layer.

Abstract: A semiconductor device that includes a semiconductor structure having a side wall that is non planar and that extends farther outward at an upper portion than at a lower portion of the side wall. The semiconductor structure extends underneath a semiconductor layer wherein a top portion of the structure contacts the semiconductor layer.

Abstract: To reduce power consumption and suppress display degradation of a liquid crystal display device. To suppress display degradation due to an external factor such as temperature. A transistor whose channel formation region is formed using an oxide semiconductor layer is used for a transistor provided in each pixel. Note that with the use of a high-purity oxide semiconductor layer, off-state current of the transistor at a room temperature can be 10 aA/?m or less and off-state current at 85° C. can be 100 aA/?m or less. Consequently, power consumption of a liquid crystal display device can be reduced and display degradation can be suppressed. Further, as described above, off-state current of the transistor at a temperature as high as 85° C. can be 100 aA/?m or less. Thus, display degradation of a liquid crystal display device due to an external factor such as temperature can be suppressed.

Abstract: A nanowire composite structure is provided. The nanowire composite structure includes a nanowire core, wherein a material of the nanowire core includes Se, Te or a combination thereof. The nanowire composite structure also includes a metal layer covering the nanowire core. A method for forming the nanowire composite structure, a protective structure of a nanowire, a sensing device, and a method for forming a sensing device are also provided.

Abstract: A method of controlling formation of junctions in a lateral bipolar junction transistor comprises: providing a starting substrate comprising a bulk silicon material as a handle substrate, a buried oxide layer on the handle substrate, and an intrinsic base semiconductor layer of germanium on the buried oxide layer; forming an extrinsic base layer on the intrinsic base semiconductor layer; etching at least a portion of the base layer; disposing a sidewall spacer on a side of the base layer; disposing a faceted germanium layer adjacent the sidewall spacer; recessing the faceted germanium layer and the intrinsic base semiconductor layer below the sidewall spacer; using a hot angle ion implantation technique to implant ions into a side of the intrinsic base semiconductor layer to form a junction edge/profile; annealing the implanted ions; and epitaxially growing a Si or SiGe layer on the germanium layer and the junction edge/profile.

Abstract: A method of manufacturing a semiconductor device includes providing a silicon substrate with multiple layers formed on a front side and a backside, wherein at least a dielectric layer is formed on the backside of the silicon substrate; defining isolation regions and active regions at the front side of the silicon substrate, wherein the active regions are separated by the isolation regions; treating the multiple layers formed at the front side and the backside of the silicon substrate, so as to remain the dielectric layer as an outermost layer exposed at the backside of the silicon substrate; and depositing a polysilicon layer on the isolation regions and the active regions at the front side of the silicon substrate.

Abstract: Disclosed herein are methods, structures, and devices for a silicon carrier-depletion based modulator with enhanced doping in at least part of slab regions between waveguide core and contact areas. Compared to prior designs, this modulator exhibits lower optical absorption loss and better modulation bandwidth without sacrificing the modulation efficiency when operating at comparable bandwidth settings.

Abstract: A lateral bipolar junction transistor (BJT) magnetic field sensor that includes a layout of two or more adjacent lateral BJT devices. Each BJT includes a semiconductor base region of a first conductivity type doping, a semiconductor emitter region of a second conductivity type doping and laterally contacting the base region; and a first semiconductor collector region of a second conductivity type doping contacting said base region on an opposite side thereof. A second collector region of the second conductivity type doping is also formed contacting the base region on the opposite side thereof in spaced apart relation with the first collector region. The first adjacent lateral BJT device includes the emitter, base and first collector region and the second adjacent lateral BJT device includes the emitter, base and second collector region. The sensor induces a detectable difference in collector current amounts in the presence of an external magnetic field transverse to a plane defined by the layout.

Abstract: Device structures and fabrication methods for a bipolar junction transistor. A first semiconductor layer is formed on a substrate containing a first terminal. An etch stop layer is formed on the first semiconductor layer, and a second semiconductor layer is formed on the etch stop layer. The second semiconductor layer is etched to define a second terminal at a location of an etch mask on the second semiconductor layer. A first material comprising the etch stop layer and a second material comprising the second semiconductor layer are selected such that the second material of the second semiconductor layer etches at a greater etch rate than the first material of the etch stop layer. The first semiconductor layer may be a base layer that is used to form an intrinsic base and an extrinsic base of the bipolar junction transistor.

Abstract: A light emitting device includes a semiconductor nanocrystal and a charge transporting layer that includes an inorganic material. The charge transporting layer can be a hole or electron transporting layer. The inorganic material can be an inorganic semiconductor.

Abstract: A semiconductor device includes: a laminated body including a channel layer that is configured of a compound semiconductor; and at least one gate electrode that is provided on a top surface side of the laminated body, wherein the laminated body includes a first low-resistance region that is provided on the top surface side of the laminated body, the first low-resistance region facing the at least one gate electrode, and a second low-resistance region that is provided externally of the first low resistance region on the top surface side of the laminated body, the second low-resistance region being continuous with the first low-resistance region.

Abstract: An integrated circuit includes a first polysilicon region having a first grain size formed on a substrate. The integrated circuit also includes a second polysilicon region, having a second grain size different from the first grain size, formed on the substrate. Furthermore, a method of fabricating an integrated circuit is also provided. The method includes forming a first polysilicon region having an initial grain size on a substrate. The first polysilicon region is implanted with a first dopant of a first conductivity type and a second dopant. After the implantation, the first polysilicon region has a first grain size larger than the initial grain size. Then, a laser rapid thermal annealing process is performed to the first polysilicon region.

Abstract: A semiconductor device includes a substrate having a cell region, wherein a contact region, page buffer regions, and a scribe lane region are defined around the cell region; a cell structure located in the cell region, including first conductive layers and first insulating layers which are alternately stacked, and having a non-stepped shape; a contact structure located in the contact region, including second conductive layers and second insulating layers which are alternately stacked, and having a stepped shape; a first dummy structure located in the page buffer region, including first sacrificial layers and third insulating layers which are alternately stacked, and having the non-stepped shape; and a second dummy structure located in the scribe lane region, including second sacrificial layers and fourth insulating layers which are alternately stacked, and having the stepped shape.

Abstract: A method of producing polycrystalline CdTe materials and devices that incorporate the polycrystalline CdTe materials are provided. In particular, a method of producing polycrystalline p-doped CdTe thin films for use in CdTe solar cells in which the CdTe thin films possess enhanced acceptor densities and minority carrier lifetimes, resulting in enhanced efficiency of the solar cells containing the CdTe material are provided.

Abstract: A semiconductor device includes a buffer layer formed with a semiconductor adapted to produce piezoelectric polarization, and a channel layer stacked on the buffer layer, wherein a two-dimensional hole gas, generated in the channel layer by piezoelectric polarization of the buffer layer, is used as a carrier of the channel layer. On a complementary semiconductor device, the semiconductor device described above and an n-type field effect transistor are formed on the same compound semiconductor substrate. Also, a level shift circuit is manufactured by using the semiconductor device. Further, a semiconductor device manufacturing method includes forming a compound semiconductor base portion, forming a buffer layer on the base portion, forming a channel layer on the buffer layer, forming a gate on the channel layer, and forming a drain and source with the gate therebetween on the channel layer.

Abstract: An object is to provide a semiconductor device with high aperture ratio or a manufacturing method thereof. Another object is to provide semiconductor device with low power consumption or a manufacturing method thereof. A light-transmitting conductive layer which functions as a gate electrode, a gate insulating film formed over the light-transmitting conductive layer, a semiconductor layer formed over the light-transmitting conductive layer which functions as the gate electrode with the gate insulating film interposed therebetween, and a light-transmitting conductive layer which is electrically connected to the semiconductor layer and functions as source and drain electrodes are included.

Abstract: Disclosed herein are a ZnO film structure and a method of forming the same. Dislocation density of a ZnO film grown through epitaxial lateral overgrowth (ELOG) is minimized. In order to block a chemical reaction between the ZnO film and a mask layer at the time of performing the ELOG, a material of the mask layer is AlF3, NaF2, SrF, or MgF2. Therefore, the chemical reaction between ZnO and the mask layer is blocked and a transfer of dislocation from a substrate is also blocked.

Abstract: A graphene capped HEMT device and a method of fabricating same are disclosed. The graphene capped HEMT device includes one or more graphene caps that enhance device performance and/or reliability of an exemplary AlGaN/GaN heterostructure transistor used in high-frequency, high-energy applications, e.g., wireless telecommunications. The HEMT device disclosed makes use of the extraordinary material properties of graphene. One of the graphene caps acts as a heat sink underneath the transistor, while the other graphene cap stabilizes the source, drain, and gate regions of the transistor to prevent cracking during high-power operation. A process flow is disclosed for replacing a three-layer film stack, previously used to prevent cracking, with a one-atom thick layer of graphene, without otherwise degrading device performance. In addition, the HEMT device disclosed includes a hexagonal boron nitride adhesion layer to facilitate deposition of the compound nitride semiconductors onto the graphene.

Abstract: A methodology enabling the formation of steep channel profiles for devices, such as SSRW FETs, having a resultant channel profiles that enables suppression of threshold voltage variation and the resulting device are disclosed. Embodiments include providing STI regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between STI regions; forming a recess in the doped silicon wafer between the STI regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming Si:C on the doped silicon wafer in the recess.

Abstract: Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A trench isolation region and a collector are formed in a semiconductor substrate. The collector is coextensive with the trench isolation region. A first semiconductor layer is formed that includes a of single crystal section disposed on the collector and on the trench isolation region. A second semiconductor layer is formed that includes a single crystal section disposed on the single crystal section of the first semiconductor layer and that has an outer edge that overlies the trench isolation region. The section of the first semiconductor layer has a second width greater than a first width of the collector. The section of the second semiconductor layer has a third width greater than the second width. A cavity extends laterally from the outer edge of section of the second semiconductor layer to the section of the first semiconductor layer.

Abstract: An optoelectronic semiconductor component includes a semiconductor layer sequence having at least one active layer, and a photonic crystal that couples radiation having a peak wavelength out of or into the semiconductor layer sequence, wherein the photonic crystal is at a distance from the active layer and formed by superimposition of at least two lattices having mutually different reciprocal lattice constants normalized to the peak wavelength.

Abstract: A power transistor includes a number of transistor cells. Each transistor cell includes a source region, a drain region, a body region and a gate electrode. Each source region is arranged in a first semiconductor fin of a semiconductor body. Each drain region is at least partially arranged in a second semiconductor fin of the semiconductor body. The second semiconductor fin is spaced from the first semiconductor fin in a first horizontal direction of the semiconductor body. Each gate electrode is arranged in a trench adjacent the first semiconductor fin, is adjacent the body region, and is dielectrically insulated from the body region by a gate dielectric. Each of the first and second semiconductor fins has a width in the first horizontal direction and a length in a second horizontal direction, wherein the length is larger than the width.

Abstract: Disclosed are bipolar devices, which incorporate an entirely monocrystalline link-up region between the intrinsic and extrinsic base layers, and methods of forming the devices. In the methods, a selective epitaxial deposition process grows monocrystalline semiconductor material for the extrinsic base layer on an exposed edge portion of a monocrystalline section of an intrinsic base layer. This deposition process is continued to intentionally overgrow the monocrystalline semiconductor material until it grows laterally and essentially covers a dielectric landing pad on a center portion of that same monocrystalline section of the intrinsic base layer. Subsequently, an opening is formed through the extrinsic base layer to the dielectric landing pad and the dielectric landing pad is selectively removed, thereby exposing monocrystalline surfaces only of the intrinsic and extrinsic base layers.

Abstract: A thin film transistor disposed on a substrate is provided. The thin film transistor includes a gate, a semi-conductive layer, a gate insulator, a source and a drain. The gate insulator is located between the gate and the semi-conductive layer. A light shows a specific color after passing through the gate insulator. The source and the drain are disposed on the semi-conductive layer. A pixel structure and a liquid crystal display panel having the pixel structure are also provided. The liquid crystal display panel can display colorful images without disposing a color filter array additionally so that the manufacturing process of the liquid crystal panel is simple and the manufacturing cost of the liquid crystal panel is low.

Abstract: A semiconductor device includes a semiconductor diode. The semiconductor diode includes a drift region and a first semiconductor region of a first conductivity type formed in or on the drift region. The first semiconductor region is electrically coupled to a first terminal via a first surface of a semiconductor body. The semiconductor diode includes a channel region of a second conductivity type electrically coupled to the first terminal, wherein a bottom of the channel region adjoins the first semiconductor region. A first side of the channel region adjoins the first semiconductor region.

Abstract: Semiconductor devices are disclosed having modified transistor dimensions configured to provide reduced phase noise in certain amplifier applications. Transistor devices having expanded emitter-poly overlap of the emitter window, which serves to separate the external base area from the lateral emitter-base junction, may experience a reduction of free electrons and holes that diffuse into the electric field of the emitter-base junction, thereby reducing phase noise.

Abstract: According to one exemplary embodiment, a fin-based bipolar junction transistor (BJT) includes a wide collector situated in a semiconductor substrate. A fin base is disposed over the wide collector. Further, a fin emitter and an epi emitter are disposed over the fin base. A narrow base-emitter junction of the fin-based BJT is formed by the fin base and the fin emitter and the epi emitter provides increased current conduction and reduced resistance for the fin-based BJT. The epi emitter can be epitaxially formed on the fin emitter and can comprise polysilicon. Furthermore, the fin base and the fin emitter can each comprise single crystal silicon.

Abstract: A field effect device is disclosed that provides a reduced variation in on-resistance as a function of junction temperature. The field effect device, having a source junction, gate junction and drain junction, includes a resistive thin film adjacent the drain junction wherein the resistive thin film comprises a material having a negative temperature coefficient of resistance. The material is selected from one or more materials from the group consisting of doped polysilicon, amorphous silicon, silicon-chromium and silicon-nickel, where the material properties, such as thickness and doping level, are chosen to create a desired resistance and temperature profile for the field effect device. Temperature variation of on-resistance for the disclosed field effect device is reduced from the temperature variation for a similar field effect device without the resistive thin film.

Abstract: Methods and apparatus for forming MEMS devices. An apparatus includes at least a portion of a semiconductor substrate having a first thickness and patterned to form a moveable mass; a moving sense electrode forming the first plate of a first capacitance; at least one anchor patterned from the semiconductor substrate and having a portion that forms the second plate of the first capacitance and spaced by a first gap from the first plate; a layer of semiconductor material of a second thickness patterned to form a first electrode forming a first plate of a second capacitance and further patterned to form a second electrode overlying the at least one anchor and forming a second plate spaced by a second gap that is less than the first gap; wherein a total capacitance is formed that is the sum of the first capacitance and the second capacitance. Methods are disclosed.

Abstract: A PIN diode includes an anode electrode, a P layer, an I layer, an N layer and a cathode electrode. A polysilicon film is formed in a region near the pn junction or n+n junction where the density of carriers implanted in a forward bias state is relatively high, as a predetermined film having a crystal defect serving as a recombination center. The lifetime can thus be controlled precisely.

Abstract: A bipolar device with an entirely monocrystalline intrinsic base to extrinsic base link-up region. To form the device, a first extrinsic base layer, which is amorphous or polycrystalline, is deposited such that it contacts an edge portion of a monocrystalline section of an intrinsic base layer through an opening in a dielectric layer. A second extrinsic base layer is deposited on the first. An anneal is performed, either before or after deposition of the second extrinsic base layer, so that the extrinsic base layers are monocrystalline. An opening is formed through the extrinsic base layers to a dielectric landing pad aligned above a center portion of the monocrystalline section of the intrinsic base layer. The dielectric landing pad is removed and a semiconductor layer is grown epitaxially on exposed monocrystalline surfaces of the extrinsic and intrinsic base layers, thereby forming the entirely monocrystalline intrinsic base to extrinsic base link-up region.

Abstract: A pressure sensor having a structure, which includes a supporting body, a circuit arrangement and at least one circuit support. The circuit arrangement includes circuit components, amongst which detection means for generating electrical signals representing a quantity to be detected. The at least one circuit support is connected to the supporting body and has a surface, formed on which is a plurality of said circuit components, amongst which electrically conductive paths, where the circuit support is laminated on the first face of the supporting body.

Abstract: The present disclosure reduces and, in some instances, eliminates the density of interface states in III-V compound semiconductor materials by providing a thin crystalline interlayer onto an upper surface of a single crystal III-V compound semiconductor material layer to protect the crystallinity of the single crystal III-V compound semiconductor material layer's surface atoms prior to further processing of the structure.

Abstract: A method of treating a sheet of semiconducting material comprises forming a sinterable first layer over each major surface of a sheet of semiconducting material, forming a second layer over each of the first layers to form a particle-coated semiconductor sheet, placing the particle-coated sheet between end members, heating the particle-coated sheet to a temperature effective to at least partially sinter the first layer and at least partially melt the semiconducting material, and cooling the particle-coated sheet to solidify the semiconducting material and form a treated sheet of semiconducting material.

Abstract: A semiconductor device includes an active body having two sidewalls facing each other in a lateral direction, a junction formed in a sidewall of the two sidewalls, a dielectric layer having an open portion to expose the junction and covering the active body, a junction extension portion having a buried region to fill the open portion, and a bit line coupled to the junction extension portion.

Abstract: A semiconductor device in which fluctuation in electric characteristics due to miniaturization is less likely to be caused is provided. The semiconductor device includes an oxide semiconductor film including a first region, a pair of second regions in contact with side surfaces of the first region, and a pair of third regions in contact with side surfaces of the pair of second regions; a gate insulating film provided over the oxide semiconductor film; and a first electrode that is over the gate insulating film and overlaps with the first region. The first region is a CAAC oxide semiconductor region. The pair of second regions and the pair of third regions are each an amorphous oxide semiconductor region containing a dopant. The dopant concentration of the pair of third regions is higher than the dopant concentration of the pair of second regions.

Abstract: A semiconductor device includes first conductive layers and first interlayer insulating layers stacked alternately with each other, at least one second conductive layer and at least one second interlayer insulating layer formed on the first conductive layers and the first interlayer insulating layers and stacked alternately with each other, a first semiconductor layer passing through the first conductive layers and the first interlayer insulating layers and including polysilicon, and a second semiconductor layer coupled to the first semiconductor layer and passing through the at least one second conductive layer the at least one second interlayer insulating layer, wherein the second semiconductor layer includes silicon germanium.