Non-single Crystal, Or Recrystallized, Semiconductor Material Forms Part Of Active Junction (including Field-induced Active Junction) Patents (Class 257/49)
  • Patent number: 11942531
    Abstract: A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: March 26, 2024
    Assignee: ROHM CO., LTD.
    Inventor: Akihiro Hikasa
  • Patent number: 11915988
    Abstract: A first electrode film is electrically connected to a source region of a semiconductor substrate, and disposed over a main surface of the semiconductor substrate. A second electrode film is electrically connected to a gate electrode, and disposed over the main surface. A third electrode film is disposed over the main surface away from the first electrode film. A protective dielectric film is disposed over the main surface, covers only a portion of each of the first electrode film and the second electrode film and covers at least portion of the third electrode film, and is made of a thermosetting resin. The main surface has a peripheral region and an inner region enclosed by the peripheral region, and the protective dielectric film has a peripheral portion covering the peripheral region and has a first inner portion crossing the inner region and covering at least portion of the third electrode film.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: February 27, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Masahiro Yokogawa, Kensuke Taguchi
  • Patent number: 11688732
    Abstract: A single chip power semiconductor device includes: first and second load terminals; a semiconductor body integrated in the single chip and coupled to the load terminals and configured to conduct a load current along a load current path between the load terminals; a control terminal and at least one control electrode electrically connected thereto, the at least one control electrode being electrically insulated from the semiconductor body and configured to control the load current based on a control voltage between the control terminal and the first load terminal; a protection structure integrated, separately from the load current path, in the single chip and including a series connection of pn junctions with first semiconductor regions of a first conductivity type and second semiconductor regions of a second conductivity type. The series connection of the pn-junctions is connected in forward bias between the control terminal and the first load terminal.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: June 27, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Guang Zeng, Anton Mauder, Joachim Weyers
  • Patent number: 11637010
    Abstract: The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: April 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bo-Jiun Lin, Hai-Ching Chen, Tien-I Bao
  • Patent number: 11508577
    Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate and an insulator layer above the substrate. A channel area may include an III-V material relaxed grown on the insulator layer. A source area may be above the insulator layer, in contact with the insulator layer, and adjacent to a first end of the channel area. A drain area may be above the insulator layer, in contact with the insulator layer, and adjacent to a second end of the channel area that is opposite to the first end of the channel area. The source area or the drain area may include one or more seed components including a seed material with free surface. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: November 22, 2022
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Matthew Metz, Willy Rachmady, Sean Ma, Nicholas Minutillo, Cheng-Ying Huang, Tahir Ghani, Jack Kavalieros, Anand Murthy, Harold Kennel
  • Patent number: 11450752
    Abstract: A semiconductor device includes a substrate having a main surface, and a temperature-sensitive diode structure having a trench formed in the main surface, a polysilicon layer embedded in the trench, a p-type anode region formed in the polysilicon layer, and an n-type cathode region formed in the polysilicon layer.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: September 20, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Yoshinori Fukuda, Hajime Okuda, Yuji Osumi
  • Patent number: 11437363
    Abstract: A diode having a simple structure and a simple manufacturing method of the diode are provided. A diode including: a semiconductor layer having a first region and a second region having a resistance lower than a resistance of the first region; a first insulating layer having a first aperture portion and a second aperture portion and covering the semiconductor layer other than the first aperture and the second aperture, the first aperture portion exposing the semiconductor layer in the first region, the second aperture portion exposing the semiconductor layer in the second region; a first conductive layer connected to the semiconductor layer in the first aperture portion and overlapping with the semiconductor layer in the first region via the first insulating layer in a planar view; and a second conductive layer connected to the semiconductor layer in the second aperture.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: September 6, 2022
    Assignee: JAPAN DISPLAY INC.
    Inventor: Toshinari Sasaki
  • Patent number: 11417855
    Abstract: A display device and a manufacturing method thereof are provided. The display device includes a display area, a non-display area surrounding the display area, a thin film transistor structure layer, a ring-shaped metal layer, a luminous layer, and a first electrode. The ring-shaped metal layer is disposed in the non-display area. The thin film transistor structure layer includes a passivation layer including a protrusion corresponding to the ring-shaped metal layer. The first electrode extends from the display area to the protrusion, and extends from a surface of the protrusion to a surface of the ring-shaped metal layer.
    Type: Grant
    Filed: November 28, 2019
    Date of Patent: August 16, 2022
    Assignees: SHENZHEN CHINA STAR OPTOELECTRONICS, SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Yanying Du
  • Patent number: 11398583
    Abstract: A light-emitting device, includes a substrate structure, including a base portion having a surface and a plurality of protrusions regularly formed on the base portion; a buffer layer covering the plurality of protrusions and the surface; and III-V compound semiconductor layers formed on the buffer layer; wherein one of the plurality of protrusions includes a first portion and a second portion formed on the first portion and the first portion is integrated with the base portion; and wherein the base portion includes a first material and the first portion includes the first material.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: July 26, 2022
    Assignee: EPISTAR CORPORATION
    Inventors: Peng Ren Chen, Yu-Shan Chiu, Wen-Hsiang Lin, Shih-Wei Wang, Chen Ou
  • Patent number: 11309416
    Abstract: A drift layer has a first conductivity type. A well region has a second conductivity type. A well contact region has a resistivity lower than that of the well region. A source contact region is provided on the well region, separated from the drift layer by the well region, and has the first conductivity type. A source resistance region is provided on the well region, separated from the drift layer by the well region, is adjacent to the source contact region, has the first conductivity type, and has a sheet resistance higher than that of the source contact region. A source electrode contacts the source contact region, the well contact region, and the source resistance region, and is continuous with the channel at least through the source resistance region.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: April 19, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hideyuki Hatta, Shiro Hino, Katsutoshi Sugawara
  • Patent number: 11295992
    Abstract: Techniques related to III-N transistors having improved performance, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include first and second crystalline III-N material layers separated by an intervening layer other than a III-N material such that the first crystalline III-N material layer has a first crystal orientation that is inverted with respect to a second crystal orientation of the second crystalline III-N material layer.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: April 5, 2022
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
  • Patent number: 11251157
    Abstract: Provided is a die stack structure including a first die and a second die. The first die and the second die are bonded together through a hybrid bonding structure. At least one of a first test pad of the first die or a second test pad of the second die has a protrusion of the at least one of the first test pad or the second test pad, and a bonding insulating layer of the hybrid bonding structure covers and contacts with the protrusion, so that the first test pad and the second test pad are electrically isolated from each other.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Jung Yang, Hsien-Wei Chen
  • Patent number: 11239075
    Abstract: A structure includes a substrate having a first semiconductor material. The substrate has a recess. A bottom portion of the recess has a first sidewall and a second sidewall. The first sidewall intersects the second sidewall. The structure further includes an isolation feature surrounding the recess and a second semiconductor material disposed in the recess and in contact with the first semiconductor material. The second semiconductor material has lattice mismatch to the first semiconductor material.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: February 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Hsien Wu, I-Sheng Chen
  • Patent number: 11171235
    Abstract: A semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor is disposed on the substrate within a first region and includes a first gate electrode. The first gate electrode includes a first filter layer between and in contact with a first conductive layer and a second conductive layer. The second transistor is disposed on the substrate within a second region and includes a second gate electrode. The second gate electrode includes a second filter layer between and in contact with a third conductive layer and a fourth conductive layer. The first transistor and the second transistor have a same conductive type, a first threshold voltage of the first transistor is lower than a second threshold voltage of the second transistor, and a first thickness of the first filter layer is larger than a second thickness of the second filter layer.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chang Wei, Chia-Lin Hsu, Hsien-Ming Lee, Ji-Cheng Chen
  • Patent number: 11165225
    Abstract: An optoelectronic device including a semiconductor layer formed from a central segment and at least two lateral segments forming tensioning arms that extend along a longitudinal axis A1. The semiconductor layer furthermore includes at least two lateral segments forming electrical biasing arms that extend along a transverse axis A2 orthogonal to the axis A1.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: November 2, 2021
    Assignee: Commissariat a l ' Energie Atomique et aux Energies Alternatives
    Inventors: Vincent Reboud, Mathieu Bertrand, Nicolas Pauc, Alexei Tchelnokov
  • Patent number: 11009404
    Abstract: A temperature-sensing device configured to monitor a temperature is disclosed. The temperature-sensing device includes: a first capacitor comprising a first oxide layer with a first thickness; a second capacitor comprising a second oxide layer with a second thickness, wherein the second thickness of the second oxide layer is different from the first thickness of the first oxide layer; and a control logic circuit, coupled to the first and second capacitors, and configured to determine whether the monitored temperature is equal to or greater than a threshold temperature based of whether at least one of the first and second oxide layers breaks down.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shih-Lien Linus Lu
  • Patent number: 10834509
    Abstract: A microphone and its manufacturing method, relating the semiconductor techniques, are presented. The microphone comprises: a substrate comprising an opening, a first electrode layer at the bottom of the opening, and at least one groove adjacent to the first electrode layer, with the groove and the opening on two opposing sides of a bottom surface of the first electrode layer; a separation material layer filling the groove; and a second electrode layer on the separation material layer, wherein the first electrode layer, the separation material layer, and the second electrode layer form a cavity. In this inventive concept, the separation material layer on the groove works as an anchor node embedding in the substrate to increases the effective contact area and the bonding power, and to improve the bonding quality between the second electrode layer and the substrate, which results in a strengthened second electrode layer.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: November 10, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: GuangCai Fu
  • Patent number: 10802124
    Abstract: Embodiments relate to integrated sonic sensors having a transmitter, a receiver and driver electronics integrated in a single, functional package. In one embodiment, a piezoelectric signal transmitter, a silicon microphone receiver and a controller/amplifier chip are concomitantly integrated in a semiconductor housing. The semiconductor housing, in embodiments, is functional in that at least a portion of the housing can comprise the piezoelectric element of the transmitter, with an inlet aperture opposite the silicon microphone receiver.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: October 13, 2020
    Assignee: Infineon Technologies AG
    Inventors: Klaus Elian, Horst Theuss
  • Patent number: 10672906
    Abstract: A transistor device disposed on a substrate and including a semiconductor layer, a first gate, a second gate, and two source drain electrodes is provided. The semiconductor layer is disposed on the substrate and has a channel region, two lightly-doped regions, and two source drain regions. Each of the two lightly-doped regions has a first boundary adjoined to the channel region and a second boundary adjoined to one of the two source drain regions. The first gate is extended over the channel region of the semiconductor layer, wherein an edge of the first gate is aligned with the first boundary. The second gate is stacked on the first gate and is in contact with the first gate, wherein in a thickness direction, the second gate is overlapped with the two lightly-doped regions. The two source drain electrodes are respectively in contact with the two source drain regions.
    Type: Grant
    Filed: July 4, 2019
    Date of Patent: June 2, 2020
    Assignee: Au Optronics Corporation
    Inventors: Ming-Yan Chen, Ming-Hsien Lee, Che-Chia Chang
  • Patent number: 10600825
    Abstract: The invention provides a manufacturing method for TFT array substrate and TFT array substrate. The manufacturing method forms a first buffer layer on the substrate; the first buffer layer is disposed with a plurality of arc protrusions or a plurality of arc recesses; then an a-Si layer is formed on the second buffer layer which is formed on the first buffer layer; in the process of forming a polysilicon layer by performing ELA on the a-Si layer, the arc protrusions or the arc recesses can change the optical path of the laser to form an energy gradient in the a-Si layer, so as to increase the grain size in the formed polysilicon layer, reduce the number of grain boundaries, improve the carrier mobility of the TFT device, and improve the electrical properties of the TFT device.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: March 24, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Ruijun Zhang, Song Wang
  • Patent number: 10593748
    Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a flowable insulating layer or a reflowable insulating layer.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: March 17, 2020
    Assignee: GlobalWafers Co., Ltd.
    Inventor: Sasha Joseph Kweskin
  • Patent number: 10566325
    Abstract: A semiconductor device, including a semiconductor layer of a first conductivity type, having a main surface with a diode trench formed therein, an inner wall insulating film, including a side wall insulating film, formed along side walls of the diode trench, and a bottom wall insulating film, formed along a bottom wall of the diode trench and having a thickness greater than a thickness of the side wall insulating film, and a bidirectional Zener diode, formed on the bottom wall insulating film inside the diode trench and having a pair of first conductivity type portions and at least one second conductivity type portion formed between the pair of first conductivity type portions.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: February 18, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Kenji Nishida, Shinpei Ohnishi, Kentaro Nasu
  • Patent number: 10510957
    Abstract: A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: December 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Agostino Pirovano, Fabio Pellizzer, Anna Maria Conti, Andrea Redaelli, Innocenzo Tortorelli
  • Patent number: 10461220
    Abstract: A method of manufacturing a semiconductor device and the device resulted thereof is disclosed. In one aspect, the device has a heterogeneous layer stack of one or more III-V type materials, at least one transmission layer of the layer stack having a roughened or textured surface for enhancement of light transmission. The method includes (a) growing the transmission layer of a III-V type material, (b) providing a mask layer on the transmission layer, the mask layer leaving first portions of the transmission layer exposed, and (c) partially decomposing the first exposed portions of the transmission layer. Suitably redeposition occurs in a single step with decomposition, so as to obtain a textured surface based on crystal facets of a plurality of grown crystals. The resulting device has a light-emitting element. The transmission layer hereof is suitably present at the top side.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: October 29, 2019
    Assignee: IMEC
    Inventor: Kai Cheng
  • Patent number: 10424524
    Abstract: Disclosed is a method of manufacturing a semiconductor device that includes adhering a plurality of semiconductor substrates and a framing member to a supporting surface of a carrier substrate. The semiconductor substrates can be wafers that can be diced or cut into a plurality of dies. Thus, the wafers each have respective active surfaces and at least one respective integrated circuit region. The method can further include encapsulating the framing member and the plurality of semiconductor substrates within an encapsulant. Subsequently, the carrier substrate is removed and a redistribution layer (RDL) is formed on the semiconductor substrates and the framing member.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: September 24, 2019
    Assignees: CHENGDU ESWIN SIP TECHNOLOGY CO., LTD., BEIJING ESWIN TECHNOLOGY CO., LTD.
    Inventors: Minghao Shen, Xiaotian Zhou
  • Patent number: 10379945
    Abstract: Techniques are disclosed for generating codes for representation of data in memory devices that may avoid the block erasure operation in changing data values. Data values comprising binary digits (bits) can be encoded and decoded using the generated codes, referred to as codewords, such that the codewords may comprise a block erasure-avoiding code, in which the binary digits of a data message m can be encoded such that the encoded data message can be stored into multiple memory cells of a data device and, once a memory cell value is changed from a first logic value to a second logic value, the value of the memory cell may remain at the second logic value, regardless of subsequently received messages, until a block erasure operation on the memory cell.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: August 13, 2019
    Assignees: CALIFORNIA INSTITUTE OF TECHNOLOGY, THE TEXAS A & M UNIVERSITY SYSTEM
    Inventors: Eyal En Gad, Yue Li, Joerg Kliewer, Michael Langberg, Anxiao Jiang, Jehoshua Bruck
  • Patent number: 10373818
    Abstract: Methods are provided for recycling a dummy wafer so that the dummy wafer may be repeatedly used in a deposition process. The dummy wafer includes a substrate and an oxide layer on the substrate that is formed by the deposition process. A thickness of the oxide layer on the dummy wafer may be measured, and the dummy wafer may be subjected to recycling depending on whether the measured thickness of the oxide layer exceeds a threshold thickness. The dummy wafer is recycled by removing the oxide layer, which may be accomplished by performing an etching process. A mechanical polishing process may be performed to smooth the surface of the substrate. The dummy wafer may then be reused in a subsequent deposition process.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: August 6, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hua Cheng, Yen-Hsun Wu
  • Patent number: 10361291
    Abstract: To reduce defects in an oxide semiconductor film in a semiconductor device. To improve the electrical characteristics and the reliability of a semiconductor device including an oxide semiconductor film. In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: July 23, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Yukinori Shima, Hajime Tokunaga, Toshinari Sasaki, Keisuke Murayama, Daisuke Matsubayashi
  • Patent number: 10355069
    Abstract: An organic light emitting diode display includes a substrate; a buffer layer on the substrate; a scan line running to a horizontal direction on the buffer layer; an intermediate insulating layer covering the scan line; a first trench having a segment shape apart from the scan line with a predetermined distance and exposing some of the substrate by patterning the intermediate insulating layer and the buffer layer; a data line running to a vertical direction on the substrate exposed by the first trench and on the intermediate insulating layer; a passivation layer covering the data line and the scan line; and a color filter filling into the trench and depositing on the passivation layer.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: July 16, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Dosung Kim, Ryosuke Tani
  • Patent number: 10347865
    Abstract: An organic electroluminescence (EL) display panel includes a multi-layered wiring laminate including: a first part on which an organic EL element array is disposed and in which a first portion of a resin insulating layer is present, the resin insulating layer being a highest layer among insulating layers; a second part surrounding the first part in plan view and in which a second portion of the resin insulating layer having a bank-shape is present; and a third part disposed between the first part and the second part in plan view and having a shape of a circumferential groove in which the resin insulating layer is not present. In the third part, wiring is on an inorganic insulating layer that is lower by a layer than the resin insulating layer. The wiring on the inorganic insulating layer is spaced away from the second portion of the resin insulating layer.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: July 9, 2019
    Assignee: JOLED INC.
    Inventors: Kenji Harada, Yasuharu Shinokawa, Akifumi Okigawa, Keiji Horikawa
  • Patent number: 10269892
    Abstract: An organic light-emitting display apparatus and a manufacturing method thereof. The organic light-emitting display apparatus includes a substrate, a display unit arranged on the substrate, a dam unit arranged at a periphery of the display unit and on the substrate and an encapsulating layer to encapsulate the display unit, wherein the encapsulating layer includes an organic film covering the display unit, and an inorganic film covering the organic film and the dam unit, and wherein a hardness of the dam unit is lower than that of the inorganic film. According to this, lateral moisture-proof characteristics of the organic light-emitting display apparatus are improved.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: April 23, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Min-Ho Oh, Yoon-Hyeung Cho, Yong-Tak Kim, So-Young Lee, Jong-Woo Kim, Ji-Young Moon
  • Patent number: 10209125
    Abstract: A semiconductor device for flame detection, including: a semiconductor body having a first conductivity type conductivity, delimited by a front surface and forming a cathode region; an anode region having a second conductivity type conductivity, which extends within the semiconductor body, starting from the front surface, and forms, together with the cathode region, the junction of a photodiode that detect ultraviolet radiation emitted by the flames; a supporting dielectric region; and a sensitive region, which is arranged on the supporting dielectric region and varies its own resistance as a function of the infrared radiation emitted by the flames.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: February 19, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Massimo Cataldo Mazzillo, Antonella Sciuto
  • Patent number: 10128383
    Abstract: A thin film transistor array substrate includes a first conductive pattern group including a gate line extending along a first direction, data lines extending along a second direction crossing the first direction and spaced apart from each other along the second direction with the gate line there between, and a gate electrode protruding from the gate line, an active pattern disposed on the gate electrode to overlap the gate electrode, a second conductive pattern group including a bridge pattern coupling the data lines, a source electrode extending to an upper portion of the active pattern from the bridge pattern and a drain electrode spaced apart from the source electrode, facing the source electrode and disposed on the active pattern and metal patterns each stacked between the active pattern and the source electrode and between the active pattern and the drain electrode.
    Type: Grant
    Filed: January 3, 2016
    Date of Patent: November 13, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Jong Hyun Choung
  • Patent number: 9952094
    Abstract: A semiconductor device for flame detection, including: a semiconductor body having a first conductivity type conductivity, delimited by a front surface and forming a cathode region; an anode region having a second conductivity type conductivity, which extends within the semiconductor body, starting from the front surface, and forms, together with the cathode region, the junction of a photodiode that detect ultraviolet radiation emitted by the flames; a supporting dielectric region; and a sensitive region, which is arranged on the supporting dielectric region and varies its own resistance as a function of the infrared radiation emitted by the flames.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: April 24, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Massimo Cataldo Mazzillo, Antonella Sciuto
  • Patent number: 9929184
    Abstract: An array substrate and a fabrication method thereof, and a display panel are provided.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: March 27, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Seungjin Choi, Youngjin Song
  • Patent number: 9911818
    Abstract: A semiconductor device includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: March 6, 2018
    Assignee: ROHM CO., LTD.
    Inventors: Yuki Nakano, Ryota Nakamura, Katsuhisa Nagao
  • Patent number: 9911814
    Abstract: A semiconductor device includes a P-type semiconductor substrate, a plurality of N-type buried diffusion layers that are arranged in the semiconductor substrate, an N-type first semiconductor layer that is arranged in a first region on a first buried diffusion layer, an N-type second semiconductor layer that is arranged in a second region on a second buried diffusion layer, an N-type first impurity diffusion region that surrounds the first region in plan view, a P-type second impurity diffusion region that is arranged in the second semiconductor layer, an N-type third impurity diffusion region that is arranged in the second semiconductor layer, an N-type fourth impurity diffusion region that is arranged in the first semiconductor layer. The second region is a region in which an N-type impurity diffusion region that has a higher impurity concentration than the second semiconductor layer cannot be arranged.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: March 6, 2018
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Hiroaki Nitta, Kazunobu Kuwazawa
  • Patent number: 9876092
    Abstract: A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: January 23, 2018
    Assignee: ROHM CO., LTD.
    Inventor: Akihiro Hikasa
  • Patent number: 9859450
    Abstract: A method of making a CIGS/inorganic thin film tandem semiconductor device including the steps of depositing a textured buffer layer on an inexpensive substrate, depositing a metal-inorganic film from a eutectic alloy on the buffer layer, the metal being selected from a group of CIGS elements, and adding the remaining CIGS elements to the metal, thereby growing a CIGS film on the inorganic film for the tandem semiconductor device.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: January 2, 2018
    Assignee: SOLAR-TECTIC, LLC
    Inventor: Ashok Chaudhari
  • Patent number: 9802817
    Abstract: Method for making a N/MEMS device including a structure provided with an active part having a first suspended element and a second suspended element with different thicknesses, the method comprising the following steps of: forming, in a first substrate (100), a sacrificial zone (105), transferring a given layer onto the sacrificial zone, defining in said given layer a first suspended element facing the first sacrificial zone, defining a second suspended element in the first substrate and said given layer, releasing at least the first suspended element.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: October 31, 2017
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventor: Audrey Berthelot
  • Patent number: 9786727
    Abstract: The present invention provides a display substrate and a manufacturing method thereof, and a flexible display device including the display substrate, which belong to the field of display technology, and can solve the problem of poor reliability of an existing display substrate due to damage to thin film transistors when the display substrate is bent. In the display substrate provided by the present invention, by providing the stress absorbing units made of a resin material in the display substrate, the stress generated during bending of the display substrate is released through the transparent resin material and the thin film transistors on the display substrate are unlikely to be damaged, thereby improving the reliability of the whole display substrate.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: October 10, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hongfei Cheng, Yuxin Zhang
  • Patent number: 9741804
    Abstract: A thin film transistor (TFT) substrate includes a substrate and a TFT. The TFT is disposed on the substrate and comprises a gate, a gate dielectric layer, a film, a source and a drain. The gate is disposed on the substrate. The gate dielectric layer is disposed on the gate and the substrate. The film is disposed above the gate dielectric layer, and the source and the drain are disposed on the film and contacts with the film respectively. Wherein, there is an interval between the source and the drain, and the film corresponding to the interval has an arc concave portion. In addition, a display panel is also disclosed.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: August 22, 2017
    Assignee: INNOLUX CORPORATION
    Inventors: Jung-Fang Chang, I-Ho Shen
  • Patent number: 9577001
    Abstract: The integrated imaging device comprises a substrate (1) with an integrated circuit (4), a cover (2), a cavity (6) enclosed between the substrate (1) and the cover (2), and a sensor (5) or an array of sensors (5) arranged in the cavity (6). A surface (11, 12) of the substrate (1) or the cover (2) opposite the cavity (6) has a structure (8) directing incident radiation. The surface structure (8) may be a plate zone or a Fresnel lens focusing infrared radiation and may be etched into the surface of the substrate or cover, respectively.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: February 21, 2017
    Assignee: AMS AG
    Inventors: Hubert Enichlmair, Rainer Minixhofer, Martin Schrems
  • Patent number: 9502496
    Abstract: A semiconductor device includes a vertical trench gate element portion and a lateral n-channel element portion for control which includes a well diffusion region, and a junction edge termination region which surrounds the vertical trench gate element portion and the lateral n-channel element portion for control. The junction edge termination region includes an oxide layer, a sustain region in contact with a trench provided at the end, and a diffusion region in contact with the sustain region. The diffusion region is deeper than the base region and has low concentration. The sustain region is shallower than the diffusion region and has high concentration. The well diffusion region is deeper than the base region and the sustain region and has low concentration. The breakdown voltage of the junction edge termination region and the well diffusion region is higher than that of the vertical trench gate element portion.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: November 22, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshiaki Toyoda
  • Patent number: 9491870
    Abstract: A display apparatus for improving corrosion resistance of a pad area and a method of manufacturing the same. The display apparatus includes a first substrate including a display area, a non-display area, and a pad area, and a second substrate facing the first substrate and corresponding to at least the display area, wherein the pad area includes, a connection area connected to a driving circuit; an exposed area spaced from the connection area; and a plurality of blocking areas between the connection area and the exposed area.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: November 8, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sun Park, Chun-Gi You
  • Patent number: 9484475
    Abstract: Disclosed herein are ferroelectric perovskites characterized as having a band gap, Egap, of less than 2.5 eV. Also disclosed are compounds comprising a solid solution of KNbO3 and BaNi1/2Nb1/2O3-delta, wherein delta is in the range of from 0 to about 1. The specification also discloses photovoltaic devices comprising one or more solar absorbing layers, wherein at least one of the solar absorbing layers comprises a semiconducting ferroelectric layer. Finally, this patent application provides solar cell, comprising: a heterojunction of n- and p-type semiconductors characterized as comprising an interface layer disposed between the n- and p-type semiconductors, the interface layer comprising a semiconducting ferroelectric absorber layer capable of enhancing light absorption and carrier separation.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: November 1, 2016
    Assignees: The Trustees Of The University Of Pennsylvania, Drexel University
    Inventors: Andrew M Rappe, Peter K Davies, Jonathan E Spanier, Ilya Grinberg, Don Vincent West
  • Patent number: 9460919
    Abstract: A manufacturing method of a two-dimensional transition-metal chalcogenide thin film includes providing a substrate, providing a reaction film, providing a source and providing a microwave. The substrate is made of material having dipole moments. The reaction film, disposed on the substrate, has a predefined thickness and includes a transition-metal compound. The source includes S, Se, or Te. The substrate is heated by the microwave to produce a heat energy to the reaction film and the source; thus a chemical reaction takes place and the two-dimensional transition-metal chalcogenide thin film is formed on the substrate. The two-dimensional transition-metal thin film includes a plurality of elements, and each of the elements aligns along a predefined direction by controlling a value of the predefined thickness.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: October 4, 2016
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Yu-Lun Chueh, Yu-Ze Chen, Yi-Chen Hsieh, Henry Medina
  • Patent number: 9437835
    Abstract: Embodiments of the invention are directed to a transparent up-conversion device having two transparent electrodes. In embodiments of the invention, the up-conversion device comprises a stack of layers proceeding from a transparent substrate including an anode, a hole blocking layer, an IR sensitizing layer, a hole transport layer, a light emitting layer, an electron transport layer, a cathode, and an antireflective layer. In an embodiment of the invention, the up-conversion device includes an IR pass visible blocking layer.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: September 6, 2016
    Assignees: University of Florida Research Foundation, Inc., Nanoholdings, LLC
    Inventors: Franky So, Do Young Kim, Bhabendra K. Pradhan
  • Patent number: 9401498
    Abstract: To provide a substrate which is light and has high reliability and high light extraction efficiency from an organic EL element. To provide a substrate which includes a protective layer in a resin layer, an uneven structure on a light incident surface, and an opening which surrounds the uneven structure and through which the protective layer is exposed. To provide a light-emitting device which includes a resin layer provided with an uneven structure on a light incident surface over a protective layer, and a light-emitting element in the protective layer and a counter substrate which are bonded with a sealant. The protective layer and the resin layer have a property of transmitting visible light. The light-emitting element includes a light-transmitting first electrode over a resin layer, a layer containing a light-transmitting organic compound over the first electrode, and a second electrode over the layer containing a light-transmitting organic compound.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: July 26, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koichiro Tanaka, Yusuke Nishido
  • Patent number: 9337314
    Abstract: A method to selectively process a three dimensional device, comprising providing a substrate having a first surface that extends horizontally, the substrate comprising a structure containing a second surface that extends vertically from the first surface; providing a film on the substrate, the film comprising carbon species; and etching a selected portion of the film by exposing the selected portion of the film to an etchant containing hydrogen species, where the etchant excludes oxygen species and fluorine species.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: May 10, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nilay A. Pradhan, Benjamin Colombeau, Naushad K. Variam, Mandar B. Pandit, Christopher Dennis Bencher, Adam Brand