Non-single Crystal, Or Recrystallized, Semiconductor Material Forms Part Of Active Junction (including Field-induced Active Junction) Patents (Class 257/49)
  • Patent number: 10600825
    Abstract: The invention provides a manufacturing method for TFT array substrate and TFT array substrate. The manufacturing method forms a first buffer layer on the substrate; the first buffer layer is disposed with a plurality of arc protrusions or a plurality of arc recesses; then an a-Si layer is formed on the second buffer layer which is formed on the first buffer layer; in the process of forming a polysilicon layer by performing ELA on the a-Si layer, the arc protrusions or the arc recesses can change the optical path of the laser to form an energy gradient in the a-Si layer, so as to increase the grain size in the formed polysilicon layer, reduce the number of grain boundaries, improve the carrier mobility of the TFT device, and improve the electrical properties of the TFT device.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: March 24, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Ruijun Zhang, Song Wang
  • Patent number: 10593748
    Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a flowable insulating layer or a reflowable insulating layer.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: March 17, 2020
    Assignee: GlobalWafers Co., Ltd.
    Inventor: Sasha Joseph Kweskin
  • Patent number: 10566325
    Abstract: A semiconductor device, including a semiconductor layer of a first conductivity type, having a main surface with a diode trench formed therein, an inner wall insulating film, including a side wall insulating film, formed along side walls of the diode trench, and a bottom wall insulating film, formed along a bottom wall of the diode trench and having a thickness greater than a thickness of the side wall insulating film, and a bidirectional Zener diode, formed on the bottom wall insulating film inside the diode trench and having a pair of first conductivity type portions and at least one second conductivity type portion formed between the pair of first conductivity type portions.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: February 18, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Kenji Nishida, Shinpei Ohnishi, Kentaro Nasu
  • Patent number: 10510957
    Abstract: A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: December 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Agostino Pirovano, Fabio Pellizzer, Anna Maria Conti, Andrea Redaelli, Innocenzo Tortorelli
  • Patent number: 10461220
    Abstract: A method of manufacturing a semiconductor device and the device resulted thereof is disclosed. In one aspect, the device has a heterogeneous layer stack of one or more III-V type materials, at least one transmission layer of the layer stack having a roughened or textured surface for enhancement of light transmission. The method includes (a) growing the transmission layer of a III-V type material, (b) providing a mask layer on the transmission layer, the mask layer leaving first portions of the transmission layer exposed, and (c) partially decomposing the first exposed portions of the transmission layer. Suitably redeposition occurs in a single step with decomposition, so as to obtain a textured surface based on crystal facets of a plurality of grown crystals. The resulting device has a light-emitting element. The transmission layer hereof is suitably present at the top side.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: October 29, 2019
    Assignee: IMEC
    Inventor: Kai Cheng
  • Patent number: 10424524
    Abstract: Disclosed is a method of manufacturing a semiconductor device that includes adhering a plurality of semiconductor substrates and a framing member to a supporting surface of a carrier substrate. The semiconductor substrates can be wafers that can be diced or cut into a plurality of dies. Thus, the wafers each have respective active surfaces and at least one respective integrated circuit region. The method can further include encapsulating the framing member and the plurality of semiconductor substrates within an encapsulant. Subsequently, the carrier substrate is removed and a redistribution layer (RDL) is formed on the semiconductor substrates and the framing member.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: September 24, 2019
    Assignees: CHENGDU ESWIN SIP TECHNOLOGY CO., LTD., BEIJING ESWIN TECHNOLOGY CO., LTD.
    Inventors: Minghao Shen, Xiaotian Zhou
  • Patent number: 10379945
    Abstract: Techniques are disclosed for generating codes for representation of data in memory devices that may avoid the block erasure operation in changing data values. Data values comprising binary digits (bits) can be encoded and decoded using the generated codes, referred to as codewords, such that the codewords may comprise a block erasure-avoiding code, in which the binary digits of a data message m can be encoded such that the encoded data message can be stored into multiple memory cells of a data device and, once a memory cell value is changed from a first logic value to a second logic value, the value of the memory cell may remain at the second logic value, regardless of subsequently received messages, until a block erasure operation on the memory cell.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: August 13, 2019
    Assignees: CALIFORNIA INSTITUTE OF TECHNOLOGY, THE TEXAS A & M UNIVERSITY SYSTEM
    Inventors: Eyal En Gad, Yue Li, Joerg Kliewer, Michael Langberg, Anxiao Jiang, Jehoshua Bruck
  • Patent number: 10373818
    Abstract: Methods are provided for recycling a dummy wafer so that the dummy wafer may be repeatedly used in a deposition process. The dummy wafer includes a substrate and an oxide layer on the substrate that is formed by the deposition process. A thickness of the oxide layer on the dummy wafer may be measured, and the dummy wafer may be subjected to recycling depending on whether the measured thickness of the oxide layer exceeds a threshold thickness. The dummy wafer is recycled by removing the oxide layer, which may be accomplished by performing an etching process. A mechanical polishing process may be performed to smooth the surface of the substrate. The dummy wafer may then be reused in a subsequent deposition process.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: August 6, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hua Cheng, Yen-Hsun Wu
  • Patent number: 10361291
    Abstract: To reduce defects in an oxide semiconductor film in a semiconductor device. To improve the electrical characteristics and the reliability of a semiconductor device including an oxide semiconductor film. In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: July 23, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Yukinori Shima, Hajime Tokunaga, Toshinari Sasaki, Keisuke Murayama, Daisuke Matsubayashi
  • Patent number: 10355069
    Abstract: An organic light emitting diode display includes a substrate; a buffer layer on the substrate; a scan line running to a horizontal direction on the buffer layer; an intermediate insulating layer covering the scan line; a first trench having a segment shape apart from the scan line with a predetermined distance and exposing some of the substrate by patterning the intermediate insulating layer and the buffer layer; a data line running to a vertical direction on the substrate exposed by the first trench and on the intermediate insulating layer; a passivation layer covering the data line and the scan line; and a color filter filling into the trench and depositing on the passivation layer.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: July 16, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Dosung Kim, Ryosuke Tani
  • Patent number: 10347865
    Abstract: An organic electroluminescence (EL) display panel includes a multi-layered wiring laminate including: a first part on which an organic EL element array is disposed and in which a first portion of a resin insulating layer is present, the resin insulating layer being a highest layer among insulating layers; a second part surrounding the first part in plan view and in which a second portion of the resin insulating layer having a bank-shape is present; and a third part disposed between the first part and the second part in plan view and having a shape of a circumferential groove in which the resin insulating layer is not present. In the third part, wiring is on an inorganic insulating layer that is lower by a layer than the resin insulating layer. The wiring on the inorganic insulating layer is spaced away from the second portion of the resin insulating layer.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: July 9, 2019
    Assignee: JOLED INC.
    Inventors: Kenji Harada, Yasuharu Shinokawa, Akifumi Okigawa, Keiji Horikawa
  • Patent number: 10269892
    Abstract: An organic light-emitting display apparatus and a manufacturing method thereof. The organic light-emitting display apparatus includes a substrate, a display unit arranged on the substrate, a dam unit arranged at a periphery of the display unit and on the substrate and an encapsulating layer to encapsulate the display unit, wherein the encapsulating layer includes an organic film covering the display unit, and an inorganic film covering the organic film and the dam unit, and wherein a hardness of the dam unit is lower than that of the inorganic film. According to this, lateral moisture-proof characteristics of the organic light-emitting display apparatus are improved.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: April 23, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Min-Ho Oh, Yoon-Hyeung Cho, Yong-Tak Kim, So-Young Lee, Jong-Woo Kim, Ji-Young Moon
  • Patent number: 10209125
    Abstract: A semiconductor device for flame detection, including: a semiconductor body having a first conductivity type conductivity, delimited by a front surface and forming a cathode region; an anode region having a second conductivity type conductivity, which extends within the semiconductor body, starting from the front surface, and forms, together with the cathode region, the junction of a photodiode that detect ultraviolet radiation emitted by the flames; a supporting dielectric region; and a sensitive region, which is arranged on the supporting dielectric region and varies its own resistance as a function of the infrared radiation emitted by the flames.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: February 19, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Massimo Cataldo Mazzillo, Antonella Sciuto
  • Patent number: 10128383
    Abstract: A thin film transistor array substrate includes a first conductive pattern group including a gate line extending along a first direction, data lines extending along a second direction crossing the first direction and spaced apart from each other along the second direction with the gate line there between, and a gate electrode protruding from the gate line, an active pattern disposed on the gate electrode to overlap the gate electrode, a second conductive pattern group including a bridge pattern coupling the data lines, a source electrode extending to an upper portion of the active pattern from the bridge pattern and a drain electrode spaced apart from the source electrode, facing the source electrode and disposed on the active pattern and metal patterns each stacked between the active pattern and the source electrode and between the active pattern and the drain electrode.
    Type: Grant
    Filed: January 3, 2016
    Date of Patent: November 13, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Jong Hyun Choung
  • Patent number: 9952094
    Abstract: A semiconductor device for flame detection, including: a semiconductor body having a first conductivity type conductivity, delimited by a front surface and forming a cathode region; an anode region having a second conductivity type conductivity, which extends within the semiconductor body, starting from the front surface, and forms, together with the cathode region, the junction of a photodiode that detect ultraviolet radiation emitted by the flames; a supporting dielectric region; and a sensitive region, which is arranged on the supporting dielectric region and varies its own resistance as a function of the infrared radiation emitted by the flames.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: April 24, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Massimo Cataldo Mazzillo, Antonella Sciuto
  • Patent number: 9929184
    Abstract: An array substrate and a fabrication method thereof, and a display panel are provided.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: March 27, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Seungjin Choi, Youngjin Song
  • Patent number: 9911814
    Abstract: A semiconductor device includes a P-type semiconductor substrate, a plurality of N-type buried diffusion layers that are arranged in the semiconductor substrate, an N-type first semiconductor layer that is arranged in a first region on a first buried diffusion layer, an N-type second semiconductor layer that is arranged in a second region on a second buried diffusion layer, an N-type first impurity diffusion region that surrounds the first region in plan view, a P-type second impurity diffusion region that is arranged in the second semiconductor layer, an N-type third impurity diffusion region that is arranged in the second semiconductor layer, an N-type fourth impurity diffusion region that is arranged in the first semiconductor layer. The second region is a region in which an N-type impurity diffusion region that has a higher impurity concentration than the second semiconductor layer cannot be arranged.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: March 6, 2018
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Hiroaki Nitta, Kazunobu Kuwazawa
  • Patent number: 9911818
    Abstract: A semiconductor device includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: March 6, 2018
    Assignee: ROHM CO., LTD.
    Inventors: Yuki Nakano, Ryota Nakamura, Katsuhisa Nagao
  • Patent number: 9876092
    Abstract: A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: January 23, 2018
    Assignee: ROHM CO., LTD.
    Inventor: Akihiro Hikasa
  • Patent number: 9859450
    Abstract: A method of making a CIGS/inorganic thin film tandem semiconductor device including the steps of depositing a textured buffer layer on an inexpensive substrate, depositing a metal-inorganic film from a eutectic alloy on the buffer layer, the metal being selected from a group of CIGS elements, and adding the remaining CIGS elements to the metal, thereby growing a CIGS film on the inorganic film for the tandem semiconductor device.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: January 2, 2018
    Assignee: SOLAR-TECTIC, LLC
    Inventor: Ashok Chaudhari
  • Patent number: 9802817
    Abstract: Method for making a N/MEMS device including a structure provided with an active part having a first suspended element and a second suspended element with different thicknesses, the method comprising the following steps of: forming, in a first substrate (100), a sacrificial zone (105), transferring a given layer onto the sacrificial zone, defining in said given layer a first suspended element facing the first sacrificial zone, defining a second suspended element in the first substrate and said given layer, releasing at least the first suspended element.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: October 31, 2017
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventor: Audrey Berthelot
  • Patent number: 9786727
    Abstract: The present invention provides a display substrate and a manufacturing method thereof, and a flexible display device including the display substrate, which belong to the field of display technology, and can solve the problem of poor reliability of an existing display substrate due to damage to thin film transistors when the display substrate is bent. In the display substrate provided by the present invention, by providing the stress absorbing units made of a resin material in the display substrate, the stress generated during bending of the display substrate is released through the transparent resin material and the thin film transistors on the display substrate are unlikely to be damaged, thereby improving the reliability of the whole display substrate.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: October 10, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hongfei Cheng, Yuxin Zhang
  • Patent number: 9741804
    Abstract: A thin film transistor (TFT) substrate includes a substrate and a TFT. The TFT is disposed on the substrate and comprises a gate, a gate dielectric layer, a film, a source and a drain. The gate is disposed on the substrate. The gate dielectric layer is disposed on the gate and the substrate. The film is disposed above the gate dielectric layer, and the source and the drain are disposed on the film and contacts with the film respectively. Wherein, there is an interval between the source and the drain, and the film corresponding to the interval has an arc concave portion. In addition, a display panel is also disclosed.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: August 22, 2017
    Assignee: INNOLUX CORPORATION
    Inventors: Jung-Fang Chang, I-Ho Shen
  • Patent number: 9577001
    Abstract: The integrated imaging device comprises a substrate (1) with an integrated circuit (4), a cover (2), a cavity (6) enclosed between the substrate (1) and the cover (2), and a sensor (5) or an array of sensors (5) arranged in the cavity (6). A surface (11, 12) of the substrate (1) or the cover (2) opposite the cavity (6) has a structure (8) directing incident radiation. The surface structure (8) may be a plate zone or a Fresnel lens focusing infrared radiation and may be etched into the surface of the substrate or cover, respectively.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: February 21, 2017
    Assignee: AMS AG
    Inventors: Hubert Enichlmair, Rainer Minixhofer, Martin Schrems
  • Patent number: 9502496
    Abstract: A semiconductor device includes a vertical trench gate element portion and a lateral n-channel element portion for control which includes a well diffusion region, and a junction edge termination region which surrounds the vertical trench gate element portion and the lateral n-channel element portion for control. The junction edge termination region includes an oxide layer, a sustain region in contact with a trench provided at the end, and a diffusion region in contact with the sustain region. The diffusion region is deeper than the base region and has low concentration. The sustain region is shallower than the diffusion region and has high concentration. The well diffusion region is deeper than the base region and the sustain region and has low concentration. The breakdown voltage of the junction edge termination region and the well diffusion region is higher than that of the vertical trench gate element portion.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: November 22, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshiaki Toyoda
  • Patent number: 9491870
    Abstract: A display apparatus for improving corrosion resistance of a pad area and a method of manufacturing the same. The display apparatus includes a first substrate including a display area, a non-display area, and a pad area, and a second substrate facing the first substrate and corresponding to at least the display area, wherein the pad area includes, a connection area connected to a driving circuit; an exposed area spaced from the connection area; and a plurality of blocking areas between the connection area and the exposed area.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: November 8, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sun Park, Chun-Gi You
  • Patent number: 9484475
    Abstract: Disclosed herein are ferroelectric perovskites characterized as having a band gap, Egap, of less than 2.5 eV. Also disclosed are compounds comprising a solid solution of KNbO3 and BaNi1/2Nb1/2O3-delta, wherein delta is in the range of from 0 to about 1. The specification also discloses photovoltaic devices comprising one or more solar absorbing layers, wherein at least one of the solar absorbing layers comprises a semiconducting ferroelectric layer. Finally, this patent application provides solar cell, comprising: a heterojunction of n- and p-type semiconductors characterized as comprising an interface layer disposed between the n- and p-type semiconductors, the interface layer comprising a semiconducting ferroelectric absorber layer capable of enhancing light absorption and carrier separation.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: November 1, 2016
    Assignees: The Trustees Of The University Of Pennsylvania, Drexel University
    Inventors: Andrew M Rappe, Peter K Davies, Jonathan E Spanier, Ilya Grinberg, Don Vincent West
  • Patent number: 9460919
    Abstract: A manufacturing method of a two-dimensional transition-metal chalcogenide thin film includes providing a substrate, providing a reaction film, providing a source and providing a microwave. The substrate is made of material having dipole moments. The reaction film, disposed on the substrate, has a predefined thickness and includes a transition-metal compound. The source includes S, Se, or Te. The substrate is heated by the microwave to produce a heat energy to the reaction film and the source; thus a chemical reaction takes place and the two-dimensional transition-metal chalcogenide thin film is formed on the substrate. The two-dimensional transition-metal thin film includes a plurality of elements, and each of the elements aligns along a predefined direction by controlling a value of the predefined thickness.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: October 4, 2016
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Yu-Lun Chueh, Yu-Ze Chen, Yi-Chen Hsieh, Henry Medina
  • Patent number: 9437835
    Abstract: Embodiments of the invention are directed to a transparent up-conversion device having two transparent electrodes. In embodiments of the invention, the up-conversion device comprises a stack of layers proceeding from a transparent substrate including an anode, a hole blocking layer, an IR sensitizing layer, a hole transport layer, a light emitting layer, an electron transport layer, a cathode, and an antireflective layer. In an embodiment of the invention, the up-conversion device includes an IR pass visible blocking layer.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: September 6, 2016
    Assignees: University of Florida Research Foundation, Inc., Nanoholdings, LLC
    Inventors: Franky So, Do Young Kim, Bhabendra K. Pradhan
  • Patent number: 9401498
    Abstract: To provide a substrate which is light and has high reliability and high light extraction efficiency from an organic EL element. To provide a substrate which includes a protective layer in a resin layer, an uneven structure on a light incident surface, and an opening which surrounds the uneven structure and through which the protective layer is exposed. To provide a light-emitting device which includes a resin layer provided with an uneven structure on a light incident surface over a protective layer, and a light-emitting element in the protective layer and a counter substrate which are bonded with a sealant. The protective layer and the resin layer have a property of transmitting visible light. The light-emitting element includes a light-transmitting first electrode over a resin layer, a layer containing a light-transmitting organic compound over the first electrode, and a second electrode over the layer containing a light-transmitting organic compound.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: July 26, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koichiro Tanaka, Yusuke Nishido
  • Patent number: 9337314
    Abstract: A method to selectively process a three dimensional device, comprising providing a substrate having a first surface that extends horizontally, the substrate comprising a structure containing a second surface that extends vertically from the first surface; providing a film on the substrate, the film comprising carbon species; and etching a selected portion of the film by exposing the selected portion of the film to an etchant containing hydrogen species, where the etchant excludes oxygen species and fluorine species.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: May 10, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nilay A. Pradhan, Benjamin Colombeau, Naushad K. Variam, Mandar B. Pandit, Christopher Dennis Bencher, Adam Brand
  • Patent number: 9319613
    Abstract: An image sensor array has a tiling unit comprising a source follower stage coupled to buffer signals from a photodiode when the unit is read onto a sense line, the source follower stage differs from conventional sensor arrays because it uses an N-channel transistor having a P-doped polysilicon gate. In embodiments, other transistors of the array have conventional N-channel transistors with N-doped polysilicon gates.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: April 19, 2016
    Assignee: OmniVision Technologies, Inc.
    Inventor: Tiejun Dai
  • Patent number: 9268346
    Abstract: Disclosed herein is a reactor including, a plurality of reaction regions, and a plurality of heaters, each arranged in each of the reaction regions, wherein the heater including a semiconductor heat generating element and a semiconductor temperature detecting element and being capable of independent temperature control, and the temperature detecting element having a heat conduction region of metal thin film in its surrounding region.
    Type: Grant
    Filed: April 13, 2009
    Date of Patent: February 23, 2016
    Assignee: Sony Corporation
    Inventors: Toshiki Moriwaki, Nobuhiro Kanai, Takanori Anaguchi
  • Patent number: 9236400
    Abstract: A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, a GOLD structure or an LDD structure. A pixel TFT has the LDD structure. A pixel electrode disposed in a pixel portion is connected to the pixel TFT through a hole bored in at least a protective insulation film formed of an inorganic insulating material and formed above a gate electrode of the pixel TFT, and in an interlayer insulating film disposed on the insulation film in close contact therewith. These process steps use 6 to 8 photo-masks.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: January 12, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuyuki Arai, Jun Koyama
  • Patent number: 9194985
    Abstract: A color filter substrate comprising: a base plate; a first conductive layer formed on the base plate in a first direction; a color resistance layer formed on the first conductive layer at positions at least corresponding to pixel regions, wherein the color resistance layer is formed with via holes at positions corresponding to each sub-pixel region; a black matrix formed on the first conductive layer at positions corresponding to pixel gaps; a second conductive layer formed on the surfaces of the black matrix and the color resistance layer in a second direction different from the first direction; a dielectric layer formed at least on the second conductive layer, wherein the dielectric layer is formed with via holes corresponding to the via holes in the color resistance layer; and a third conductive layer formed on the dielectric layer and electrically connected with a corresponding portion of the first conductive layer through aligned via holes of the color resistance layer and the dielectric layer.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: November 24, 2015
    Assignees: BOE TECHNOLOGY GROUPCO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Lan Feng, Qingna Hou
  • Patent number: 9184314
    Abstract: Solar cell structures and formation methods which utilize the surface texture in conjunction with a passivating dielectric layer to provide a practical and controllable technique of forming an electrical contact between a conducting layer and underlying substrate through the passivating dielectric layer, achieving both good surface passivation and electrical contact with low recombination losses, as required for high efficiency solar cells. The passivating dielectric layer is intentionally modified to allow direct contact, or tunnel barrier contact, with the substrate. Additional P-N junctions, and dopant gradients, are disclosed to further limit losses and increase efficiency.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: November 10, 2015
    Assignee: TETRASUN, INC.
    Inventors: Douglas Crafts, Oliver Schultz-Wittman
  • Patent number: 9171955
    Abstract: The present invention provides a structure of the TFT in which a current-voltage characteristic can be improved. The present invention refers to a thin film transistor comprising a lamination layer wherein a first conductive film, a first insulating film and a second conductive film are sequentially laminated, a semiconductor film formed so as to be in contact with the side surface of the lamination layer, and a third conductive film covering the semiconductor film through a second insulating film. The first conductive film and the second conductive film are a source electrode and a drain electrode, and a region which is in contact with the first insulating film and the third conductive film is a channel forming region in semiconductor film, and the third conductive film is a gate electrode.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: October 27, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiharu Hirakata, Yukie Nemoto
  • Patent number: 9153510
    Abstract: A semiconductor device includes a semiconductor substrate provided with a predetermined element and having wirings formed on its main surface connected to back wirings by a plurality of through silicon vias (TSVs), and a conductive cover which covers the main surface of the semiconductor substrate. The semiconductor substrate and the conductive cover are bonded to each other with a conductive bonding member. The TSV bonded to the conductive cover with the conductive bonding member is connected to an external electrode pad to which a ground potential is supplied.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: October 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masafumi Sugimoto, Eiichi Hosomi, Atsushi Murakawa, Kazumi Takahashi, Kazuhito Higuchi, Susumu Obata
  • Patent number: 9070812
    Abstract: An active matrix substrate includes: an electrode layer formed on the insulating substrate within a display region; a mark disposed on the insulating substrate within a non-display region, and made of a same material as the electrode layer; a first insulating film directly covering each of the electrode layer and the mark; and a second insulating film covering a part of the first insulating film. Within at least a part of the sealing region, the second insulating film is removed from the insulating substrate. The mark is disposed in the at least the part of the sealing region in which the second insulating film is removed, and is provided to overlap at least a part of the sealing region. A protective film is formed on the insulating substrate to cover a side surface and a surface of the first insulating film covering the mark, the surface of the first insulating film being located opposite from the insulating substrate.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: June 30, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiro Yoshida, Takaharu Yamada, Satoshi Horiuchi, Kazuyori Mitsumoto
  • Patent number: 9040987
    Abstract: A semiconductor device including a substrate, a metal layer, an insulating layer, a semiconductor layer, a drain and a source is provided. The substrate has a surface and a first cavity. The metal layer is disposed on the substrate and covers the surface and inner-wall of the first cavity to define a second cavity corresponding to the first cavity. The insulating layer covers the metal layer and inner-wall of the second cavity to define a third cavity corresponding to the second cavity. The semiconductor layer exposes a portion of the insulating layer and covers the inner-wall of the third cavity to define a fourth cavity corresponding to the third cavity. The drain and source are disposed on the semiconductor layer and covers a portion of the semiconductor layer and a portion of the insulating layer, in which the drain and source expose the fourth cavity.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: May 26, 2015
    Assignee: E Ink Holdings Inc.
    Inventors: Wei-Chou Lan, Ted-Hong Shinn, Henry Wang, Chia-Chun Yeh
  • Patent number: 9041202
    Abstract: An object is to provide a semiconductor device with high aperture ratio or a manufacturing method thereof. Another object is to provide semiconductor device with low power consumption or a manufacturing method thereof. A light-transmitting conductive layer which functions as a gate electrode, a gate insulating film formed over the light-transmitting conductive layer, a semiconductor layer formed over the light-transmitting conductive layer which functions as the gate electrode with the gate insulating film interposed therebetween, and a light-transmitting conductive layer which is electrically connected to the semiconductor layer and functions as source and drain electrodes are included.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: May 26, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 9035415
    Abstract: A technology for a vertical semiconductor device having a RESURF structure, which is capable of preventing the drop of the withstand voltage when the adhesion of external electric charges occurs is provided. The vertical semiconductor device disclosed in the present specification has a cell region and a non-cell region disposed outside the cell region. This vertical semiconductor device has a diffusion layer disposed in at least part of the non-cell region. When the vertical semiconductor device is viewed in a plane, the diffusion layer has an impurity surface density higher than that satisfying a RESURF condition at an end part close to the cell region, and an impurity surface density lower than that satisfying the RESURF condition at an end part far from the cell region.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: May 19, 2015
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Masaru Senoo
  • Patent number: 9012912
    Abstract: Glass treatment methods, wafer, panels, and semiconductor devices are disclosed. In some embodiments, a method of treating a glass substrate includes forming a first film on the glass substrate, the first film having a first porosity. The method includes forming a second film on the first film, the second film comprising an electrically insulating material and having a second porosity. The first porosity is lower than the second porosity.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: April 21, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Wen-Shiang Liao
  • Patent number: 9012900
    Abstract: An organic light emitting diode display device capable of improving capacitance Cst of a storage capacitor and transmittance and a method of fabricating the same are disclosed. The organic light emitting diode display device includes a driving thin film transistor (TFT) formed on the substrate, a passivation film formed to cover the TFT driver, a color filter formed on the passivation film in a luminescent region, a planarization film formed to cover the color filter, a transparent metal layer formed on the planarization film, an insulating film formed on the transparent metal layer, a first electrode connected to the TFT driver and overlapping the transparent metal layer while interposing the insulating film therebetween, an organic light emitting layer and a second electrode which are sequentially formed on the first electrode. The transparent metal layer, the insulating film, and the first electrode constitute a storage capacitor in the luminescent region.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: April 21, 2015
    Assignee: LG Display Co., Ltd.
    Inventors: Jung-Sun Beak, Jeong-Oh Kim, Yong-Min Kim
  • Patent number: 9006584
    Abstract: An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: April 14, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas Dyer Bonifield, Byron Williams, Shrinivasan Jaganathan, David Larkin, Dhaval Atul Saraiya
  • Patent number: 9000436
    Abstract: Disclosed is a thin film transistor including an active pattern including a first conductive region, a first channel region adjacent to the first conductive region, a second conductive region spaced apart from the first conductive region, a second channel region spaced apart from the first channel region, and a third conductive region spaced apart from the second conductive region, and a gate electrode positioned on the active pattern and including a first gate region crossing the first channel region, a second gate region crossing the second channel region, and a connection gate region connecting the first gate region. The connection gate region, the first gate region, and the second gate region together surround the second conductive region.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: April 7, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: So-Ra Kwon
  • Patent number: 8999105
    Abstract: An etch mask is formed on a substrate. The substrate is positioned in an enclosure configured to shield an interior of the enclosure from electromagnetic fields exterior to the enclosure; and the substrate is etched in the enclosure, including removing a portion of the substrate to form a structure having at least a portion that is isolated and/or suspended over the substrate.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: April 7, 2015
    Assignee: President and Fellows of Harvard College
    Inventors: Marko Loncar, Mikhail D. Lukin, Michael J. Burek, Nathalie de Leon, Brendan Shields
  • Patent number: 8994021
    Abstract: An oxide semiconductor film which has more stable electric conductivity is provided. The oxide semiconductor film comprises a crystalline region. The oxide semiconductor film has a first peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.4 nm?1 and less than or equal to 0.7 nm?1 in a region where a magnitude of a scattering vector is greater than or equal to 3.3 nm?1 and less than or equal to 4.1 nm?1. The oxide semiconductor film has a second peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.45 nm?1 and less than or equal to 1.4 nm?1 in a region where a magnitude of a scattering vector is greater than or equal to 5.5 nm?1 and less than or equal to 7.1 nm?1.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masashi Tsubuku, Kengo Akimoto, Hiroki Ohara, Tatsuya Honda, Takatsugu Omata, Yusuke Nonaka, Masahiro Takahashi, Akiharu Miyanaga
  • Patent number: 8987737
    Abstract: Provided is a polycrystalline silicon wafer produced by a melting and unidirectional solidification method, where the polycrystalline silicon wafer has a diameter of 450 mm or more, a thickness of 900 ?m or more, and an average crystal grain size of 5 to 50 mm, and is made up of one piece. The present invention provides a large-sized polycrystalline silicon wafer having a wafer size of 450 mm or more, of which: mechanical properties are similar to those of monocrystalline silicon wafers; the crystal size is large; the surface roughness is low; the surface has a high cleanliness; the polished surface has less unevenness by having a definite crystal orientation; and the sag value is similar to that of monocrystalline silicon wafers.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: March 24, 2015
    Assignee: JX Nippon Mining & Metals Corporation
    Inventors: Hiroshi Takamura, Ryo Suzuki
  • Patent number: 8987736
    Abstract: Novel articles and methods to fabricate the same resulting in flexible, large-area, [100] or [110] textured, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: March 24, 2015
    Inventor: Amit Goyal