At Least Three Regions Of Alternating Conductivity Types With Dopant Concentration Gradients Decreasing From Surface Of Semiconductor (e.g., "triple-diffused" Integrated Circuit) Patents (Class 257/548)
  • Patent number: 10714612
    Abstract: A high voltage device includes: a semiconductor layer, an isolation structure, a drift oxide region, a well, a body region, a gate, at least one sub-gate, a source, a drain and a conductive connection structure. The drift oxide region is located on a drift region in an operation region. The sub-gate is formed on the drift oxide region in the operation region. The sub-gate is a rectangle shape extending along a width direction, and in parallel with the gate. A conductive connection structure connects the gate and the sub-gate.
    Type: Grant
    Filed: December 25, 2018
    Date of Patent: July 14, 2020
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Tsung-Yi Huang
  • Patent number: 9680009
    Abstract: In some embodiments, a semiconductor device includes a transistor, an isolation component, and a conductive layer. The transistor includes a source region and a drain region. The isolation component surrounds the source region. The conductive layer is configured for interconnection of the drain region. The conductive component is between the conductive layer and the isolation component, configured to shield the isolation component from an electric field over the isolation component.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: June 13, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Karthick Murukesan, Yi-Cheng Chiu, Hung-Chou Lin, Chih-Yuan Chan, Yi-Min Chen, Chen-Chien Chang, Chiu-Hua Chung, Fu-Chih Yang, Chun Lin Tsai
  • Patent number: 9225378
    Abstract: An RF switch circuit and method for switching RF signals that may be fabricated using common integrated circuit materials such as silicon, particularly using insulating substrate technologies. The RF switch includes switching and shunting transistor groupings to alternatively couple RF input signals to a common RF node, each controlled by a switching control voltage (SW) or its inverse (SW_), which are approximately symmetrical about ground. The transistor groupings each comprise one or more insulating gate FET transistors connected together in a “stacked” series channel configuration, which increases the breakdown voltage across the series connected transistors and improves RF switch compression. A fully integrated RF switch is described including control logic and a negative voltage generator with the RF switch elements. In one embodiment, the fully integrated RF switch includes an oscillator, a charge pump, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: December 29, 2015
    Assignee: Peregrine Semiconductor Corpopration
    Inventors: Mark L. Burgener, James S. Cable
  • Patent number: 9214932
    Abstract: Embodiments provide a switching device including one or more field-effect transistors (FETs). In embodiments, a body-bias circuit may derive a bias voltage based on a radio frequency signal applied to a switch field-effect transistor and apply the bias voltage to the body terminal of the switch field-effect transistor.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: December 15, 2015
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: William J. Clausen, James P. Furino, Jr., Michael D. Yore
  • Patent number: 9006863
    Abstract: A diode string voltage adapter includes diodes formed in a substrate of a first conductive type. Each diode includes a deep well region of a second conductive type formed in the substrate. A first well region of the first conductive type formed on the deep well region. A first heavily doped region of the first conductive type formed on the first well region. A second heavily doped region of the second conductive type formed on the first well region. The diodes are serially coupled to each other. A first heavily doped region of a beginning diode is coupled to a first voltage. A second heavily doped region of each diode is coupled to a first heavily doped region of a next diode. A second heavily doped region of an ending diode provides a second voltage. The deep well region is configured to be electrically floated.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Peng Hsieh, Jaw-Juinn Horng
  • Patent number: 8994194
    Abstract: A method of manufacturing a biosensor semiconductor device in which copper electrodes at a major surface of the device are modified to form Au—Cu alloy electrodes. Such modification is effected by depositing a gold layer over the device, and then thermally treating the device to promote interdiffusion between the gold and the electrode copper. Alloyed gold-copper is removed from the surface of the device, leaving the exposed electrodes. The electrodes are better compatible with further processing into a biosensor device than is the case with conventional copper electrodes, and the process windows are wider than for gold capped copper electrodes. A biosensor semiconductor device having Au—Cu alloy electrodes is also disclosed.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: March 31, 2015
    Assignee: NXP, B.V.
    Inventors: David van Steenwinckel, Thomas Merelle, Franciscus Petrus Widdershoven, Viet Hoang Nguyen, Dimitri Soccol, Jan Leo Dominique Fransaer
  • Patent number: 8933534
    Abstract: An isolation structure of a high-voltage driving circuit includes a P-type substrate and a P-type epitaxial layer; a high voltage area, a low voltage area and a high and low voltage junction terminal area are arranged on the P-type epitaxial layer; a first P-type junction isolation area is arranged between the high and low voltage junction terminal area and the low voltage area, and a high-voltage insulated gate field effect tube is arranged between the high voltage area and the low voltage area; two sides of the high-voltage insulated gate field effect tube and an isolation structure between the high-voltage insulated gate field effect tube and a high side area are formed as a second P-type junction isolation area.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: January 13, 2015
    Assignee: Southeast University
    Inventors: Longxing Shi, Qinsong Qian, Weifeng Sun, Jing Zhu, Xianguo Huang, Shengli Lu
  • Patent number: 8766402
    Abstract: A semiconductor device structure a semiconductor substrate having a first conductivity type and a top surface. A plurality of first doped regions is at a first depth below the top surface arranged in a checkerboard fashion. The first doped regions are of a second conductivity type. A dielectric layer is over the top surface. An inductive element is over the dielectric layer, wherein the inductive element is over the first doped regions.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: July 1, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ertugrul Demircan, Thomas F. McNelly
  • Patent number: 8759937
    Abstract: A Schottky junction diode device having improved performance and a multiple well structure is fabricated in a conventional CMOS process. A substrate including a material doped to a first conductivity type is formed. A first well is disposed over the substrate. The first well includes a material doped differently, such as to a second conductivity type opposite that of the first conductivity type. A second well is disposed within the first well. A region of metal-containing material is disposed in the second well to form a Schottky junction at an interface between the region of metal-containing material and the second well. In one embodiment, a second well contact is disposed in a portion of the second well.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: June 24, 2014
    Assignee: Synopsys, Inc.
    Inventors: Yanjun Ma, Ronald A. Oliver, Todd E. Humes, Jaideep Mavoori
  • Patent number: 8716763
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first doped region and a semiconductor region. The first doped region has a first type conductivity. The semiconductor region is in the first doped region. A source electrode and a drain electrode are respectively electrically connected to parts of the first doped region on opposite sides of the semiconductor region.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: May 6, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Li-Fan Chen, Wing-Chor Chan
  • Patent number: 8603918
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion thereof. A trench is disposed in the workpiece extending at least through the buried layer. At least one sinker contact is disposed in the top portion of the workpiece. The at least one sinker contact is proximate sidewalls of at least a portion of the trench and is adjacent the buried layer. An insulating material is disposed on the sidewalls of the trench. A conductive material is disposed within the trench and is coupled to a lower portion of the workpiece.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: December 10, 2013
    Assignee: Infineon Technologies AG
    Inventors: Karl-Heinz Mueller, Holger Arnim Poehle
  • Patent number: 8479384
    Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: July 9, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Mirzafer Abatchev, David Wells, Baosuo Zhou, Krupakar M. Subramanian
  • Patent number: 8354723
    Abstract: An electrostatic discharge protection device including a gate electrode formed on a substrate. First and second diffusion regions of a first conductivity type are formed in the substrate with the gate electrode located in between. A first silicide layer is formed in the first diffusion region. A silicide block region is formed between the gate electrode and the first suicide layer. A third diffusion region is formed below the first silicide layer to partially overlap the first diffusion region. The third diffusion region and first silicide layer have substantially the same shapes and dimensions. The third diffusion region and a portion below the gate electrode located at the same depth as the third diffusion region contain impurities of a second conductivity type. The third diffusion region has an impurity concentration that is higher than that of the portion below the gate electrode.
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: January 15, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Teruo Suzuki
  • Patent number: 8330233
    Abstract: A semiconductor device 1 including a cell region 2 formed with a semiconductor element 6 and a periphery region 3 formed in the periphery of the cell region 2. The semiconductor region 1 is arranged with an n? type drift region 12 formed in the cell region 2 and periphery region 3, a plurality of p? type columnar regions formed in the n? drift region 12 of the cell region 2, a plurality of p? type columnar resistance improvement regions 23n formed in the n? type drift region 12 of the periphery region 3, and a plurality of electrical field buffer regions 24n formed in an upper part of the p? type columnar region 23n. An interval Sn between the electrical field buffer region 24n and an adjacent electrical field buffer region 24n is different between an interior side and an exterior side of the periphery region 3.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: December 11, 2012
    Assignee: Sanken Electric Co., Ltd.
    Inventor: Tomoyuki Omori
  • Patent number: 8237225
    Abstract: Provided is a semiconductor device for electrostatic discharge protection capable of protecting an inner circuit from both noises of an overcurrent noise of an ESD and an overcurrent noise of a latch-up test while achieving size reduction, by sharing a guard ring formed in a periphery of an ESD protection element with a cathode of a latch-up protection diode for protecting the inner circuit from the overcurrent noise of the latch-up test.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: August 7, 2012
    Assignee: Seiko Instruments Inc.
    Inventor: Shinjiro Kato
  • Patent number: 8174081
    Abstract: A extractor implanted region is used in a silicon-on-insulator CMOS memory device. The extractor region is reversed biased to remove minority carriers from the body region of partially depleted memory cells. This causes the body region to be fully depleted without the adverse floating body effects.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: May 8, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 8115279
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion of the workpiece. An isolation ring structure is disposed within the top portion of the workpiece extending completely through at least a portion of the buried layer, the isolation ring structure comprising a ring having an interior region. A diffusion confining structure is disposed within the interior region of the isolation ring structure. A conductive region is disposed within the top portion of the workpiece within a portion of the interior of the isolation ring structure, the conductive region comprising at least one dopant element implanted and diffused into the top portion of the workpiece. The diffusion confining structure defines at least one edge of the conductive region, and the conductive region is coupled to the buried layer.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: February 14, 2012
    Assignee: Infineon Technologies AG
    Inventors: Armin Tilke, Cajetan Wagner, Lincoln O'Riain
  • Patent number: 8110895
    Abstract: A first wiring layer in a circuit substrate structure is provided with a first inductor and a second inductor. A dielectric layer is provided with a first via and a second via electrically connected to the first inductor and the second inductor, respectively. A second wiring layer is provided with: a bridge electrically connecting the first via and the second via; and a conductive pattern provided around the bridge, the outer edge of the conductive pattern being located outside the outer edge of the first wiring pattern and the second wiring pattern in the first wiring layer. The bridge functions as a coplanar line and suppresses generation of electromagnetic field.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: February 7, 2012
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Toshikazu Imaoka, Tetsuro Sawai, Atsushi Saita, Takeshi Yamaguchi
  • Patent number: 8106480
    Abstract: The invention, in one aspect, provides a semiconductor device that comprises a collector located in a semiconductor substrate and an isolation region located under the collector, wherein a peak dopant concentration of the isolation region is separated from a peak dopant concentration of the collector that ranges from about 0.9 microns to about 2.0 microns.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: January 31, 2012
    Assignee: Agere Systems Inc.
    Inventors: Alan S. Chen, Mark Dyson, Daniel C. Kerr, Nace M. Rossi
  • Patent number: 8084843
    Abstract: A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated area are formed by implants that are formed from the second conductivity and extend down to the buried layer. The isolated region has implanted source lines and is further subdivided by overlay strips of the second conductivity that extend substantially down to the buried layer. Each isolation region can contain one or more blocks of memory cells.
    Type: Grant
    Filed: October 6, 2008
    Date of Patent: December 27, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Patent number: 8084844
    Abstract: A semiconductor device in which potential is uniformly controlled and in which the influence of noise is reduced. A p-type well region is formed beneath a surface of a p-type Si substrate. n-type MOS transistors are formed on the p-type well region. An n-type well region is formed in the p-type Si substrate so that it surrounds the p-type well region. A plurality of conductive regions which pierce through the n-type well region are formed at regular intervals. By doing so, parasitic resistance from the p-type Si substrate, through the plurality of conductive regions, to the n-type MOS transistors becomes low. Accordingly, when back bias is applied to a contact region, the back bias potential of the n-type MOS transistors can be controlled uniformly. As a result, the influence of noise from the p-type Si substrate or the p-type well region can be reduced.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: December 27, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Takuji Tanaka
  • Patent number: 8039925
    Abstract: A plurality of devices, such as devices that are utilized for implementing radio frequency applications, can be formed in the same substrate. Each of these devices may be formed over a triple well that includes at least one well capable of being biased. Each of the wells is coupled to a well bias through a resistor. In some embodiments, a plurality of wells operating at a relatively high frequency may be connected to the same bias potential, each through separate resistors. The noise coupling may be reduced through the use of the bias resistors.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: October 18, 2011
    Assignee: Altera Corporation
    Inventors: Ting-Wah Wong, Chong L. Woo
  • Patent number: 8011090
    Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: September 6, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Mirzafer Abatchev, David Wells, Baosuo Zhou, Krupakar M. Subramanian
  • Patent number: 7982288
    Abstract: A semiconductor device including a substrate, a high voltage device, a medium voltage device and a low voltage device is provided. The substrate includes a high voltage circuit area, a medium voltage circuit area and a low voltage circuit area. The high voltage device, the medium voltage device and the low voltage device are respectively disposed in the high voltage circuit area, the medium voltage circuit area and the low voltage circuit area. The medium voltage device and the high voltage device have the same structure while the medium voltage device and the low voltage device have different structures. Further, the high voltage device, the medium voltage device and the low voltage device respectively include a first gate dielectric layer, a second gate dielectric layer and a third gate dielectric layer, and the thickness of the second gate dielectric layer is smaller than that of the first gate dielectric layer.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: July 19, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Lung Chen, Han-Min Huang
  • Patent number: 7977768
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion thereof. A trench is disposed in the workpiece extending at least through the buried layer. At least one sinker contact is disposed in the top portion of the workpiece. The at least one sinker contact is proximate sidewalls of at least a portion of the trench and is adjacent the buried layer. An insulating material is disposed on the sidewalls of the trench. A conductive material is disposed within the trench and is coupled to a lower portion of the workpiece.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: July 12, 2011
    Assignee: Infineon Technologies AG
    Inventors: Karl-Heinz Mueller, Holger Arnim Poehle
  • Patent number: 7973370
    Abstract: A extractor implanted region is used in a silicon-on-insulator CMOS memory device. The extractor region is reversed biased to remove minority carriers from the body region of partially depleted memory cells. This causes the body region to be fully depleted without the adverse floating body effects.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: July 5, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 7881679
    Abstract: A phase locked loop and power amplifier are integrated on single chip. To eliminate cross-talk between the components, a frequency translation block is introduced to change the output frequency of the PLL. To isolate the components from unwanted feedback, a high isolation buffer is introduced between the components. To further isolate the components, the voltage supply domains for each component is physically separated. Each separate voltage supply domain can include a separate high isolation ring, separate voltage regulator, and separate bandgap reference.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: February 1, 2011
    Assignee: RF Micro Devices, Inc.
    Inventors: Shayan Faravash, Nathaniel King, Jr., Robert A. Koupal, David A. Schwan, Matthew C. Romney, Chee Quang Quek
  • Publication number: 20110018101
    Abstract: A semiconductor device 1 including a cell region 2 formed with a semiconductor element 6 and a periphery region 3 formed in the periphery of the cell region 2. The semiconductor region 1 is arranged with an n? type drift region 12 formed in the cell region 2 and periphery region 3, a plurality of p? type columnar regions formed in the n? drift region 12 of the cell region 2, a plurality of p? type columnar resistance improvement regions 23n formed in the n? type drift region 12 of the periphery region 3, and a plurality of electrical field buffer regions 24n formed in an upper part of the p? type columnar region 23n. An interval Sn between the electrical field buffer region 24n and an adjacent electrical field buffer region 24n is different between an interior side and an exterior side of the periphery region 3.
    Type: Application
    Filed: July 15, 2010
    Publication date: January 27, 2011
    Applicant: Sanken Electric Co., Ltd.
    Inventor: Tomoyuki OMORI
  • Patent number: 7868423
    Abstract: A structure for a semiconductor device includes an isolated MOSFET (e.g., NFET) having triple-well technology adjacent to an isolated PFET which itself is adjacent to an isolated NFET. The structure includes a substrate in which is formed a deep n-band region underneath any n-wells, p-wells and p-band regions within the substrate. One p-band region is formed above the deep n-band region and underneath the isolated p-well for the isolated MOSFET, while another p-band region is formed above the deep n-band region and underneath all of the p-wells and n-wells, including those that are part of the isolated PFET and NFET devices within the substrate. The n-wells for the isolated MOSFET are connected to the deep n-band region.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: January 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: John J. Benoit, David S. Collins, Natalie B. Feilchenfeld, Michael L. Gautsch, Xuefeng Liu, Robert M. Rassel, Stephen A. St. Onge, James A. Slinkman
  • Patent number: 7808174
    Abstract: A light-emitting diode (1) has a first electrode (3), a second electrode (4), a light-emitting layer (5) which comprises a matrix, and ions. A layer (6) of a cation receptor (CR) is positioned adjacent to the first electrode (3), has captured cations, and has generated immobilized cations (+). A layer (7) of an anion receptor (AR) is positioned adjacent to the second electrode (4), has captured anions, and has generated immobilized anions (?). The ion gradients provide for quick response in emission of light (L) when the diode (1) is exposed to a forward bias. A diode (1) is manufactured by first forming a laminate (2) of the above structure. The laminate (2) is exposed to a forward bias to make the ions become immobilized at respective sites (S1, S2) of the respective receptors (CR, AR).
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: October 5, 2010
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Eduard Johannes Meijer, Eric Alexander Meulenkamp, Ralph Kurt, Steve Klink
  • Patent number: 7750437
    Abstract: A semiconductor device has a rectifier circuit and integrated circuit on a semiconductor substrate of a first conduction type, and has a first well region in the substrate, a second well region in first well region, and a diode region formed in second well region and constituting a diode with second well region. The rectifier circuit is formed by the diodes. An input power supply terminal, changing between positive and negative potentials, is connected to second and first well regions of a first diode and to diode region of a second diode. A current supply terminal is provided in the vicinity of first well region of first diode, and is connected to the substrate and a prescribed power supply, so as to supply a current to the PN junction between the first well region and the semiconductor substrate when the input power supply terminal is at negative potential.
    Type: Grant
    Filed: September 19, 2005
    Date of Patent: July 6, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hideaki Suzuki, Hidetoshi Sugiyama
  • Patent number: 7750434
    Abstract: A first wiring layer in a circuit substrate structure is provided with a first inductor and a second inductor. A dielectric layer is provided with a first via and a second via electrically connected to the first inductor and the second inductor, respectively. A second wiring layer is provided with: a bridge electrically connecting the first via and the second via; and a conductive pattern provided around the bridge, the outer edge of the conductive pattern being located outside the outer edge of the first wiring pattern and the second wiring pattern in the first wiring layer. The bridge functions as a coplanar line and suppresses generation of electromagnetic field.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: July 6, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Toshikazu Imaoka, Tetsuro Sawai, Atsushi Saita, Takeshi Yamaguchi, Makoto Tsubonoya, Kazunari Kurokawa
  • Patent number: 7709925
    Abstract: A semiconductor device, including: a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on the semiconductor substrate; a trench formed in the semiconductor region; a trench diffusion layer of the first conductivity type formed along wall surfaces of the trench; and a buried conductor buried in the trench, wherein an insulation film is further disposed between the wall surfaces of the trench and the buried conductor.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: May 4, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Takahashi, Tomohide Terashima
  • Patent number: 7622741
    Abstract: A semiconductor device of a double diffused MOS structure employing a silicon carbide semiconductor substrate. The semiconductor device comprises a silicon carbide semiconductor epitaxial layer provided on a surface of the silicon carbide semiconductor substrate and having a first conductivity which is the same conductivity as the silicon carbide semiconductor substrate, and an impurity region formed by doping a surface portion of the silicon carbide semiconductor epitaxial layer with an impurity of a second conductivity, the impurity region having a profile such that a near surface thereof has a relatively low second-conductivity impurity concentration and a deep portion thereof has a relatively high second-conductivity impurity concentration.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: November 24, 2009
    Assignee: Rohm Co., Ltd.
    Inventor: Mineo Miura
  • Publication number: 20090243041
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion thereof. A trench is disposed in the workpiece extending at least through the buried layer. At least one sinker contact is disposed in the top portion of the workpiece. The at least one sinker contact is proximate sidewalls of at least a portion of the trench and is adjacent the buried layer. An insulating material is disposed on the sidewalls of the trench. A conductive material is disposed within the trench and is coupled to a lower portion of the workpiece.
    Type: Application
    Filed: April 1, 2008
    Publication date: October 1, 2009
    Inventors: Karl-Heinz Mueller, Holger Arnim Poehle
  • Patent number: 7525151
    Abstract: An integrated circuit that includes at least one vertical conduction DMOS device and other semiconductor devices.
    Type: Grant
    Filed: January 5, 2006
    Date of Patent: April 28, 2009
    Assignee: International Rectifier Corporation
    Inventor: Robert P Haase
  • Publication number: 20090057831
    Abstract: A high voltage/power semiconductor device has a semiconductor layer having a high voltage terminal end and a low voltage terminal end. A drift region extends between the high and low voltage terminal ends. A dielectric layer is provided above the drift region. An electrical conductor extends across at least a part of the dielectric layer above the drift region, the electrical conductor being connected or connectable to the high voltage terminal end. The drift region has plural trenches positioned below the electrical conductor. The trenches extend laterally across at least a part of the drift region in the direction transverse the direction between the high and low voltage terminal ends of the semiconductor layer, each trench containing a dielectric material. The trenches improve the distribution of electric field in the device in the presence of the electrical conductor.
    Type: Application
    Filed: August 29, 2007
    Publication date: March 5, 2009
    Applicant: Cambridge Semiconductor Limited
    Inventors: Florin Udrea, Cerdin Lee
  • Patent number: 7495264
    Abstract: A semiconductor device has a substrate and a dielectric film formed directly or indirectly on the substrate. The dielectric film contains a metal silicate film, and a silicon concentration in the metal silicate film is lower in a center portion in the film thickness direction than in an upper portion and in a lower portion.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: February 24, 2009
    Assignee: NEC Corporation
    Inventors: Heiji Watanabe, Haruhiko Ono, Nobuyuki Ikarashi
  • Patent number: 7443009
    Abstract: A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated area are formed by implants that are formed from the second conductivity and extend down to the buried layer. The isolated region has implanted source lines and is further subdivided by overlay strips of the second conductivity that extend substantially down to the buried layer. Each isolation region can contain one or more blocks of memory cells.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: October 28, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Patent number: 7411272
    Abstract: A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region. In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface and at least one electrical terminal is connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region. In each of these embodiments, the bottom surface of the membrane does not have a semiconductor substrate positioned adjacent thereto.
    Type: Grant
    Filed: July 6, 2005
    Date of Patent: August 12, 2008
    Assignee: Cambridge Semiconductor Limited
    Inventors: Florin Udrea, Gehan A. J. Amaratunga
  • Patent number: 7358191
    Abstract: According to one exemplary embodiment, a method includes a step of forming a number of trenches in a dielectric layer, where the dielectric layer is situated over a wafer. The method further includes forming a metal layer over the dielectric layer and in the trenches such that the metal layer has a dome-shaped profile over the wafer. The method further includes performing a planarizing process to form a number of interconnect lines, where each of the interconnect lines is situated in one of the trenches. The dome-shaped profile of the metal layer causes the interconnect lines to have a reduced thickness variation across the wafer after performing the planarizing process. The interconnect lines are situated in an interconnect metal layer, where the dome-shaped profile of the metal layer causes the interconnect metal layer to have increased sheet resistivity uniformity across the wafer after performing the planarizing process.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: April 15, 2008
    Assignees: Spansion LLC, Advanced Micro Devices, Inc.
    Inventors: Krishnashree Achuthan, Brad Davis, James Xie, Kashmir Sahota
  • Patent number: 7345355
    Abstract: Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two species effective at limiting junction broadening by channeling during dopant implantation and/or by thermal diffusion. Following dopant implantation, the electronically-active dopant is activated by thermal processing.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: March 18, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Amitabh Jain, Stephanie W. Butler
  • Patent number: 7306990
    Abstract: An information memory device capable of reading and writing of information by mechanical operation of a floating gate layer, in which a gate insulation film has a cavity (6), and a floating gate layer (5) having two stable deflection states in the cavity (6), the state stabilized by deflecting toward the channel side of transistor, and the state stabilized by deflecting toward the gate (7) side, writing and reading of information can be made by changing the stable deflection state of the floating gate layer (5) by Coulomb interactive force between the electrons (or positive holes 8) accumulated in the floating gate layer (5) and external electric field, and by reading the channel current change based on the state of the floating gate layer (5).
    Type: Grant
    Filed: November 28, 2003
    Date of Patent: December 11, 2007
    Assignee: Japan Science & Technology Agency
    Inventors: Shinya Yamaguchi, Masahiko Ando, Toshikazu Shimada, Natsuki Yokoyama, Shunri Oda, Nobuyoshi Koshida
  • Patent number: 7268410
    Abstract: Improvements in the level of integration of a core buck and/or boost DC-DC voltage regulator sub-circuit lead to a lower manufacturing cost structure, an improved performance from lessened intrinsic parasitic resistance, a smaller die size and, thus, higher wafer yield. Further, by integrating certain components on-chip, the cost and complexity of the conventional hybrid circuit implementation is improved.
    Type: Grant
    Filed: January 24, 2005
    Date of Patent: September 11, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Peter Johnson, Kyuwoon Hwang, Robert Drury
  • Patent number: 7259428
    Abstract: A semiconductor device includes a support substrate, a buried insulation film, provided on the support substrate, having a thickness of 5 to 10 nm, a silicon layer provided on the buried insulation film, a MOSFET provided in the silicon layer, and a triple-well region provided in the support substrate under the MOSFET.
    Type: Grant
    Filed: April 4, 2005
    Date of Patent: August 21, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Satoshi Inaba
  • Patent number: 7247533
    Abstract: A method of fabricating a semiconductor device uses selective epitaxial growth (SEG), by which leakage current generation is minimized using lateral SEG growth in case a contact intrudes a shallow track isolation feature. The method includes steps of forming a sidewall spacer on a gate, selectively growing an epitaxial layer in a lateral direction relative to the sidewall spacer and the gate, and forming a contact on the epitaxial layer.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: July 24, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Heui Gyun Ahn
  • Patent number: 7230314
    Abstract: A semiconductor device having an active region is formed in a layer provided on a semiconductor substrate. At least a portion of the semiconductor substrate below at least a portion of the active region is removed such that the portion of the active region is provided in a membrane defined by that portion of the layer below which the semiconductor substrate has been removed. A heat conducting and electrically insulating layer is applied to the bottom surface of the membrane. The heat conducting and electrically insulating layer has a thermal conductivity that is higher than the thermal conductivity of the membrane so that the heat conducting and electrically insulating layer allows heat to pass from the active region into the heat conducting and electrically insulating layer during normal operation of the device.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: June 12, 2007
    Assignee: Cambridge Semiconductor Limited
    Inventors: Florin Udrea, Gehan A. J. Amaratunga
  • Patent number: 7230263
    Abstract: In a gallium nitride semiconductor device comprising an active layer made of an n-type gallium nitride semiconductor that includes In and is doped with n-type impurity and a p-type cladding layer made of a p-type gallium nitride semiconductor that includes Al and is doped with p-type impurity, a first cap layer, made of a gallium nitride semiconductor that includes n-type impurity of lower concentration than that of said active layer and p-type impurity of lower concentration than that of said p-type cladding layer, and a second cap layer made p-type gallium nitride semiconductor that includes Al and is doped with p-type impurity are stacked one on another between said active layer and said p-type cladding layer.
    Type: Grant
    Filed: April 8, 2002
    Date of Patent: June 12, 2007
    Assignee: Nichia Corporation
    Inventor: Kimihiro Kawagoe
  • Patent number: 7183216
    Abstract: A thermal oxidation process is used to fill trenches with an oxide; however, the oxidation process consumes some of the silicon. The embodiments herein advantageously apply this tendency for the oxidation process to consume silicon so as to convert all the silicon substrate material between the multiple trenches into an oxide. Therefore, because all of the silicon between the multiple trenches is consumed by the oxidation process, the multiple smaller trenches are combined into a single larger trench filled with the oxide.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: February 27, 2007
    Assignee: Xerox Corporation
    Inventors: Cathie J. Burke, Peter M. Gulvin
  • Patent number: 7119393
    Abstract: A floating-gate transistor for an integrated circuit is formed on a p-type substrate. An n-type region is disposed over the p-type substrate. A p-type region is disposed over the n-type region. Spaced apart n-type source and drain regions are disposed in the p-type region forming a channel therein. A floating gate is disposed above and insulated from the channel. A control gate is disposed above and insulated from the floating gate. An isolation trench disposed in the p-type region and surrounding the source and drain regions, the isolation trench extending down into the n-type region. The substrate, the n-type region and the p-type region each biased such that the p-type region is fully depleted.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: October 10, 2006
    Assignee: Actel Corporation
    Inventor: John McCollum