Abstract: System, method, and silicon chip package for providing structural strength, heat dissipation and electrical connectivity using “W” shaped frame bonded to the one or more dies, wherein the “W” shaped frame provides compression strength to the silicon chip package when the one or more dies are bonded, and electrically conductivity between for the one or more dies to leads of silicon chip package, and heat dissipation for the silicon chip package.

Abstract: By configuring an ESD protection element of an NPN transistor (101), it is possible to reduce the area of the ESD protection element and reduce the voltage in a region in which the current increases sharply, and thus possible to increase ESD tolerance. Also, it is possible to provide a highly reliable semiconductor device wherein it is possible to flatten and smooth the surface of an upper layer pad electrode (16) by dividing a pad electrode (8) into a two-layer structure sandwiching an interlayer insulating film (15), and possible to increase the junction strength of a bonding wire, and suppress damage to underlying silicon layers when bonding.

Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a collector region of semiconductor material having a first conductivity type, a base region of semiconductor material within the collector region, the base region having a second conductivity type opposite the first conductivity type, and a doped region of semiconductor material having the second conductivity type, wherein the doped region is electrically connected to the base region and the collector region resides between the base region and the doped region. In exemplary embodiments, the dopant concentration of the doped region is greater than a dopant concentration of the collector region to deplete the collector region as the electrical potential of the base region exceeds that of the collector region.

Abstract: A method for forming a semiconductor structure is disclosed. The method includes forming a high-k dielectric layer over a semiconductor substrate and forming a gate layer over the high-k dielectric layer. The method also includes heating the gate layer to 350° C., wherein, if the gate layer includes non-conductive material, the non-conductive material becomes conductive. The method further includes annealing the substrate, the high-k dielectric layer, and the gate layer in excess of 350° C. and, during the annealing, applying a negative electrical bias to the gate layer relative to the semiconductor substrate. A semiconductor structure is also disclosed. The semiconductor structure includes a high-k dielectric layer over a semiconductor substrate, and a gate layer over the high-k dielectric layer. The gate layer has a negative electrical bias during anneal. A p-channel FET including this semiconductor structure is also disclosed.

Abstract: A photodetector with internal gain comprising a semiconductor structure in which impact ionization events are produced mostly by minority charge carriers; a first biasing contact and a second biasing contact located in the semiconductor structure; a means of defining, in the semiconductor structure, a photon collection region close to first biasing contact; a P-N type junction formed in the semiconductor structure between the two biasing contacts and close to the second biasing contact; and a collector contact which is located in the P-N junction and used to collect current in the P-N junction.

Abstract: A system and method providing for the detection of an input signal, either optical or electrical, by using a single independent discrete amplifier or by distributing the input signal into independent signal components that are independently amplified. The input signal can either be the result of photoabsorption process in the wavelengths greater than 950 nm or a low-level electrical signal. The discrete amplifier is an avalanche amplifier operable in a non-gated mode while biased in or above the breakdown region, and includes a composite dielectric feedback layer monolithically integrated with input signal detection and amplification semiconductor layers.

Abstract: A power semiconductor device with improved avalanche capability structures is disclosed. By forming at least an avalanche capability enhancement doped regions with opposite conductivity type to epitaxial layer underneath an ohmic contact doped region which surrounds at least bottom of trenched contact filled with metal plug between two adjacent gate trenches, avalanche current is enhanced with the disclosed structures.

Abstract: A bipolar transistor of the invention has a second base region 116 which is formed in the surface layer of a deep well, placed between a first base region and a sinker, connected to the first base region, has an impurity concentration larger than that of the first base region, and has a depth shallower than that of the first base region; and a buried layer formed in a semiconductor layer, which has the top surface thereof brought into contact with the deep well and the sinker, and has an impurity concentration larger than that of the deep well.

Abstract: A method for fabricating a recess gate in a semiconductor device includes etching a silicon substrate to form a trench that defines an active region, forming a device isolation layer that gap-fills the trench, forming a hard mask layer over the silicon substrate, the hard mask layer comprising a stack of an oxide layer and an amorphous carbon layer, wherein the hard mask layer exposes a channel target region of the active region, and forming a recess region with a dual profile by first etching and second etching the channel target region using the hard mask layer as an etch barrier, wherein the second etching is performed after removing the amorphous carbon layer.

Abstract: An integrated circuit includes a vertical diode defined by crossed line lithography.

Abstract: A dual-sided semiconductor device is formed on a wafer with a resistive element that is formed through the wafer. By forming the resistive element through the wafer, a resistive element, such as a large resistive element, can be formed on the wafer that requires very little silicon surface area.

Abstract: A sequential mesa type avalanche photodiode (APD) includes a semiconductor substrate and a sequential mesa portion formed on the substrate. In the sequential mesa portion, a plurality of semiconductor layers, including a light absorbing layer and a multiplying layer, are laminated by epitaxial growth. In the plurality of semiconductor layers, a pair of semiconductor layers forming a pn junction is included. The carrier density of a semiconductor layer which is near to the substrate among the pair of semiconductor layers is larger than the carrier density of a semiconductor layer which is far from the substrate among the pair of semiconductor layers. In the APD, light-receiving current based on movement of electrons and positive holes generated in the sequential mesa portion when light is incident from the substrate toward the light absorbing layer is larger at a central portion than at a peripheral portion of the sequential mesa portion.

Abstract: A cold electron emitter may include a heavily a p-doped semiconductor, and dielectric layer, and a metallic layer (p-D-M structure). A modification of this structure includes a heavily n+ doped region below the p region (n+-p-D-M structure). These structures make it possible to combine high current emission with stable (durable) operation. The high current density is possible since under certain voltage drop across the dielectric layer, effective negative electron affinity is realized for the quasi-equilibrium “cold” electrons accumulated in the depletion layer in the p-region next to the dielectric layer. These electrons are generated as a result of the avalanche in the p-D-M structure or injection processes in the n+-p-D-M structure. These emitters are stable since they make use of relatively low extracting field in the vacuum region and are not affected by contamination and absorption from accelerated ions. In addition, the structures may be fabricated with current state-of-the-art technology.

Abstract: A semiconductor device comprises a first semiconductor layer of a first conductivity type provided on a semiconductor substrate of the first conductivity type, a base layer of a second conductivity type provided in the first semiconductor layer, for defining a vertical MISFET including source regions and a gate electrode on a gate insulation film, a Schottky barrier diode (SBD)-forming region provided in the first semiconductor layer around the base layer, a guard ring region of the second conductivity type provided around SBD-forming region, a first main electrode disposed above the first semiconductor layer and provided in common as both a source electrode of the MISFET and an anode of the SBD, a surface gate electrode disposed above the first semiconductor layer, and a second main electrode provided in common as a drain electrode of the MISFET and a cathode of the SBD.

Abstract: A semiconductor die package is disclosed. In one embodiment, the package includes a semiconductor die comprising a vertical power transistor. A source electrode and a gate contact region are at the first surface of the semiconductor die. A drain electrode is at the second surface of the semiconductor die. A base member is proximate to the second surface of the semiconductor die and is distal to the first surface of the semiconductor die and a cover disposed over the first surface of the semiconductor die. The cover is coupled to the base member and is adapted to transfer beat away from the semiconductor die.

Abstract: In a MOS transistor of an LDD structure, a cobalt silicide film is formed in a region where adjacent gates are formed widely apart from each other, but is not formed in a region where adjacent gates are formed close to each other. The particular construction permits suppressing the leak current through the PN junction that is generated under the influence of the metal silicide compound in the region where adjacent gates are formed close to each other, and also permits ensuring the signal processing at a high speed in the region where adjacent gates are formed widely apart from each other.

Abstract: A least one one-time programmable nonvolatile (NV) memory element uses a field-effect transistor (FET) as a selectively programmed element. A short duration applied drain voltage exceeding the FET's drain-to-source breakdown voltage results in a drain source resistance which is substantially unaffected by the voltages typically applied at the gate terminal. Since the programmed resistance is less than 200 ohms and a high programming voltage is not required, the present invention compares favorably with antifuse nonvolatile memory techniques. The nonvolatile memory element is implemented without adding complexity to a very large scale integrated (VLSI) circuit process.

Abstract: The present invention provides a bipolar transistor in which a lightly doped n-type hot-carrier shield extends in an epitaxial layer adjacent from a poly-emitter to an extrinsic base. This hot-carrier shield minimizes performance impairment that would otherwise occur due to a hot-carrier effect. Key steps in the method of making the bipolar transistor include a differential thermal oxidation while the poly-emitter is covered with a nitride cap. After the nitride cap is removed, an n-type dopant is implanted. The unprotected poly emitter is heavily doped. The implant partially penetrates a relatively thin oxide growth, thereby forming the hot-carrier shield. Other areas, such as the extrinsic base, and a polycrystalline base extension are covered by a relatively thick oxide growth and are unaffected by the n-type implant.

Abstract: A bipolar avalanche phototransistor has a thin, heavily doped base portion adjacent the collector to improve avalanche characteristics. The structure may have a lateral, as well as vertical, collector, with the thin heavily doped base portion adjoining the surface lateral collector.

Abstract: An npn transistor having a low collector-base breakdown voltage. An emitter region (104, 106) of a first conductivity type is located in a semiconductor substrate (102). A base region (14) of a second conductivity type is located within the emitter region (104,106) and a shallow collector region (18) of the first conductivity type is located within the base region (14). The shallow collector region (18) may be doped with arsenic and/or phosphorus such that the dopant concentration and depth of the shallow collector region (18) provide a low collector-base breakdown voltage.

Abstract: An insulated gate controlled avalanche bipolar transistor has a heavily doped (with doping of at least 1.times.10.sup.18 cm.sup.-3) substrate and a lightly doped channel layer of the same conductivity type on the substrate. The source/emitter and drain/collector regions extend through the lightly doped surface layer to reach the heavily doped substrate, so that the junction between the drain and the heavily doped substrate promotes avalanche breakdown. A lightly doped region of the same type as the substrate is provided betwen the heavily doped substrate and the contact to the substrate, to provide a resistance between the substrate, which acts as the base of the transistor, and the substrate contact, to permit biasing of the base by resistive voltage drop across the resistance, while the lightly doped channel layer permits a low FET threshold voltage.

Abstract: The present invention relates to a semiconductor device which comprises: an n.sup.- type buried collector provided on an n type silicon epitaxial layer disposed in an emitter opening; an n.sup.- type silicon collector disposed on said collector; a p.sup.+ type single crystal silicon intrinsic base layer; and an n.sup.+ type single crystal silicon emitter wherein said p.sup.+ type single crystal silicon intrinsic base layer is connected with a p.sup.+ type base electrode polycrystalline silicon through a p.sup.+ type polycrystalline silicon graft base.

Abstract: A circuit for generating a negative voltage includes: a bipolar transistor including, a) an N type collector region, b) a P type base region, and c) an N type emitter region, the base region width between the emitter region and the collector region being less than about 5,000 angstroms and the dopant concentration of the base region being in the range of about 1-10.times.10.sup.18 atoms/cm.sup.3 ; means for applying a reference potential to the base region; and means for applying a bias potential to the emitter region so as to generate a negative output potential at the collector region. The circuit can likewise comprise a PNP bipolar transistor biased to generate a negative voltage. The circuit can be used on integrated circuit chips to provide a complementary voltage, thereby obviating the requirement for separate, complementary power supplies.