Bipolar Transistor Structure Patents (Class 257/565)
  • Patent number: 10381467
    Abstract: According to an embodiment of a semiconductor device, the device includes first and second trenches formed in a semiconductor body and an electrode disposed in each of the trenches. One of the electrodes is a gate electrode, and the other electrode is electrically disconnected from the gate electrode. The semiconductor device further includes a semiconductor mesa between the trenches. The semiconductor mesa includes a separation region and at least one of a source region and a body region located in the semiconductor mesa. A drift zone is provided below the at least one of the source region and the body region. In the separation region, at least one of (i) a capacitive coupling between the gate electrode and the semiconductor mesa and (ii) a conductivity of majority charge carriers of the drift zone is lower than outside of the separation region.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 13, 2019
    Assignee: Infineon Technologies AG
    Inventors: Roman Baburske, Matteo Dainese, Peter Lechner, Hans-Joachim Schulze, Johannes Georg Laven
  • Patent number: 10354917
    Abstract: A method for manufacturing includes providing a semiconductor substrate having a semiconductor device including at least two device layers to be contacted. A first device layer is smaller than a lithographic minimum feature size used for manufacturing the semiconductor device. Further, the method includes providing an isolation layer on the semiconductor device such that the semiconductor device is covered by the isolation layer; planarizing the isolation layer up to the semiconductor device; providing a first lithographic mask on the semiconductor device, such that the first device layer and a portion of the isolation layer are covered by the first lithographic mask; selectively removing the isolation layer to expose a second device layer while maintaining the portion of the isolation layer that is covered by the first lithographic mask; and providing a stop layer on the first device layer, the second device layer and the portion of the isolation layer.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: July 16, 2019
    Assignee: Infineon Technologies AG
    Inventors: Dmitri Alex Tschumakow, Claus Dahl
  • Patent number: 10263296
    Abstract: A semiconductor device capable of reducing an inter-source electrode resistance RSS (on) and reducing a chip size is provided. A semiconductor device according to the present invention includes a chip partitioned into three areas including a first area, a second area, and a third area, and a common drain electrode provided on a back surface of the chip, in which the second area is formed between the first and third areas, a first MOSFET is formed in the first area and the third area, and a second MOSFET is formed in the second area.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: April 16, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Kazutaka Suzuki, Takahiro Korenari
  • Patent number: 10242615
    Abstract: The present disclosure relates to an organic light-emitting diode (OLED) display device and a compensation circuit of an OLED. The compensation circuit of the OLED includes: a first thin film transistor (TFT), a second TFT, a third TFT, a fourth TFT, a fifth TFT, a sixth TFT, a first capacitor, and a second capacitor. As such, the compensation circuit of the present disclosure only requires the scanning signals and the emission signals, so as to simplify configurations of the circuit, and to reduce costs.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: March 26, 2019
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Di Zhang
  • Patent number: 10224320
    Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate having a first plane and a second plane, a plurality of first semiconductor areas provided on the first plane, a plurality of second semiconductor areas provided between the plurality of first semiconductor areas, a plurality of insulator regions provided between the first semiconductor areas and the second semiconductor areas, first-conductivity-type drain regions provided in the first semiconductor areas, first-conductivity-type source regions provided in the second semiconductor areas, gate electrodes, first-conductivity-type first impurity regions that are provided between the first-conductivity-type drain regions and the second plane and have a lower first-conductivity-type impurity concentration than the first-conductivity-type drain regions, and a plurality of second-conductivity-type second impurity regions provided between the first-conductivity-type source regions and the second plane.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: March 5, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Fumio Takeuchi
  • Patent number: 10224322
    Abstract: A semiconductor device includes a diode provided with: a drift layer being a first conductivity type; a cathode region being provided in a back face side of the drift layer and being the first conductivity type; a second conductivity type region provided in a surface layer part of the drift layer; multiple trenches dividing the second conductivity type region into pieces by being provided deeper than the second conductivity type region, and configuring an anode region; a gate insulation film provided in a surface of the trench; a gate electrode provided in a surface of the gate insulation film; an upper electrode electrically connected with the anode region; and a lower electrode electrically connected with the cathode region. A width between the trenches is narrowest in the drift layer is defined as a mesa width. The mesa width is set to be equal to or greater than 0.3 ?m.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: March 5, 2019
    Assignee: DENSO CORPORATION
    Inventors: Weitao Cheng, Shigeki Takahashi, Masakiyo Sumitomo
  • Patent number: 10224319
    Abstract: An electrostatic protection element whose electrostatic breakdown resistance can be adjusted with a required minimum design change is provided. A semiconductor device includes an electrostatic protection element including a bipolar transistor whose base region and emitter region are electrically coupled together through a resistance region. At this time, the base region of the electrostatic protection element has a side including a facing portion that faces the collector region. The facing portion of the side includes an exposed portion that is exposed from an emitter wiring in plan view and a covered portion that is covered by the emitter wiring in plan view.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: March 5, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Eisuke Kodama
  • Patent number: 10186587
    Abstract: A power semiconductor device has a semiconductor body configured to conduct a load current in parallel to an extension direction between first and second load terminals of the power semiconductor device. The semiconductor body includes a doped contact region electrically connected to the second load terminal, a doped drift region having a dopant concentration that is smaller than a dopant concentration of the contact region, and an epitaxially grown doped transition region separated from the second load terminal by the contact region and that couples the contact region to the drift region. An upper subregion of the transition region is in contact with the drift region, and a lower subregion of the transition region is in contact with the contact region. The transition region has a dopant concentration of at least 0.5*1015 cm?3 for at least 5% of the total extension of the transition region in the extension direction.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: January 22, 2019
    Assignee: Infineon Technologies AG
    Inventors: Matthias Kuenle, Daniel Schloegl, Hans-Joachim Schulze, Christoph Weiss
  • Patent number: 10186605
    Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A cyclical epitaxy process is performed to provide a collector region of a first conductivity type on the collector contact region that is laterally separated from a silicon layer by an air gap. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: January 22, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis Gauthier, Fabien Deprat, Yves Campidelli
  • Patent number: 10139563
    Abstract: A method is for making a photonic chip including EO devices having multiple thicknesses. The method may include forming a first semiconductor layer over a semiconductor film, forming a second semiconductor layer over the first semiconductor layer, and forming a mask layer over the second semiconductor layer. The method may include performing a first selective etching of the mask layer to provide initial alignment trenches, performing a second etching, aligned with some of the initial alignment trenches and using the first semiconductor layer as an etch stop, to provide multi-level trenches, and filling the multi-level trenches to make the EO devices having multiple thicknesses.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: November 27, 2018
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Charles Baudot, Alain Chantre, Sébastien Cremer
  • Patent number: 10102803
    Abstract: A display apparatus includes a plurality of pixels. Each pixel includes a first capacitor connected between a first voltage line receiving a driving signal and a first node; a first transistor comprising a control electrode connected to the first node, a first electrode connected to a second voltage line receiving a first power source signal, and a second electrode connected to a second node; an organic light emitting diode comprising an anode electrode connected to the second node and a cathode electrode receiving a second power source signal; a second capacitor connected between an m-th data line and the second node; a second transistor comprising a control electrode connected to an n-th gate line, a first electrode connected to the first node, and a second electrode connected to the second node; and a third transistor comprising a control electrode connected to an n-th scan line, a first electrode connected to the first voltage line, and a second electrode connected to the second node.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: October 16, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jun-Hyun Park, An-Su Lee, Bo-Yong Chung, Chong-Chul Chai
  • Patent number: 10043825
    Abstract: A method comprises forming shallow trenches in an intrinsic base semiconductor layer and forming a first base layer thereon; applying a first mask to the layer; etching the first base layer; forming a second base layer on the intrinsic base semiconductor layer adjacent the first base layer; removing the first mask; applying a second mask to the base layers; simultaneously etching the layers to produce extrinsic bases of reduced cross dimensions, a length of the second extrinsic base layer being different from a length of the first extrinsic base layer; disposing spacers on the extrinsic bases; etching around the bases leaving the intrinsic base semiconductor layer under the bases and spacers; implanting ions into sides of the intrinsic base semiconductor layer under the extrinsic bases to form emitter/collector junctions; depositing semiconductor material adjacent to the junctions and the trenches; and removing the applied second mask.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • Patent number: 10020386
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-voltage, analog bipolar devices and methods of manufacture. The structure includes: a base region formed in a substrate; a collector region formed in the substrate and comprising a deep n-well region and an n-well region; and an emitter region formed in the substrate and comprising a deep n-well region and an n-well region.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: July 10, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jagar Singh, Baofu Zhu
  • Patent number: 9997443
    Abstract: In accordance with an embodiment of the present invention, a semiconductor chip includes a device region disposed in or over a substrate, a doped region disposed in the device region, and a through via disposed in the substrate. The through via extends through the doped region.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: June 12, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Helmut Brech, Albert Birner
  • Patent number: 9985120
    Abstract: Disclosed herein is a bipolar transistor capable of improving a current amplification rate while improving voltage resistance. A bipolar transistor is provided with a p-type emitter region, a p-type collector region, an n-type base region located between the emitter region and the collector region, a p-type first embedded region located below the base region, and an n-type region having a lower n-type impurity concentration than the base region, being in contact with the emitter region, the collector region, the base region and the first embedded region, separating the emitter region from the base region and the first embedded region, and separating the collector region from the base region and the first embedded region. A part of the base region projects out toward a collector region side than the first embedded region does.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: May 29, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takashi Okawa, Hiroomi Eguchi, Hiromichi Kinpara, Satoshi Ikeda
  • Patent number: 9978856
    Abstract: Presented is a bipolar transistor capable of improving a current amplification rate while improving voltage resistance. A bipolar transistor is provided with a p-type emitter region, a p-type collector region, an n-type base region located between the emitter region and the collector region, a p-type first embedded region located below the base region, and an n-type region having a lower n-type impurity concentration than the base region. The base region is provided with a first high-concentration region and a low-concentration region positioned above the first embedded region, and a second high-concentration region positioned on a collector region side than the low-concentration region, wherein the second high-concentration region has a higher n-type impurity concentration than the low-concentration region.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: May 22, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takashi Okawa, Hiroomi Eguchi, Hiromichi Kinpara, Satoshi Ikeda
  • Patent number: 9964366
    Abstract: The heat-radiating system which radiates heat by heat exchange between a substrate 22 and cooling fluid. The heat-radiating system has a cooling structure that includes a vortex flow generating portion C1 on the surface of the substrate 22 in contact with the cooling fluid. The vortex flow generating portion C1 is composed of a plurality of recesses 22b that extend in the direction ? intersecting the flow direction of the cooling fluid and causes a vortex flow depending on the flow condition of the cooling fluid. The recess depth H of the vortex flow generating portion and the laminar sub-layer thickness ?b near the wall surface satisfy the relation of H>?b=63.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: May 8, 2018
    Assignee: NISSAN MOTOR CO., LTD.
    Inventors: Yousuke Koizuka, Tatsuomi Nakayama
  • Patent number: 9899260
    Abstract: A method of fabricating a semiconductor device. A wafer having a front side and a back side opposite to the front side is prepared. A plurality of through substrate vias (TSVs) is formed on the front side. A redistribution layer (RDL) is then formed on the TSVs. The wafer is bonded to a carrier. A wafer back side grinding process is performed to thin the wafer on the back side. An anneal process is performed to recrystallize the TSVs. A chemical-mechanical polishing (CMP) process is performed to polish the back side.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: February 20, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Ching-Hua Lai, Chien-Hung Shih, Ting-Chung Chiu
  • Patent number: 9892958
    Abstract: An advanced contact module for optimizing emitter and contact resistance and methods of manufacture are disclosed. The method includes forming a first contact via to a first portion of a first device. The method further includes filling the first contact via with metal material to form a first metal contact to the first portion of the first device. The method further includes forming additional contact vias to other portions of the first device and contacts of a second device. The method further includes cleaning the additional contact vias while protecting the first metal contact of the first portion of the first device. The method further includes filling the additional contact vias with metal material to form additional metal contacts to the other portions of the first device and the second device.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: February 13, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: James W. Adkisson, Anthony K. Stamper
  • Patent number: 9882034
    Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening having sidewalls lined with an insulating sheath. A portion of the insulating sheath adjacent the base region is removed and a base contact region is formed by epitaxial material grown from a portion of the base region exposed by removal of the portion of the insulating sheath.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: January 30, 2018
    Assignee: STMicroelectronics SA
    Inventor: Pascal Chevalier
  • Patent number: 9876100
    Abstract: A semiconductor device includes a semiconductor mesa having source zones separated from each other along a longitudinal axis of the semiconductor mesa and at least one body zone forming first pn junctions with the source zones and a second pn junction with a drift zone. Electrode structures are on opposite sides of the semiconductor mesa, at least one of which includes a gate electrode configured to control a charge carrier flow through the at least one body zone. First portions of the at least one body zone are formed between the source zones and separation regions. In the separation regions, at least one of (i) a capacitive coupling between the gate electrode and the semiconductor mesa and (ii) a conductivity of majority charge carriers of the drift zone is lower than outside of the separation region.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: January 23, 2018
    Assignee: Infineon Technologies AG
    Inventors: Roman Baburske, Matteo Dainese, Peter Lechner, Hans-Joachim Schulze, Johannes Georg Laven
  • Patent number: 9825020
    Abstract: A semiconductor device is provided which comprises an ESD protection device. The structure of the semiconductor device comprises a p-doped isolated region in which a structure is manufactured which operates as a Silicon Controlled Rectifier which is coupled between an I/O pad and a reference voltage or ground voltage. The semiconductor device also comprises a pnp transistor which is coupled parallel to the Silicon Controlled Rectifier. The base of the transistor is coupled to the gate of the Silicon Controlled Rectifier. In an optional embodiment, the base and gate are also coupled to the I/O pad.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: November 21, 2017
    Assignee: NXP USA, Inc.
    Inventors: Patrice Besse, Alexis Huot-Marchand, Jean-Philippe Laine, Alain Salles
  • Patent number: 9824630
    Abstract: A pixel unit structure of an organic light emitting diode display panel includes a switch transistor, a storage capacitor, an organic light emitting diode, a driving transistor, a reset circuit, and a control circuit. The organic light emitting diode is controlled by the driving transistor and the control circuit to emit light. The pixel unit operates in a number of time events repeating in sequence.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: November 21, 2017
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chung-Wen Lai, Sheng-Han Li
  • Patent number: 9755018
    Abstract: The present disclosure relates to a bipolar junction transistor (BJT) structure that significantly reduces current crowding while improving the current gain relative to conventional BJTs. The BJT includes a collector, a base region, and an emitter. The base region is formed over the collector and includes at least one extrinsic base region and an intrinsic base region that extends above the at least one extrinsic base region to provide a mesa. The emitter is formed over the mesa. The BJT may be formed from various material systems, such as the silicon carbide (SiC) material system. In one embodiment, the emitter is formed over the mesa such that essentially none of the emitter is formed over the extrinsic base regions. Typically, but not necessarily, the intrinsic base region is directly laterally adjacent the at least one extrinsic base region.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: September 5, 2017
    Assignee: Cree, Inc.
    Inventors: Lin Cheng, Anant K. Agarwal, Sei-Hyung Ryu
  • Patent number: 9741795
    Abstract: An IGBT includes at least one first type transistor cell, including a base region, first and second emitter regions, and a body region arranged between the first emitter region and base region. The base region is arranged between the body region and second emitter region. A gate electrode adjacent the body region is dielectrically insulated from the body region by a gate dielectric. A base electrode adjacent the base region is dielectrically insulated from the base region by a base electrode dielectric. The base region has a first base region section adjoining the base electrode dielectric and a second base region section arranged between the second emitter region and the first base region section. A ratio between the doping concentration of the first base region section and the doping concentration of the second base region section is at least 10. The base electrode dielectric is thicker than the gate dielectric.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: August 22, 2017
    Assignee: Infineon Technologies AG
    Inventors: Christian Philipp Sandow, Hans-Joachim Schulze, Johannes Georg Laven, Franz-Josef Niedernostheide, Frank Pfirsch, Hans-Peter Felsl
  • Patent number: 9735546
    Abstract: The present invention relates to a semiconductor laser for use in an optical module for measuring distances and/or movements, using the self-mixing effect. The semiconductor laser comprises a layer structure including an active region (3) embedded between two layer sequences (1, 2) and further comprises a photodetector arranged to measure an intensity of an optical field resonating in said laser. The photodetector is a phototransistor composed of an emitter layer (e), a collector layer (c) and a base layer (b), each of which being a bulk layer and forming part of one of said layer sequences (1, 2). With the proposed semiconductor laser an optical module based on this laser can be manufactured more easily, at lower costs and in a smaller size than known modules.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: August 15, 2017
    Assignee: Koninklijke Philips N.V.
    Inventor: Marcel Franz Christian Schemmann
  • Patent number: 9728461
    Abstract: A method for fabricating a semiconductor device includes forming a first gate stack over a first fin feature and second gate stack over a second fin feature, removing the first gate stack to form a first gate trench that exposes the first fin structure, removing the second gate stack to form a second gate trench that exposes the second fin feature, performing a high-pressure-anneal process to a portion of the first fin feature and forming a first high-k/metal gate (HK/MG) within the first gate trench over the portion of the first fin feature and a second HK/MG within the second gate trench over the second fin feature. Therefore the first HK/MG is formed with a first threshold voltage and the second HK/MG is formed with a second threshold voltage, which is different than the first threshold voltage.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: August 8, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yi Peng, Chia-Cheng Ho, Chih Chieh Yeh, Tsung-Lin Lee, Yu-Lin Yang
  • Patent number: 9711088
    Abstract: A display device includes a display panel and a scan driver including transistors formed in a non-display area of the display panel. A compensation voltage is supplied to the scan driver through a compensation gate electrode included in at least one transistor of the scan driver. Namely, the at least one transistor includes a gate electrode, to which a signal or a voltage for activating a channel is supplied, and the compensation gate electrode, to which the compensation voltage for recovering a threshold voltage is supplied.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: July 18, 2017
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Sehwan Na, Joungmi Choi, Dahye Shim, Daegyu Jo, Sohyun Kim, Hyunguk Jang
  • Patent number: 9691465
    Abstract: Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: June 27, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Farid Nemati, Scott T. Robins, Rajesh N. Gupta
  • Patent number: 9685512
    Abstract: A semiconductor device includes a diode region and an IGBT region. The diode region includes a front side anode region, an n-type diode barrier region, an n-type diode pillar region reaching the diode barrier region through the front side anode region, and a p-type back side anode region separated from the front side anode region by the diode barrier region. The IGBT region includes a front side body region, an n-type IGBT barrier region, and a back side body region separated from the front side body region by the IGBT barrier region. When a gate-off voltage is applied to a gate electrode, a resistance between the IGBT barrier region and the emitter electrode is higher than a resistance between the diode barrier region and the anode electrode.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: June 20, 2017
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Jun Okawara, Yusuke Yamashita, Satoru Machida
  • Patent number: 9620495
    Abstract: A semiconductor device is provided which comprises an ESD protection device. The structure of the semiconductor device comprises a p-doped isolated region in which a structure is manufactured which operates as a Silicon Controlled Rectifier which is coupled between an I/O pad and a reference voltage or ground voltage. The semiconductor device also comprises a pnp transistor which is coupled parallel to the Silicon Controlled Rectifier. The base of the transistor is coupled to the gate of the Silicon Controlled Rectifier. In an optional embodiment, the base and gate are also coupled to the I/O pad.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: April 11, 2017
    Assignee: NXP USA, Inc.
    Inventors: Patrice Besse, Alexis Huot-Marchand, Jean-Philippe Laine, Alain Salles
  • Patent number: 9595602
    Abstract: The present invention provides a switching device (100) for power conversion in which a first gate electrode (6), a p-type channel layer (2) having an n-type emitter region (3), a second gate electrode (13), and a p-type floating layer (15) are repeatedly arranged in order on the surface side of an n-type semiconductor substrate (1). An interval a between the two gates (6, 13) that sandwich the p-type channel layer (2) is configured to be smaller than an interval b between the two gates (13, 6) that sandwich the p-type floating layer (15). The first gate electrode (6) and the second gate electrode (13) are both supplied with drive signals having a time difference in drive timing.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: March 14, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Hashimoto, Mutsuhiro Mori, Masahiro Masunaga
  • Patent number: 9543390
    Abstract: A transistor includes a semiconductor substrate comprising a first region and a second region. The transistor further includes an emitter and a base disposed on the first region, and a collector disposed on the second region. The emitter includes a heterojunction. The heterojunction is at a same height as a junction between two different insulating materials that separate the emitter and the base.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: January 10, 2017
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Mieno Fumitake
  • Patent number: 9543401
    Abstract: A 3D semiconductor integrated circuit device and a method of manufacturing the same are provided. An active pillar is formed on a semiconductor substrate, and an interlayer insulating layer is formed so that the active pillar is buried in the interlayer insulating layer. The interlayer insulating layer is etched to form a hole so that the active pillar and a peripheral region of the active pillar are exposed. An etching process is performed on the peripheral region of the active pillar exposed through the hole by a certain depth, and a space having the depth is provided between the active pillar and the interlayer insulating layer. A silicon material layer is formed to be buried in the space having the depth, and an ohmic contact layer is formed on the silicon material layer and the active pillar.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: January 10, 2017
    Assignee: SK Hynix Inc.
    Inventors: Jin Ha Kim, Jun Kwan Kim, Kang Sik Choi, Su Jin Chae, Young Ho Lee
  • Patent number: 9520486
    Abstract: An apparatus including an electrostatic discharge (ESD) protection device comprising a semiconductor having first, second and third regions arranged to form a transistor, wherein the first region is doped with a first impurity of a first conductivity type and is separated from the second region which is doped with a second impurity of a second conductivity type opposite the first type, and wherein a dimensional constraint of the regions defines an operational threshold of the ESD protection device. In one example, the separation between a collector and an emitter of a bipolar transistor defines a trigger voltage to cause the electrostatic discharge protection device to become conducting. In another example, a width of a bipolar transistor base controls a holding voltage of the electrostatic discharge protection device.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: December 13, 2016
    Assignee: Analog Devices, Inc.
    Inventors: Edward John Coyne, Patrick Martin McGuinness, Paul Malachy Daly, Bernard Patrick Stenson, David J. Clarke, Andrew David Bain, William Allan Lane
  • Patent number: 9514677
    Abstract: A method of driving an OLED display includes: during a scanning period of a first frame, turning off a relay transistor and turning on a switching transistor to enable a second data voltage applied to a data line to be stored in a first capacitor; and during a light emitting period of the first frame, performing an operation to turn on a light emitting transistor and a compensation transistor to enable a voltage into which a first data voltage and a threshold voltage of a driving transistor are reflected to be applied to a second node for enabling the OLED to emit light by a driving current which flows into a driving transistor. The scanning period and the light emitting period temporally overlap each other.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: December 6, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Bo-Yong Chung, Hae-Yeon Lee, Yong-Jae Kim
  • Patent number: 9508824
    Abstract: A method of producing a semiconductor device, comprising a substrate layer made of a semiconductor material of a first conductivity type and having a first insulation region, and a vertical bipolar transistor having a first vertical portion of a collector made of monocrystalline semiconductor material of a second conductivity type and disposed in an opening of the first insulation region, a second insulation region lying partly on the first vertical portion of the collector and partly on the first insulation region and having an opening in the region of the collector, in which opening a second vertical portion of the collector made of monocrystalline material is disposed, the portion including an inner region of the second conductivity type, a base made of monocrystalline semiconductor material of the first conductivity type, a base connection region surrounding the base in the lateral direction, a T-shaped emitter made of semiconductor material of the second conductivity type and overlapping the base connect
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: November 29, 2016
    Assignee: IHP GmbH—Innovations for High Perforamce Microelectronics/Leibniz-Institut fur Innovative Mikroelektronik
    Inventors: Alexander Fox, Bernd Heinemann, Steffen Marschmeyer
  • Patent number: 9508711
    Abstract: A semiconductor device includes a bipolar junction transistor cell including an emitter region which is at least partly formed between mesas of a semiconductor body. The emitter region extends between a first surface of the semiconductor body and an emitter bottom plane. The transistor cell further includes a collector region and a base region that separates the emitter region and the collector region.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: November 29, 2016
    Assignee: Infineon Technologies AG
    Inventors: Jens Peter Konrath, Hans-Joachim Schulze
  • Patent number: 9496250
    Abstract: Methods for designing and fabricating a bipolar junction transistor. A predetermined size for a device region of the bipolar junction transistor is determined based on a given current gain. A trench isolation layout is determined for a plurality of trench isolation regions to be formed in a substrate to surround the device region. The trench isolation regions are laterally spaced relative to each other in the trench isolation layout in order to set the predetermined size of the device region. An interconnect layout is determined that specifies one or more contacts coupled with a terminal of the bipolar junction transistor. The specification of the one or more contacts in the interconnect layout is unchanged by the determination of the trench isolation layout.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: November 15, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vibhor Jain, Alvin J. Joseph, Anthony K. Stamper
  • Patent number: 9466687
    Abstract: Instability and drift sometimes observed in bipolar transistors, having a portion of the base extending to the transistor surface between the emitter and base contact, can be reduced or eliminated by providing a further doped region of the same conductivity type as the emitter at the transistor surface between the emitter and the base contact. The further region is desirably more heavily doped than the base region at the surface and less heavily doped than the adjacent emitter. In another embodiment, a still or yet further region of the same conductivity type as the emitter is provided either between the further region and the emitter or laterally within the emitter. The still or yet further region is desirably more heavily doped than the further region. Such further regions shield the near surface base region from trapped charge that may be present in dielectric layers or interfaces overlying the transistor surface.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: October 11, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Xin Lin, Daniel J. Blomberg, Hongning Yang, Jiang-Kai Zuo
  • Patent number: 9384978
    Abstract: The present invention provides a method for forming trenches. First, a mandrel layer is formed on a substrate, wherein the mandrel layer comprises a stop layer and a sacrificial layer. A spacer is formed on at least a sidewall of the mandrel layer, following by forming a material layer on the substrate for covering the spacer and the mandrel layer. After performing a removing process to remove apart of the material layer, apart of the spacer and the sacrificial layer; the spacer is removed to form at least one first trench in the remaining material layer and the mandrel.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: July 5, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chao-Hung Lin, Shih-Fang Hong, Li-Wei Feng, Shih-Hung Tsai, Ssu-I Fu, Jyh-Shyang Jenq
  • Patent number: 9349827
    Abstract: In an IGBT, defects generated by ion implantation for introduction of the P-type collector region or N-type buffer region into the N?-type drift region near the N-type buffer region remain to improve the switching speed, however the leak current increases by bringing a depletion layer into contact with the crystal defects at the off time. To avoid this, an IGBT is provided which includes an N-type buffer region having a higher concentration than that of an N?-type drift region and being in contact with a P-type on its backside, and a defect remaining region provided near the boundary between the N-type buffer region and the N?-type drift region. The N?-type drift region located on the front surface side with respect to the defect remaining region is provided with an N-type field stopping region having a higher concentration than that of the N?-type drift region.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: May 24, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hitoshi Matsuura, Makoto Koshimizu, Yoshito Nakazawa
  • Patent number: 9324828
    Abstract: Various particular embodiments include a method of amorphizing a portion of silicon underneath the N+ base section of a PNP transistor structure. After amorphizing, the method can include selectively etching that implant-amorphized silicon to trim the collector-base area and collector-base junction. The selective etching is enhanced because the unimplanted silicon region etches at a distinct rate than the implant-amorphized silicon, allowing for control over the trimming of the collector-base junction.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: April 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Joseph R. Greco, Qizhi Liu, Aaron L. Vallett, Robert F. Vatter
  • Patent number: 9324264
    Abstract: A pixel and an organic light emitting diode (OLED) display using the pixel are disclosed. The pixel includes a driving transistor for transmitting a driving current, an organic light emitting diode (OLED) receiving a first portion of the driving current, and a bypass transistor receiving a second portion of the driving current.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: April 26, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jin-Tae Jeong, Won-Kyu Kwak
  • Patent number: 9299817
    Abstract: A bipolar junction transistor (BJT) is provided. The BJT can include a semiconductor substrate, a first well disposed in the substrate and implanted with a first impurity, a second well disposed at one side of the first well and implanted with a second impurity, a first device isolation layer disposed in the first well and defining an emitter area, and a second device isolation layer disposed in the second well and defining a collector area, The BJT can also include an emitter having a second impurity, a base having a first impurity, a collector having a second impurity, and a high concentration doping area having a second impurity at high concentration. The high concentration doping area can be provided at one side of the collector in the second well.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 29, 2016
    Assignee: Dongbu HiTek Co., Ltd.
    Inventors: Jae Hyun Yoo, Jong Min Kim
  • Patent number: 9287141
    Abstract: A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: March 15, 2016
    Assignee: International Business Machines Corporation
    Inventor: Mattias E. Dahlstrom
  • Patent number: 9276093
    Abstract: Aspects of the invention provide a method of forming a bipolar junction transistor. The method includes: providing a semiconductor substrate including a uniform silicon nitride layer over an emitter pedestal, and a base layer below the emitter pedestal; applying a photomask at a first end and a second end of a base region; and performing a silicon nitride etch with the photomask to simultaneously form silicon nitride spacers adjacent to the emitter pedestal and exposing the base region of the bipolar junction transistor. The silicon nitride etch may be an end-pointed etch.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: March 1, 2016
    Assignee: GlobalFoundries, Inc.
    Inventors: Margaret A. Faucher, Paula M. Fisher, Thomas H. Gabert, Joseph P. Hasselbach, Qizhi Liu, Glenn C. MacDougall
  • Patent number: 9240448
    Abstract: Device structures for a bipolar junction transistor. The device structure includes a collector region, an intrinsic base formed on the collector region, an emitter coupled with the intrinsic base and separated from the collector by the intrinsic base, and an isolation region extending through the intrinsic base to the collector region. The isolation region is formed with a first section having first sidewalls that extend through the intrinsic base and a second section with second sidewalls that extend into the collector region. The second sidewalls are inclined relative to the first sidewalls. The isolation region is positioned in a trench that is formed with first and second etching process in which the latter etches different crystallographic directions of a single-crystal semiconductor material at different etch rates.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: January 19, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: James W. Adkisson, James R. Elliott, David L. Harame, Marwan H. Khater, Robert K. Leidy, Qizhi Liu, John J. Pekarik
  • Patent number: 9231089
    Abstract: Disclosed is a trench formation technique wherein an opening having a first sidewall with planar contour and a second sidewall with a saw-tooth contour is etched through a semiconductor layer and into a semiconductor substrate. Then, a crystallographic wet etch process expands the portion of the opening within the semiconductor substrate to form a trench. Due to the different contours of the sidewalls and, thereby the different crystal orientations, one sidewall etches faster than the other, resulting in an asymmetric trench. Also disclosed is a bipolar semiconductor device formation method that incorporates the above-mentioned trench formation technique when forming a trench isolation region that undercuts an extrinsic base region and surrounds a collector pedestal.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: January 5, 2016
    Assignee: International Business Machines Corporation
    Inventors: Robert K. Leidy, Mark D. Levy, Qizhi Liu, Gary L. Milo
  • Patent number: 9184267
    Abstract: A power semiconductor device comprises a substrate, a first electrode, a conductive layer, at least one electrical connecting element, a plurality of doped semiconductor layers, an insulating layer, and a second electrode. The first electrode is formed on a surface of the substrate. The conductive layer is formed on another surface of the substrate. The electrical connecting element is formed through the substrate and electrically connects the first electrode and the conductive layer. The doped semiconductor layers are stacked on the conductive layer. The upper most semiconductor layer comprises two doped sub-regions. The insulating layer is formed on the plurality of doped semiconductor layers. The second electrode is formed on the insulating layer and at least extends on an area between the doped sub-regions.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: November 10, 2015
    Assignee: CHUNG HUA UNIVERSITY
    Inventor: Jium Ming Lin