Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a substrate, forming a metallization layer on the substrate, forming an upper dielectric layer over the metallization layer, forming a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer penetrating the upper dielectric layer and the metallization layer, wherein the first sacrificial layer is aligned with the third sacrificial layer along a first axis, and the second sacrificial layer is free from overlapping the first sacrificial layer and the third sacrificial layer along the first axis, forming a width controlling structure between the first sacrificial layer and the third sacrificial layer, wherein the width controlling structure defines a recess exposing the upper dielectric layer, forming a protective layer within the recess, removing the width controlling structure to expose a portion of the metallization layer.

Abstract: The ability of a grounded gate NMOS (ggNMOS) device to withstand and protect against human body model (HBM) electrostatic discharge (ESD) events is greatly increased by resistance balancing straps. The resistance balancing straps are areas of high resistance formed in the substrate between an active area that includes a MOSFET of the ggNMOS device and a bulk ring that surrounds the active area. A Vss rail is coupled to the substrate beneath the MOSFET through the bulk ring. The substrate beneath the MOSFET provides base regions for parasitic transistors that switch on for the ggNMOS device to operate. The straps inhibit low resistance pathways between the base regions and the bulk ring and prevent a large portion of the ggNMOS device from being switched off while a remaining portion of the ggNMOS device remains switched on. The strap may be divided into segments inserted at strategic locations.

Abstract: A BJT and methods of forming the same are described. The BJT includes a collector region disposed in a substrate, a lower base structure disposed on the collector region, a first dielectric layer surrounding a bottom portion of the lower base structure, and a second dielectric layer surrounding a top portion of the lower base structure. The first dielectric layer includes a first oxide, the second dielectric layer includes a second oxide, and the first and second oxides have different densities. The BJT further includes an upper base structure disposed on the second dielectric layer and the lower base structure, an emitter region disposed on the lower base structure, a sidewall spacer structure disposed between the emitter region and the upper base structure, and the sidewall spacer structure includes a material different from materials of the first and second dielectric layers.

Abstract: A silicon-on-insulator metal-oxide-semiconductor field-effect transistor (SOI MOSFET) structure is provided, including a substrate layer; a buried oxide layer which is arranged on an upper surface of the substrate layer and is made of SiO2; an active zone which is arranged on an upper surface of the buried oxide layer; a source electrode and a drain electrode which are arranged on an upper surface of the active zone; a gate dielectric layer which is arranged between the source electrode and the drain electrode; a gate electrode which is provided in the gate dielectric layer; and a heat conduction column which penetrates through the buried oxide layer, and its top wall is in contact with the active zone. The heat conduction column dissipates heat in the active zone, resulting in a lattice temperature of the active zone will not increase extremely and avoiding a decrease of a current of the drain electrode.

Abstract: A semiconductor device including a well region in a substrate, an impurity region in the well region, a first active fin on the impurity region, a second active fin on the well region, and a connection pattern penetrating the second active fin and connected to the well region may be provided. The substrate and the impurity region include impurities having a first conductivity type. The well region includes impurities having a second conductivity type different from the first conductivity type. The first active fin includes a plurality of first semiconductor patterns that are spaced apart from each other in a direction perpendicular to a top surface of the substrate. The first semiconductor patterns and the impurity region include impurities having the first conductivity type.

Abstract: A mechatronic module includes: a hybrid circuit arrangement having at least one interrupter, which interrupter includes at least one first mechanical switch and at least one first semiconductor circuit arrangement. The hybrid circuit arrangement is situated on a first face of a ceramic substrate, a second face, opposite the first face, of the ceramic substrate being connected to a metal plate. A housing shell is fastened to the metal plate and encloses the ceramic substrate and the hybrid circuit arrangement. The metal plate and the housing shell form a housing of the mechatronic module. Interstices within the housing are filled at least in some regions with a potting compound.

Abstract: A semiconductor device includes: a carrier stored layer; an upper-stage active portion disposed on a first insulating film along an inner wall of an upper portion of a trench penetrating the carrier stored layer, the upper-stage active portion being upper-stage polysilicon connected to a gate electrode; and lower-stage polysilicon disposed on a second insulating film along an inner wall of a lower portion of the trench, the lower-stage polysilicon provided with a third insulating film disposed between the upper-stage active portion and the lower-stage polysilicon. The lower end of the upper-stage active portion is positioned below the lower end of the carrier stored layer.

Abstract: A display apparatus and a method for driving the same are provided. The display apparatus includes pixel circuits and a threshold detection module. The pixel circuit includes a driving transistor and a data voltage writing module including an output terminal electrically connected to the driving transistor. The threshold detection module is configured to detect a threshold voltage of the driving transistor. An operating process of the pixel circuit includes a first phase and a second phase. The first phase includes a data writing phase and a light-emitting phase. The second phase includes an adjusting phase and a light-emitting phase. The driving transistor receives a data voltage during the data writing phase. During the adjusting phase, the driving transistor receives an adjusting voltage corresponding to the threshold voltage of the driving transistor that is detected by the threshold detection module.

Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a collector having a raised portion, an emitter having a raised portion, and a base laterally arranged between the raised portion of the emitter and the raised portion of the collector. The base includes an intrinsic base layer and an extrinsic base layer stacked with the intrinsic base layer. The structure further includes a stress liner positioned to overlap with the raised portion of the collector, the raised portion of the emitter, and the extrinsic base layer.

Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes an emitter having a raised portion, a collector having a raised portion, and a base having a base layer and an extrinsic base layer stacked with the base layer. The base layer and the extrinsic base layer are positioned in a lateral direction between the raised portion of the emitter and the raised portion of the collector, the base layer has a first width in the lateral direction, the extrinsic base layer has a second width in the lateral direction, and the second width is greater than the first width.

Abstract: A structure for a lateral bipolar junction transistor is provided. The structure comprising an emitter including a first concentration of a first dopant. A collector including a second concentration of the first dopant, the first concentration of the first dopant may be different from the second concentration of the first dopant. An intrinsic base may be laterally arranged between the emitter and the collector, and an extrinsic base region may be above the intrinsic base. An emitter extension may be arranged adjacent to the emitter, whereby the emitter extension laterally extends under a portion of the extrinsic base region. A halo region may be arranged adjacent to the emitter extension, whereby the halo region laterally extends under another portion of the extrinsic base region.

Abstract: The object is to provide a semiconductor device that prevents a snapback operation and has excellent heat dissipation. The semiconductor device includes a semiconductor substrate, transistor portions, diode portions, a surface electrode, and external wiring. The transistor portions and the diode portions are provided in the semiconductor substrate and are arranged in one direction parallel with the surface of the semiconductor substrate. A bonding portion of the external wiring is connected to the surface electrode. The transistor portions and the diode portions are provided in a first region and a second region and alternately arranged in the one direction. A first transistor width and a first diode width in the first region are smaller than a width of the bonding portion. A second transistor width and a second diode width in the second region are larger than the width of the bonding portion.

Abstract: The present invention relates to an electronic device including an input and an output, the device generating an output voltage when the input of the device is supplied, the device comprising: a conversion unit converting a spin current into a charge current having an amplitude and a sign, a spin current application unit applying a spin current to the conversion unit, a ferroelectric layer, which has a ferroelectric polarization and is arranged such that the ferroelectric polarization controls at least one among the amplitude and the sign of the charge current, and an electric field application unit suitable for applying an electric field to the ferroelectric layer to control the ferroelectric polarization.

Abstract: A charge control structure is provided for a bipolar junction transistor to control the charge distribution in the depletion region extending into the bulk collector region when the collector-base junction is reverse-biased. The charge control structure comprises a lateral field plate above the upper surface of the collector and dielectrically isolated from the upper surface of the collector and a vertical field plate which is at a side of the collector and is dielectrically isolated from the side of the collector. The charge in the depletion region extending into the collector is coupled to the base as well as the field-plates in the charge-control structure, instead of only being coupled to the base of the bipolar junction transistor. In this way, a bipolar junction transistor is provided where the dependence of collector current on the collector-base voltage, also known as Early effect, can be reduced.

Abstract: Display panel, display device and detection compensation method of display panel are disclosed herein. In one embodiment, a display panel includes: display pixels arranged in M rows and N columns and provided in a display area, where both M and N are both positive integers; first power supply lines provided in the display area; and an integrated circuit, a switch circuit and a voltage stabilization transistor provided in a border area. One row of display pixels is electrically connected to one first power supply line. The first power supply lines are electrically connected to a first pin of the integrated circuit. A detection pin of the integrated circuit is electrically connected to the switch circuit. The voltage stabilization transistor includes: a control electrode electrically connected to the second pin, a first electrode electrically connected to the detection pin, and a second electrode electrically connected to one row of display pixels.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device capable of suppressing breakdown due to current concentration while suppressing an increase in chip size are provided. According to one embodiment, a semiconductor device has a gate resistance on a main surface side of a semiconductor substrate, a first contact and a second contact connected to an upper surface of the gate resistance, and a carrier discharging portion that discharges the carrier formed in the semiconductor substrate below the gate resistance, the gate resistance having a first contacting portion to which a first contact is connected, a second contacting portion to which a second contact is connected, and a plurality of extending portions with one end connected to the first contacting portion and the other end connected to the second contacting portion. The gate resistance forms an opening between adjacent extending portions and the carrier discharge portion is formed in the opening.

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a semiconductor-based isolation structure on a substrate. A shallow trench isolation (STI) structure may be positioned on the semiconductor-based isolation structure. An active semiconductor region is on the substrate and adjacent each of the semiconductor-based isolation structure and the STI structure. The active semiconductor region includes a doped semiconductor material. At least one device on the active semiconductor region may be horizontally distal to the STI structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a sub-collector region; a collector region in electrical connection to the sub-collector region; an emitter located adjacent to the collector region and comprising emitter material, recessed sidewalls on the emitter material and an extension region extending at an upper portion of the emitter material above the recessed sidewalls; and an extrinsic base separated from the emitter by the recessed sidewalls.

Abstract: A semiconductor apparatus includes a power semiconductor device, a resin film and a sealing insulating material. The power semiconductor device includes: a first electrode covering a first region on one main surface of the semiconductor substrate; a second electrode formed on the other main surface of the semiconductor substrate; a guard ring formed in a second region outer than the first region; and a non-conductive inorganic film located in the second region and covering the guard ring. The resin film overlaps the guard ring in a plan view, and the resin film on the non-conductive inorganic film has a thickness of 35 ?m or more. The resin film is a film of a single layer, and the resin film has an outermost edge in the form of a downwardly spreading fillet. The outermost edge of the resin film is inner than an outermost edge of the semiconductor substrate.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having one or more sealed airgap and methods of manufacture. The structure includes: a subcollector region in a substrate; a collector region above the substrate; a sealed airgap formed at least partly in the collector region; a base region adjacent to the collector region; and an emitter region adjacent to the base region.

Abstract: An electrical device includes an integrated circuit having device circuitry, a passive breakdown protection circuit, and a resistor coupled to or included with the device circuitry. The resistor includes: a polysilicon layer coupled between a first terminal and a second terminal; an epitaxial layer terminal; and a buried layer terminal. The passive breakdown protection circuit is coupled between the second terminal and the epitaxial layer terminal. The passive breakdown protection circuit is also coupled between the epitaxial layer terminal and the buried layer terminal.

Abstract: Memory devices and electronic systems include an array of vertical memory cells positioned along respective vertical channels to define vertical memory strings. Each of the vertical channels includes a channel material exhibiting an electron mobility of at least about 30 cm2/(V·s) and a room temperature band gap of at least about 1.40 eV (e.g., zinc oxide, silicon carbide, indium phosphide, indium gallium zinc oxide, gallium arsenide, or molybdenum disulfide) and a bottom plug material exhibiting a room temperature band gap of less than about 1.10 eV (e.g., silicon germanium, germanium, or indium gallium arsenide). Methods of fabricating a memory device include forming such a bottom plug material within vertical channels and forming such a channel material electrically coupled to the bottom plug material.

Abstract: One illustrative device disclosed herein includes a semiconductor substrate, a bipolar junction transistor (BJT) device that comprises a collector, a base and an emitter, at least one piezoelectric structure comprising a piezoelectric material positioned adjacent the BJT device, and at least first and second conductive contact structures that are conductively coupled to the piezoelectric structure.

Abstract: A semiconductor device includes a semiconductor substrate with a collector region formed within the semiconductor substrate. A base region, including a first base region and a second base region, is formed over the collector region. An extrinsic base region is formed laterally adjacent to and coupled to the second base region. A base link region is disposed proximate to the second base region, wherein the base link region couples the extrinsic base sidewall to the second base region. A method for forming a semiconductor device includes forming the collector region within the semiconductor substrate, forming a plurality of dielectric layers over the collector region, forming an extrinsic base layer over the collector region, etching an emitter window, forming the first base region over the collector region, forming the second base region over the first base region, wherein forming the second base region includes forming the base link region.

Abstract: A power semiconductor transistor includes a semiconductor body having a front side and a backside with a backside surface. The semiconductor body includes a drift region of a first conductivity type and a field stop region of the first conductivity type. The field stop region is arranged between the drift region and the backside and includes, in a cross-section along a vertical direction from the backside to the front side, a concentration profile of donors of the first conductivity type that has: a first local maximum at a first distance from the backside surface, a front width at half maximum associated with the first local maximum, and a back width at half maximum associated with the first local maximum. The front width at half maximum is smaller than the back width at half maximum and amounts to at least 8% of the first distance.

Abstract: According to a semiconductor device herein, the device includes a substrate. An active device is formed in the substrate. The active device includes a collector region, a base region formed on the collector region, and an emitter region formed on the base region. An isolation structure is formed in the substrate around the active device. A trench filled with a compressive material is formed in the substrate and positioned laterally adjacent to the emitter region and base region. The trench extends at least partially into the base region.

Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a semiconductor mesa having source zones arranged along a longitudinal axis of the semiconductor mesa and at least one body zone forming first pn junctions with the source zones and a second pn junction with a drift zone. The semiconductor device further includes stripe-shaped electrode structures on opposite sides of the semiconductor mesa and separation regions between neighboring ones of the source zones. At least one of the electrode structures includes a gate electrode. In the separation regions, at least one of (i) a capacitive coupling between the gate electrode and the semiconductor mesa and (ii) a conductivity of majority charge carriers of the drift zone is lower than outside of the separation regions.

Abstract: The present application discloses a method for driving a display apparatus. The display apparatus includes an OLED and a driver transistor. An anode of the OLED is connected to a source of the driver transistor, a drain of the driver transistor is connected to a positive power supply, a cathode of the OLED is connected to a negative power supply, and a voltage difference between the positive power supply and the negative power supply is in a range from 7.1 V to 9.6 V.

Abstract: An electronic component includes a die, a first protective layer, a second protective layer, a first conductive pillar and a second conductive pillar. The die includes a conductive pad. The first protective layer is disposed on the die. The first protective layer defines a first opening to expose the conductive pad of the die. The second protective layer is disposed on the first protective layer. The second protective layer defines a second opening and a first recess. The second opening exposes the conductive pad of the die. The first conductive pillar is disposed within the second opening and electrically connected to the conductive pad. The second conductive pillar is disposed within the first recess. A height of the first conductive pillar is substantially equal to a height of the second conductive pillar. A bottom surface of the first recess is disposed between a top surface of the first protective layer and a top surface of the second protective layer.

Abstract: A method includes forming a base layer on a top surface of a substrate. A dielectric layer is formed on exposed surfaces of the base layer. A hardmask layer is formed on the base layer and the dielectric layer. A pattern is formed from the hardmask with a first opening and a second opening. Portions of a dielectric layer are removed from the top surface of the base layer at positions consistent with the pattern of the first opening and the second opening to form exposed surfaces defined as a first window and a second window in the dielectric layer. Deposits of a dopant-containing layer are limited on the exposed surfaces of: a first portion on the top surface of the base layer inside of the first window, and a second portion on the top surface of the base layer inside of the second window.

Abstract: Cards made in accordance with the invention include a specially treated thin decorative layer attached to a thick core layer of metal or ceramic material, where the thin decorative layer is designed to provide selected color(s) and/or selected texture(s) to a surface of the metal cards. Decorative layers for use in practicing the invention include: (a) an anodized metal layer; or (b) a layer of material derived from plant or animal matter (e.g., wood, leather); or (c) an assortment of aggregate binder material (e.g., cement, mortar, epoxies) mixed with laser reactive materials (e.g., finely divided carbon); or (d) a ceramic layer; and (e) a layer of crystal fabric material. The cards may be dual interface smart cards which can be read in a contactless manner and/or via contacts.

Abstract: A heterojunction bipolar transistor (HBT) and methods of fabrication provide a substrate, a base having a first lateral area, an emitter, a sub-collector having a second lateral area, and a collector above the sub-collector, wherein the second lateral area of the sub-collector is less than the first lateral area of the base, which enables the fabrication of HBTs with high linearity, as measured by an improved third order distortion (OIP3) parameter, while maintaining high gain; which enables the fabrication of HBTs with a selectively grown or overgrown collector/sub-collector; and which reduces a capacitance between the base and collector of the HBTs.

Abstract: A display device includes data lines extending in a first direction, gate lines extending in a second direction, a source driver that supplies a data signal to the data lines, a gate driver that supplies a gate signal to the gate lines, and a timing controller that determines scan order of the gate lines and outputs image data to the source driver based on the scan order. The timing controller determines the scan order of the gate lines based on an input image corresponding to input image data input from an outside, and switches first scan order and second scan order in each frame, the first scan order and the second scan order being different from each other in the scan order.

Abstract: An advanced contact module for optimizing emitter and contact resistance and methods of manufacture are disclosed. The method includes forming a first contact via to a first portion of a first device. The method further includes filling the first contact via with metal material to form a first metal contact to the first portion of the first device. The method further includes forming additional contact vias to other portions of the first device and contacts of a second device. The method further includes cleaning the additional contact vias while protecting the first metal contact of the first portion of the first device. The method further includes filling the additional contact vias with metal material to form additional metal contacts to the other portions of the first device and the second device.

Abstract: According to an embodiment of a semiconductor device, the device includes first and second trenches formed in a semiconductor body and an electrode disposed in each of the trenches. One of the electrodes is a gate electrode, and the other electrode is electrically disconnected from the gate electrode. The semiconductor device further includes a semiconductor mesa between the trenches. The semiconductor mesa includes a separation region and at least one of a source region and a body region located in the semiconductor mesa. A drift zone is provided below the at least one of the source region and the body region. In the separation region, at least one of (i) a capacitive coupling between the gate electrode and the semiconductor mesa and (ii) a conductivity of majority charge carriers of the drift zone is lower than outside of the separation region.

Abstract: A method for manufacturing includes providing a semiconductor substrate having a semiconductor device including at least two device layers to be contacted. A first device layer is smaller than a lithographic minimum feature size used for manufacturing the semiconductor device. Further, the method includes providing an isolation layer on the semiconductor device such that the semiconductor device is covered by the isolation layer; planarizing the isolation layer up to the semiconductor device; providing a first lithographic mask on the semiconductor device, such that the first device layer and a portion of the isolation layer are covered by the first lithographic mask; selectively removing the isolation layer to expose a second device layer while maintaining the portion of the isolation layer that is covered by the first lithographic mask; and providing a stop layer on the first device layer, the second device layer and the portion of the isolation layer.

Abstract: A semiconductor device capable of reducing an inter-source electrode resistance RSS (on) and reducing a chip size is provided. A semiconductor device according to the present invention includes a chip partitioned into three areas including a first area, a second area, and a third area, and a common drain electrode provided on a back surface of the chip, in which the second area is formed between the first and third areas, a first MOSFET is formed in the first area and the third area, and a second MOSFET is formed in the second area.

Abstract: The present disclosure relates to an organic light-emitting diode (OLED) display device and a compensation circuit of an OLED. The compensation circuit of the OLED includes: a first thin film transistor (TFT), a second TFT, a third TFT, a fourth TFT, a fifth TFT, a sixth TFT, a first capacitor, and a second capacitor. As such, the compensation circuit of the present disclosure only requires the scanning signals and the emission signals, so as to simplify configurations of the circuit, and to reduce costs.

Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate having a first plane and a second plane, a plurality of first semiconductor areas provided on the first plane, a plurality of second semiconductor areas provided between the plurality of first semiconductor areas, a plurality of insulator regions provided between the first semiconductor areas and the second semiconductor areas, first-conductivity-type drain regions provided in the first semiconductor areas, first-conductivity-type source regions provided in the second semiconductor areas, gate electrodes, first-conductivity-type first impurity regions that are provided between the first-conductivity-type drain regions and the second plane and have a lower first-conductivity-type impurity concentration than the first-conductivity-type drain regions, and a plurality of second-conductivity-type second impurity regions provided between the first-conductivity-type source regions and the second plane.

Abstract: An electrostatic protection element whose electrostatic breakdown resistance can be adjusted with a required minimum design change is provided. A semiconductor device includes an electrostatic protection element including a bipolar transistor whose base region and emitter region are electrically coupled together through a resistance region. At this time, the base region of the electrostatic protection element has a side including a facing portion that faces the collector region. The facing portion of the side includes an exposed portion that is exposed from an emitter wiring in plan view and a covered portion that is covered by the emitter wiring in plan view.

Abstract: A semiconductor device includes a diode provided with: a drift layer being a first conductivity type; a cathode region being provided in a back face side of the drift layer and being the first conductivity type; a second conductivity type region provided in a surface layer part of the drift layer; multiple trenches dividing the second conductivity type region into pieces by being provided deeper than the second conductivity type region, and configuring an anode region; a gate insulation film provided in a surface of the trench; a gate electrode provided in a surface of the gate insulation film; an upper electrode electrically connected with the anode region; and a lower electrode electrically connected with the cathode region. A width between the trenches is narrowest in the drift layer is defined as a mesa width. The mesa width is set to be equal to or greater than 0.3 ?m.

Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A cyclical epitaxy process is performed to provide a collector region of a first conductivity type on the collector contact region that is laterally separated from a silicon layer by an air gap. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.

Abstract: A power semiconductor device has a semiconductor body configured to conduct a load current in parallel to an extension direction between first and second load terminals of the power semiconductor device. The semiconductor body includes a doped contact region electrically connected to the second load terminal, a doped drift region having a dopant concentration that is smaller than a dopant concentration of the contact region, and an epitaxially grown doped transition region separated from the second load terminal by the contact region and that couples the contact region to the drift region. An upper subregion of the transition region is in contact with the drift region, and a lower subregion of the transition region is in contact with the contact region. The transition region has a dopant concentration of at least 0.5*1015 cm?3 for at least 5% of the total extension of the transition region in the extension direction.

Abstract: A method is for making a photonic chip including EO devices having multiple thicknesses. The method may include forming a first semiconductor layer over a semiconductor film, forming a second semiconductor layer over the first semiconductor layer, and forming a mask layer over the second semiconductor layer. The method may include performing a first selective etching of the mask layer to provide initial alignment trenches, performing a second etching, aligned with some of the initial alignment trenches and using the first semiconductor layer as an etch stop, to provide multi-level trenches, and filling the multi-level trenches to make the EO devices having multiple thicknesses.

Abstract: A display apparatus includes a plurality of pixels. Each pixel includes a first capacitor connected between a first voltage line receiving a driving signal and a first node; a first transistor comprising a control electrode connected to the first node, a first electrode connected to a second voltage line receiving a first power source signal, and a second electrode connected to a second node; an organic light emitting diode comprising an anode electrode connected to the second node and a cathode electrode receiving a second power source signal; a second capacitor connected between an m-th data line and the second node; a second transistor comprising a control electrode connected to an n-th gate line, a first electrode connected to the first node, and a second electrode connected to the second node; and a third transistor comprising a control electrode connected to an n-th scan line, a first electrode connected to the first voltage line, and a second electrode connected to the second node.

Abstract: A method comprises forming shallow trenches in an intrinsic base semiconductor layer and forming a first base layer thereon; applying a first mask to the layer; etching the first base layer; forming a second base layer on the intrinsic base semiconductor layer adjacent the first base layer; removing the first mask; applying a second mask to the base layers; simultaneously etching the layers to produce extrinsic bases of reduced cross dimensions, a length of the second extrinsic base layer being different from a length of the first extrinsic base layer; disposing spacers on the extrinsic bases; etching around the bases leaving the intrinsic base semiconductor layer under the bases and spacers; implanting ions into sides of the intrinsic base semiconductor layer under the extrinsic bases to form emitter/collector junctions; depositing semiconductor material adjacent to the junctions and the trenches; and removing the applied second mask.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-voltage, analog bipolar devices and methods of manufacture. The structure includes: a base region formed in a substrate; a collector region formed in the substrate and comprising a deep n-well region and an n-well region; and an emitter region formed in the substrate and comprising a deep n-well region and an n-well region.

Abstract: In accordance with an embodiment of the present invention, a semiconductor chip includes a device region disposed in or over a substrate, a doped region disposed in the device region, and a through via disposed in the substrate. The through via extends through the doped region.

Abstract: Disclosed herein is a bipolar transistor capable of improving a current amplification rate while improving voltage resistance. A bipolar transistor is provided with a p-type emitter region, a p-type collector region, an n-type base region located between the emitter region and the collector region, a p-type first embedded region located below the base region, and an n-type region having a lower n-type impurity concentration than the base region, being in contact with the emitter region, the collector region, the base region and the first embedded region, separating the emitter region from the base region and the first embedded region, and separating the collector region from the base region and the first embedded region. A part of the base region projects out toward a collector region side than the first embedded region does.

Abstract: Presented is a bipolar transistor capable of improving a current amplification rate while improving voltage resistance. A bipolar transistor is provided with a p-type emitter region, a p-type collector region, an n-type base region located between the emitter region and the collector region, a p-type first embedded region located below the base region, and an n-type region having a lower n-type impurity concentration than the base region. The base region is provided with a first high-concentration region and a low-concentration region positioned above the first embedded region, and a second high-concentration region positioned on a collector region side than the low-concentration region, wherein the second high-concentration region has a higher n-type impurity concentration than the low-concentration region.