Abstract: A wide band gap semiconductor device includes a first doping region of a first conductivity type and a second doping region of a second conductivity type. A drift portion of the second doping region has a first average net doping concentration lower than 1e17 cm?3. A highly doped portion of the second doping region has a second average net doping concentration higher than 5e18 cm?3. A compensation portion of the second doping region located between the drift and highly doped portions extends from a first area with a net doping concentration higher than 1e16 cm?3 and lower than 1e17 cm?3 to a second area with a net doping concentration higher than 5e18 cm?3. A maximum gradient of the net doping concentration within at least a part of the compensation portion extending from the second area towards the first area for at least 100 nm is lower than 5e22 cm?4.

Abstract: A CZ silicon ingot is doped with donors and acceptors and includes an axial gradient of doping concentration of the donors and of the acceptors. An electrically active net doping concentration, which is based on a difference between the doping concentrations of the donors and acceptors varies by less than 60% for at least 40% of an axial length of the CZ silicon ingot due to partial compensation of at least 20% of the doping concentration of the donors by the acceptors.

Abstract: A semiconductor device includes: a first base layer; a drain layer disposed on the back side surface of the first base layer; a second base layer formed on the surface of the first base layer; a source layer formed on the surface of the second base layer; a gate insulating film disposed on the surface of both the source layer and the second base layer; a gate electrode disposed on the gate insulating film; a column layer formed in the first base layer of the lower part of both the second base layer and the source layer by opposing the drain layer; a drain electrode disposed in the drain layer; and a source electrode disposed on both the source layer and the second base layer, wherein heavy particle irradiation is performed to the column layer to form a trap level locally.

Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) having a deep pseudo buried layer is disclosed. The SiGe HBT includes isolation structures formed in trenches, first pseudo buried layers and second pseudo buried layers, and a collector region. The first pseudo buried layers are formed under the respective trenches and the second pseudo buried layers are formed under the first pseudo buried layers, with each first pseudo buried layer vertically contacting with a second pseudo buried layer. The second pseudo buried layers are laterally connected to each other, and the collector region is surrounded by the trenches, the first pseudo buried layers and the second pseudo buried layers. The cross section of each of the trenches has a regular trapezoidal shape, namely, each trench's width of its top is smaller than that of its bottom. A manufacturing method of the SiGe HBT is also disclosed.

Abstract: Disclosed is a method for controlling the recombination rate in the base region of a bipolar semiconductor component, and a bipolar semiconductor component.

Abstract: An integrated circuit includes a bipolar transistor disposed over a substrate. The bipolar transistor includes a base electrode disposed around at least one germanium-containing layer. An emitter electrode is disposed over the at least one germanium-containing layer. At least one isolation structure is disposed between the emitter electrode and the at least one germanium-containing layer. A top surface of the at least one isolation structure is disposed between and electrically isolating a top surface of the emitter electrode from a top surface of the at least one germanium-containing layer.

Abstract: The invention, in one aspect, provides a semiconductor device that comprises a collector located in a semiconductor substrate and an isolation region located under the collector, wherein a peak dopant concentration of the isolation region is separated from a peak dopant concentration of the collector that ranges from about 0.9 microns to about 2.0 microns.

Abstract: An n+-emitter layer arranged under an emitter electrode is formed of convex portions arranged at predetermined intervals and a main body coupled to the convex portions. A convex portion region is in contact with the emitter electrode, and a p+-layer doped more heavily than a p-base layer is arranged at least below the emitter layer. In a power transistor of a lateral structure, a latch-up immunity of a parasitic thyristor can be improved, and a turn-off time can be reduced.

Abstract: According to one embodiment, a semiconductor device comprises a body of a first conductivity type having a source region and a channel, the body being in contact with a top contact layer. The device also comprises a gate arranged adjacent the channel and a drift zone of a second conductivity type arranged between the body and a bottom contact layer. An integrated diode is formed partially by a first zone of the first conductivity type within the body and being in contact with the top contact layer and a second zone of the second conductivity type being in contact with the bottom contact layer. A reduced charge carrier concentration region is formed in the drift zone having a continuously increasing charge carrier lifetime in the vertical direction so that the charge carrier lifetime is lowest near the body and highest near the bottom contact layer.

Abstract: An n+-emitter layer arranged under an emitter electrode is formed of convex portions arranged at predetermined intervals and a main body coupled to the convex portions. A convex portion region is in contact with the emitter electrode, and a p+-layer doped more heavily than a p-base layer is arranged at least below the emitter layer. In a power transistor of a lateral structure, a latch-up immunity of a parasitic thyristor can be improved, and a turn-off time can be reduced.

Abstract: An n+-emitter layer arranged under an emitter electrode is formed of convex portions arranged at predetermined intervals and a main body coupled to the convex portions. A convex portion region is in contact with the emitter electrode, and a p+-layer doped more heavily than a p-base layer is arranged at least below the emitter layer. In a power transistor of a lateral structure, a latch-up immunity of a parasitic thyristor can be improved, and a turn-off time can be reduced.

Abstract: A base layer made of SiGe mixed crystal includes a spacer layer formed in contact with a collector layer with no base impurities diffused therein and an intrinsic base layer formed in contact with an emitter layer with base impurities diffused therein. The spacer layer contains C at a low concentration. The intrinsic base layer has a first region containing C at a low concentration on the collector side and a second region containing C at a high concentration on the emitter side.

Abstract: A semiconductor device includes a semiconductor material, the semiconductor material including a base region and a field stop zone including a first side adjacent the base region and a second side opposite the first side. The field stop zone includes a first dopant implant and a second dopant implant. The first dopant implant has a first dopant concentration maximum and the second dopant implant has a second dopant concentration maximum with the first dopant concentration maximum being less than the second dopant concentration maximum, and being located closer to the second side than the second dopant concentration maximum.

Abstract: A semiconductor diode (30) has an anode (32), a cathode (33) and a semiconductor volume (31) provided between the anode (32) and the cathode (33). An electron mobility and/or hole mobility within a zone (34) of the semiconductor volume (31) that is situated in front of the cathode (33) is reduced relative to the rest of the semiconductor volume (31).

Abstract: Semiconductor devices having recombination centers comprised of well-positioned heavy metals. At least one lattice defect region within the semiconductor device is first created using particle beam implantation. Use of particle beam implantation positions the lattice defect region(s) with high accuracy in the semiconductor device. A heavy metal implantation treatment of the device is applied. The lattice defects created by the particle beam implantation act as gettering sites for the heavy metal implantation. Thus, after the creation of lattice defects and heavy metal diffusion, the heavy metal atoms are concentrated in the well-positioned lattice defect region(s).

Abstract: A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

Abstract: A MOS field effect transistor includes an auxiliary diffusion formed in the drain region where the auxiliary diffusion has a conductivity type opposite to the drain region and is electrically shorted to the drain region. The auxiliary diffusion region forms a parasitic bipolar transistor having the effect of reducing substrate conduction caused by a forward biased drain to body junction.

Abstract: A bipolar transistor of the present invention comprises a collector layer made of an n-type semiconductor and an emitter layer made of an n-type semiconductor provided on this collector layer. A gate layer for injecting p-type carriers (holes) into the emitter layer is provided on the emitter layer. A p-type carrier retaining layer is formed between the collector layer and the emitter layer. The p-type carrier retaining layer temporarily retains the p-type carriers that are injected from the gate layer into the emitter layer and diffused in the emitter layer and reach the p-type carrier retaining layer. The bipolar transistor has a structure whose performance is not influenced by sheet resistance of the base layer, and is able to exhibit a high current gain even in a high-frequency region.

Abstract: One aspect of the present invention relates to a method for forming a strained semiconductor structure. In various embodiments, at least two strong bonding regions are defined for a desired bond between a crystalline semiconductor membrane and a crystalline semiconductor substrate. The two strong bonding regions are separated by a weak bonding region. The membrane is bonded to the substrate at a predetermined misorientation. The membrane is pinned to the substrate in the strong bonding regions. The predetermined misorientation provides the membrane in the weak bonding region with a desired strain. In various embodiments, the membrane is bonded to the substrate at a predetermined twist angle to biaxially strain the membrane in the weak bonding region. In various embodiments, the membrane is bonded to the substrate at a predetermined tilt angle to uniaxially strain the membrane in the weak bonding region. Other aspects are provided herein.

Abstract: A semiconductor device and a method for manufacturing the device using a semiconductor substrate of a high resistance with improved Q value of a passive circuit element. Leakage current due to an impurity fluctuation, in the high resistance semiconductor substrate and noise resistance of an active element in the high resistance semiconductor substrate are improved. The semiconductor device includes a bipolar transistor at a main surface of and in the semiconductor substrate. The bipolar transistor includes a semiconductor layer of a first conductivity type at a bottom portion of the bipolar transistor and the semiconductor device includes a buried layer of a second conductivity type, located in the semiconductor substrate and facing the semiconductor layer of the first conductivity type.

Abstract: A vertical bipolar transistor has a J-FET incorporated in an epitaxial layer. The pinch-off voltage of the J-FET is less than the collector-emitter breakdown voltage of a bipolar transistor without the J-FET.

Abstract: An ESD protection device encompassing a vertical bipolar transistor that is connected as a diode and has an additional displaced base area. The assemblage has a space-saving configuration and a decreased difference between snapback voltage and breakdown voltage.

Abstract: Novel heterojunction bipolar transistors (HBT's) with high current gain and extremely low offset voltage are disclosed. Owing to the insertion of spacer/&dgr;-doped sheet/spacer at base-emitter (B-E) heterojunction in this invention, the potential spike at B-E junction can be eliminated and the confinement effect for holes are enhanced. The potential spike is not observed under large B-E bias, and the offset voltage is still relatively small with small increase. In particular, for the HBT's with large conduction band discontinuity, the method of the invention is more efficient for completely eliminating the potential spike. For the example of InP/GaInAs HBT, a maximum common-emitter current gain of 455 and above 320 at IB=5 &mgr;A, and a low offset voltage less 60 mV are achieved.

Abstract: A phototransistor structure is disclosed. A sidewall is grown on the collector side and under the base. The surface of the sidewall is formed with a sidewall contact. When the contact is connected to an external voltage, the holes accumulated at the junction of the base and emitter can be quickly removed. This solves the problem in the prior art that using a bias between the base and the emitter to remove holes usually results in a large dark current (bias current), power consumption, and diminishing optoelectronic conversion gain.

Abstract: The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the substrate.

Abstract: A DRAM memory unit contains a memory bit (mbit) transistor and a capacitive region for storing charge. The memory is configured to store data as a charge stored by the capacitive region. Each memory unit is accessed by an associated wordline and the data stored by the memory unit is read from an associated bitline connected to the memory unit. The memory units are connected to the associated wordline via a wordline contact and connected to the associated bitline via a bitline contact. The memory units are arranged in memory unit clusters that include multiple memory units having a common bitline contact. The wordline contact is configured to provide for orientation of the wordlines in the memory array independent of the orientation of the bitlines. The wordline contact is also configured to provide for at least one wordline layer separated from the memory unit by a height of the wordline contact.

Abstract: A CMOS image sensor structure for improving the fill factor due to design rule limitations of a conventional image sensor that incorporates a photo diode and three N-type transistors. In a first embodiment, two N-type transistors are changed to P-type transistors and the P-type transistors are formed directly within the N-well of the photo diode. In a second embodiment, the other reset N-type transistor is changed to a reset diode and the reset diode is also formed directly within the N-well of the photo diode. In a third embodiment, the reset diode and the source follower transistor are implemented using a single transistor. In addition, the output selection transistors inside all three types of CMOS image sensor structures may be deleted to increase the fill factor even further.

Abstract: A GaN-based high electron mobility transistor (HEMT) has an undoped GaN layer where a two-dimensional electron gas layer is formed, the undoped GaN layer having a high electric resistivity enabling a pinch-off state to be obtained even when the gate bias voltage is 0 V. The GaN-based HEMT comprises a semi-insulating substrate on which a GaN buffer layer is formed. An undoped GaN layer is disposed on the GaN buffer layer and has an electric resistivity of not less than 1×106 &OHgr;/cm2. An undoped AlGaN layer is disposed on the undoped GaN layer via a heterojunction such that an undercut portion is formed therebetween. An n-type GaN layer is further disposed in such a manner as to bury side portions of the undoped AlGaN layer and the undercut portion. The individual layers thus form a layered structure. A gate electrode G is formed on the undoped AlGaN layer, and a source electrode S and a drain electrode D are formed on the n-type GaN layer.

Abstract: The semiconductor switching element blocks in both directions between a first and a second load terminal. The switching element has a field effect transistor and a bipolar transistor. The field effect transistor has a controlled gate, a source connected to the first load terminal, a drain connected to the second load terminal and a body connection. The bipolar transistor has a base, an emitter, and a collector. The emitter is connected to the body connection of the field effect transistor.

Abstract: A guard ring structure formed around the periphery of a bipolar semiconductor device. A guard region (11) is formed in a substrate (1) of the device so as to extend adjacent a peripheral portion of the device. An insulating layer (3) is formed on the substrate between the peripheral portion of the device and the guard region (11). A polysilicon layer (13) is formed on the insulating layer (3) and covered with a layer of densified dielectic (14). Electrical interconnections are provided between the polysilicon layer (13) and the guard region (11) at spaced apart portions of the device where the guard structure does not need to be protected by the densified dielectric.

Abstract: The present invention relates to a collector pin and a trench in an integrated circuit intended for high speed communication, and to a manufacturing method for these items. The collector pin is achieved by creating an area which is implantation damaged or made amorphous and at least partially doped (139) by means of ion implantation from an upper silicon surface comprised in a semiconductor structure (144) down to a depth lower than the depth of the surrounding field oxide (120), and that the semiconductor structure (144) is then heat treated.

Abstract: A semiconductor layer, through which a main current flows, is so structured that a carrier life time in the semiconductor layer is ununiform in accordance with a predetermined distribution of the carrier life time. Thus, turn OFF characteristics of a semiconductor switching device can be improved without causing any unacceptable disadvantages for other characteristics.

Abstract: A bipolar transistor comprising an external base diffusion layer formed on the outer circumference of an intrinsic base diffusion layer is provided with the high withstand voltage and high reliability. A intrinsic base diffusion layer is formed on the substantially central portion of a semiconductor region surrounded by a separating insulation film on the major surface of a semiconductor substrate. An external base diffusion layer overlapping with the outer circumference of the intrinsic base diffusion layer, surrounding this intrinsic base diffusion layer, and reaching the separating insulation film is formed. Furthermore, common base diffusion layers overlapping with the intrinsic base diffusion layer, and overlapping with at least the inner circumference of the external base diffusion layer are formed. The depth of these common base diffusion layers is made deeper than the depth of the external base diffusion layer, but not exceeding the depth of the intrinsic base diffusion layer.

Abstract: An insulated gate bipolar transistor having a collector electrode 3, an emitter region 6 and a base region 4 formed between the collector electrode and the emitter region, further including a channel stop region 17 spaced from the emitter region and electrically connected to the collector electrode. The base region 4 includes a first region 4c between the emitter region and the channel stop region and a second region between the first region and the collector electrode, the first region having a higher minority-carrier-lifetime than the second region, whereby the first region provides a conductivity modulated conduction path between the emitter region and the channel stop region when the insulated gate bipolar transistor is reverse biased.

Abstract: A voltage variable resistor formed on heterojunction bipolar transistor epitaxial material includes a current channel made on emitter material. Emitter mesas separated by a recess provide the contacts for the voltage variable resistor. Each mesa is topped with emitter metal forming the resistor contacts. The emitter mesas are layered on top of the current channel that is layered atop of a base layer. The voltage variable resistor's control contact is provided by a base contact located on the base layer and separated from the current channel.

Abstract: In a semiconductor switch device such as an NPN transistor (T) or a power switching diode (D), a multiple-zone first region (1) of one conductivity type forms a switchable p-n junction (12) with a second region (2) of opposite conductivity type. In accordance with the invention, this first region (1) includes three distinct zones, namely a low-doped zone (23), a high-doped zone (25), and an intermediate additional zone (24). The low-doped zone (23) is provided by a semiconductor body portion (11) having a substantially uniform p-type doping concentration (P−) and forms the p-n junction (12) with the second region (2). The distinct additional zone (24) is present between the low-doped zone (23) and the high-doped zone (25). The high-doped zone (25) which may form a contact zone has a doping concentration (P++) which is higher than that of the low-doped zone (23) and which decreases towards the low-doped zone (23).

Abstract: A semiconductor device comprising an isolating layer (diffusion layer) having a deep depth which can be produced with improved productivity and a method of the same. The semiconductor device comprises a semiconductor substrate of a first conductivity type; a first diffusion layer of a second conductivity type formed in the semiconductor substrate; a first semiconductor layer formed on the semiconductor substrate; a second diffusion layer of the second conductivity type formed in the first semiconductor layer and connected to the first diffusion layer; and a second semiconductor layer formed on the first semiconductor layer; the second semiconductor layer being electrically isolated from the semiconductor substrate by the first diffusion layer and the second diffusion layer.

Abstract: The invention relates to a semiconductor device including a preferably discrete bipolar transistor with a collector region, a base region, and an emitter region which are provided with connection conductors. A known means of preventing a saturation of the transistor is that the latter is provided with a Schottky clamping diode. The latter is formed in that case in that the connection conductor of the base region is also put into contact with the collector region. In a device according to the invention, the second connection conductor is exclusively connected to the base region, and a partial region of that portion of the base region which lies outside the emitter region, as seen in projection, lying below the second connection conductor is given a smaller flux of dopant atoms. The bipolar transistor in a device according to the invention is provided with a pn clamping diode which is formed between the partial region and the collector region.

Abstract: There is provided a semiconductor device having a novel structure in which high reliability and high field effect mobility can be simultaneously achieved. In an insulated gate transistor formed on a single crystal silicon substrate, pinning regions 105 and 106 are formed at the ends of a channel formation region 102. The pinning regions 105 and 106 suppress the expansion of a depletion layer from the drain side to prevent a short channel effect. In addition, they also serve as a path for extracting minority carriers generated as a result of impact ionization to prevent breakdown phenomena induced by carrier implantation.

Abstract: The boundary between the P type silicon base and N+ buffer layer of an IGBT is intentionally damaged, as by a germanium implant, to create well defined and located damage sites for reducing lifetime in the silicon.

Abstract: In one aspect, the invention pertains to a method of forming a gettering region within an Si semiconductor wafer, the method including: a) providing a semiconductor material wafer; b) providing a background region within the semiconductor material wafer, the background region being doped with a first-type conductivity enhancing dopant, the first-type conductivity enhancing dopant being either n-type or p-type; c) implanting a second-type conductivity enhancing dopant into the background region to form a second-type implant region entirely contained within the background region, the second-type conductivity enhancing dopant being of an opposite type than the first-type conductivity enhancing dopant of the background region; and d) implanting a neutral-conductivity-type conductivity enhancing dopant into the second-type implant region to form a metals gettering damage region entirely contained within the second-type implant region. The invention also pertains to gettering region structures.

Abstract: A semiconductor device having two or more p-n junctions, being in particular a bipolar transistor or a thyristor. The device has an gold ion implant in a region of the device between two of or the two p-n junctions, which region is the base in the case of a bipolar transistor, located away from the current carrying active region of the device. The device has a low resistance and may be turned off rapidly because the implanted gold provides recombination centers which act as a sink for carriers drawing them from the active region.

Abstract: Semiconductor structure for a transistor, having at least one doped crystalline semiconductor layer (3) consisting of a semiconductor material such as silicon or germanium which is applied onto a further crystalline layer, wherein the doped semiconductor layer (3) contains carbon alloyed with this semiconductor material to improve the conduction characteristics, and wherein a desired strain can be set in the active semiconductor layer (3) via the proportion of carbon relation to the semiconductor material.

Abstract: A bipolar silicon transistor includes at least one emitter zone with n.sup.+ arsenic doping and with a phosphorus doping. The ratio between arsenic dopant concentration and phosphorus dopant concentration is between 10:1 and 500:1 in the at least one emitter zone. The at least one emitter zone may also have a penetration depth of less than 0.5 .mu.m. A method for producing a bipolar silicon transistor includes implanting a n.sup.+ -doped emitter zone with arsenic, implanting the n.sup.+ -doped emitter zone with phosphorus, setting a ratio in the n.sup.+ -doped emitter zone between the arsenic dopant concentration and phosphorus dopant concentration to between 10:1 and 500:1, and annealing crystal defects.

Abstract: Silicon is formed at selected locations on a silicon-on-insulator (SOI) substrate during fabrication of selected electronic components, including resistors, capacitors, and diodes. The silicon location is defined using a patterned, removable mask, and the silicon may be applied by deposition or growth and may take the form of polysilicon or crystalline silicon. Electrostatic discharge (ESD) characteristics of the SOI device is significantly improved by having a thick double layer of silicon in selected regions.

Abstract: The present invention induces provides a gettering trench on the front surface of a device substrate. In one embodiment it induces stress and simultaneously forms a gettering zone 40 for gettering impurities in an integrated circuit structure. In another embodiment, the trench is filled with gettering material 72 such as polysilicon. The two gettering mechanisms may be combined 82,84. The invention is useful for providing gettering in bonded wafers and in silicon-on-insulator devices (FIGS. 4,5).

Abstract: A semiconductor device improves its electrical characteristics by reducing crystal defects in the vicinity of junction interfaces between a semiconductor layer, and a metal compound layer composed of semiconductor and metal elements, and between an epitaxial layer and its forming substrate. A pair of source/drain layers (52) are separately formed in a surface of a well layer (50), and a metal silicide layer (8) is formed thereon. A nitrogen inclusion region (9) is formed in the vicinity of a junction interface between the source/drain layers (52) and the metal silicide layer (8).

Abstract: A method and apparatus for the localized reduction of the lifetime of charge carriers in integrated electronic devices. The method comprises the step of implanting ions, at a high dosage and at a high energy level, of a noble gas, preferably helium, in the active regions of the integrated device so that the ions form bubbles in the active regions. A further thermal treatment is performed after the formation of bubbles of the noble gas in order to improve the structure of the bubbles and to make the noble gas evaporate, leaving cavities in the active regions.

Abstract: It is an object to provide a semiconductor apparatus having both fast switching characteristics and high dielectric breakdown strength or small leakage current characteristics, as well as a process for fabricating such improved semiconductor apparatus. The apparatus comprises a semiconductor substrate; a semiconductor layer on said semiconductor substrate, said semiconductor layer having a pn junction formed along the surface of said semiconductor substrate, wherein crystal defects being formed by irradiation with particle rays to the only vertical direction of said pn junction; and a silicon nitride film provided on the substrate surface of said layer for restraining the exposure to particle rays being provided on the substrate surface of said element in the areas other than said pn junction.

Abstract: A semiconductor device having a dielectric isolation (DI) structure using an SOI substrate or the like. An active region as a main current path of the semiconductor device is sandwiched between DI grooves having a side wall substantially vertical to the main surface of the substrate, and the width W of the main current path between the DI grooves is set to 5 .mu.m or narrower to reduce excessive carriers. The reverse recovery charge Q.sub.rr prolonging the turn-off time can be shortened, which enables high speed switching.