With Groove To Define Plural Diodes Patents (Class 257/594)
  • Patent number: 9793262
    Abstract: A method includes forming a first plurality of fins having a first width in a first region of a semiconductor substrate. A second plurality of fins having a second width greater than the first width is formed in a second region of a semiconductor substrate. A doped region is formed in a surface portion of the second plurality of fins to define an anode region of a diode. A junction is defined between the doped region and a cathode region of the second plurality of fins. A first contact interfacing with the anode region is formed.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: October 17, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kasun Anupama Punchihewa, Jagar Singh
  • Patent number: 9768350
    Abstract: An optoelectronic device includes at least first and second light-emitting nanowires on a support, each comprising an area for the injection of holes and an area for the injection of electrons, a series electric connection including a connection nanowire on the support, which includes a first region forming an electric path with the hole injection area of the first nanowire, a second region forming an electric path with the electron injection area of the second nanowire, and a third region enabling a current to flow between first and second regions. Also included are a first conductive area connecting the hole injection area of the first nanowire and the first region of the connection nanowire and electrically insulated from the second nanowire, and a second conductive area connecting the second region of the connection nanowire and electron injection area of the second nanowire and electrically insulated from the first nanowire.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: September 19, 2017
    Assignee: Commissariat A L'Energie Atomique Et Aux Energies Alternatives
    Inventors: Anne-Laure Bavencove, Philippe Gilet, Pierre Moller
  • Patent number: 9496435
    Abstract: Techniques for enhancing the absorption of photons in semiconductors with the use of microstructures arc described. The microstructures, such as pillars and/or holes, effectively increase the effective absorption length resulting in a greater absorption of the photons. Using microstructures for absorption enhancement for silicon photodiodes and silicon avalanche photodiodes can result in bandwidths in excess of 10 Gb/s at photons with wavelengths of 850 nm, and with quantum efficiencies of approximately 90% or more.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: November 15, 2016
    Assignee: W&Wsens Devices, Inc.
    Inventors: Shih-Yuan Wang, Shih-Ping Wang
  • Patent number: 9472714
    Abstract: Provided is a method of fabricating a light-emitting diode (LED) device. A wafer is provided. The wafer has a sapphire substrate and a semiconductor layer formed on the sapphire substrate. The semiconductor layer contains a plurality of un-separated LED dies. A photo-sensitive layer is formed over the semiconductor layer. A photolithography process is performed to pattern the photo-sensitive layer into a plurality of patterned portions. The patterned portions are separated by a plurality of openings that are each substantially aligned with one of the LED dies. A metal material is formed in each of the openings. The wafer is radiated in a localized manner such that only portions of the wafer that are substantially aligned with the openings are radiated. The sapphire substrate is removed along with un-radiated portions of the semiconductor layer, thereby separating the plurality of LED dies into individual LED dies.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: October 18, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Hsing-Kuo Hsia, Chih-Kuang Yu, Gordon Kuo
  • Patent number: 9337197
    Abstract: In one aspect there is set forth herein a semiconductor structure having fins extending upwardly from an ultrathin body (UTB). In one embodiment a multilayer structure can be disposed on a wafer and can be used to pattern voids extending from a UTB layer of the wafer. Selected material can be formed in the voids to define fins extending upward from the UTB layer. In one embodiment silicon (Si) can be grown within the voids to define the fins. In one embodiment, germanium based material can be grown within the voids to define the fins.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: May 10, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Bingwu Liu
  • Patent number: 9005736
    Abstract: An electronic component manufacturing method that efficiently grinds a cover layer provided on a substrate even when the substrate is warped includes the step of forming first grooves at intervals in a cover layer provided on a substrate by repeating grinding with a rotary blade at a pitch more than a thickness W of the rotary blade. Next, at least portions provided in the cover layer along the first grooves are removed to reduce the thickness of the cover layer by repeating grinding at a pitch equal to or less than the thickness W of the rotary blade.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: April 14, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Hidemasa Kawai
  • Patent number: 8946038
    Abstract: A method of forming one or more diodes in a fin field-effect transistor (FinFET) device includes forming a hardmask layer having a fin pattern, said fin pattern including an isolated fin area, a fin array area, and a FinFET area. The method further includes etching a plurality of fins into a semiconductor substrate using the fin pattern, and depositing a dielectric material over the semiconductor substrate to fill spaces between the plurality of fins. The method further includes planarizing the semiconductor substrate to expose the hardmask layer. The method further includes implanting a p-type dopant into the fin array area and portions of the FinFET area, and implanting an n-type dopant into the isolated fin area, a portion of the of fin array area surrounding the p-well and portions of the FinFET area. The method further includes annealing the semiconductor substrate.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hsin Hu, Sun-Jay Chang, Jaw-Juinn Horng, Chung-Hui Chen
  • Patent number: 8912033
    Abstract: Provided is a method of fabricating a light-emitting diode (LED) device. The method includes providing a substrate having opposite first and second sides. A semiconductor layer is formed on the first side of the substrate. The method includes forming a photoresist layer over the semiconductor layer. The method includes patterning the photoresist layer into a plurality of photoresist components. The photoresist components are separated by openings. The method includes filling the openings with a plurality of thermally conductive components. The method includes separating the semiconductor layer into a plurality of dies using a radiation process that is performed to the substrate from the second side. Each of the first regions of the substrate is aligned with one of the conductive components.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: December 16, 2014
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Hsing-Kuo Hsia, Chih-Kuang Yu, Gordon Kuo
  • Patent number: 8907414
    Abstract: Aspects of the present disclosure describe high voltage fast recovery trench diodes and methods for make the same. The device may have trenches that extend at least through a top P-layer and an N-barrier layer. A conductive material may be disposed in the trenches with a dielectric material lining the trenches between the conductive material and sidewalls of the trenches. A highly doped P-pocket may be formed in an upper portion of the top P-layer between the trenches. A floating N-pocket may be formed directly underneath the P-pocket. The floating N-pocket may be as wide as or wider than the P-pocket. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: December 9, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Jun Hu, Karthik Padmanabhan, Madhur Bobde, Hamza Yilmaz
  • Patent number: 8883565
    Abstract: In accordance with an embodiment of the present invention, a semiconductor device is manufactured by arranging a plurality of semiconductor devices on a frame with an adhesive foil. The plurality of semiconductor devices is attached to the adhesive foil. The plurality of semiconductor devices is removed from the frame with the adhesive foil using a carbon dioxide snow jet and/or a laser process.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: November 11, 2014
    Assignee: Infineon Technologies AG
    Inventors: Mathias Vaupel, Sebastian Bernrieder, Adolf Koller, Stefan Martens
  • Patent number: 8847360
    Abstract: An electrostatic discharge (ESD) protection device is fabricated in a vertical space between active layers of stacked semiconductor dies thereby utilizing space that would otherwise be used only for communication purposes. The vertical surface area of the through silicon vias (TSVs) is used for absorbing large voltages resulting from ESD events. In one embodiment, an ESD diode is created in a vertical TSV between active layers of the semiconductor dies of a stacked device. This ESD diode can be shared by circuitry on both semiconductor dies of the stack thereby saving space and reducing die area required by ESD protection circuitry.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: September 30, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Kenneth Kaskoun, Shiqun Gu, Matthew Nowak
  • Patent number: 8759935
    Abstract: A power semiconductor device includes an active device region disposed in a semiconductor substrate, an edge termination region disposed in the semiconductor substrate between the active device region and a lateral edge of the semiconductor substrate and a trench disposed in the edge termination region which extends from a first surface of the semiconductor substrate toward a second opposing surface of the semiconductor substrate. The trench has an inner sidewall, an outer sidewall and a bottom. The inner sidewall is spaced further from the lateral edge of the semiconductor substrate than the outer sidewall, and an upper portion of the outer sidewall is doped opposite as the inner sidewall and bottom of the trench to increase the blocking voltage capacity. Other structures can be provided which yield a high blocking voltage capacity such as a second trench or a region of chalcogen dopant atoms disposed in the edge termination region.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: June 24, 2014
    Assignee: Infineon Technologies Austria AG
    Inventor: Gerhard Schmidt
  • Patent number: 8759888
    Abstract: A Schottky diode includes an n+-substrate, an n-epilayer, trenches introduced into the n-epilayer, floating Schottky contacts being located on their side walls and on the entire trench bottom, mesa regions between the adjacent trenches, a metal layer on its back face, this metal layer being used as a cathode electrode, and an anode electrode on the front face of the Schottky diode having two metal layers, the first metal layer of which forms a Schottky contact and the second metal layer of which is situated below the first metal layer and also forms a Schottky contact. Preferably, these two Schottky contacts have different barrier heights.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: June 24, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Ning Qu, Alfred Goerlach
  • Patent number: 8735228
    Abstract: A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: May 27, 2014
    Assignee: PFC Device Corp.
    Inventors: Mei-Ling Chen, Hung-Hsin Kuo, Kuo-Liang Chao
  • Patent number: 8729605
    Abstract: Provided is a semiconductor device in which on-resistance is largely reduced. In a region (2a) of an N type epitaxial layer (2) of the semiconductor device 20, each region between neighboring trenches (3) is blocked with a depletion layer (14) formed around a trench (3) so that a current passage (12) is interrupted, while a part of the depletion layer (14) formed around the trench (3) is deleted so that the current passage (12) is opened. In a region (2b), a junction portion (8) between the N type epitaxial layer (2) and a P+ type diffusion region (7) makes a Zener diode (8).
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: May 20, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Masaru Takaishi
  • Patent number: 8710585
    Abstract: Aspects of the present disclosure describe high voltage fast recovery trench diodes and methods for make the same. The device may have trenches that extend at least through a top P-layer and an N-barrier layer. A conductive material may be disposed in the trenches with a dielectric material lining the trenches between the conductive material and sidewalls of the trenches. A highly doped P-pocket may be formed in an upper portion of the top P-layer between the trenches. A floating N-pocket may be formed directly underneath the P-pocket. The floating N-pocket may be as wide as or wider than the P-pocket. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: April 29, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Jun Hu, Karthik Padmanabhan, Madhur Bobde, Hamza Yilmaz
  • Patent number: 8664687
    Abstract: Provided are a nitride semiconductor light-emitting device comprising a polycrystalline or amorphous substrate made of AlN; a plurality of dielectric patterns formed on the AlN substrate and having a stripe or lattice structure; a lateral epitaxially overgrown-nitride semiconductor layer formed on the AlN substrate having the dielectric patterns by Lateral Epitaxial Overgrowth; a first conductive nitride semiconductor layer formed on the nitride semiconductor layer; an active layer formed on the first conductive nitride semiconductor layer; and a second conductive nitride semiconductor layer formed on the active layer; and a process for producing the same.
    Type: Grant
    Filed: July 26, 2004
    Date of Patent: March 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Hyun Cho, Masayoshi Koike, Yuiji Imai, Min Ho Kim, Bang Won Oh, Hun Joo Hahm
  • Patent number: 8643085
    Abstract: A high-voltage-resistant semiconductor component (1) has vertically conductive semiconductor areas (17) and a trench structure (5). These vertically conductive semiconductor areas are formed from semiconductor body areas (10) of a first conductivity type and are surrounded by a trench structure (5) on the upper face (6) of the semiconductor component. For this purpose the trench structure has a base (7) and a wall area (8) and is filled with a material (9) with a relatively high dielectric constant (?r). The base area (7) of the trench structure (5) is provided with a heavily doped semiconductor material (11) of the same conductivity type as the lightly doped semiconductor body areas (17), and/or having a metallically conductive material (12).
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: February 4, 2014
    Assignee: Infineon Technologies AG
    Inventor: Frank Pfirsch
  • Patent number: 8610241
    Abstract: Diodes and bipolar junction transistors (BJTs) are formed in IC devices that include fin field-effect transistors (FinFETs) by utilizing various process steps in the FinFET formation process. The diode or BJT includes an isolated fin area and fin array area having n-wells having different depths and a p-well in a portion of the fin array area that surrounds the n-well in the isolated fin area. The n-wells and p-well for the diodes and BJTs are implanted together with the FinFET n-wells and p-wells.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: December 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hsin Hu, Sun-Jay Chang, Jaw-Juinn Horng, Chung-Hui Chen
  • Patent number: 8471337
    Abstract: An integrated circuit is disclosed having a semiconductor component comprising a first p-type region and a first n-type region adjoining the first p-type region, which together form a first pn junction having a breakdown voltage. A further n-type region adjoining the first p-type region or a further p-type region adjoining the first n-type region is provided, the first p-type or n-type region and the further n-type or p-type region adjoining the latter together forming a further pn junction having a further breakdown voltage, the first pn junction and the further pn junction being connected or connectable to one another in such a way that, in the case of an overloading of the semiconductor component, on account of a current loading of the first pn junction, first of all the further pn junction breaks down.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: June 25, 2013
    Assignee: Infineon Technologies AG
    Inventors: Nils Jensen, Marie Denison
  • Patent number: 8373255
    Abstract: A diode comprises a P-type well formed in a semiconductor substrate, at least one N-type impurity doping area formed in the P-type well, an isolation area formed to surround the N-type impurity doping area, a P-type impurity doping area formed to surround the isolation area, first contacts formed in the N-type impurity doping area in a single row or a plurality of rows, and second contacts formed in the P-type impurity doping area in a single row or a plurality of rows, wherein pin resistance can be adjusted through changing any one of a distance between the N-type impurity doping area and the P-type impurity doping area, a contact pitch between the first contacts, and a contact pitch between the second contacts.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: February 12, 2013
    Assignee: SK Hynix Inc.
    Inventor: Kook Whee Kwak
  • Patent number: 8368178
    Abstract: A phase change memory apparatus is provided that includes a first electrode that is longer than it is wide, the first electrode having a trench formed on an active region of a semiconductor substrate, a second electrode formed in a bottom portion of the trench, and a bottom electrode contact formed on the second electrode.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: February 5, 2013
    Assignee: SK Hynix Inc.
    Inventor: Jang Uk Lee
  • Patent number: 8299486
    Abstract: A semiconductor light emitting device including a substrate, an electrode and a light emitting region is provided. The substrate may have protruding portions formed in a repeating pattern on substantially an entire surface of the substrate while the rest of the surface may be substantially flat. The cross sections of the protruding portions taken along planes orthogonal to the surface of the substrate may be semi-circular in shape. The cross sections of the protruding portions may in alternative be convex in shape. A buffer layer and a GaN layer may be formed on the substrate.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: October 30, 2012
    Assignee: Nichia Corporation
    Inventors: Isamu Niki, Motokazu Yamada, Masahiko Sano, Shuji Shioji
  • Patent number: 8283709
    Abstract: A semiconductor device is disclosed which includes a silicide substrate, a nitride layer, two STIs, and a strain nitride. The silicide substrate has two doping areas. The nitride layer is deposited on the silicide substrate. The silicide substrate and the nitride layer have a recess running through. The two doping areas are at two sides of the recess. The end of the recess has an etching space bigger than the recess. The top of the silicide substrate has a fin-shaped structure. The two STIs are at the two opposite sides of the silicide substrate (recess). The strain nitride is spacer-formed in the recess and attached to the side wall of the silicide substrate, nitride layer, two STIs. The two doping areas cover the strain nitride. As a result, the efficiency of semiconductor is improved, and the drive current is increased.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: October 9, 2012
    Assignee: Inotera Memories, Inc.
    Inventors: Tzung Han Lee, Chung-Lin Huang, Hsien-Wen Liu
  • Patent number: 8253223
    Abstract: A diode comprises a P-type well formed in a semiconductor substrate, at least one N-type impurity doping area formed in the P-type well, an isolation area formed to surround the N-type impurity doping area, a P-type impurity doping area formed to surround the isolation area, first contacts formed in the N-type impurity doping area in a single row or a plurality of rows, and second contacts formed in the P-type impurity doping area in a single row or a plurality of rows, wherein pin resistance can be adjusted through changing any one of a distance between the N-type impurity doping area and the P-type impurity doping area, a contact pitch between the first contacts, and a contact pitch between the second contacts.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: August 28, 2012
    Assignee: SK hynix Inc.
    Inventor: Kook Whee Kwak
  • Patent number: 8217495
    Abstract: A high-frequency metal-insulator-metal (MIM) type diode is constructed as a bridge suspended above a substrate to significantly reduce parasitic capacitances affecting the operation frequency of the diode thereby permitting improved high-frequency rectification, demodulation, or the like.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: July 10, 2012
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Robert H. Blick, Chulki Kim, Jonghoo Park
  • Patent number: 8217419
    Abstract: Provided is a semiconductor device in which on-resistance is largely reduced. In a region (2a) of an N type epitaxial layer (2) of the semiconductor device 20, each region between neighboring trenches (3) is blocked with a depletion layer (14) formed around a trench (3) so that a current passage (12) is interrupted, while a part of the depletion layer (14) formed around the trench (3) is deleted so that the current passage (12) is opened. In a region (2b), a junction portion (8) between the N type epitaxial layer (2) and a P+ type diffusion region (7) makes a Zener diode (8).
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: July 10, 2012
    Assignee: Rohm Co., Ltd.
    Inventor: Masaru Takaishi
  • Patent number: 8193610
    Abstract: A semiconductor wafer contains a plurality of semiconductor die with bumps formed over contact pads on an active surface of the semiconductor die. A b-stage conductive polymer is deposited over the contact pads on the semiconductor wafer. The semiconductor wafer is singulated to separate the die. An insulating layer is formed over a carrier with openings formed in the insulating layer. The die is mounted to the carrier with the conductive polymer disposed in the openings of the insulating layer. The conductive polymer is heated to a glass transition temperature to liquefy the conductive polymer to an electrically conductive state. An encapsulant is deposited over the die and insulating layer. The carrier is removed to expose the conductive polymer. An interconnect structure is formed over the die, encapsulant, and conductive polymer. The interconnect structure is electrically connected through the conductive polymer to the contact pads on the die.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: June 5, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Byung Tai Do, Reza A. Pagaila
  • Patent number: 8193015
    Abstract: A method for forming a light-emitting-diode (LED) array is disclosed includes forming an LED structure on a substrate. The LED structure is divided into at least a first LED device and a second LED device with a gap between the first LED device and the second LED device. At least one polymer material is deposited over the LED structure to substantially fill the gap with the at least one polymer material. Portions of the at least one polymer material are removed to expose a first electrode of the first LED device and a second electrode of the second LED device. An interconnect is formed on top of the at least one polymer material electrically connecting the first and second electrode.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: June 5, 2012
    Assignee: Pinecone Energies, Inc.
    Inventors: Ray-Hua Horng, Yi-An Lu, Heng Liu
  • Patent number: 8148744
    Abstract: A semiconductor light emitting device including a substrate, an electrode and a light emitting region is provided. The substrate may have protruding portions formed in a repeating pattern on substantially an entire surface of the substrate while the rest of the surface may be substantially flat. The cross sections of the protruding portions taken along planes orthogonal to the surface of the substrate may be semi-circular in shape. The cross sections of the protruding portions may in alternative be convex in shape. A buffer layer and a GaN layer may be formed on the substrate.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: April 3, 2012
    Assignee: Nichia Corporation
    Inventors: Isamu Niki, Motokazu Yamada, Masahiko Sano, Shuji Shioji
  • Patent number: 8134174
    Abstract: A light-emitting diode and a method for manufacturing the same are described. The light-emitting diode includes a bonding substrate, a first conductivity type electrode, a bonding layer, an epitaxial structure, a second conductivity type electrode, a growth substrate and an encapsulant layer. The first conductivity type electrode and the bonding layer are respectively disposed on two surfaces of the bonding substrate. The epitaxial structure includes a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer. A trench is set around the epitaxial structure and extends from the second conductivity type semiconductor layer to the first conductivity type semiconductor layer. The second conductivity type electrode is electrically connected to the second conductivity type semiconductor layer. The growth substrate is disposed on the epitaxial structure and includes a cavity exposing the epitaxial structure and the trench.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: March 13, 2012
    Assignee: Chi Mei Lighting Technology Group.
    Inventors: Kuohui Yu, Chienchun Wang, Changhsin Chu, Menghsin Li
  • Publication number: 20120012973
    Abstract: A lateral transient voltage suppressor with ultra low capacitance is disclosed. The suppressor comprises a first type substrate and at least one diode cascade structure arranged in the first type substrate. The cascade structure further comprises at least one second type lightly doped well and at least one first type lightly doped well, wherein there are two heavily doped areas arranged in the second type lightly doped well and the first type lightly doped well. The cascade structure neighbors a second type well, wherein there are three heavily doped areas arranged in the second type well. The suppressor further comprises a plurality of deep isolation trenches arranged in the first type substrate and having a depth greater than depths of the second type lightly doped well, the second type well and the first type lightly doped well. Each doped well is isolated by trenches.
    Type: Application
    Filed: July 15, 2010
    Publication date: January 19, 2012
    Inventors: Che-Hao Chuang, Kun-Hsien Lin, Ryan Hsin-Chin Jiang
  • Patent number: 8089095
    Abstract: In one embodiment, a two terminal multi-channel ESD device is configured to include a zener diode and a plurality of P-N diodes. In another embodiment, the ESD devices has an asymmetrical characteristic.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: January 3, 2012
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Ali Salih, Mingjiao Liu
  • Patent number: 8080862
    Abstract: An electrostatic discharge (ESD) protection device is fabricated in a vertical space between active layers of stacked semiconductor dies thereby utilizing space that would otherwise be used only for communication purposes. The vertical surface area of the through silicon vias (TSVs) is used for absorbing large voltages resulting from ESD events. In one embodiment, an ESD diode is created in a vertical TSV between active layers of the semiconductor dies of a stacked device. This ESD diode can be shared by circuitry on both semiconductor dies of the stack thereby saving space and reducing die area required by ESD protection circuitry.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: December 20, 2011
    Assignee: QUALCOMM Incorporate
    Inventors: Kenneth Kaskoun, Shiqun Gu, Matthew Nowak
  • Publication number: 20110304020
    Abstract: A wafer level vertical diode package structure includes a first semiconductor layer, a second semiconductor layer, an insulative unit, a first conductive structure, and a second conductive structure. The second semiconductor layer is connected with one surface of the first semiconductor layer. The insulative unit is disposed around a lateral side of the first semiconductor layer and a lateral side of the second semiconductor layer. The first conductive structure is formed on a top surface of the first semiconductor layer and on one lateral side of the insulative layer. The second conductive structure is formed on a top surface of the second semiconductor layer and on another opposite lateral side of the insulative layer.
    Type: Application
    Filed: August 25, 2011
    Publication date: December 15, 2011
    Applicant: HARVATEK CORPORATION
    Inventors: BILY WANG, SUNG-YI HSIAO, JACK CHEN
  • Patent number: 8071482
    Abstract: A manufacturing method for a silicon carbide semiconductor device is disclosed. It includes an etching method in which an Al film and Ni film are laid on an SiC wafer in this order and wet-etched, whereby a two-layer etching mask is formed in which Ni film portions overhang Al film portions. Mesa grooves are formed by dry etching by using this etching mask.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: December 6, 2011
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Yasuyuki Kawada
  • Patent number: 8072013
    Abstract: Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: December 6, 2011
    Assignee: Vishay-Siliconix
    Inventors: Qufei Chen, Robert Xu, Kyle Terrill, Deva Pattanayak
  • Patent number: 8034716
    Abstract: Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer may be formed over the interior surface of the diode opening and contacting the active region. The diode opening may initially be filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that may be heavily doped with a first type dopant and a bottom portion that may be lightly doped with a second type dopant. The top portion may be bounded by the bottom portion so as not to contact the titanium silicide layer. In one embodiment of the vertical diode structure, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: October 11, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung T. Doan, Raymond A. Turi, Graham R. Wolstenholme
  • Patent number: 7989306
    Abstract: Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: August 2, 2011
    Assignee: International Business Machines Corporation
    Inventors: Xuefeng Liu, Robert M. Rassel, Steven H. Voldman
  • Patent number: 7989921
    Abstract: An SOI device comprises an isolation trench defining a vertical drift zone, a buried insulating layer to which the isolation trench extends, and an electrode region for emitting charge carriers that is formed adjacent to the insulating layer and that is in contact with the drift zone. The electrode region comprises first strip-shaped portions having a first type of doping and second strip-shaped portions having a second type of doping that is inverse to the first type of doping. A first sidewall doping of the first type of doping is provided at a first sidewall of the isolation trench and a second sidewall doping of the second type of doping is provided at a second sidewall of the isolation trench. The first strip-shaped portions are in contact with the first sidewall doping and the second strip-shaped portions are in contact with the second sidewall doping.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: August 2, 2011
    Assignee: X-Fab Semiconductor Foundries AG
    Inventor: Ralf Lerner
  • Patent number: 7964892
    Abstract: A light emitting device, comprises: a first semiconductor light emitting element; a second semiconductor light emitting element; a first metal member mounting on its top face the first semiconductor light emitting element; a second metal member mounting on its top face the second semiconductor light emitting element; and a resin package having on its top face a window through which light is taken off from the first semiconductor light emitting element and the second semiconductor light emitting element, wherein the second metal member is thinner around its peripheral edge than in its middle, and the rear face of the first metal member is facing the top face of the peripheral edge.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: June 21, 2011
    Assignee: Nichia Corporation
    Inventor: Naofumi Sumitani
  • Patent number: 7960198
    Abstract: A wide bandgap semiconductor device with surge current protection and a method of making the device are described. The device comprises a low doped n-type region formed by plasma etching through the first epitaxial layer grown on a heavily doped n-type substrate and a plurality of heavily doped p-type regions formed by plasma etching through the second epitaxial layer grown on the first epitaxial layer. Ohmic contacts are formed on p-type regions and on the backside of the n-type substrate. Schottky contacts are formed on the top surface of the n-type region. At normal operating conditions, the current in the device flows through the Schottky contacts. The device, however, is capable of withstanding extremely high current densities due to conductivity modulation caused by minority carrier injection from p-type regions.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: June 14, 2011
    Assignee: Semisouth Laboratories
    Inventors: Igor Sankin, Joseph Neil Merrett
  • Patent number: 7868388
    Abstract: In some aspects, a memory circuit is provided that includes (1) a two-terminal memory element formed on a substrate; and (2) a CMOS transistor formed on the substrate and adapted to program the two-terminal memory element. The two-terminal memory element is formed between a gate layer and a first metal layer of the memory circuit. Numerous other aspects are provided.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: January 11, 2011
    Assignee: SanDisk 3D LLC
    Inventor: Christopher J. Petti
  • Patent number: 7838892
    Abstract: An optoelectronic semiconductor chip, comprising a plurality of semiconductor function regions (10) arranged on a common carrier layer (1, 7), at least one of the semiconductor function regions being a defect region (12), and a contact structure (18) for making electrical contact with the optoelectronic semiconductor chip. The contact structure is electrically conductively connected to at least one of the semiconductor function regions, and the contact structure is adapted to be electrically separated, or it is electrically separated, from the defect region.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: November 23, 2010
    Assignee: Osram Opto Semiconductors GmbH
    Inventor: Ralph Wirth
  • Patent number: 7830940
    Abstract: A nitride semiconductor laser element comprises a nitride semiconductor substrate and a nitride semiconductor layer laminated thereon, wherein the nitride semiconductor substrate has a high dislocation density region and a low dislocation density region containing lower dislocation than that of the high dislocation density region, and has at least one recess formed in at least the high dislocation density region, the nitride semiconductor layer has a first nitride semiconductor layer in which the grown film thickness in the lateral direction from the side faces of the recess in the substrate is greater than the grown film thickness in the heightwise direction from a region other than the recess, and a second nitride semiconductor layer that is disposed on the first nitride semiconductor layer and contains indium, and the first nitride semiconductor layer and second nitride semiconductor layer have recess over the recess in the nitride semiconductor substrate.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: November 9, 2010
    Assignee: Nichia Corporation
    Inventors: Shingo Masui, Tomonori Morizumi
  • Patent number: 7821099
    Abstract: A diode having a capacitance below 0.1 pF and a breakdown voltage of at least 500V. The diode has an anode of a first conductivity type and a cathode of a second conductivity type disposed below the anode. At least one of the cathode and anode have multiple, vertically abutting diffusion regions. The cathode and anode are disposed between and bounded by adjacent isolation regions.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: October 26, 2010
    Assignee: International Business Machines Corporation
    Inventor: Steven H. Voldman
  • Patent number: 7812367
    Abstract: In one embodiment, a two terminal multi-channel ESD device is configured to include a zener diode and a plurality of P-N diodes.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: October 12, 2010
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Ali Salih, Mingjiao Liu, Thomas Keena
  • Patent number: 7807484
    Abstract: A light-emitting diode (LED) device is disclosed. The LED device includes a semiconductor substrate with a light-emitting diode chip disposed thereon. At least two isolated outer wiring layers are disposed on the bottom surface of the semiconductor substrate and are electrically connected to the light-emitting diode chip, serving as input terminals. A lens module is adhered to the top surface of the semiconductor substrate to cap the light-emitting diode chip. In one embodiment, the lens module comprises a glass substrate having a first cavity formed at a first surface thereof, a fluorescent layer formed over a portion of a first surface exposed by the first cavity, facing the light-emitting diode chip, and a molded lens formed over a second surface of the glass carrier opposing to the first surface.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: October 5, 2010
    Assignee: VisEra Technologies Company Limited
    Inventors: Wei-Ko Wang, Tzu-Han Lin
  • Patent number: 7804101
    Abstract: A semiconductor light emitting device including a substrate, an electrode and a light emitting region is provided. The substrate may have protruding portions formed in a repeating pattern on substantially an entire surface of the substrate while the rest of the surface may be substantially flat. The cross sections of the protruding portions taken along planes orthogonal to the surface of the substrate may be semi-circular in shape. The cross sections of the protruding portions may in alternative be convex in shape. A buffer layer and a GaN layer may be formed on the substrate.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: September 28, 2010
    Assignee: Nichia Corporation
    Inventors: Isamu Niki, Motokazu Yamada, Masahiko Sano, Shuji Shioji
  • Patent number: 7786545
    Abstract: Disclosed are an image sensor and a method for manufacturing the same. The image sensor includes a substrate provided with a transistor circuit, first and second interconnections separated from each other on the substrate, a first conductive-type conductive layer formed at side surfaces of the first interconnection, a second conductive-type conductive layer formed at side surfaces of the second interconnection, and an intrinsic layer formed between the first and second conductive-type conductive layers thereby forming a P-I-N structure.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: August 31, 2010
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Seoung Hyun Kim