Abstract: Certain aspects of the present disclosure provide a semiconductor variable capacitor based on a buried oxide process. The semiconductor variable capacitor generally includes a first conductive pad coupled to a first non-insulative region and a second conductive pad coupled to a second non-insulative region. The second non-insulative region may be coupled to a semiconductor region. The capacitor may also include a first control region coupled to the first semiconductor region such that a capacitance between the first conductive pad and the second conductive pad is configured to be adjusted by varying a control voltage applied to the first control region. The capacitor also includes an insulator region disposed below the semiconductor region, wherein at least a portion of the first non-insulative region is separated from the second non-insulative region by the insulator region such that the first conductive pad is electrically isolated from the second conductive pad.

Abstract: An electronic device can include a substrate, lower and upper semiconductor layers over the substrate, and a doped region at the interface between the lower and upper semiconductor layers. The doped region can have a conductivity type opposite that of a dopant within the lower semiconductor layer. Within the lower semiconductor layer, the dopant can have a dopant concentration profile that has a relatively steeper portion adjacent to the substrate, another relatively steeper portion adjacent to an interface between the first and second semiconductor layers, and a relatively flatter portion between the relative steeper portions. A diode lies at a pn junction where a second dopant concentration profile of the first doped region intersects the relatively flatter portion of the first dopant concentration profile. The electronic device can be formed using different processes described herein.

Abstract: A novel semiconductor variable capacitor is presented. The semiconductor structure is simple and is based on a semiconductor variable MOS capacitor structure suitable for integrated circuits, which has at least three terminals, one of which is used to modulate the equivalent capacitor area of the MOS structure by increasing or decreasing its DC voltage with respect to another terminal of the device, in order to change the capacitance over a wide ranges of values. Furthermore, the present invention decouples the AC signal and the DC control voltage minimizing the distortion and increasing the performance of the device, such as its control characteristic. The present invention is simple and only slightly dependent on the variations due to the fabrication process. It exhibits a high value of capacitance density and, if opportunely implemented, shows a quasi linear dependence of the capacitance value with respect to the voltage of its control terminal.

Abstract: Methods for fabricating integrated circuits having low resistance metal gate structures are provided. One method includes forming a metal gate stack in a FET trench formed in a FET region. The metal gate stack is etched to form a recessed metal gate stack and a recess. The recess is defined by sidewalls in the FET region and is disposed above the recessed metal gate stack. A liner is formed overlying the sidewalls and the recessed metal gate stack and defines an inner cavity in the recess. A copper layer is formed overlying the liner and at least partially fills the inner cavity. The copper layer is etched to expose an upper portion of the liner while leaving a copper portion disposed in a bottom portion of the inner cavity. Copper is electrolessly deposited on the copper portion to fill a remaining portion of the inner cavity.

Abstract: A Metal-Oxide Semiconductor (MOS) transistor includes a substrate having a topside semiconductor surface doped with a first dopant type having a baseline doping level. A well is formed in the semiconductor surface doped with a second doping type. The well forms a well-substrate junction having a well depletion region. A retrograde doped region is below the well-substrate junction doped with the first dopant type having a peak first dopant concentration of between five (5) and one hundred (100) times above the baseline doping level at a location of the peak first dopant concentration, wherein with zero bias across the well-substrate junction at least (>) ninety (90) % of a total dose of the retrograde doped region is below the bottom of the well depletion region. A gate structure is on the well. Source and drain regions are on opposing sides of the gate structure.

Abstract: A silicon carbide semiconductor element and a manufacturing method thereof are disclosed in which a low contact resistance is attained between an electrode film and a wiring conductor element, and the wiring conductor element is hardly detached from the electrode film. In the method, a nickel film and a nickel oxide film are laminated in this order on a surface of an n-type silicon carbide substrate or an n-type silicon carbide region of a silicon carbide substrate, followed by a heat treatment under a non-oxidizing condition. The heat treatment transforms a portion of the nickel film into a nickel silicide film. Then, the nickel oxide film is removed with hydrochloric acid solution, and subsequently, a nickel aluminum film and an aluminum film are laminated in this order on a surface of the nickel silicide film.

Abstract: An improved varactor diode is obtained by providing a substrate having a first surface and in which are formed a first N region having a first peak dopant concentration located at a first depth beneath the surface, and a first P region having a second peak dopant concentration greater than the first peak dopant concentration located at a second depth beneath the surface less than the first depth, and a second P region having a third peak dopant concentration greater than the second peak dopant concentration and located at a third depth at or beneath the surface less than the second depth, so that the first P region provides a retrograde doping profile whose impurity concentration increases with distance from the inward edge of the second P region up to the second peak dopant concentration.

Abstract: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The second and third doped regions are of the same type sandwiching the first doped region of the second type. A first varactor terminal is coupled to the second and third doped regions and a second varactor terminal is coupled to the first doped region. At the interfaces of the doped regions are first and second depletion regions, the widths of which can be varied by varying the voltage across the terminals from zero to full reverse bias. At zero bias condition, junction capacitance (Cmax) is enhanced due to summation of two junction capacitances in parallel. At reverse bias condition, with the merging of the two junction depletion widths, the capacitor areas are drastically reduced, thereby reducing Cmin significantly.

Abstract: A varactor element having a junction region, in which the depletion capacitance of the varactor element varies when a reverse bias voltage is applied to the varactor element. The varactor element has an exponential depletion capacitance-voltage relation, e.g. obtained by providing a predetermined doping profile in the junction region. The varactor element can be used in a narrow tone spacing varactor stack arrangement, in which two varactor elements are connected in an anti-series configuration. A low impedance path for base band frequency components between a control node and each of two RF connection nodes is provided, while for fundamental and higher order harmonic frequencies, a high impedance path is provided.

Abstract: An improved varactor diode (40) is obtained by providing a substrate (41) having a first surface (43), in which are formed a P+ region (53, 46) proximate the first surface (43), a first N region (54, 45) located beneath the P+ region (53, 46), an N well region (56, 44) located beneath the first N region (54, 45) and a first P counter-doped region (55) located between the first N region (54, 45) and the N well region (56, 44), thereby forming an P+NPN structure for the varactor diode. In some embodiments, a second P-type counter-doped region (59) is provided within the N-well region (56, 44) so as to reduce the N doping concentration within the N well region (56, 44) but without creating a further PN junction therein. The net doping profile (52) provides varactor diodes (40) having a larger tuning ratio than varactors (20) without such counter-doped regions. By interchanging N and P regions an N+PNP varactor is obtained.

Abstract: Methods and heterostructure barrier varactor (HBV) diodes optimized for application with frequency multipliers at providing outputs at submillimeter wave frequencies and above. The HBV diodes include a silicon-containing substrate, an electrode over the silicon-containing substrate, and one or more heterojunction quantum wells of alternating layers of Si and SiGe of one or more electrodes of the diode. Each SiGe quantum well preferably has a floating SiGe layer between adjacent SiGe gradients followed by adjacent Si layers, such that, a single homogeneous structure is provided characterized by having no distinct separations. The plurality of Si/SiGe heterojunction quantum wells may be symmetric or asymmetric.

Abstract: In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device.

Abstract: A varactor element having a junction region, in which the depletion capacitance of the varactor element varies when a reverse bias voltage is applied to the varactor element. The varactor element has an exponential depletion capacitance-voltage relation, e.g. obtained by providing a predetermined doping profile in the junction region. The varactor element can be used in a narrow tone spacing varactor stack arrangement, in which two varactor elements are connected in an anti-series configuration. A low impedance path for base band frequency components between a control node and each of two RF connection nodes is provided, while for fundamental and higher order harmonic frequencies, a high impedance path is provided.

Abstract: A method for forming a metallization layer (30). A first layer (14) is formed outwardly from a semiconductor substrate (10). Contact vias (16) are formed through the first layer (14) to the semiconductor substrate (10). A second layer (20) is formed outwardly from the first layer (14). Portions of the second layer (20) are selectively removed such that the remaining portion of the second layer (20) defines the layout of the metallization layer (30) and the contact vias (16). The first and second layers (14) and (20) are electroplated by applying a bi-polar modulated voltage having a positive duty cycle and a negative duty cycle to the layers in a solution containing metal ions. The voltage and surface potentials are selected such that the metal ions are deposited on the remaining portions of the second layer (20). Further, metal ions deposited on the first layer (14) during a positive duty cycle are removed from the first layer (14) during a negative duty cycle.

Abstract: The present invention disclosed a silicon barrier capacitor device structure. By applying CVD or PVD technologies to deposit poly-silicon layers as the dielectric of capacitor on the doping region of the wafer, then implant a high-density (1016˜1021/cm3) impurity of the group III or group V elements and oxygen ion or nitrogen ion to the poly-silicon layer. After implantation, deposit a low resistance and high melting point conductor on the poly-silicon layer for the electrode. to form a capacitor structure, or repeat all of the deposition poly-silicon and both of the low resistance and high melting point conductor on the poly-silicon layer more than once. All of the odd electrodes are connected together. The even electrodes and the substrate are connected together, too. At last, apply high temperature furnace annealing to the devices. The grain boundary of the silicon was oxidized by oxygen and nitrogen to form an isolation film to be the insulation film.

Abstract: A PN-junction varactor includes a first ion well of first conductivity type formed on a semiconductor substrate of second conductivity type. A first dummy gate is formed over the first ion well. A first gate dielectric layer is formed between the first dummy gate and the first ion well. A second dummy gate is formed over the first ion well at one side of the first dummy gate. A second gate dielectric layer is formed between the second dummy gate and the first ion well. A first heavily doped region of the second conductivity type is located in the first ion well between the first dummy gate and the second dummy gate. The first heavily doped region of the second conductivity type serving as an anode of the PN-junction varactor.

Abstract: A semiconductor device includes a plurality of barrier layers and a plurality of quantum well layers which are alternately interleaved with each other and disposed on a substrate of semiconductor material so as to form a multiple-heterojunction varactor diode. The barrier layers and quantum well layers are doped with impurities. The varactor diode includes an ohmic contact which is electrically connected to a heavily doped embedded region and a Schottky contact which is electrically connected to a depletion region of the diode. The ohmic contact and the Schottky contact enable an external voltage source to be applied to the contacts so as to provide a bias voltage to the varactor diode. A variable capacitance is produced as a result of the depletion region varying with a variation in the bias voltage. The varactor diode also provides a constant series resistance.

Abstract: A semiconductor device comprises an n-conductive type Si substrate, a n-conductive type Si film formed on the n-conductive type Si substrate, a p-conductive type SiGe film formed on the n-conductive type Si film, a p-conductive type Si film formed on the p-conductive type SiGe film, a n-conductive type Si film formed on the p-conductive type Si film, a base electrode formed by removing a part of the n-conductive type Si film or changing the conductive type of a part of the n-conductive type Si film to a p-conductive type, and joining a metal terminal to a part of the p-conductive type Si film exposed by removing the N-type Si film or to the part of the n-conductive type Si film whose conductive type is changed to a p-conductive type, an emitter electrode formed by joining a metal terminal to the n-conductive type Si film, and a collector electrode formed by joining a metal terminal to a back surface of the n-conductive type Si substrate.

Abstract: An electronic structure including a metallic interlocking structure for bonding a conductive plated layer to metal surface, and a method of forming the electronic structure. The method provides a substrate having a metallic sheet within a dielectric layer. The metallic sheet includes a metal such as copper. An opening in the substrate, such as a blind via, is formed by laser drilling through the dielectric layer and partially through the metallic sheet. If the opening is a blind via, then the laser drilling is within an outer ring of the blind via cross section using a laser beam having a target diameter between about 20% and about 150% of a radius of the blind via cross section. A surface at the bottom of the opening, called a “blind surface,” includes a metallic protrusion formed by the laser drilling, such that the metallic protrusion is integral with a portion of the blind surface.

Abstract: A varactor comprising a substrate of semiconductor material on which is grown both an electrostatic barrier having a first layer of material doped with donor impurities and a second layer of material doped with acceptor impurities and a depletable layer. In other embodiments of the present invention varactors are provided that include a plurality of barrier and depletable layer pairs grown in a serial arrangement.

Abstract: The invention comprises a diode in a well having trench isolation that has an edge. Both the well contact of the diode and the rectifying contact of the diode are silicided, but the silicide on the rectifying contact is spaced from the trench isolation edge. The spacing is provided by a gate stack or other mask. In one embodiment, the gate stack alone spaces the two diode contacts from each other, eliminating the need for trench isolation therebetween. The structure reduces diode series resistance and silicide junction penetration. It significantly improves heat flow in trench isolation technologies, increasing the level of ESD protection. The invention also comprises an SOI diode having a lightly doped region in the thin layer of semiconductor under a gate stack with an ohmic contact to the lightly doped region self-aligned to an edge of the gate stack.

Abstract: A variable-capacitance device has an n-type diffusion layer which has an impurity concentration profile such that a region where the impurity concentration remains substantially constant and a region where the impurity concentration changes abruptly are alternately repeated, and the impurity concentration increases as the deepness from the surface increases. The impurity concentration profile can be achieved by implanting n-type impurity atoms a plurality of times with different energies in an ion implantation process or varying the concentration of n-type impurity atoms such as of phosphorus added upon epitaxial layer growth. The variable-capacitance device, and a semiconductor integrated circuit device composed of a plurality of such variable-capacitance devices can be fabricated on a semiconductor substrate, and are highly stable.

Abstract: There is provided a variable capacitance diode device. The device comprises a semiconductor substrate of a first conductive type, an epitaxial layer of the first conductive type with a high specific resistance formed on the semiconductor substrate, a first diffusion layer of the first conductive type, in which impurities are more diffused than the epitaxial layer, formed in the epitaxial layer and a second diffusion layer of a second conductive type which forms a junction with the first diffusion layer. The first diffusion layer is formed in a hollow cylindrical body or a hollow square pole body, etc., so as to enlarge an outer peripheral area thereof.