Abstract: An oscillator and a clock circuit are disclosed. In an oscillator (100), a tail inductor connected to a cross-coupled transistor includes at least two inductors connected in parallel. Therefore, an inductance of the tail inductor is less than an inductance of any one of the inductors. This can address a design difficulty that a tail inductor with a smaller inductance needs to be used as an operating frequency of a VCO increases. The oscillator (100) includes a first cross-coupled transistor (121) and a first tail inductor (111). The first tail inductor (111) includes at least two inductors connected in parallel. The first tail inductor (111) is coupled to a source of the first cross-coupled transistor (121). The source of the first cross-coupled transistor (121) is coupled to a power supply or a ground through the first tail inductor (111).

Abstract: A method of forming interconnects is provided. The method includes forming a plurality of mandrels on an interlayer dielectric (ILD) layer. The method further includes forming sidewall spacers on opposite sides of the each mandrel, wherein a portion of the ILD layer is exposed between adjacent sidewall spacers on adjacent mandrels, and removing the exposed portions of the ILD layer to form a first set of trenches between adjacent sidewall spacers. The method further includes forming a first set of interconnects in the first set of trenches, and removing the mandrels to expose portions of the ILD layer between the sidewall spacers. The method further includes removing the exposed portions of the ILD layer to form a second set of trenches between the sidewall spacers, and forming a second set of interconnects in the second set of trenches.

Abstract: A semiconductor structure includes a first metal-dielectric-metal layer, a first dielectric layer, a first conductive layer, a second conductive layer, and a second dielectric layer. The first metal-dielectric-metal layer includes a plurality of first fingers, a plurality of second fingers, and a first dielectric material. The first fingers are electrically connected to a first voltage. The second fingers are electrically connected to a second voltage different from the first voltage, and the first fingers and the second fingers are arranged in parallel and staggeredly. The first dielectric material is between the first fingers and the second fingers. The first dielectric layer is over the first metal-dielectric-metal layer. The first conductive layer is over the first dielectric layer. The second conductive layer is over the first conductive layer. The second dielectric layer is between the first conductive layer and the second conductive layer.

Abstract: A varactor is described that may be constructed in CMOS and has a high tuning range. In some embodiments, the varactor includes a well, a plurality of gates formed over the well and having a capacitive connection to the well, the gates comprising a first subset of the gates that are adjacent and consecutive and coupled to a positive pole of an excitation oscillation signal, and a second subset of the gates that are adjacent and consecutive and coupled to a negative pole of the excitation oscillation signal, and a plurality of source/drain terminals formed over the well and having an ohmic connection to the well, each coupled to a respective gate to receive a control voltage to control the capacitance of the varactor.

Abstract: A transistor includes a gate electrode with multiple metals distributed along the width of the gate electrode. Each of the metals in the gate electrode has different work functions. Such a compound gate provides higher linearity when, e.g., operated as a radio frequency transistor.

Abstract: A transistor includes a gate electrode with multiple metals distributed along the width of the gate electrode. Each of the metals in the gate electrode has different work functions. Such a compound gate provides higher linearity when, e.g., operated as a radio frequency transistor.

Abstract: A semiconductor device may include a substrate and a hyper-abrupt junction region carried by the substrate. The hyper-abrupt junction region may include a first semiconductor layer having a first conductivity type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer and having a second conductivity type different than the first conductivity type, and a second superlattice layer on the second semiconductor layer. The semiconductor device may further include a first contact coupled to the hyper-abrupt junction regions and a second contact coupled to the substrate to define a varactor. The first and second superlattices may each include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A semiconductor device may include a substrate and a hyper-abrupt junction region carried by the substrate. The hyper-abrupt junction region may include a first semiconductor layer having a first conductivity type, a superlattice layer on the first semiconductor layer, and a second semiconductor layer on the superlattice layer and having a second conductivity type different than the first conductivity type. The first, second, and the superlattice layers may be U-shaped. The semiconductor device may further include a gate dielectric layer on the second semiconductor layer of the hyper-abrupt junction region, a gate electrode on the gate dielectric layer, and spaced apart source and drain regions adjacent the hyper-abrupt junction region.

Abstract: Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices.

Abstract: An equivalent circuit of a converter (4) is represented by a series connection between an equivalent capacitor (41) and an equivalent resistor (42), and the converter (4) includes a controller that adjusts a power factor of the input power by controlling a capacitive reactance (Xc) of the equivalent capacitor (41).

Abstract: Systems, devices, and methods for micro-electro-mechanical system (MEMS) tunable capacitors can include a fixed actuation electrode attached to a substrate, a fixed capacitive electrode attached to the substrate, and a movable component positioned above the substrate and movable with respect to the fixed actuation electrode and the fixed capacitive electrode. The movable component can include a movable actuation electrode positioned above the fixed actuation electrode and a movable capacitive electrode positioned above the fixed capacitive electrode. At least a portion of the movable capacitive electrode can be spaced apart from the fixed capacitive electrode by a first gap, and the movable actuation electrode can be spaced apart from the fixed actuation electrode by a second gap that is larger than the first gap.

Abstract: Various embodiments of solid state transducer (“SST”) devices are disclosed. In several embodiments, a light emitter device includes a metal-oxide-semiconductor (MOS) capacitor, an active region operably coupled to the MOS capacitor, and a bulk semiconductor material operably coupled to the active region. The active region can include at least one quantum well configured to store first charge carriers under a first bias. The bulk semiconductor material is arranged to provide second charge carriers to the active region under the second bias such that the active region emits UV light.

Abstract: The present invention provides a variable area capacitive lateral acceleration sensor and a preparation method. The acceleration sensor at least includes: three-layer stack structure bonded by a first substrate, a second substrate and a third substrate which are electrically isolated with each other, wherein, the second substrate includes a movable seismic mass, a frame surrounded the movable seismic mass, a elastic beam connected to the movable seismic mass and the frame, a plurality of bar structure electrodes positioned on two surfaces of the movable seismic mass, an anti-overloading structure arranged on the movable seismic mass, etc.

Abstract: Systems, devices, and methods for tunable filters that are configured to support multiple frequency bands, such as within the field of cellular radio communication, can include a first resonator and a second resonator configured to block signals within one or more frequency ranges, and one or more coupling element connected to both the first resonator and the second resonator. The one or more coupling element can be configured to provide low insertion loss within a pass band.

Abstract: An electrical device includes at least one graphene quantum capacitance varactor. In some examples, the graphene quantum capacitance varactor includes an insulator layer, a graphene layer disposed on the insulator layer, a dielectric layer disposed on the graphene layer, a gate electrode formed on the dielectric layer, and at least one contact electrode disposed on the graphene layer and making electrical contact with the graphene layer. In other examples, the graphene quantum capacitance varactor includes an insulator layer, a gate electrode recessed in the insulator layer, a dielectric layer formed on the gate electrode, a graphene layer formed on the dielectric layer, wherein the graphene layer comprises an exposed surface opposite the dielectric layer, and at least one contact electrode formed on the graphene layer and making electrical contact with the graphene layer.

Abstract: An integrated heterostructure material is achieved by combining the attributes of two perovskite oxide film growth methods, RF sputtering and the metallo-organic solution deposition (MOSD) technique, in combination with employing a novel integrated material design consisting of a SrTO3 thin film layer which serves as a template to achieve a property enhanced, BST-based thin film overgrowth. In specific the integrated materials design consists of a thin RF sputtered SrTiO3 film (lower layer) which underlies a substantially thicker MOSD over-growth Mg doped BST-based film (upper layer). The inventive material design and combinational film growth fabrication method thereof enables beneficial critical material/device characteristics which include enhanced dielectric permittivity in concert with low loss; low leakage current density; high voltage breakdown strength; high tunability; controlled and optimized film microstructure; and a smooth surface morphology with minimal surface defects.

Abstract: An analog open-loop self-oscillating boost converter is provided including: an output terminal for supplying an output voltage bus; an input terminal for receiving variable input power; a varactor positioned in series with the input terminal; and an oscillating network having an inductor, a resistor and a capacitor in a parallel orientation, the oscillating network connected to a semiconductor device and the varactor.

Abstract: A variable capacitance device including: first and second transistors coupled in parallel between first and second nodes of the capacitive device, a control node of the first transistor being adapted to receive a control signal, and a control node of the second transistor being adapted to receive the inverse of the control signal, wherein the first and second transistors are formed in a same semiconductor well.

Abstract: According to one embodiment, there is disclosed a MEMS element. The MEMS element includes a lower electrode having a surface on which a plurality of minute convex portions are formed. A plurality of dielectric bumps are provided on the upper surface of the lower electrode and are thicker than heights of the convex portions. A dielectric layer is provided on the dielectric bumps and the lower electrode. An upper electrode is provided above the dielectric layer. The upper electrode is movable so as to vary capacitance between the upper electrode and the lower electrode.

Abstract: A variable capacitance device includes a capacitor having a first capacitance and a variable resistor coupled in series with the capacitor. The variable resistor includes a gate structure formed over a channel region defined in a doped well formed in a semiconductor substrate. A resistance of the variable resistor is based on a voltage applied to the gate structure, which adjusts a resistance of the channel and a capacitance of the variable capacitance device.

Abstract: A system and method for a memory cell layout is disclosed. An embodiment comprises forming dummy layers and spacers along the sidewalls of the dummy layer. Once the spacers have been formed, the dummy layers may be removed and the spacers may be used as a mask. By using the spacers instead of a standard lithographic process, the inherent limitations of the lithographic process can be avoided and further scaling of FinFET devices can be achieved.

Abstract: A variable capacitance device includes a fixed substrate, a movable portion, driving electrodes, an RF capacitance electrode and an insulating film. The movable portion faces the fixed substrate and can change a gap between the movable portion and the fixed substrate. The driving electrodes are formed on the fixed substrate so as to face the movable portion. The RF capacitance electrode is formed on the fixed substrate so as to face the movable portion and be spaced apart from the driving electrodes. The insulating film is formed between the movable portion and the driving electrodes. The level of a voltage applied to the driving electrodes and the level of a voltage applied to the movable portion are periodically switched and the level of a voltage applied to the RF capacitance electrode and the level of a voltage applied to the movable portion are always the same.

Abstract: A varactor diode includes a contact layer having a first conductivity type, a voltage blocking layer having the first conductivity and a first net doping concentration on the contact layer, a blocking junction on the voltage blocking layer, and a plurality of discrete doped regions in the voltage blocking layer and spaced apart from the carrier injection junction. The plurality of discrete doped regions have the first conductivity type and a second net doping concentration that is higher than the first net doping concentration, and the plurality of discrete doped regions are configured to modulate the capacitance of the varactor diode as a depletion region of the varactor diode expands in response to a reverse bias voltage applied to the blocking junction. Related methods of forming a varactor diode are also disclosed.

Abstract: An electronic product includes a case; a first board placed inside the case; and a second board having an Electromagnetic Band Gap (EBG) structure inserted therein. The second board is coupled to an inside of the case facing the first board so as to shield a noise radiated from the first board.

Abstract: A voltage-switchable dielectric layer may be employed on a die for electrostatic discharge (ESD) protection. The voltage-switchable dielectric layer functions as a dielectric layer between terminals of the die during normal operation of the die. When ESD events occur at the terminals of the die, a high voltage between the terminals switches the voltage-switchable dielectric layer into a conducting layer to allow current to discharge to a ground terminal of the die without the current passing through circuitry of the die. Thus, damage to the circuitry of the die is reduced or prevented during ESD events on dies with the voltage-switchable dielectric layer. The voltage-switchable dielectric layer may be deposited on the back side of a die for protection during stacking with a second die to form a stacked IC. A method includes depositing a voltage-switchable dielectric layer on a first die between a first terminal and a second terminal.

Abstract: A semiconductor device comprises a circuit cell and a basic end cell. The circuit cell includes a plurality of elements aligned in a first direction, and the basic end cell is arranged adjacent to the circuit cell in the first direction and has a compensation capacitor capable of being connected to a supply voltage of the circuit cell. In the semiconductor device, a diffusion layer forming the compensation capacitor extends along the first direction in a predetermined region of the circuit cell.

Abstract: A voltage-switchable dielectric layer may be employed on a die for electrostatic discharge (ESD) protection. The voltage-switchable dielectric layer functions as a dielectric layer between terminals of the die during normal operation of the die. When ESD events occur at the terminals of the die, a high voltage between the terminals switches the voltage-switchable dielectric layer into a conducting layer to allow current to discharge to a ground terminal of the die without the current passing through circuitry of the die. Thus, damage to the circuitry of the die is reduced or prevented during ESD events on dies with the voltage-switchable dielectric layer. The voltage-switchable dielectric layer may be deposited on the back side of a die for protection during stacking with a second die to form a stacked IC.

Abstract: In an embodiment of the present invention is provided a varactor comprising a substrate, a plurality of bottom electrodes positioned on a surface of the substrate separated to form a gap therein, a tunable dielectric material positioned on the surface of the substrate and within the gap, the tunable dielectric at least partially overlaying the plurality of electrodes, and a top electrode in contact with the tunable dielectric.

Abstract: A semiconductor structure includes a semiconductor substrate having a first region of a first polarity and a second region of a second polarity adjacent to the first region; and a first terminal including: a first deep trench located in the first region, a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first deep trench; a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric; and a first electrical contact electrically coupling the first conductive inner electrode to the first region.

Abstract: A schottky diode, a resistive memory device including the schottky diode and a method of manufacturing the same. The resistive memory device includes a semiconductor substrate including a word line, a schottky diode formed on the word line, and a storage layer formed on the schottky diode. The schottky diode includes a first semiconductor layer, a conductive layer formed on the first semiconductor layer and having a lower work function than the first semiconductor layer, and a second semiconductor layer formed on the to conductive layer.

Abstract: A memory capacitor based on a field configurable ion-doped polymer is reported. The device can be dynamically and reversibly programmed to analog capacitances with low-voltage (<5 V) pulses. After the device is programmed to a specific value, its capacitance remains nonvolatile. The field configurable capacitance is attributed to the modification of ionic dopant concentrations in the polymer. The ion and dipole concentrations in the ion conductive layer can be modified when the voltage biases applied to the electrodes exceeds a threshold value and can operate as a conventional capacitor when a voltage less than the threshold value is applied. The ion conductive layer will remain at a stable value after the device is modified without applying external voltage. The device has a nonvolatile memory function even when the external voltage is turned off. The memory capacitors may be used for analog memory, nonlinear analog and neuromorphic circuits.

Abstract: A replaceable chamber element for use in a plasma processing system, such as a plasma etching system, is described. The replaceable chamber element includes a chamber component configured to be exposed to plasma in a plasma processing system, wherein the chamber component is fabricated to include a semiconductor junction, and wherein a capacitance of the chamber component is varied when a voltage is applied across the semiconductor junction.

Abstract: The present invention provides a differential varactor device including a substrate having a first conductive type, a well having a second conductive type, five doped regions having the second conductive type, a first gate, a second gate, a third gate, and a fourth gate. The well is disposed in the substrate, and the doped regions are disposed in the well and arranged along a direction. The first gate, the second gate, the third gate and the fourth gate are respectively disposed on the well between any two of the adjacent doped regions, and are arranged sequentially along the direction.

Abstract: Disclosed is a semiconductor structure, which includes a non-planar varactor having a geometrically designed depletion zone with a taper, as to provide improved Cmax/Cmin with low series resistance. Because of the taper, the narrowest portion of the depletion zone can be designed to be fully depleted, while the remainder of the depletion zone is only partially depleted. The fabrication of semiconductor structure may follow that of standard FinFET process, with a few additional or different steps. These additional or different steps may include formation of a doped trapezoidal (or triangular) shaped silicon mesa, growing/depositing a gate dielectric, forming a gate electrode over a portion of the mesa, and forming a highly doped contact region in the mesa where it is not covered by the gate electrode.

Abstract: A variable capacitance device including: first and second transistors coupled in parallel between first and second nodes of the capacitive device, a control node of the first transistor being adapted to receive a control signal, and a control node of the second transistor being adapted to receive the inverse of the control signal, wherein the first and second transistors are formed in a same semiconductor well.

Abstract: A replaceable chamber element for use in a plasma processing system, such as a plasma etching system, is described. The replaceable chamber element includes a chamber component configured to be exposed to plasma in a plasma processing system, wherein the chamber component is fabricated to include a semiconductor junction, and wherein a capacitance of the chamber component is varied when a voltage is applied across the semiconductor junction.

Abstract: The present invention relates to using an insulator layer between two metal layers of a semiconductor die to provide a micro-electromechanical systems (MEMS) device, such as an ohmic MEMS switch or a capacitive MEMS switch. In an ohmic MEMS switch, the insulator layer may be used to reduce metal undercutting during fabrication, to prevent electrical shorting of a MEMS actuator to a MEMS cantilever, or both. In a capacitive MEMS switch, the insulator layer may be used as a capacitive dielectric between capacitive plates, which are provided by the two metal layers. A fixed capacitive element may be provided by the insulator layer between the two metal layers. In one embodiment of the present invention, an ohmic MEMS switch, a capacitive MEMS switch, a fixed capacitive element, or any combination thereof may be integrated into a single semiconductor die.

Abstract: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The first and third doped regions are of the same type sandwiching the second doped region of the second type. A first input terminal is coupled to the first and third doped regions and a second terminal is coupled to the second doped region. At the interfaces of the doped regions are first and second depletion regions whose width can be varied by varying the voltage across the terminals from zero to full reverse bias.

Abstract: A filter device is provided including a substrate (302) and a plurality of horizontal gap closing actuator (GCA) devices (550) disposed on a first surface of the substrate. The plurality of GCA devices includes and one or more GCA varactors (700). Each one of the plurality of horizontal GCA devices includes at least one drive comb structure (602a, 602b, 702a, 702b), at least one input/output (I/O) comb structure (616a, 676b, 716a, 716b), and at least one truss comb structure (604, 704) interdigitating the drive comb and the I/O comb structures. The truss comb structure is configured to move along a motion axis between at least a first interdigitated position and a second interdigitated position based on a bias voltage applied between the truss comb structure and the drive comb structure.

Abstract: A printed circuit board and an electronic product are disclosed. In accordance with an embodiment of the present invention, the printed circuit board includes a first board, which has an electronic component mounted thereon, and a second board, which is positioned on an upper side of the first board and covers at least a portion of an upper surface of the first board and in which an EBG structure is inserted into the second board such that a noise radiating upwards from the first board is shielded. Thus, the printed circuit board can readily absorb various frequencies, be easily applied without any antenna effect and be cost-effective in manufacturing.

Abstract: Embodiments of the present disclosure include devices or systems that include a composite thermal capacitor disposed in thermal communication with a hot spot of the device, methods of dissipating thermal energy in a device or system, and the like.

Abstract: A three-dimensional integrated circuit includes a semiconductor substrate where the substrate has an opening extending through a first surface and a second surface of the substrate and where the first surface and the second surface are opposite surfaces of the substrate. A conductive material substantially fills the opening of the substrate to form a conductive through-substrate-via (TSV). An active circuit is disposed on the first surface of the substrate, an inductor is disposed on the second surface of the substrate and the TSV is electrically coupled to the active circuit and the inductor. The three-dimensional integrated circuit may include a varactor formed from a dielectric layer formed in the opening of the substrate such that the conductive material is disposed adjacent the dielectric layer and an impurity implanted region disposed surrounding the TSV such that the dielectric layer is formed between the impurity implanted region and the TSV.

Abstract: An ESD protection device includes a first well of a first semiconductor type disposed in a substrate of a second semiconductor type forming a first diode. A second well of the second semiconductor type is formed in the substrate to form a second diode with the first well. A first plurality of doped regions of the first semiconductor type are formed in an upper surface of the first well. A second plurality of doped regions of the second semiconductor type are formed in the upper surface of the first well forming a third diode with the first well. A plurality of STI regions are formed in the upper surface of the first well. Each STI region is disposed between a doped region of the first and second semiconductor types. The third diode provides a current bypass when an ESD voltage spike is received at one of the first or second plurality of doped regions.

Abstract: One example of the present invention is a nanoscale electronic device comprising a first conductive electrode, a second conductive electrode, and an anisotropic dielectric material layered between the first and second electrodes having a permittivity in a direction approximately that of the shortest distance between the first and second electrodes less than the permittivity in other directions within the anisotropic dielectric material. Additional examples of the present invention include integrated circuits that contain multiple nanoscale electronic devices that each includes an anisotropic dielectric material layered between first and second electrodes having a permittivity in a direction approximately that of the shortest distance between the first and second electrodes less than the permittivity in other directions within the anisotropic dielectric material.

Abstract: A semiconductor structure includes a semiconductor substrate having a first region of a first polarity and a second region of a second polarity adjacent to the first region; and a first terminal including: a first deep trench located in the first region, a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first deep trench; a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric; and a first electrical contact electrically coupling the first conductive inner electrode to the first region.

Abstract: Mixed gate varactors are provided. The mixed gate varactors may include a semiconductor region of a given doping type. A first terminal for the varactor may be formed from a gate structure on the semiconductor region. A second terminal for the varactor may be formed from a heavily doped region in the semiconductor region that has the same doping type as the given doping type. A third terminal for the varactor may be formed from a heavily doped region in the semiconductor region that has a different doping type than the given doping type. The gate structure may include multiple gate conductors on a gate insulator. The gate insulator may be a high-K dielectric. The gate conductors may be metals or other materials that have different work functions. A conductive layer such as a layer of polysilicon may electrically connect the first and second gate conductors.

Abstract: On-chip capacitors with a variable capacitance, as well as design structures for a radio frequency integrated circuit, and method of fabricating and method of tuning on-chip capacitors. The on-chip capacitor includes first and second ports powered with opposite polarities, first and second electrodes, and first and second voltage-controlled units. Each of the first and second voltage-controlled units is switched between a first state in which the first and second electrodes are electrically isolated from the first and second ports and a second state. When the first voltage-controlled unit is switched to the second state, the first electrode is electrically connected with the first port. When the second voltage-controlled unit is switched to the second state the second electrode is electrically connected with the second port. The on-chip capacitor has a larger capacitance value when the first and second voltage-controlled units are in the second state.

Abstract: A semiconductor structure includes a semiconductor substrate having a first region of a first polarity and a second region of a second polarity adjacent to the first region; and a first terminal including: a first deep trench located in the first region, a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first deep trench; a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric; and a first electrical contact electrically coupling the first conductive inner electrode to the first region.

Abstract: An internal matching transistor comprises: a conductive base material including a groove, a first region, and a second region which is located opposite to the first region across the groove; a transistor bonded onto the first region of the base material; an internal matching circuit bonded onto the second region of the base material; a wire connecting the transistor to the internal matching circuit across above the groove; and a conductive or non-conductive material located between the wire and the groove, wherein capacitance between the wire and the base material is adjusted by the material.

Abstract: After the formation of a first interlayer insulating, an etching stopper film made of SiON is formed thereon. Subsequently, a contact hole extending from the upper surface of the etching stopper film and reaching a high concentration impurity region is formed, and a first plug is formed by filling W into the contact hole. Next, a ferroelectric capacitor, a second interlayer insulating film, and the like are formed. Thereafter, a contact hole extending from the upper surface of the interlayer insulating film and reaching the first plug is formed. Then, the contact hole is filled with W to form a second plug. With this, even when misalignment occurs, the interlayer insulating film is prevented from being etched.