Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The transient voltage suppression (TVS) device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer. The TVS device also includes a conductive path electrically coupled between the second layer and an electrical connection to a circuit external to the TVS device, the conductive path configured to permit controlling a turning on of the TVS device at less than a breakdown voltage of the TVS device.

Abstract: A method for controlling a semiconductor circuit, including forming an inductor and a capacitor on a substrate, which are inductively coupled to one another. The inductor has an inductance value while the capacitor has a capacitance value. The inductor and capacitor make up an oscillator circuit with two terminals. Eddy currents are generated through the capacitor when an operating current flows along the inductor. These eddy currents influence, by inductive coupling, the inductance value and performance of the oscillator circuit, thus simultaneously tuning the inductance and capacitance of the oscillator circuit.

Abstract: Described herein is a protective structure. The protective structure includes a semiconductor substrate, a first diode disposed at least one of in or on the semiconductor substrate and a diode arrangement disposed at least one of in or on the semiconductor substrate. The diode arrangement includes a stack of a second diode and a transient voltage suppressor (TVS) diode connected in series with the second diode. The diode arrangement is in parallel with the first diode.

Abstract: Methods and devices relating to diodes including single-wall carbon nanotubes (SWCNT) are disclosed according to embodiments of the present invention. According to one embodiment, a diode may include one or more SWCNTs. The SWCNTs may be grouped together in multiple bundles with the SWCNTs being generally aligned parallel to each other in the bundles.

Abstract: A diode string voltage adapter includes diodes formed in a substrate of a first conductive type. Each diode includes a deep well region of a second conductive type formed in the substrate. A first well region of the first conductive type formed on the deep well region. A first heavily doped region of the first conductive type formed on the first well region. A second heavily doped region of the second conductive type formed on the first well region. The diodes are serially coupled to each other. A first heavily doped region of a beginning diode is coupled to a first voltage. A second heavily doped region of each diode is coupled to a first heavily doped region of a next diode. A second heavily doped region of an ending diode provides a second voltage. The deep well region is configured to be electrically floated.

Abstract: A parallel capacitor varactor shunt switch device may include a shunt layer, a coplanar waveguide (CPW) layer, and a tunable thin film dielectric layer that is interposed between the shunt layer and the CPW layer. The tunable thin film dielectric layer electrically isolates the shunt layer from the CPW layer. The shunt layer includes a plurality of parallel shunt lines. The CPW layer includes a CPW signal transmission line with two CPW ground lines parallel to the CPW signal transmission line. A plurality of varactor areas equal in number to the plurality of parallel shunt lines are defined in the CPW signal transmission line, each varactor area corresponding to an overlap of the CPW signal transmission line with a respective shunt line and each respective parallel shunt line and its corresponding varactor area defines a capacitor.

Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second pads to protect an internal circuit therebetween. Under a normal operating condition, a voltage on the first pad is higher than that on the second pad. The ESD protection circuit includes a substrate of a first conductivity type; first well of a second conductivity type in the substrate, wherein the first well is coupled to the first pad; a snapback device housed in the first well; and a diode string in the substrate, connected in series with the snapback device and separated from the first well, wherein the serially connected diode string and snapback device is connected between the first pad and the second pad. With the isolation from the first well, the holding voltage of the ESD protection circuit can be tuned by adjusting the number of diodes in the diode string without using a guard ring.

Abstract: A diode includes a first region having a first conductive type impurity and formed in a first well having the first conductive type impurity, a second region formed in the first well and having a second conductive type impurity, and a semiconductor pattern disposed above the first well and including a first portion having the first conductive type impurity and a second portion having the second conductive type impurity. The first region and the first portion are coupled with an anode, and the second region and the second portion are coupled with a cathode.

Abstract: A semiconductor device according to an embodiment of the present invention includes fuse patterns spaced apart from each other by a predetermined distance over a first interlayer insulation film; a second interlayer insulation film disposed between the fuse patterns over the first interlayer insulation film; and a capping film pattern formed over the fuse patterns and the second interlayer insulation films, the capping film pattern including a slot exposing the second interlayer insulation film.

Abstract: A semiconductor device has a field insulating film provided on a semiconductor substrate, and a fuse provided on the field insulating film and having a fuse trimming laser irradiation portion and fuse terminals. The semiconductor device further includes an intermediate insulating film covering the fuse, a first TEOS layer on the intermediate insulating film, an SOG layer for planarizing the first TEOS layer, a second TEOS layer on the SOG layer and on the first TEOS layer, a protective film on the second TEOS layer, and an opening portion above the fuse trimming laser irradiation portion in a region from the protective film to the first TEOS layer. A seal ring is provided on the intermediate insulating film so as to surround the opening portion. The seal ring is disposed over the fuse so as to overlap each of the fuse terminals in plan view.

Abstract: An integrated circuit device provides electrostatic discharge (ESD) protection. In connection with various example embodiments, an ESD protection circuit includes a diode-type circuit having a p-n junction that exhibits a low breakdown voltage. Connected in series with the diode between an internal node susceptible to an ESD pulse and ground, are regions of opposite polarity having junctions therebetween for mitigating the passage of leakage current via voltage sharing with the diode's junction. Upon reaching the breakdown voltage, the diode shunts current to ground via another substrate region, bypassing one or more junctions of the regions of opposite polarity and facilitating a low clamping voltage.

Abstract: A semiconductor device having an active element and an MIM capacitor and a structure capable of reducing the number of the manufacturing steps thereof and a manufacturing method therefor are provided. The semiconductor device has a structure that the active element having an ohmic electrode and the MIM capacitor having a dielectric layer arranged between a lower electrode and an upper electrode are formed on a semiconductor substrate, wherein the lower electrode and ohmic electrode have the same structure. In an MMIC 100 in which an FET as an active element and the MIM capacitor are formed on a GaAs substrate 10, for example, a source electrode 16a and a drain electrode 16b, which are ohmic electrodes of the FET, are manufactured simultaneously with a lower electrode 16c of the MIM capacitor. Here the electrodes are formed with the same metal.

Abstract: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The first and third doped regions are of the same type sandwiching the second doped region of the second type. A first input terminal is coupled to the first and third doped regions and a second terminal is coupled to the second doped region. At the interfaces of the doped regions are first and second depletion regions whose width can be varied by varying the voltage across the terminals from zero to full reverse bias.

Abstract: A phase change memory apparatus is provided that includes a first electrode that is longer than it is wide, the first electrode having a trench formed on an active region of a semiconductor substrate, a second electrode formed in a bottom portion of the trench, and a bottom electrode contact formed on the second electrode.

Abstract: A serially-connected diode pair made of diodes having a high withstand voltage and a low on-resistance is formed based on a high withstand voltage vertical PNP bipolar transistor process technology. Two of the diode pairs are connected in parallel to form a bridge so that there is formed a high-efficiency full-wave rectifier circuit that is free from a leakage current due to a parasitic transistor. The serially-connected diode pair is formed by connecting a diode composed of a P type semiconductor substrate, that makes an anode, and an N type buried layer, that makes a cathode, and a diode composed of a P+ type conductive layer, that makes an anode, and an N type epitaxial layer, that makes a cathode, in series with an electrode AC1.

Abstract: The embodiments of the invention provide a structure, method, etc. for a fin differential MOS varactor diode. More specifically, a differential varactor structure is provided comprising a substrate with an upper surface, a first vertical anode plate, and a second vertical anode plate electrically isolated from the first vertical anode plate. Moreover, a semiconductor fin comprising a cathode is between the first vertical anode plate and the second vertical anode plate, wherein the semiconductor fin, the first vertical anode plate, and the second vertical anode plate are each positioned over the substrate and perpendicular to the upper surface of the substrate.

Abstract: Integrated mask-programmable device, having a plurality of metal levels including a top metal level, a bottom metal level and a first intermediate metal level formed between the top and bottom metal levels, and a plurality of via levels arranged between the bottom and the first intermediate metal levels and between the first intermediate and the top metal levels and connecting each metal level to adjacent metal levels. The plurality of metal levels forms a first, a second and at least a third terminal, the top and bottom metal levels having at least two metal regions, and the first intermediate metal level having at least three metal regions. The first terminal is connected to third terminal or the second terminal is connected to the third terminal by modifying a single metal or via level.

Abstract: A memory device includes a diode driver and a data storage element, such as an element comprising phase change memory material, and in which the diode driver comprises a silicide element on a silicon substrate with a single crystal silicon node on the silicide element. The silicide element separates the single crystal silicon node from the underlying silicon substrate, preventing the flow of carriers from the single crystal silicon node into the substrate, and is capable of acting as a conductive element for interconnecting devices on the device. The single crystal silicon node acts as one terminal of a diode, and a second semiconductor node is formed on top of it, acting as the other terminal of the diode.

Abstract: A semiconductor element for macro and micro frequency tuning, and an antenna and a frequency tuning circuit having the semiconductor element, are provided. The semiconductor element includes first and second semiconductors which have a same polarity, a third semiconductor which has a polarity opposite to the polarity of the first and second semiconductors and is interposed between the first and the second semiconductors, a first intrinsic semiconductor which is interposed between the first and the third semiconductors, and a second intrinsic semiconductor which is interposed between the third and the second semiconductors.

Abstract: A high-frequency switch includes a semiconductor body made of a semiconductor material having a first surface and a second surface, and two direct current terminals and two high-frequency terminals.

Abstract: Methods and heterostructure barrier varactor (HBV) diodes optimized for application with frequency multipliers at providing outputs at submillimeter wave frequencies and above. The HBV diodes include a silicon-containing substrate, an electrode over the silicon-containing substrate, and one or more heterojunction quantum wells of alternating layers of Si and SiGe of one or more electrodes of the diode. Each SiGe quantum well preferably has a floating SiGe layer between adjacent SiGe gradients followed by adjacent Si layers, such that, a single homogeneous structure is provided characterized by having no distinct separations. The plurality of Si/SiGe heterojunction quantum wells may be symmetric or asymmetric.

Abstract: A ferroelectric varactor suitable for capacitive shunt switching is disclosed. High resistivity silicon with a SiO2 layer and a patterned metallic layer deposited on top is used as the substrate. A ferroelectric thin-film layer deposited on the substrate is used for the implementation of the varactor. A top metal electrode is deposited on the ferroelectric thin-film layer forming a CPW transmission line. By using the capacitance formed by the large area ground conductors in the top metal electrode and bottom metallic layer, a series connection of the ferroelectric varactor with the large capacitor defined by the ground conductors is created. The large capacitor acts as a short to ground, eliminating the need for vias. The concept of switching ON and OFF state is based on the dielectric tunability of the ferroelectric thin-films. At 0 V, the varactor has the highest capacitance value, resulting in the signal to be shunted to ground, thus isolating the output from the input.

Abstract: Structure and methods for a differential junction varactor. The structure includes: a silicon first region formed in a silicon substrate, the first region of a first dopant type; and a plurality of silicon second regions in physical and electrical contact with the first region, the plurality of second regions spaced apart and not in physical contact with each other, the plurality of second regions of a second dopant type, the first dopant type different from the second dopant type; a cathode terminal electrically connected to the first region; a first anode terminal electrically connected to a first set of second regions of the plurality of second regions; and a second anode terminal electrically connected to a second set of second silicon regions of the plurality of second regions, second regions of the first set of second regions alternating with second regions of the second set of second regions.

Abstract: A component formed in a substrate of a first conductivity type, having two inputs and two outputs and: a first diode having its anode connected to a first input and having its cathode connected to a first output; a second diode having its anode connected to a second output and having its cathode connected to the first input; a one-way switch having its anode connected to the first output, its cathode being connected to the second output; and a third diode having its anode connected to the second output, its cathode being connected to the first output; the first, second, and third diodes being formed in a first portion of the substrate separated by a wall of the second conductivity type from a second substrate portion comprising the switch.

Abstract: This invention discloses a decoupling capacitor in an integrated circuit, comprising a plurality of dedicated PN diodes with a total junction area greater than one tenth of a total active area of functional devices for which the dedicated PN diodes are intended to protect, a N-type region of the dedicated PN diodes coupling to a positive supply voltage (Vdd), and a P-type region of the dedicated PN diodes coupling to a complimentary lower supply voltage (Vss), wherein the dedicated PN diodes are reversely biased.

Abstract: An arrangement of pillar shaped p-i-n diodes having a high aspect ration are formed on a semiconductor substrate. Each device is formed by an intrinsic or lightly doped region (i-region) positioned between a P+ region and an N+ region at each end of the pillar. The arrangement of pillar p-i-n diodes is embedded in an optical transparent medium. For a given surface area, more light energy is absorbed by the pillar arrangement of p-i-n diodes than by conventional planar p-i-n diodes. The pillar p-i-n diodes are preferably configured in an array formation to enable photons reflected from one pillar p-i-n diode to be captured and absorbed by another p-i-n diode adjacent to the first one, thereby optimizing the efficiency of energy conversion.

Abstract: A multi-layer structure including a base insulating layer and a thin metal film layer (seed layer) is prepared. A plating resist layer is formed to have a prescribed pattern on the upper surface of the thin metal film layer. A metal plating layer is formed on the thin metal film layer exposed by electroplating. Then, the plating resist layer is removed, and the thin metal film layer in the region having the plating resist layer is removed. In this way, a conductive pattern including the thin metal film layer and the metal plating layer is formed. The upper surface of the base insulating layer in the region without the conductive pattern is subjected to roughening treatment. A cover insulating layer is formed on the upper surfaces of the base insulating layer and the conductive pattern. In this way, a printed circuit board is completed.

Abstract: Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure that includes a vapor-deposited dielectric material. The dielectric material has a predetermined microstructure formed using a glancing angle deposition (GLAD) process. The microstructure includes columnar structures that provide a porous dielectric material. One aspect is a method of forming a low-k insulator structure. In one embodiment, a predetermined vapor flux incidence angle ? is set with respect to a normal vector for a substrate surface so as to promote a dielectric microstructure with individual columnar structures. Vapor deposition and substrate motion are coordinated so as to form columnar structures in a predetermined shape. Other aspects are provided herein.

Abstract: An apparatus for protecting electronic equipment from voltage surges includes a network interface coupled to a computer device for connecting the computer device to a computer network and a discrete voltage surge protection device coupled to the computer network with a first unshielded cable and to the network interface with a second unshielded cable. The unshielded cable comprises at least one wire pair and the discrete protection device comprises a voltage suppressor device coupled between the wires of each wire pair. The discrete voltage surge protection device renders the apparatus compliant with the Telcordia (Bellcore) GR-1089-CORE Intrabuilding Lightning Surge Tests.

Abstract: Structure and methods for a differential junction varactor. The structure includes: a silicon first region formed in a silicon substrate, the first region of a first dopant type; and a plurality of silicon second regions in physical and electrical contact with the first region, the plurality of second regions spaced apart and not in physical contact with each other, the plurality of second regions of a second dopant type, the first dopant type different from the second dopant type; a cathode terminal electrically connected to the first region; a first anode terminal electrically connected to a first set of second regions of the plurality of second regions; and a second anode terminal electrically connected to a second set of second silicon regions of the plurality of second regions, second regions of the first set of second regions alternating with second regions of the second set of second regions.

Abstract: This invention discloses a decoupling capacitor in an integrated circuit, comprising a plurality of dedicated PN diodes with a total junction area greater than one tenth of a total active area of functional devices for which the dedicated PN diodes are intended to protect, a N-type region of the dedicated PN diodes coupling to a positive supply voltage (Vdd), and a P-type region of the dedicated PN diodes coupling to a complimentary lower supply voltage (Vss), wherein the dedicated PN diodes are reversely biased.

Abstract: A semiconductor element for macro and micro frequency tuning, and an antenna and a frequency tuning circuit having the semiconductor element, are provided. The semiconductor element includes first and second semiconductors which have a same polarity, a third semiconductor which has a polarity opposite to the polarity of the first and second semiconductors and is interposed between the first and the second semiconductors, a first intrinsic semiconductor which is interposed between the first and the third semiconductors, and a second intrinsic semiconductor which is interposed between the third and the second semiconductors.

Abstract: An optical semiconductor device 1a includes a lead frame 4 having an aperture 7, a submount 8 disposed on one surface of the lead frame 4 to close the aperture 7, a semiconductor optical element 3 which has an optical portion 6 and which is mounted on a surface of the submount 8 opposite to a surface on a side of the aperture 7 with the optical portion 6 facing the aperture 7 through the submount 8, a molding portion 10 made of a non-transparent molding resin which exposes at least a region including the aperture 7 on the other surface side of the lead frame 4 and which encapsulates the lead frame 4, the semiconductor optical element 3 and the submount 8, and a lens 9 disposed on the other surface of the lead frame 4 to close the aperture 7.

Abstract: A semiconductor device comprises varactor regions Va and transistor regions Tr. An active region for a varactor is formed with a substrate contact impurity diffusion region obtained by doping an N well region with N-type impurity at a relatively high concentration. However, any extension region (or LDD region) as in a varactor of a known semiconductor device is not formed in the active region for a varactor. On the other hand, parts of a P well region located to both sides of the polysilicon gate electrode in the transistor region Tr are formed with high-concentration source/drain regions and extension regions. Therefore, the extendable range of a depletion layer is kept wide to extend the capacitance variable range of the varactor.

Abstract: A high-density Germanium (Ge)-on-Insulator (GOI) photodiode array and corresponding fabrication method are provided. The method includes: forming an array of pixel driver nMOST devices, each device having a gate connected to a row line in a first orientation, a first source/drain (S/D) region, and a second S/D region connected to Vdd; forming a P-I-N Ge diode for each pixel as follows: forming a n+ region; forming an intrinsic Ge region overlying the n+ region; forming a p+ junction in the intrinsic Ge; and, isolating the P-I-N Ge diodes; and, forming an Indium Tin oxide (ITO) column in a second orientation, about orthogonal to the first orientation, overlying the P-I-N Ge diodes.

Abstract: A device for protecting I/O lines using low capacitance steering diodes (1200) and PIN or NIP diodes (1202), (1203) is disclosed. A low capacitance diode arrangement configured as steering diodes protect a signal line or input/output (I/O) port (1201) from high voltage transients by diverting or directing the transient to either the positive side of the power supply line (1204) or to ground (1205).

Abstract: It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer portion of the SOI layer (171) with a part of the SOI layer (171) remaining as a P? well region (169). Consequently, an isolation (partial isolation) structure is obtained. An N+ diffusion region (168) is formed in the SOI layer (171) between the isolating oxide films (167a) and (167b) and a P+ diffusion region (170) is formed in the SOI layer (171) between the isolating oxide films (167b) and (167c). Consequently, there is obtained a junction type variable capacitance (C23) having a PN junction surface of the P? well region (169) provided under the isolating oxide film (167b) and the N+ diffusion region (168).

Abstract: The invention relates to a semiconductor component which is capable of blocking such as an (IGBT), a thyristor, a GTO or diodes, especially schottky diodes. An insulator profile section (10a, 10b, 10c, 10d, 11) provided in the border area of an anode metallic coating (1, 31) is fixed (directly in the edge area) on the substrate (9) of the component. The insulator profile has a curved area (KB) and a base area (SB), said curved area having a surface (OF) which begins flat and curves outward and upward in a steadily increasing manner. A metallic coating (MET1; 30a, 30b, 30c, 30d, 31b) is deposited on the surface (OF). Said coating directly follows the surface curvature and laterally extends the inner anode metallic coating. The upper end of the curved metallic coating (MET1; 30a, 30b . . . ) is distanced and insulated from one of these surrounding outer metallic coatings (MET2; 3) by the surrounding base area (SB) of the insulator profile (10a, . . .

Abstract: A fuse used for redundancy function in a semiconductor device includes a pair of fuse terminals formed as a common layer with top interconnect lines by using a damascene technique, and a fuse element made of refractive metal and bridging the fuse terminals. The fuse element is formed as a common layer with the protective cover films covering the interconnect lines.

Abstract: A semiconductor device manufacturing method is used for packaging a thin semiconductor chip in an economical manner. A semiconductor chip having one electrode terminal, a first member having a first conductor on its surface, and a second member having a second conductor on its surface are prepared. The first and second members are positioned such that the first and second conductors face each other, and the semiconductor chip is held between the members. In this arrangement, one of the first and second conductors is in electrical contact with the first electrode.

Abstract: In one embodiment, a varactor includes a first node and a second node. The varactor includes: at least one first varactor element including a source, a drain, and a p-type doped gate; at least one second varactor element including a source, a drain, and an n-type doped gate; and at least one third varactor element including a source, a drain, and an intermediately doped gate, the intermediately doped gate having doping characteristics intermediate to doping characteristics of the p-type and n-type gates. The varactor includes one or more wells in a substrate region underlying the first, second, and third varactor elements. The first, second, and third varactor elements are coupled in parallel between the first and second nodes.

Abstract: An electronic component has at least a first diode and a second diode that are capacitance diodes. The characteristic curve of the second diode has a fixed, known relationship to that of the first diode. For example, the first diode and the second diode can have an identical variation ratio, being the quotient of the maximum and minimum adjustable capacitances. These components are suitable for use in television tuners, for example in three-band tuners, where diodes having the same characteristic curve and coming from different components are arranged and connected in each sub-receiving unit. The integration of a plurality of diodes reduces the number of components required, and also the time and cost involved in grouping together diodes with good synchronization properties.

Abstract: A monolithic bidirectional switch formed in a semiconductor substrate of type N, including a first main vertical thyristor, the rear surface layer of which is of type P, a second main vertical thyristor, the rear surface layer of which is of type N, an auxiliary vertical thyristor, the rear surface layer of which is of type P and is common with that of the first main thyristor, a peripheral region of type P especially connecting the rear surface layer of the auxiliary thyristor to the layer of this thyristor located on the other side of the substrate, a first metallization on the rear surface side, a second metallization on the front surface side connecting the front surface layers of the first and second thyristors. An additional region has a function of isolating the rear surface of the auxiliary thyristor and the first metallization.

Abstract: A semiconductor device includes a plurality of barrier layers and a plurality of quantum well layers which are alternately interleaved with each other and disposed on a substrate of semiconductor material so as to form a multiple-heterojunction varactor diode. The barrier layers and quantum well layers are doped with impurities. The varactor diode includes an ohmic contact which is electrically connected to a heavily doped embedded region and a Schottky contact which is electrically connected to a depletion region of the diode. The ohmic contact and the Schottky contact enable an external voltage source to be applied to the contacts so as to provide a bias voltage to the varactor diode. A variable capacitance is produced as a result of the depletion region varying with a variation in the bias voltage. The varactor diode also provides a constant series resistance.

Abstract: A set of radio frequency (RF) integrated circuits includes a transmit chip having a power amplifier and a receive chip adapted to work with the transmit chip. The receive chip has one or more low noise amplifiers to receive RF signals, and a processor coupled to the low noise amplifiers, the processor transmitting data through the transmit chip and receiving data from the on-chip low noise amplifiers.

Abstract: A varactor diode having a first electrode comprising a well region of a first conductivity type in a substrate, a second electrode comprising a first plurality of diffusion regions of a second conductivity type abutting isolation regions disposed in said well region, and a second plurality of diffusion regions of said first conductivity type extending laterally from portions of said first plurality of diffusion regions not adjacent said isolation regions and having a dopant concentration greater than that of said first plurality of diffusion regions. The varactor has a tunability of at least approximately 3.5 in a range of applied voltage between approximately 0V to 3V, an approximately linear change in capacitive value in a range of applied voltage between approximately 0V to 2V, and a Q of at least approximately 100 at a circuit operating frequency of approximately 2 GHz.

Abstract: A semiconductor device includes a plurality of diodes including a substrate of a first conductivity type biased to a reference potential, a well region of a second conductivity type formed in a surface region of the substrate, and a first diffusion region of the first conductivity type formed in a surface region of the well region, wherein the plurality of diodes have sizes of at least two kinds and are cascade-connected to each other.

Abstract: A varactor circuit having an increased tuning range comprises a first varactor in series with a second varactor between first and second terminals. A resistor is connected between the first and second terminals. A tap of the resistor is connected to a junction of the first and second varactors. This circuit effectively doubles tuning range compared to a single varactor.

Abstract: A configuration for a conventional lead frame for conserving limited leads and for allowing the location of bond pads anywhere on the periphery of the semiconductor device and for reducing the cost of tooling changes by permitting the use of current tooling. The present invention utilizes an extended lead finger that extends along the periphery of a semiconductor device to provide a power source or ground so that any number of bond pads may be used in any position without requiring additional leads or tooling changes.

Abstract: A set of radio frequency (RF) integrated circuits includes a transmit chip having a power amplifier and a receive chip adapted to work with the transmit chip. The receive chip has one or more low noise amplifiers to receive RF signals, and a processor coupled to the low noise amplifiers, the processor transmitting data through the transmit chip and receiving data from the on-chip low noise amplifiers.