With Electrical Contact In Hole In Semiconductor (e.g., Lead Extends Through Semiconductor Body) Patents (Class 257/621)
  • Patent number: 10420171
    Abstract: An integrated circuit device includes only semiconductor devices with a same first polarity on one side of an insulator layer and only semiconductor devices with a different second polarity on an opposite side of the insulator layer to reduce size and complexity of the integrated circuit device as well as reducing the process steps associated with fabricating the integrated circuit device. Shared contacts between backside source/drain regions or spacers of the semiconductor devices with the first polarity and front-side source/drain regions or spacers of the semiconductor devices with the first polarity are used to connect the semiconductor devices on opposite sides of the insulator layer.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: September 17, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: Sinan Goktepeli
  • Patent number: 10403618
    Abstract: A semiconductor device assembly that includes a first side of a semiconductor device supported on a substrate to permit the processing of a second side of the semiconductor device. A filler material deposited on the semiconductor device supports the semiconductor device on the substrate. The filler material does not adhere to the semiconductor device or the substrate. Alternatively, the filler material may be deposited on the substrate. Instead of a filler material, the substrate may include a topography configured to support the semiconductor device. Adhesive applied between an outer edge of the first side of the semiconductor and the substrate bonds the outer edge of the semiconductor device to the substrate to form a semiconductor device assembly. A second side of the semiconductor device may then be processed and the outer edge of the semiconductor device may be cut off to release the semiconductor device from the assembly.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Chandra S. Tiwari, Tony M. Lindenberg, Jonathan S. Hacker, Christopher J. Gambee, Kurt J. Bossart
  • Patent number: 10396024
    Abstract: A wiring substrate includes a first insulating layer including a first through-hole formed through the first insulating layer in a thickness direction, a wiring layer formed on a lower surface of the first insulating layer, and a via wiring filled in the first through-hole and connected to the wiring layer, the via wiring having such a shape that it gradually becomes thinner from one side close to the lower surface of the first insulating layer toward the other side close to an upper surface of the first insulating layer, the via wiring including a first recess formed in an upper end surface of the via wiring. An upper end portion of the via wiring is an electrode pad for electric connection with an electronic component.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: August 27, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Kosuke Tsukamoto
  • Patent number: 10388681
    Abstract: The present disclosure relates to a solid-state image pickup apparatus and an electronic apparatus capable of preventing charges accumulated in a PD from being lost and suppressing reductions of an S/N and a dynamic range. The apparatus according to an embodiment of the present disclosure includes: a photoelectric conversion unit; a first holding unit that holds the charge transferred from the photoelectric conversion unit; a first transfer gate unit that controls the transfer of the charge; a charge drain unit that is a drain destination of the charge generated by the photoelectric conversion unit; a first drain gate unit that controls the transfer of the charge from the photoelectric conversion unit to the charge drain unit; and a second drain gate unit that connects the charge drain unit with a constant voltage source. The present disclosure can be applied to a CIS and an electronic apparatus provided with the CIS.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: August 20, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Hiroyuki Ohri
  • Patent number: 10381377
    Abstract: A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the material. The etch mask comprises an elevationally-extending mask opening in the silicon nitride-comprising region that has a minimum horizontal open dimension that is greater in an elevationally-innermost portion of the region than in an elevationally-outermost portion of the region. The elevationally-outermost portion has a greater etch rate in at least one of HF and H3PO4 than does the elevationally-innermost portion. The etch mask is used as a mask while etching an elevationally-extending mask opening into the material. The silicon nitride-comprising region is exposed to at least one of HF and H3PO4 to increase the minimum horizontal open dimension in the elevationally-outermost portion to a greater degree than increase, if any, in the minimum horizontal open dimension in the elevationally-innermost portion.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Fei Wang, Tom J. John, Kunal Shrotri, Anish A. Khandekar, Aaron R. Wilson, John D. Hopkins, Derek F. Lundberg
  • Patent number: 10347606
    Abstract: A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Wei-Yu Chen, Ying-Ju Chen, Tsung-Shu Lin, Chin-Chuan Chang, Hsien-Wei Chen, Wei-Cheng Wu, Li-Hsien Huang, Chi-Hsi Wu, Der-Chyang Yeh
  • Patent number: 10347592
    Abstract: An integrated circuit (IC) device includes a device layer and a passivation layer, where the passivation layer has vias formed in an interior region of the passivation layer that are larger than vias formed in a perimeter region of the passivation layer. As such, a varying diameter via layer is provided. The interior region vias may be configured to reduce a risk of damage to the IC device due to tensile stress, with sizes or shapes selected based on the amount of tensile stress expected to occur during subsequent use of the IC device. The perimeter region vias may be configured to reduce a risk of damage to the IC device due to sheer stress, with sizes or shapes selected based on the amount of sheer stress expected to occur during subsequent assembly or use of the IC device. Method and apparatus examples are described for use with flip-chip dies.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: July 9, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: William Michael Stone
  • Patent number: 10325946
    Abstract: A packaging method and a package for an image sensing chip are provided. The packaging method includes: providing a wafer including a first surface and a second surface opposite to the first surface, where the wafer has multiple image sensing chips arranged in a grid, each of the image sensing chips has an image sensing region and contact pads arranged on a side of the first surface; forming an opening corresponding to each of the contact pads and cutting trenches on a side of the second surface of the wafer, where the contact pad is exposed through the opening; filling the cutting trenches with a first photosensitive ink; and applying a second photosensitive ink on the second surface of the wafer to cover the opening with the second photosensitive ink and form a hollow cavity in the opening.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: June 18, 2019
    Assignee: China Wafer Level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Zhuowei Wang, Guoliang Xie
  • Patent number: 10319611
    Abstract: A semiconductor device package includes a substrate having a first surface and a second surface facing away from the first surface, a conductive column extending in the substrate between the first surface and the second surface, a dielectric layer on the first surface of the substrate, a redistribution structure provided in the dielectric layer and electrically connected to the conductive column, a semiconductor chip provided above the dielectric layer and electrically connected to the redistribution structure, and an encapsulation layer on the dielectric layer and encapsulating the semiconductor chip. The package is manufactured such that each of the substrate and the encapsulation layer is formed of molding compound.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: June 11, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yinan Li
  • Patent number: 10319668
    Abstract: An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: June 11, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Ho Do, Tae-Joong Song, Seung-Young Lee, Jong-Hoon Jung
  • Patent number: 10319673
    Abstract: An interconnection component includes a first support portion, a second support portion, a redistribution layer and a passive device, wherein at least one of the first and second support portions is comprised of a semiconductor material. The first support portion includes first and second opposed major surfaces and a plurality of first conductive vias extending through the first support portion substantially perpendicular to major surfaces. The second support portion includes first and second opposed major surfaces and a plurality of second conductive vias extending through the second support portion substantially perpendicular to the first and second major surfaces of the second support. The redistribution layer can be disposed between the second surfaces of the first and second support portions. The passive device can be positioned at least partially within the redistribution layer and electrically connected with one or more of the first conductive vias and the second conductive vias.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: June 11, 2019
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Kishor Desai
  • Patent number: 10312389
    Abstract: An optical detector device may include a substrate, a reflector layer carried by the substrate, and a first dielectric layer over the reflector layer. The optical detector device may include a graphene layer over the first dielectric layer and having a perforated pattern.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: June 4, 2019
    Assignee: UNIVERSITY OF CENTRAL FLORIDA RESEARCH FOUNDATION, INC.
    Inventors: Debashis Chanda, Alireza Safaei, Michael Leuenberger
  • Patent number: 10304818
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first semiconductor chip including a first substrate and a first conductive feature formed over the first substrate, and a second semiconductor chip bonded to the first semiconductor chip. The second semiconductor chip includes a second substrate and a second conductive feature formed over the second substrate. A conductive plug is disposed through the first conductive feature and is coupled to the second conductive feature. The conductive plug includes a first portion disposed over the first conductive feature, the first portion having a first width, and a second portion disposed beneath or within the first conductive feature. The second portion has a second width. The first width is greater than the second width.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: May 28, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Szu-Ying Chen, U-Ting Chen
  • Patent number: 10290495
    Abstract: According to one embodiment, an electronic apparatus includes a first substrate including a first basement and a first conductive layer, a second substrate including a second basement, which is opposed to the first conductive layer and is separated from the first conductive layer, a second conductive layer, and a first hole penetrating the second basement, and a connecting material which electrically connects the first conductive layer and the second conductive layer via the first hole.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: May 14, 2019
    Assignee: Japan Display Inc.
    Inventors: Yoshikatsu Imazeki, Shoji Hinata
  • Patent number: 10276514
    Abstract: A semiconductor structure includes a semiconductor device, a first seal ring, a second seal ring, and a plurality of through semiconductor vias (TSV). The semiconductor device has a first surface and a second surface opposite to the first surface. The first seal ring is disposed on the first surface of the semiconductor device and is adjacent to edges of the first surface. The second seal ring is disposed on the second surface of the semiconductor device and is adjacent to edges of the second surface. The TSVs penetrate through the semiconductor device and physically connect the first seal ring and the second seal ring.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Rung-De Wang, Chen-Hsun Liu, Chin-Yu Ku, Te-Hsun Pang, Chia-Hua Wang, Pei-Shing Tsai, Po-Chang Lin
  • Patent number: 10236208
    Abstract: The present disclosure relates to a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a semiconductor substrate having a first surface and a second surface opposite the first surface. The semiconductor substrate has a space extending from the second surface to the first surface and an insulation body is disposed in the space. The semiconductor package structure includes conductive posts in the insulation body.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: March 19, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chin-Cheng Kuo, Pao-Nan Lee, Chih-Pin Hung, Ying-Te Ou
  • Patent number: 10211233
    Abstract: According to one embodiment, a display device includes a first substrate including a support substrate, a light shield, an insulating substrate disposed above the support substrate and the light shield and including a through hole, a pad electrode formed above the insulating substrate, and a signal line electrically connected to the pad electrode, and a first substrate including, in a plan view, a first area in which the support substrate and the light shield are disposed and a second area in which the through hole is disposed, a line substrate including a connection line and disposed below the insulating substrate, and a conductive material disposed inside the through hole to electrically connect the pad electrode and the connection line.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: February 19, 2019
    Assignee: Japan Display Inc.
    Inventors: Yasushi Kawata, Takumi Sano
  • Patent number: 10197872
    Abstract: A liquid crystal display apparatus includes a conductive paste, which connects a connection pad in a TFT array substrate and a transparent conductive film in a color filter substrate, and a ridge which is disposed adjacent to a conductive paste in a surrounding region of the TFT array substrate. A sealing member located between the color filter substrate and the TFT array substrate convexly extends in a direction from a display region to a surrounding region to form the ridge.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: February 5, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takahiro Ueno, Hisatomo Ota, Shingo Sonoda
  • Patent number: 10199274
    Abstract: A method is provided for producing at least one electrical via in a substrate, the method comprising: producing a protective layer over a component structure which has been produced or is present on a front side of the substrate; forming at least one contact hole which extends from a surface of a backside of the substrate to a contact surface of the component structure; forming a metal-containing and thus conductive lining in the at least one contact hole creating a hollow electrically conductive structure in the at least one contact hole; and applying a passivation layer over the backside of the substrate, the passivation layer spanning over the hollow electrically conductive structure for forming the at least one electrical via. Also provided is a micro-technical component comprising at least one electrical via.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: February 5, 2019
    Assignee: X-FAB Semiconductor Foundries GmbH
    Inventors: Roy Knechtel, Sophia Dempwolf, Daniela Guenther, Uwe Schwarz
  • Patent number: 10192813
    Abstract: A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: January 29, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Kambiz Samadi, Shreepad A. Panth, Yang Du, Robert P. Gilmore
  • Patent number: 10192853
    Abstract: The present disclosure provides a method for preparing a semiconductor apparatus. The semiconductor apparatus includes a first semiconductor die and a second semiconductor die stacked onto the first semiconductor die in a horizontally shifted manner. The first semiconductor die includes a first chip selection terminal and a first lower terminal electrically connected to the first chip selection terminal. The second semiconductor die includes a second chip selection terminal electrically connected to a first upper terminal of the first semiconductor die via a second lower terminal of the second semiconductor die. The first upper terminal which is electrically connected to the second chip selection terminal is not electrically connected to the first lower terminal which is electrically connected to the first chip selection terminal.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: January 29, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Po-Chun Lin, Chin-Lung Chu
  • Patent number: 10173891
    Abstract: There is provided a MEMS device which includes a second substrate which is disposed with an interval from a first substrate, and an interposed member which is interposed between the first substrate and the second substrate, and which has space which is defined by the first substrate, the second substrate, and the interposed member, in which the first substrate includes a wiring which extends from a first surface side which is a surface on a side opposite to the second substrate toward a second surface side which is a surface of the second substrate side and is made of a conductor, in which an end portion of the first surface side of the wiring is covered by a first protective film provided on the first surface side, and in which an end portion of the second surface side of the wiring faces the space.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: January 8, 2019
    Assignee: Seiko Epson Corporation
    Inventor: Masashi Yoshiike
  • Patent number: 10170392
    Abstract: Techniques for wafer level integration of embedded cooling structures for integrated circuit devices are provided. In one embodiment, a method includes forming channel structures on a first surface of a silicon first wafer, wherein the channel structures respectively include radial channels that extend from central fluid distribution areas, and wherein integrated circuits are formed on a second surface of the silicon first wafer that opposes the first surface. The method can further include bonding a manifold wafer to the first surface of the silicon wafer such that inlet openings formed through the manifold wafer respectively connect to the central fluid distribution areas, thereby enclosing the radial channels and forming a bonded structure.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy Joseph Chainer, Pritish Ranjan Parida, Mark Delorman Schultz
  • Patent number: 10170360
    Abstract: A reflow enhancement layer is formed in an opening prior to forming and reflowing a contact metal or metal alloy. The reflow enhancement layer facilitates the movement (i.e., flow) of the contact metal or metal alloy during a reflow anneal process such that a void-free metallization structure of the contact metal or metal alloy is provided.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten
  • Patent number: 10163824
    Abstract: An integrated fan-out package including an insulating encapsulation, a radio frequency integrated circuit (RF-IC), an antenna, a ground conductor, and a redistribution circuit structure is provided. The integrated circuit includes a plurality of conductive terminals. The RF-IC, the antenna, and the ground conductor are embedded in the insulating encapsulation. The ground conductor is between the RF-IC and the antenna. The redistribution circuit structure is disposed on the insulating encapsulation, and the redistribution circuit structure is electrically connected to the conductive terminals, the antenna, and the ground conductor. A method of fabricating the integrated fan-out package is also provided.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shou-Zen Chang, Chung-Hao Tsai, Chuei-Tang Wang, Kai-Chiang Wu, Ming-Kai Liu
  • Patent number: 10157792
    Abstract: A through substrate via (TSV) and method of forming the same are provided. The method of making the TSV may include etching a via opening into the backside of semiconductor substrate, the via opening exposing a surface of a metal landing structure. A conductive layer is deposited over the backside of semiconductor substrate, sidewalls of the via opening, and exposed surface of the metal landing structure. The conductive layer is coated with a polymer material, filling the via opening. The polymer material is developed to remove the polymer material from the backside of semiconductor substrate, leaving the via opening filled with undeveloped polymer material. A planar backside surface of semiconductor substrate is formed by removing the conductive layer.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: December 18, 2018
    Assignee: NXP USA, INC.
    Inventors: Qing Zhang, Lianjun Liu
  • Patent number: 10147704
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first integrated circuit die, a second integrated circuit die coupled to the first integrated circuit die, and a through-via coupled between a first conductive feature of the first integrated circuit die and second conductive feature of the second integrated circuit die. A conductive shield is disposed around a portion of the through-via.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: December 4, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Pin Yuan, Chen-Hua Yu, Ming-Fa Chen
  • Patent number: 10141362
    Abstract: A semiconductor device having a protection layer wrapping around a conductive structure is provided. The semiconductor device comprises an image sensor device layer, an interconnect layer over the image sensor device layer, a first bonding layer over the interconnect layer, a second bonding layer bonded with the first bonding layer, a substrate over the second bonding layer, and a conductive via passing through the substrate, the second bonding layer, and the first bonding layer. The conductive via comprises a protection layer and a conductive material. The protection layer is peripherally enclosed by the substrate, the second bonding layer, and the first bonding layer. The protection layer covers a sidewall cut formed at an interface of the second bonding layer and the first bonding layer. The conductive material is peripherally enclosed by the protection layer.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: November 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Wei Sung, Yi-Hung Chen, Keng-Ying Liao, Yi-Fang Yang, Chih-Yu Wu
  • Patent number: 10133133
    Abstract: A liquid crystal display base includes a liquid crystal module, both a power circuit and a integration circuit, a electric device mounted on the power circuit. The liquid crystal module includes a TFT array substrate and a color filter substrate mounted on the TFT array substrate. The power circuit board mounted on the TFT array substrate. The TFT array substrate has a first surface and a second surface opposite to the first surface, a plurality of through holes extend through the first surface and the second surface, each through hole has equal inner diameter from the first surface to the second surface. the TFT array substrate 11 is made of glass, sapphire, ceramic, a plurality of conductive layers are in the plurality of through holes, both the electric device, the integration circuit and the power circuit board are coupled with the liquid crystal module.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: November 20, 2018
    Assignee: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC
    Inventors: Hsin-Chiang Lin, Chien-Cheng Kuo, Pin-Chuan Chen, Lung-Hsin Chen, Wen-Liang Tseng
  • Patent number: 10121799
    Abstract: A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the material. The etch mask comprises an elevationally-extending mask opening in the silicon nitride-comprising region that has a minimum horizontal open dimension that is greater in an elevationally-innermost portion of the region than in an elevationally-outermost portion of the region. The elevationally-outermost portion has a greater etch rate in at least one of HF and H3PO4 than does the elevationally-innermost portion. The etch mask is used as a mask while etching an elevationally-extending mask opening into the material. The silicon nitride-comprising region is exposed to at least one of HF and H3PO4 to increase the minimum horizontal open dimension in the elevationally-outermost portion to a greater degree than increase, if any, in the minimum horizontal open dimension in the elevationally-innermost portion.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: November 6, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Fei Wang, Tom J. John, Kunal Shrotri, Anish A. Khandekar, Aaron R. Wilson, John D. Hopkins, Derek F. Lundberg
  • Patent number: 10115635
    Abstract: A wafer via solder filling device includes a solder bath comprising an accommodation space for accommodating a molten solder, with an open top, and an air outlet for exhausting air from the accommodation space; a fixing unit for fixing the wafer having a via formed in one surface in the accommodation space to seal the accommodation space airtight; and a pressing unit for pressing a bottom of the molten solder arranged in the solder bath and moving the molten solder upward, to fill the molten solder in the via.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: October 30, 2018
    Assignee: KOREA INSTITUTE OF INDUSTRIAL TECHNOLOGY
    Inventors: Sehoon Yoo, Chang Woo Lee, Jun Ki Kim, Jeong Han Kim, Young Ki Ko
  • Patent number: 10087072
    Abstract: A microelectromechanical system structure and a method for fabricating the same are provided. A method for fabricating a MEMS structure includes the following steps. A first substrate is provided, wherein a transistor, a first dielectric layer and an interconnection structure are formed thereon. A second substrate is provided, wherein a second dielectric layer and a thermal stability layer are formed on the second substrate. The first substrate is bonded to the second substrate, and the second substrate removed. A conductive layer is formed within the second dielectric layer and electrically connected to the interconnection structure. The thermal stability layer is located between the conductive layer and the interconnection structure. A growth temperature of a material of the thermal stability layer is higher than a growth temperature of a material of the conductive layer and a growth temperature of a material of the interconnection structure.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: October 2, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Chang-Sheng Hsu, Chih-Fan Hu, Chia-Wei Lee, En Chan Chen, Shih-Wei Li
  • Patent number: 10090213
    Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: October 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzuan-Horng Liu, Chen-Hua Yu, Hsien-Pin Hu, Tzu-Yu Wang, Wei-Cheng Wu, Shang-Yun Hou, Shin-Puu Jeng
  • Patent number: 10074594
    Abstract: A semiconductor structure includes a substrate including a first side, a second side opposite to the first side, and a device layer over the second side, and a conductive via extending through the substrate, and including a first portion adjacent to the first side and a second portion adjacent to the device layer, wherein the conductive via includes an interface between the first portion and the second portion, an average grain size of the first portion is substantially different from an average grain size of the second portion.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: September 11, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Li-Yen Fang, Chih-Chang Huang, Jung-Chih Tsao, Yao-Hsiang Liang, Yu-Ku Lin
  • Patent number: 10049926
    Abstract: A dielectric material stack including at least a via level dielectric material layer, at least one patterned etch stop dielectric material portion, a line level dielectric material layer, and optionally a dielectric cap layer is formed over a substrate. At least one patterned hard mask layer including a first pattern can be formed above the dielectric material stack. A second pattern is transferred through the line level dielectric material layer employing the at least one etch stop dielectric material portion as an etch stop structure. The first pattern is transferred through the line level dielectric material layer employing the at least one etch stop dielectric material portion as an etch stop structure while the second pattern is transferred through the via level dielectric material layer to form integrated line and via trenches, which are filled with a conductive material to form integrated line and via structures.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: August 14, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Junjing Bao, Wai-Kin Li
  • Patent number: 10043755
    Abstract: An electronic device includes a first wiring substrate and a semiconductor device mounted on the first wiring substrate. The semiconductor device includes a second wiring substrate having a plurality of terminals, a plurality of first semiconductor chips mounted on the second wiring substrate, and a second semiconductor chip mounted on the second wiring substrate. The first wiring substrate includes a first power supply line and a second power supply line supplying a plurality of power supply potentials, whose types are different from each other, to the second semiconductor chip. In a plan view, the second power supply line is arranged to cross over a first substrate side of the second wiring substrate and a first chip side of the second semiconductor chip. In a plan view, the first power supply line is arranged to pass between the second power supply line and a part of the plurality of first semiconductor chips and to extend toward a region overlapping with the second semiconductor chip.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: August 7, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takafumi Betsui, Motoo Suwa
  • Patent number: 10032737
    Abstract: A semiconductor device includes a substrate includes a first layer and a second layer over the first layer, a bump disposed over the second layer, a molding disposed over the second layer and surrounding the bump, and a retainer disposed over the second layer, wherein the retainer is disposed between the molding and a periphery of the substrate. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing several bumps on the substrate, disposing a retainer on the substrate and surrounding the bumps, and disposing a molding between the bumps and the retainer.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: July 24, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tung-Liang Shao, Yu-Chia Lai, Hsien-Ming Tu, Chang-Pin Huang, Ching-Jung Yang
  • Patent number: 9984956
    Abstract: Provided are a through electrode including an organic side-wall insulating film, capable of eliminating a barrier layer and achieving satisfactory mechanical reliability and electrical reliability and a manufacturing method thereof, and a semiconductor device and a manufacturing method thereof. According to one aspect of the present invention, a through electrode disposed in a semiconductor substrate is provided, including: a copper layer in the semiconductor substrate; and a side-wall insulating film that is disposed between the copper layer and the semiconductor substrate so as to be in contact with the copper layer and the semiconductor substrate, the side-wall insulating film being represented by the following chemical formula (1).
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: May 29, 2018
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Masahiro Aoyagi, Tung Thanh Bui, Naoya Watanabe, Fumiki Kato, Katsuya Kikuchi
  • Patent number: 9964788
    Abstract: A liquid crystal display structure includes a liquid crystal display panel, a backlight assembly arranged on one side of the liquid crystal display panel, and a polarizer arranged on a side of the liquid crystal display panel opposite from the backlight assembly. The liquid crystal display structure includes a display area and a non-display area surrounding the display area. The polarizer includes a first section and a second section, the first section being located in a central portion of the polarizer and corresponding in position to the display area, and the second section surrounding the first section and corresponding to the non-display area. The second section of the polarizer defines at least one through hole between every two adjacent corners of the second section.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: May 8, 2018
    Assignee: Century Technology (Shenzhen) Corporation Limited
    Inventors: Hai-Bo Peng, Chen-Fu Mai, Ping Liu
  • Patent number: 9966349
    Abstract: A semiconductor memory device and front-end method of fabricating nickel plated caps over bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication. In some examples, the method and device include one or more conductive and insulating layers formed over a substrate, and a plurality of memory cells over the conductive and insulating layers.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: May 8, 2018
    Assignee: OVONYX MEMORY TECHNOLOGY, LLC
    Inventors: John Moore, Joseph F. Brooks
  • Patent number: 9960081
    Abstract: A method for selective etching using a dry film photoresist includes forming an opening through a substrate from a first surface to expose a stop layer at a second surface of the substrate. A material layer is formed over an inner surface of the opening and over the stop layer. The dry film photoresist is applied over the first surface of the substrate and over the opening. A second photoresist is applied on the dry film photoresist. First and second aligned holes are formed in the second photoresist and the dry film photoresist, respectively. The holes are approximately centered over the opening and are smaller in diameter than the opening so that a composite structure of the dry film photoresist and the second photoresist overhangs edges of the opening. The material layer is removed from the stop layer by etching via the first and second holes.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: May 1, 2018
    Assignee: NXP USA, Inc.
    Inventors: Colin Bryant Stevens, Lianjun Liu, Ruben B. Montez
  • Patent number: 9941210
    Abstract: An embodiment of a semiconductor die includes a base semiconductor substrate and an electrically conductive through substrate via (TSV) extending between the surfaces of the base semiconductor substrate. The bottom surface of the base semiconductor substrate includes a recessed region proximate to the TSV so that an end of the TSV protrudes from the bottom surface, and so that the TSV sidewall has an exposed portion at the protruding end of the TSV. Back metal, consisting of one or more metallic layers, is deposited on the bottom surface of the base semiconductor substrate and in contact with the TSV. The back metal can include a gold layer, a sintered metallic layer, and/or a plurality of other conductive layers. The die may be attached to a substrate using solder, another sintered metallic layer, or other materials.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: April 10, 2018
    Assignee: NXP USA, INC.
    Inventors: Lakshminarayan Viswanathan, Jaynal A. Molla, Mali Mahalingam, Colby Rampley
  • Patent number: 9926422
    Abstract: A material includes a base resin; a solvent; and a foaming agent and a photosensitizer, and/or a substance that serves as a foaming agent and a photosensitizer.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: March 27, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Junichi Kon
  • Patent number: 9917061
    Abstract: A semiconductor apparatus includes a chip ID generation unit, a chip ID transmission unit and a chip stack information generation unit. The chip ID generation unit is configured to generate a chip ID signal. The chip ID transmission unit is configured to output the chip ID signal to a common line on the basis of whether another chip is electrically coupled therewith. The chip stack information generation unit is configured to be electrically coupled with the common line in response to the chip ID signal and generate a stack information signal.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: March 13, 2018
    Assignee: SK hynix Inc.
    Inventor: Sang Jin Byeon
  • Patent number: 9911643
    Abstract: Some embodiments include semiconductor constructions having first and second electrically conductive lines that intersect with one another at an intersection. The first line has primarily a first width, and has narrowed regions directly against the second line and on opposing sides of the second line from one another. Electrically conductive contacts are along the first line and directly electrically coupled to the first line, and one of the electrically conductive contacts is directly against the intersection. Some embodiments include methods of forming intersecting lines of material. First and second trenches are formed, and intersect with one another at an intersection. The first trench has primarily a first width, and has narrowed regions directly against the second trench and on opposing sides of the second trench from one another. Material is deposited within the first and second trenches to substantially entirely fill the first and second trenches.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: March 6, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Hongqi Li, Gowrisankar Damarla, Robert J. Hanson, Jin Lu, Shyam Ramalingam
  • Patent number: 9904009
    Abstract: A through-silicon-via structure formed within a semiconductor device is provided. The TSV structure may include a trench located within a substrate of the semiconductor device, an insulator layer located on at least one side wall of the trench, an electrically conductive layer located on the insulator layer, a first dielectric layer located on the electrically conductive layer, and a second dielectric layer located on the first dielectric layer and filling the trench. The second dielectric layer includes a higher refractive index relative to the first dielectric layer, such that the first and the second dielectric layer create an optical waveguide.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: February 27, 2018
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 9899261
    Abstract: A semiconductor package structure having a substrate, wherein the substrate has a front side and a back side, a through silicon via (TSV) interconnect structure formed in the substrate, and a first guard ring doped region and a second guard ring doped region formed in the substrate. The second guard ring doped region is disposed between the first guard ring doped region and the TSV interconnect structure.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: February 20, 2018
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Chou Hung, Ming-Tzong Yang, Tung-Hsing Lee, Wei-Che Huang, Yu-Hua Huang, Tzu-Hung Lin
  • Patent number: 9899308
    Abstract: A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurrence of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: February 20, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Wen-Tsung Tseng, Yi-Che Lai, Shih-Kuang Chiu, Mao-Hua Yeh
  • Patent number: 9881873
    Abstract: A fan-out semiconductor package includes a frame having a through hole, a semiconductor chip disposed in the through hole and including connection pads, an encapsulant encapsulating at least a portion of the frame and the semiconductor chip, and a redistribution layer disposed on the frame and the semiconductor chip and including a first region and a second region. In the first region, a first via and a second via, electrically connected to one of the connection pads, disposed in different layers, and connected by a wiring pattern, are disposed. In the second region, a third via and a fourth via, electrically connected to another of the connection pads, disposed in different layers, and connected by the wiring pattern, are disposed. A distance between axes of the first via and the second via is shorter than a distance between axes of the third via and the fourth via.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: January 30, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Kyung Seob Oh, Kyoung Moo Harr, Doo Hwan Lee, Seung Chul Oh, Hyoung Joon Kim, Yoon Suk Cho
  • Patent number: 9881990
    Abstract: A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: January 30, 2018
    Assignee: INTEL CORPORATION
    Inventors: Andreas Duevel, Telesphor Kamgaing, Valluri R. Rao, Uwe Zillmann