With Electrical Contact In Hole In Semiconductor (e.g., Lead Extends Through Semiconductor Body) Patents (Class 257/621)
  • Patent number: 11380726
    Abstract: A sensor device including an interposer including a first via and a lower pad, the lower pad being on a bottom surface of the interposer; an image sensor chip on a top surface of the interposer, the image sensor chip including a logic chip and a sensing chip on the logic chip, the logic chip including first wiring patterns and a second via, and the sensing chip including second wiring patterns; a conductive structure penetrating a portion of the logic chip and the sensing chip, the conductive structure being connected to at least one of the first wiring patterns and at least one of the second wiring patterns; and a passivation layer on an inner surface of the conductive structure, wherein a side surface of the interposer is coplanar with a side surface of the image sensor chip.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: July 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyunsu Jun
  • Patent number: 11355379
    Abstract: A method of fabricating a semiconductor structure includes forming a scissionable layer that is able to absorb infrared (IR) radiation, below a first carrier wafer. A first hard-dielectric layer is formed below the scissionable layer. A second hard-dielectric layer is formed on a top surface of a semiconductor wafer. The first dielectric layer is bonded with the second dielectric layer. Connectors on a bottom portion of the semiconductor wafer are formed to provide an electric connection to the semiconductor wafer. A second carrier wafer is connected to the connectors on the bottom portion of the semiconductor wafer. The first carrier wafer is separated from the semiconductor wafer by degrading the scissionable layer with an IR, by passing the IR through the first carrier wafer. A back end of line (BEOL) wiring passing from a top surface of the semiconductor wafer through the first and second dielectric layers is provided.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: June 7, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mukta Ghate Farooq, Dale Curtis McHerron, Spyridon Skordas
  • Patent number: 11348879
    Abstract: A semiconductor structure includes a semiconductor device, a plurality of through semiconductor vias (TSV), a first seal ring, and a second seal ring. The TSVs penetrate through the semiconductor device. The TSVs are adjacent to an edge of the semiconductor device. The first seal ring is disposed on and physically connected to one end of each of the TSVs. The second seal ring is disposed on and physically connected to another end of each of the TSVs.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: May 31, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Rung-De Wang, Chen-Hsun Liu, Chin-Yu Ku, Te-Hsun Pang, Chia-Hua Wang, Pei-Shing Tsai, Po-Chang Lin
  • Patent number: 11329092
    Abstract: The present disclosure relates to a semiconductor device, a manufacturing method of the semiconductor device, and electronic equipment that are directed to improving quality and reliability of a semiconductor device including a through electrode, or electronic equipment. The semiconductor device includes a first semiconductor substrate including a through electrode, a first insulating film laminated on a first surface of the first semiconductor substrate, and a second insulating film laminated on the first insulating film, in which an inner wall and a bottom surface of the through electrode are covered with a conductor, the first insulating film and the second insulating film are laminated on the conductor, and the through electrode includes a groove which reaches the first insulating film on the bottom surface from the first surface of the first semiconductor substrate. The present technology may be applied to a packaged solid-state imaging device or the like, for example.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: May 10, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Tomohiro Sugiyama
  • Patent number: 11322421
    Abstract: Provided is a package structure including a composite wafer, a plurality of dies, an underfill, and a plurality of dam structures. The composite wafer has a first surface and a second surface opposite to each other. The composite wafer includes a plurality of seal rings dividing the composite wafer into a plurality of packages; and a plurality of through holes respectively disposed between the seal rings and penetrating through the first and second surfaces. The dies are respectively bonded onto the packages at the first surface by a plurality of connectors. The underfill laterally encapsulates the connectors. The dam structures are disposed on the first surface of the composite wafer to separate the underfill from the through holes.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mao-Yen Chang, Chih-Wei Lin, Hao-Yi Tsai, Kuo-Lung Pan, Chun-Cheng Lin, Tin-Hao Kuo, Yu-Chia Lai, Chih-Hsuan Tai
  • Patent number: 11302640
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a first electrode extending in a first direction through the semiconductor substrate between the first surface and the second surface, a first wiring layer on the first surface and electrically connected to the first electrode, and a second wiring layer on the first wiring layer, the first wiring layer being between the semiconductor substrate and the second wiring layer in the first direction. The second wiring layer includes a connection region at which a second electrode is connected and a first air gap between the connection region and an outer edge of the second wiring layer in a second direction crossing the first direction.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: April 12, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Motoshi Seto, Hitomi Kawaguchiya
  • Patent number: 11296031
    Abstract: An apparatus is provided which comprises: a substrate, the substrate comprising crystalline material, a first set of one or more contacts on a first substrate surface, a second set of one or more contacts on a second substrate surface, the second substrate surface opposite the first substrate surface, a first via through the substrate coupled with a first one of the first set of contacts and with a first one of the second set of contacts; a second via through the substrate coupled with a second one of the first set of contacts and with a second one of the second set of contacts, a trench in the substrate from the first substrate surface toward the second substrate surface, wherein the trench is apart from, and between, the first via and the second via, and dielectric material filling the trench. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: April 5, 2022
    Assignee: Intel Corporation
    Inventors: Kemal Aygun, Zhiguo Qian, Jianyong Xie
  • Patent number: 11296032
    Abstract: An array of through-silicon via (TSV) structures is formed through a silicon substrate, and package-side metal pads are formed on backside surfaces of the array of TSV structures. The silicon substrate is disposed over a carrier substrate, and an encapsulant interposer frame, such as an epoxy molding compound (EMC) interposer frame is formed around the silicon substrate. A die-side redistribution structure is formed over the silicon substrate and the EMC interposer frame, and at least one semiconductor die is attached to the die-side redistribution structure. The carrier substrate is removed from underneath the package-side metal pads. A package-side redistribution structure is formed on the package-side metal pads and on the EMC interposer frame. Overlay tolerance between the package-side redistribution wiring interconnects and the package-side metal pads increases due to increased areas of the package-side metal pads.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsien-Ju Tsou, Chih-Wei Wu, Ying-Ching Shih, Szu-Wei Lu
  • Patent number: 11270977
    Abstract: An apparatus includes a first die including a first substrate with first TSVs running through it, a first top metal layer and first chimney stack vias (CSVs) connecting the first TSVs with the first top metal layer. The apparatus further includes an uppermost die including an uppermost substrate and an uppermost top metal layer, and uppermost CSVs connecting the uppermost substrate with the uppermost top metal layer. The first and uppermost dies are stacked face to face, the first TSVs and the first CSVs are mutually aligned, and the dies are configured such that current is delivered to the apparatus from the first TSVs up through the first CSVs, the first and uppermost top metal layers, and the uppermost CSVs.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: March 8, 2022
    Assignee: XILINX, INC.
    Inventors: Praful Jain, Steven P. Young, Martin L. Voogel, Brian C. Gaide
  • Patent number: 11264295
    Abstract: Integrated circuit substrates having features for containing liquid adhesive, and methods for fabricating such substrates, are provided. A device can include a first substrate layer and a second substrate layer adhered to the first substrate layer such that a portion of the top surface of the first substrate layer is exposed to define a bottom of a cavity, and an edge of the second substrate layer adjacent to the exposed top surface of the first substrate layer defines an edge of the cavity. The device can include an integrated circuit die adhered to the exposed top surface of first substrate layer with a liquid adhesive. The first substrate layer can define a trench in the bottom of the cavity between a region of the integrated circuit die and the edge of the cavity such that the trench can receive bleed-out of the liquid adhesive from between the integrated circuit die and the top surface of the first substrate layer.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: March 1, 2022
    Assignee: Google LLC
    Inventors: Woon Seong Kwon, Ryohei Urata, Teckgyu Kang
  • Patent number: 11256591
    Abstract: Power regulation in an integrated memory assembly having control semiconductor dies and memory semiconductor is disclosed herein. A master control die regulates power usage by the integrated memory assembly. Each control die reports information about its expected power usage to the master control die. The master control die determines a plan that meets a power criterion for the integrated memory assembly. The plan may maximize the power usage in each time period, while staying within a power budget. The plan can include selecting which of the memory dies perform a memory operation (or phase of a memory operation) during a given time period. The master control die may send a die scheduling plan to each of the other control dies. Each die scheduling plan indicates when memory operations and/or phases of memory operations are to be performed.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: February 22, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Idan Alrod, Eran Sharon, Alexander Bazarsky
  • Patent number: 11257764
    Abstract: An integrated circuit (IC) chip that includes a semiconductor substrate including active devices on its front side, and at least part of a power delivery network (PDN) on its back side, is disclosed. In one aspect, the PDN includes a power supply terminal (Vdd) and a reference terminal (Vss) at the back of the IC. A plurality of TSV (Through Semiconductor Via) connections through the substrate bring the power to the front of the substrate. A field effect transistor is integrated at the back side of the substrate, and includes a source electrode, a drain electrode, and a gate electrode, which are contacted at the back side of the substrate. The IC further includes a gate control terminal for controlling the gate voltage. The transistor is coupled between the power supply terminal and one or more of the active devices of the IC.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: February 22, 2022
    Assignee: IMEC vzw
    Inventors: Gaspard Hiblot, Geert Van Der Plas
  • Patent number: 11244928
    Abstract: There are provided a stacked type semiconductor device and a manufacturing method of the stacked type semiconductor device. The stacked type semiconductor device includes: semiconductor chips stacked to overlap with each other; through electrodes respectively penetrating the semiconductor chips, the through electrodes being bonded to each other; and empty gaps respectively buried in the through electrodes.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: February 8, 2022
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 11239175
    Abstract: A semiconductor package includes: a substrate; a semiconductor chip disposed on a first surface of the substrate; solder bumps disposed between a first surface of the semiconductor chip and the substrate; and a redistribution layer provided on a second surface, opposite to the first surface, of the semiconductor chip. The substrate includes substrate patterns, and the substrate patterns cover a second surface of the substrate. The substrate patterns cover 60% to 100% of a total area of the second surface of the substrate.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: February 1, 2022
    Assignees: SAMSUNG ELECTRONICS CO., LTD., INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIV
    Inventors: Young-Ho Kim, Hwan Pil Park, Sung-Chul Kim, Key-One Ahn
  • Patent number: 11222873
    Abstract: A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: January 11, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joonho Jun, Un-Byoung Kang, Sunkyoung Seo, Jongho Lee, Young Kun Jee
  • Patent number: 11222992
    Abstract: An optoelectronic component, comprising: a structured semiconductor layer, a metallic mirror layer arranged on the semiconductor layer, a diffusion barrier layer arranged on the metallic mirror layer, a passivation layer arranged on the diffusion barrier layer, wherein the semiconductor layer comprises a mesa structure with mesa trenches. The mesa trenches taper from the surface of the semiconductor layer towards the mirror layer.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: January 11, 2022
    Assignee: OSRAM OLED GmbH
    Inventors: Stephan Kaiser, Andreas Ploessl
  • Patent number: 11217512
    Abstract: A semiconductor module includes a semiconductor chip having a first surface provided with a first electrode pad and a second surface, opposite to the first surface, provided with a second electrode pad, a first substrate connected to the first electrode pad, a second substrate provided on the side of the second surface, and a conductor section, electrically connecting the second electrode pad and the second substrate, and having a size greater than the second electrode pad in a plan view viewed from the side of the second substrate.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: January 4, 2022
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kenichi Sawada, Jiro Shinkai
  • Patent number: 11211363
    Abstract: In the semiconductor device, a semiconductor substrate has first and second surfaces. A circuitry layer is formed over the first surface and a first insulating layer is further formed over the circuitry layer. A second insulating layer including a first insulating element is formed over the second surface. A third insulating layer including a second insulating element different from the first insulating element of the second insulating layer is formed over the second surface with an intervention of the second insulating layer therebetween. A penetration electrode penetrates through the semiconductor substrate, the circuitry layer, the first insulating layer, the second insulating layer and the third insulating layer.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: December 28, 2021
    Assignee: Longitude Licensing Limited
    Inventors: Ryohei Kitada, Masahiro Yamaguchi
  • Patent number: 11201106
    Abstract: A structure includes a first substrate having a front side and a back side and a second substrate having a front side and a back side, wherein the back side of the second substrate is attached to the back side of the first substrate. The structure further includes a device layer over the front side of the second substrate; a first conductor going through a semiconductor layer in the second substrate; and a conductive connection that connects the first conductor to a conductive feature in the device layer.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: December 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Ping Chen, Ming-Han Lee, Shau-Lin Shue
  • Patent number: 11164802
    Abstract: A wafer manufacturing method includes a wafer preparing step of preparing a wafer partitioned into a plurality of separate areas by a plurality of crossing streets, the wafer including a plurality of semiconductor devices respectively formed in the plural separate areas, a removing step of determining whether each semiconductor device formed in the wafer is an acceptable product or a defective product and removing a defective device area including the semiconductor device determined as the defective product, from the wafer, and a fitting step of fitting a device chip adapted to be fitted into a space formed by the removal of the defective device area from the wafer into the space of the wafer, the device chip including an acceptable semiconductor device having the same function as that of the semiconductor device determined as the defective product.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: November 2, 2021
    Assignee: DISCO CORPORATION
    Inventors: Akihito Kawai, Youngsuk Kim
  • Patent number: 11164827
    Abstract: An electronic circuit including a substrate having a first dielectric characteristic. The substrate can include a first side and a second side. An intermediary material can be disposed within the substrate. For instance, the intermediary material can be located between the first side and the second side. The intermediary material can include a second dielectric characteristic, where the second dielectric characteristic is different than the first dielectric characteristic. A first conductive layer can be disposed on the first side, and a second conductive layer can be disposed on the second side. A conductive path can be electrically coupled between the first conductive layer and the second conductive layer. The conductive path can be in contact with at least a portion of the intermediary material.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: November 2, 2021
    Assignee: Intel Corporation
    Inventors: Jackson Chung Peng Kong, Bok Eng Cheah, Ping Ping Ooi, Kooi Chi Ooi
  • Patent number: 11152319
    Abstract: A micro-connection structure is provided. The micro-connection structure includes an under bump metallurgy (UBM) pad, a bump and an insulating ring. The UBM pad is electrically connected to at least one metallic contact of a substrate. The bump is disposed on the UBM pad and electrically connected with the UBM pad. The insulating ring surrounds the bump and the UBM pad. The bump is separate from the insulating ring with a distance and the bump is isolated by a gap between the insulating ring and the bump.
    Type: Grant
    Filed: May 10, 2020
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hsiung Lu, Chen-Shien Chen, Chen-En Yen, Cheng-Jen Lin, Chin-Wei Kang, Kai-Jun Zhan
  • Patent number: 11101176
    Abstract: A method of fabricating a redistribution circuit structure including the following steps is provided. A conductive via is formed. A photosensitive dielectric layer is formed to cover the conductive via. The photosensitive dielectric layer is partially removed to reveal the conductive via at least through an exposure and development process. A redistribution wiring is formed on the photosensitive dielectric layer and the revealed conductive via.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 11093677
    Abstract: A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: August 17, 2021
    Assignee: iCometrue Company Ltd.
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Patent number: 11088086
    Abstract: A method for forming a chip package structure is provided. The method includes bonding a first chip structure and a second chip structure to a surface of a substrate. The first chip structure and the second chip structure are spaced apart from each other. There is a first gap between the first chip structure and the second chip structure. The method includes removing a first portion of the first chip structure and a second portion of the second chip structure to form a trench partially in the first chip structure and the second chip structure and partially over the first gap. The method includes forming an anti-warpage bar in the trench. The anti-warpage bar is over the first chip structure, the second chip structure, and the first gap.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiun-Ting Chen, Ying-Ching Shih, Szu-Wei Lu, Chih-Wei Wu
  • Patent number: 11063020
    Abstract: There is provided a semiconductor device a method for manufacturing a semiconductor device, and an electronic apparatus that comprises a semiconductor device, the semiconductor device including a first chip, a second chip that is bonded onto a first surface side of the first chip, a through electrode that is formed to penetrate from a second surface side of the first chip to a wiring layer on the second semiconductor base substrate, and an insulation layer that is disposed between the through electrode and a semiconductor base substrate in the first chip.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: July 13, 2021
    Assignee: SONY CORPORATION
    Inventors: Satoru Wakiyama, Masaki Okamoto, Yutaka Ooka, Reijiroh Shohji, Yoshifumi Zaizen, Kazunori Nagahata, Masaki Haneda
  • Patent number: 11044812
    Abstract: A component carrier includes a base structure and an electrically conductive wiring structure on the base structure. The wiring structure has a nonrectangular cross-sectional shape configured so that an adhesion promoting constriction is formed by at least one of the group consisting of the wiring structure and a transition between the base structure and the wiring structure.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: June 22, 2021
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventor: Hannes Voraberger
  • Patent number: 11037908
    Abstract: A bonded assembly includes a first semiconductor die including a first substrate, first semiconductor devices located on the first substrate, first dielectric material layers located on the first semiconductor devices and embedding first metal interconnect structures, and first through-substrate via structures extending through the first substrate and contacting a respective first metal interconnect structure. Each of the first through-substrate via structures laterally surrounds a respective core cavity that contains a void or a dielectric fill material portion.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: June 15, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Chen Wu, Peter Rabkin, Yangyin Chen, Masaaki Higashitani
  • Patent number: 11037916
    Abstract: An apparatus is provided which comprises: a substrate; a first active device adjacent to the substrate; a first set of one or more layers to interconnect the one or more active devices; a second set of one or more layers; a second active device coupled to the second set of one or more layers; and a layer adjacent to one of the layers of the first set and the second active device, wherein the layer is to bond the one of the layers of the first set and the second active device.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: June 15, 2021
    Assignee: Intel Corporation
    Inventors: Anup Pancholi, Prashant Majhi, Paul B. Fischer, Patrick Morrow
  • Patent number: 11031327
    Abstract: In accordance with an embodiment of the present invention, a semiconductor chip includes a device region disposed in or over a substrate, a doped region disposed in the device region, and a through via disposed in the substrate. The through via extends through the doped region.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: June 8, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Helmut Brech, Albert Birner
  • Patent number: 11018000
    Abstract: According to one embodiment, an electronic apparatus including a first substrate comprising a first conductive layer; a second substrate which is opposed to the first conductive layer and is separated from the first conductive layer, the second substrate including: a second conductive layer, and a first hole penetrating the second substrate; and a connecting material which electrically connects the first conductive layer and the second conductive layer via the first hole, wherein the second conductive layer is located on the second substrate on a side opposite to a side that is opposed to the first conductive layer.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: May 25, 2021
    Assignee: Japan Display Inc.
    Inventors: Yoshikatsu Imazeki, Shoji Hinata
  • Patent number: 11018114
    Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: May 25, 2021
    Assignee: Intel IP Corporation
    Inventors: Bernd Waidhas, Georg Seidemann, Andreas Augustin, Laurent Millou, Andreas Wolter, Reinhard Mahnkopf, Stephan Stoeckl, Thomas Wagner
  • Patent number: 11004832
    Abstract: A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Pin Chang, Weng-Jin Wu, Wen-Chih Chiou, Chen-Hua Yu
  • Patent number: 11004770
    Abstract: A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: May 11, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Mattias E. Dahlstrom
  • Patent number: 10993332
    Abstract: A circuit substrate includes a substrate, a wire build-up layer structure, and an insulating layer. The substrate has a first surface and a second surface opposites to the first surface. The substrate includes a plurality of patterned pads. The patterned pads are disposed on the first surface of the substrate, and having contact openings. The wire build-up layer structure is disposed on the first surface of the substrate. The wire build-up layer structure includes an interconnect build-up layer and a plurality of conductive pillars. The conductive pillars electrically connect to the interconnect build-up layer and the patterned pads. The insulating layer is disposed between the substrate and the wire build-up layer structure.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: April 27, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Kai-Ming Yang, Chen-Hao Lin
  • Patent number: 10985057
    Abstract: A method for producing an integrated circuit (IC) chip on a semiconductor device wafer is disclosed. In one aspect, the IC chip includes buried interconnect rails in the front end of line and a power delivery network (PDN) on the back side of the chip. The PDN is connected to the front side by micro-sized through semiconductor via (TSV) connections through the thinned semiconductor wafer. The production of the TSVs is integrated in the process flow for fabricating the interconnect rails, with the TSVs being produced in a self-aligned manner relative to the interconnect rails. After bonding the device wafer to a landing wafer, the semiconductor layer onto which the active devices of the chip have been produced is thinned from the back side, and the TSVs are exposed. The self-aligned manner of producing the TSVs enables scaling down the process towards smaller dimensions without losing accurate positioning of the TSVs.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: April 20, 2021
    Assignee: IMEC vzw
    Inventors: Anne Jourdain, Nouredine Rassoul, Eric Beyne
  • Patent number: 10966338
    Abstract: Components selected from bare die, surface mount devices and stacked devices are assembled using flip chip assembly methods on a printed circuit board assembly (PCBA) with no components having a mounted height exceeding a preferred height. The preferred height may correspond with the components having the highest power rating, because the most effective thermal coupling to a heat sinking surface will then be provided to these high-power components. A blade server is configured with the back face of high-power components coupled to a metal tank carrying cooling water. An electronic system has laminate blocks comprising repeated laminations of PCBAs coupled to metal foils. The laminate blocks are coupled to heat sink surfaces in direct contact with cooling liquid. Power density is superior to existing high-performance computing (HPC) systems and data center servers.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: March 30, 2021
    Inventor: Peter C. Salmon
  • Patent number: 10943864
    Abstract: A device and method of utilizing a programmable redistribution die to redistribute the outputs of semiconductor dies. Integrated circuit packages using a programmable redistribution die are shown. Methods of creating a programmable redistribution die are shown.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Min Suet Lim, J-Wing Teh, Bok Eng Cheah
  • Patent number: 10910346
    Abstract: A semiconductor package includes: a lower semiconductor chip including a first semiconductor substrate, which includes a first semiconductor device on an active surface thereof and a protrusion defined by a recess region on an inactive surface thereof opposite to the active surface, a plurality of external connecting pads on a bottom surface of the first semiconductor substrate, and a plurality of through-electrodes electrically connected to the plurality of external connecting pads; and at least one upper semiconductor chip stacked on the protrusion of the lower semiconductor chip and electrically connected to the plurality of through-electrodes, the at least one upper semiconductor chip including a second semiconductor substrate which includes a second semiconductor device on an active surface thereof.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: February 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-seok Hong, Ji-hoon Kim
  • Patent number: 10903142
    Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: January 26, 2021
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Tat Hin Tan, Wai Ling Lee
  • Patent number: 10903179
    Abstract: Semiconductor apparatus and method for manufacturing semiconductor apparatus are provided. Semiconductor apparatus includes a semiconductor substrate having metal pads, a first passivation layer, a second passivation layer, an under bump metal layer, a stress buffer layer, a copper pillar and a solder structure. First passivation layer is formed on the semiconductor substrate and covers a portion of each metal pad, the first passivation layer has first passivation layer openings to expose a first portion of each metal pad. Second passivation layer is formed on the first passivation layer, the second passivation layer has second passivation layer openings to expose a second portion of each metal pad. Under bump metal layer is formed on the second portion of each metal pad exposed by the second passivation layer opening. Stress buffer layer is formed on the under bump metal layer, and the copper pillar is disposed on the stress buffer layer.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: January 26, 2021
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventor: Yu-Jie Lin
  • Patent number: 10903223
    Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: January 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Haitao Liu, Kamal M. Karda, Gurtej S. Sandhu, Sanh D. Tang, Akira Goda, Lifang Xu
  • Patent number: 10896848
    Abstract: A method of manufacturing a semiconductor device includes forming a precursor structure including a substrate having a via hole, a liner on a sidewall of the via hole, a conductor in the via hole, a first and a second insulating layers respectively on the top and bottom surfaces, and a first and a second redistribution layers in contact with the conductor through a first hole in the first insulating layer and a second hole in the second insulating layer. A first opening and a second opening are then respectively formed in the first insulating layer and the second insulating layer to expose a portion of the liner. The liner is then etched through the first opening and the second opening to form an air gap surrounding the conductor. The first opening and the second opening are then filled to seal the air gap.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: January 19, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsih-Yang Chiu
  • Patent number: 10886195
    Abstract: A semiconductor structure is described. The semiconductor structure includes a semiconductor substrate and a through-silicon via (TSV). The TSV is disposed between a first surface of the semiconductor substrate and an interconnection layer disposed on a second surface of the semiconductor substrate, where the first surface of the semiconductor substrate is opposite to the second surface. The TSV has an external surface that interfaces with the semiconductor substrate. In one embodiment, the external surface includes a protrusion that extends into the semiconductor substrate. In another embodiment, the TSV includes one or more voids. In yet another embodiment, the TSV includes both protrusions and voids. The protrusions and/or the one or more voids may reduce thermal expansion stress. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Doug B. Ingerly, Candi S. Cook
  • Patent number: 10886263
    Abstract: A semiconductor device package comprises a bottom electronic device, an interposer module, a top electronic device, and a double sided redistribution layer (RDL) structure. The interposer module includes a plurality of conductive vias. The top electronic device has an active surface and is disposed above the bottom electronic device and above the interposer module. The double sided RDL structure is disposed between the bottom electronic device and the top electronic device. The active surface of the bottom electronic device faces toward the double sided RDL structure. The active surface of the top electronic device faces toward the double sided RDL structure. The double sided RDL structure electrically connects the active surface of the bottom electronic device to the active surface of the top electronic device. The double sided RDL structure electrically connects the active surface of the top electronic device to the interposer module.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 5, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: William T. Chen, John Richard Hunt, Chih-Pin Hung, Chen-Chao Wang, Chih-Yi Huang
  • Patent number: 10854568
    Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming an insulation layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device to the insulation layer and a portion of the plurality of bond pads through hybrid bonding.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chen-Hua Yu
  • Patent number: 10854244
    Abstract: A semiconductor memory device includes n interconnect layers above a substrate; and a first interconnect region between an end of a control circuit and an end of the substrate in a direction of a first axis beside a first pad region in a direction of a second axis. The n interconnect layers are located at different levels from the substrate. Each of the n interconnect layers includes an interconnect. The first interconnect region includes no transistor, and no contact coupled to the substrate. The first interconnect region includes an interconnect extending along the second axis in m (m is a natural number equal to or larger than 3, larger than n/2, and equal to or smaller than n) interconnect layers of the n interconnect layers.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: December 1, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Jumpei Sato
  • Patent number: 10833154
    Abstract: An electronic device can include a substrate and an insulating structure. In an aspect, an anchor can include a portion of the substrate that extends into the insulating structure or a portion of the insulating structure that extends into the substrate. In another aspect, a process of forming an electronic device can include patterning a substrate to define a trench and a first anchor; and forming an insulating structure within the trench and adjacent to the first anchor. In a further aspect, a process of forming an electronic device can include patterning a substrate to define a trench having a sidewall and a first pillar spaced apart from the sidewall; doping the first pillar to change a conductivity type of the first pillar; and forming an insulating structure that surrounds the first pillar.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: November 10, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Gordon M. Grivna, Steven M. Etter, Hiroyuki Suzuki, Miki Ichiyanagi, Toshihiro Hachiyanagi
  • Patent number: 10825728
    Abstract: A method is provided for producing at least one electrical via in a substrate, the method comprising: producing a protective layer over a component structure which has been produced or is present on a front side of the substrate; forming at least one contact hole which extends from a surface of a backside of the substrate to a contact surface of the component structure; forming a metal-containing and thus conductive lining in the at least one contact hole creating a hollow electrically conductive structure in the at least one contact hole; and applying a passivation layer over the backside of the substrate, the passivation layer spanning over the hollow electrically conductive structure for forming the at least one electrical via. Also provided is a micro-technical component comprising at least one electrical via.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: November 3, 2020
    Assignee: X-FAB Semiconductor Foundries GmbH
    Inventors: Roy Knechtel, Sophia Dempwolf, Daniela Guenther, Uwe Schwarz
  • Patent number: 10796930
    Abstract: A semiconductor device package includes a substrate having a first surface and a second surface facing away from the first surface, a conductive column extending in the substrate between the first surface and the second surface, a dielectric layer on the first surface of the substrate, a redistribution structure provided in the dielectric layer and electrically connected to the conductive column, a semiconductor chip provided above the dielectric layer and electrically connected to the redistribution structure, and an encapsulation layer on the dielectric layer and encapsulating the semiconductor chip. The package is manufactured such that each of the substrate and the encapsulation layer is formed of molding compound.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: October 6, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yinan Li