With Electrical Contact In Hole In Semiconductor (e.g., Lead Extends Through Semiconductor Body) Patents (Class 257/621)
  • Patent number: 10993332
    Abstract: A circuit substrate includes a substrate, a wire build-up layer structure, and an insulating layer. The substrate has a first surface and a second surface opposites to the first surface. The substrate includes a plurality of patterned pads. The patterned pads are disposed on the first surface of the substrate, and having contact openings. The wire build-up layer structure is disposed on the first surface of the substrate. The wire build-up layer structure includes an interconnect build-up layer and a plurality of conductive pillars. The conductive pillars electrically connect to the interconnect build-up layer and the patterned pads. The insulating layer is disposed between the substrate and the wire build-up layer structure.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: April 27, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Kai-Ming Yang, Chen-Hao Lin
  • Patent number: 10985057
    Abstract: A method for producing an integrated circuit (IC) chip on a semiconductor device wafer is disclosed. In one aspect, the IC chip includes buried interconnect rails in the front end of line and a power delivery network (PDN) on the back side of the chip. The PDN is connected to the front side by micro-sized through semiconductor via (TSV) connections through the thinned semiconductor wafer. The production of the TSVs is integrated in the process flow for fabricating the interconnect rails, with the TSVs being produced in a self-aligned manner relative to the interconnect rails. After bonding the device wafer to a landing wafer, the semiconductor layer onto which the active devices of the chip have been produced is thinned from the back side, and the TSVs are exposed. The self-aligned manner of producing the TSVs enables scaling down the process towards smaller dimensions without losing accurate positioning of the TSVs.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: April 20, 2021
    Assignee: IMEC vzw
    Inventors: Anne Jourdain, Nouredine Rassoul, Eric Beyne
  • Patent number: 10966338
    Abstract: Components selected from bare die, surface mount devices and stacked devices are assembled using flip chip assembly methods on a printed circuit board assembly (PCBA) with no components having a mounted height exceeding a preferred height. The preferred height may correspond with the components having the highest power rating, because the most effective thermal coupling to a heat sinking surface will then be provided to these high-power components. A blade server is configured with the back face of high-power components coupled to a metal tank carrying cooling water. An electronic system has laminate blocks comprising repeated laminations of PCBAs coupled to metal foils. The laminate blocks are coupled to heat sink surfaces in direct contact with cooling liquid. Power density is superior to existing high-performance computing (HPC) systems and data center servers.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: March 30, 2021
    Inventor: Peter C. Salmon
  • Patent number: 10943864
    Abstract: A device and method of utilizing a programmable redistribution die to redistribute the outputs of semiconductor dies. Integrated circuit packages using a programmable redistribution die are shown. Methods of creating a programmable redistribution die are shown.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Min Suet Lim, J-Wing Teh, Bok Eng Cheah
  • Patent number: 10910346
    Abstract: A semiconductor package includes: a lower semiconductor chip including a first semiconductor substrate, which includes a first semiconductor device on an active surface thereof and a protrusion defined by a recess region on an inactive surface thereof opposite to the active surface, a plurality of external connecting pads on a bottom surface of the first semiconductor substrate, and a plurality of through-electrodes electrically connected to the plurality of external connecting pads; and at least one upper semiconductor chip stacked on the protrusion of the lower semiconductor chip and electrically connected to the plurality of through-electrodes, the at least one upper semiconductor chip including a second semiconductor substrate which includes a second semiconductor device on an active surface thereof.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: February 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-seok Hong, Ji-hoon Kim
  • Patent number: 10903179
    Abstract: Semiconductor apparatus and method for manufacturing semiconductor apparatus are provided. Semiconductor apparatus includes a semiconductor substrate having metal pads, a first passivation layer, a second passivation layer, an under bump metal layer, a stress buffer layer, a copper pillar and a solder structure. First passivation layer is formed on the semiconductor substrate and covers a portion of each metal pad, the first passivation layer has first passivation layer openings to expose a first portion of each metal pad. Second passivation layer is formed on the first passivation layer, the second passivation layer has second passivation layer openings to expose a second portion of each metal pad. Under bump metal layer is formed on the second portion of each metal pad exposed by the second passivation layer opening. Stress buffer layer is formed on the under bump metal layer, and the copper pillar is disposed on the stress buffer layer.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: January 26, 2021
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventor: Yu-Jie Lin
  • Patent number: 10903223
    Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: January 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Haitao Liu, Kamal M. Karda, Gurtej S. Sandhu, Sanh D. Tang, Akira Goda, Lifang Xu
  • Patent number: 10903142
    Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: January 26, 2021
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Tat Hin Tan, Wai Ling Lee
  • Patent number: 10896848
    Abstract: A method of manufacturing a semiconductor device includes forming a precursor structure including a substrate having a via hole, a liner on a sidewall of the via hole, a conductor in the via hole, a first and a second insulating layers respectively on the top and bottom surfaces, and a first and a second redistribution layers in contact with the conductor through a first hole in the first insulating layer and a second hole in the second insulating layer. A first opening and a second opening are then respectively formed in the first insulating layer and the second insulating layer to expose a portion of the liner. The liner is then etched through the first opening and the second opening to form an air gap surrounding the conductor. The first opening and the second opening are then filled to seal the air gap.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: January 19, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsih-Yang Chiu
  • Patent number: 10886263
    Abstract: A semiconductor device package comprises a bottom electronic device, an interposer module, a top electronic device, and a double sided redistribution layer (RDL) structure. The interposer module includes a plurality of conductive vias. The top electronic device has an active surface and is disposed above the bottom electronic device and above the interposer module. The double sided RDL structure is disposed between the bottom electronic device and the top electronic device. The active surface of the bottom electronic device faces toward the double sided RDL structure. The active surface of the top electronic device faces toward the double sided RDL structure. The double sided RDL structure electrically connects the active surface of the bottom electronic device to the active surface of the top electronic device. The double sided RDL structure electrically connects the active surface of the top electronic device to the interposer module.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 5, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: William T. Chen, John Richard Hunt, Chih-Pin Hung, Chen-Chao Wang, Chih-Yi Huang
  • Patent number: 10886195
    Abstract: A semiconductor structure is described. The semiconductor structure includes a semiconductor substrate and a through-silicon via (TSV). The TSV is disposed between a first surface of the semiconductor substrate and an interconnection layer disposed on a second surface of the semiconductor substrate, where the first surface of the semiconductor substrate is opposite to the second surface. The TSV has an external surface that interfaces with the semiconductor substrate. In one embodiment, the external surface includes a protrusion that extends into the semiconductor substrate. In another embodiment, the TSV includes one or more voids. In yet another embodiment, the TSV includes both protrusions and voids. The protrusions and/or the one or more voids may reduce thermal expansion stress. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Doug B. Ingerly, Candi S. Cook
  • Patent number: 10854244
    Abstract: A semiconductor memory device includes n interconnect layers above a substrate; and a first interconnect region between an end of a control circuit and an end of the substrate in a direction of a first axis beside a first pad region in a direction of a second axis. The n interconnect layers are located at different levels from the substrate. Each of the n interconnect layers includes an interconnect. The first interconnect region includes no transistor, and no contact coupled to the substrate. The first interconnect region includes an interconnect extending along the second axis in m (m is a natural number equal to or larger than 3, larger than n/2, and equal to or smaller than n) interconnect layers of the n interconnect layers.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: December 1, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Jumpei Sato
  • Patent number: 10854568
    Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming an insulation layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device to the insulation layer and a portion of the plurality of bond pads through hybrid bonding.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chen-Hua Yu
  • Patent number: 10833154
    Abstract: An electronic device can include a substrate and an insulating structure. In an aspect, an anchor can include a portion of the substrate that extends into the insulating structure or a portion of the insulating structure that extends into the substrate. In another aspect, a process of forming an electronic device can include patterning a substrate to define a trench and a first anchor; and forming an insulating structure within the trench and adjacent to the first anchor. In a further aspect, a process of forming an electronic device can include patterning a substrate to define a trench having a sidewall and a first pillar spaced apart from the sidewall; doping the first pillar to change a conductivity type of the first pillar; and forming an insulating structure that surrounds the first pillar.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: November 10, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Gordon M. Grivna, Steven M. Etter, Hiroyuki Suzuki, Miki Ichiyanagi, Toshihiro Hachiyanagi
  • Patent number: 10825728
    Abstract: A method is provided for producing at least one electrical via in a substrate, the method comprising: producing a protective layer over a component structure which has been produced or is present on a front side of the substrate; forming at least one contact hole which extends from a surface of a backside of the substrate to a contact surface of the component structure; forming a metal-containing and thus conductive lining in the at least one contact hole creating a hollow electrically conductive structure in the at least one contact hole; and applying a passivation layer over the backside of the substrate, the passivation layer spanning over the hollow electrically conductive structure for forming the at least one electrical via. Also provided is a micro-technical component comprising at least one electrical via.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: November 3, 2020
    Assignee: X-FAB Semiconductor Foundries GmbH
    Inventors: Roy Knechtel, Sophia Dempwolf, Daniela Guenther, Uwe Schwarz
  • Patent number: 10796958
    Abstract: A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: October 6, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sampath Purushothaman, Roy Rongqing Yu
  • Patent number: 10796930
    Abstract: A semiconductor device package includes a substrate having a first surface and a second surface facing away from the first surface, a conductive column extending in the substrate between the first surface and the second surface, a dielectric layer on the first surface of the substrate, a redistribution structure provided in the dielectric layer and electrically connected to the conductive column, a semiconductor chip provided above the dielectric layer and electrically connected to the redistribution structure, and an encapsulation layer on the dielectric layer and encapsulating the semiconductor chip. The package is manufactured such that each of the substrate and the encapsulation layer is formed of molding compound.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: October 6, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yinan Li
  • Patent number: 10784103
    Abstract: A method for forming sequencing flow cells can include providing a semiconductor wafer covered with a dielectric layer, and forming a patterned layer on the dielectric layer. The patterned layer has a differential surface that includes alternating first surface regions and second surface regions. The method can also include attaching a cover wafer to the semiconductor wafer to form a composite wafer structure including a plurality of flow cells. The composite wafer structure can then be singulated to form a plurality of dies. Each die forms a sequencing flow cell. The sequencing flow cell can include a flow channel between a portion of the patterned layer and a portion of the cover wafer, an inlet, and an outlet. Further, the method can include functionalizing the sequencing flow cell to create differential surfaces.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: September 22, 2020
    Assignee: MGI TECH CO., LTD.
    Inventors: Shifeng Li, Jian Gong, Yan-You Lin, Cheng Frank Zhong
  • Patent number: 10777454
    Abstract: An article of manufacture is formed by preparing a first silicon-on-insulator (SOI) wafer with first bonding pads at a first top or back-end-of-line (BEOL) surface thereof, preparing a second SOI wafer with second bonding pads at a second BEOL surface thereof, and attaching the first and second SOI wafers by bonding their bonding pads together, thereby producing a sandwiched wafer with first and second bottom or front-end-of-line (FEOL) surfaces facing outward and with first and second BEOL surfaces facing each other near the midline of the sandwiched wafer. The first SOI wafer then is prepared for packaging by first removing the silicon substrate from the first FEOL surface to reveal a buried oxide (BOX) layer, then fabricating interconnects atop the BOX layer and forming input output pads atop the interconnects.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sampath Purushothaman, Roy Rongqing Yu
  • Patent number: 10748842
    Abstract: The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventors: Zhiguo Qian, Kaladhar Radhakrishnan, Kemal Aygun
  • Patent number: 10741512
    Abstract: An embodiment is a method including forming a first passive device in a first wafer, forming a first dielectric layer over a first side of the first wafer, forming a first plurality of bond pads in the first dielectric layer, planarizing the first dielectric layer and the first plurality of bond pads to level top surfaces of the first dielectric layer and the first plurality of bond pads with each other, hybrid bonding a first device die to the first dielectric layer and at least some of the first plurality of bond pads, and encapsulating the first device die in a first encapsulant.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Hsi Wu, Der-Chyang Yeh, Hsien-Wei Chen, Jie Chen
  • Patent number: 10720377
    Abstract: Examples described herein provide for an electronic device apparatus with multiple thermally conductive paths for heat dissipation. In an example, an electronic device apparatus includes a package comprising a die attached to a package substrate. The electronic device apparatus further includes a ring stiffener disposed around the die and on the package substrate, a heat sink disposed on the package, and a wedge disposed between the heat sink and the ring stiffener.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: July 21, 2020
    Assignee: XILINX, INC.
    Inventors: Gamal Refai-Ahmed, Ho Hyung Lee, Hui-Wen Lin, Henley Liu, Suresh Ramalingam
  • Patent number: 10714437
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a passivation layer disposed on the second interconnection member.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: July 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo Hwan Lee, Jong Rip Kim, Hyoung Joon Kim, Jin Yul Kim, Kyung Seob Oh
  • Patent number: 10692836
    Abstract: A semiconductor device has a plurality of first semiconductor die with an encapsulant deposited over a first surface of the first semiconductor die and around the first semiconductor die. An insulating layer is formed over the encapsulant and over a second surface of the first semiconductor die opposite the first surface. The insulating layer includes openings over the first semiconductor die. A first conductive layer is formed over the first semiconductor die within the openings. A second conductive layer is formed over the first conductive layer to form vertical conductive vias. A second semiconductor die is disposed over the first semiconductor die and electrically connected to the first conductive layer. A bump is formed over the second conductive layer outside a footprint of the first semiconductor die. The second semiconductor die is disposed over an active surface or a back surface of the first semiconductor die.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: June 23, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 10685917
    Abstract: A semiconductor device and a manufacture method of the semiconductor device are provided. In the semiconductor device, a back surface of a substrate is covered with a first insulating layer, where the first insulating layer covers the bottom and the sidewall of a through hole and the back surface of the substrate outside the through hole. The first insulating layer outside the through hole is covered with a second insulating layer. When etching the first insulating layer at the bottom of the through hole, although an etching speed for a region outside the through hole is greater than an etching speed for the bottom of the through hole, the first insulating layer outside the through hole is protected from being over-etched by the second insulating layer, which improves reliability of the device.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: June 16, 2020
    Assignee: China Wafer Level CSP Co., Ltd.
    Inventor: Zhiqi Wang
  • Patent number: 10679924
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate; an active circuit portion including at least an active component and formed on a topside of the semiconductor device; and a radiating metal sheet formed on a backside of the semiconductor device. A hole is formed within the substrate and the hole penetrates through the substrate. The active circuit portion and the radiating metal sheet are coupled through the hole.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: June 9, 2020
    Assignee: WIN Semiconductors Corp.
    Inventors: Chih-Wen Huang, Jui-Chieh Chiu
  • Patent number: 10667410
    Abstract: A method of making a fusion bonded circuit structure. Each major surface of an LCP substrate is provided with a seed layers of a conductive material. Resist layers are deposited on the seed layers. The resist layers are processed to create recesses corresponding to a desired circuitry layers on each side of the LCP substrate. The recesses expose portions of the seed layers of conductive material. The LCP substrate is electroplated to simultaneously create conductive traces defined by the first recesses on both sides of the LCP substrate. The resist layers are removed to reveal the conductive traces. The LCP substrate is etched to remove exposed portions of the seed layers adjacent the conductive traces. LCP layers are fusion bonded to the major surfaces of the LCP substrate to encapsulate the conductive traces in an LCP material. The LCP layers can be laser drilled to expose the conductive traces.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: May 26, 2020
    Assignee: HSIO Technologies, LLC
    Inventor: James J. Rathburn
  • Patent number: 10665541
    Abstract: At least one opening having a biconvex shape is formed into a dielectric material layer. A void-free metallization region (interconnect metallic region and/or metallic contact region) is provided to each of the openings. The void-free metallization region has the biconvex shape and exhibits a low wire resistance.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: May 26, 2020
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten
  • Patent number: 10658229
    Abstract: A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: May 19, 2020
    Assignee: Sony Corporation
    Inventor: Masaki Okamoto
  • Patent number: 10643871
    Abstract: A transfer head, a transfer head array, and a method for transferring an inorganic light-emitting diode are provided. The transfer head for transferring an inorganic light-emitting diode includes a first groove and a second groove. The first groove and the second groove are arranged sequentially in a first direction, and are connected to each other. The first groove is configured to provide an inlet and an outlet for the inorganic light-emitting diode to enter and exit the transfer head. After the inorganic light-emitting diode enters the second groove through the first groove, at least a partial structure of the inorganic light-emitting diode is confined in the second groove. Picking up and transferring the inorganic light-emitting diode is realized by the transfer head with a simple structure.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: May 5, 2020
    Assignee: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventor: Zeshang He
  • Patent number: 10636678
    Abstract: Methods for forming semiconductor die assemblies with heat transfer features are disclosed herein. In some embodiments, the methods comprise providing a wafer having a first side and a second side opposite the first side, attaching a semiconductor die stack to the first side of the wafer, and forming a plurality of heat transfer features at the second side of the wafer. The heat transfer features can be defined by a plurality of grooves that define an exposed continuous surface of the wafer at the second side compared to a planar surface of the wafer.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: April 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Wei Zhou, Zhaohui Ma, Aibin Yu
  • Patent number: 10622397
    Abstract: A semiconductor layer includes an opening, and in a joint surface between structures, a portion between a semiconductor layer and an opening in a direction in which the semiconductor layers are stacked together includes a plurality of conductor portions and an insulator portion located between the plurality of conductor portions in a direction orthogonal to the direction.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: April 14, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hideaki Ishino, Takumi Ogino
  • Patent number: 10615174
    Abstract: A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the material. The etch mask comprises an elevationally-extending mask opening in the silicon nitride-comprising region that has a minimum horizontal open dimension that is greater in an elevationally-innermost portion of the region than in an elevationally-outermost portion of the region. The elevationally-outermost portion has a greater etch rate in at least one of HF and H3PO4 than does the elevationally-innermost portion. The etch mask is used as a mask while etching an elevationally-extending mask opening into the material. The silicon nitride-comprising region is exposed to at least one of HF and H3PO4 to increase the minimum horizontal open dimension in the elevationally-outermost portion to a greater degree than increase, if any, in the minimum horizontal open dimension in the elevationally-innermost portion.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: April 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Fei Wang, Tom J. John, Kunal Shrotri, Anish A. Khandekar, Aaron R. Wilson, John D. Hopkins, Derek F. Lundberg
  • Patent number: 10607888
    Abstract: A conductive through-plating for a substrate includes a metal component, a first conductive structure situated on or in the environment of a surface of the substrate, and a second conductive structure situated on or in the environment of a further surface of the substrate. A method for producing the through-plating includes, in a first step, at least partially applying above the surface a grid structure that includes a group of openings; in a second step following the first step, carrying out an etching producing a trench in the substrate and at least partially also underneath the group of openings; and, in a fifth step following the second step, carrying out a metallization situating a metal component at least partially in the trench such that the metal component is part of a seal sealing the trench in the area of the surface.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: March 31, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Christoph Schelling, Johannes Classen, Simon Genter
  • Patent number: 10607965
    Abstract: A stacked semiconductor device includes a plurality of semiconductor dies stacked in a first direction, M data paths electrically connecting the plurality of semiconductor dies, one data path including one or more through-silicon vias, where M is a positive integer, a transmission circuit including M serialization units configured to serialize P transmission signals to M serial signals and output the M serial signals to the M data paths, respectively, where P is a positive integer greater than M and a reception circuit including M parallelization units configured to receive the M serial signals from the M data paths and parallelize the M serial signals to P reception signals corresponding to the P transmission signals. The number of the through-silicon vias is reduced by serializing the transmission signals, transferring the serialized signals through the smaller number of data paths between the stacked semiconductor dies and then parallelizing the transferred signals.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: March 31, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Haesuk Lee, So-Young Kim, Seung-Han Woo
  • Patent number: 10607947
    Abstract: A semiconductor device includes a metallization system positioned above a substrate and a die seal positioned at least in the metallization system and delimiting a die region. The die seal includes a via line feature having an axial length and including one or more first portions having a first target dimension and one or more second portions along the axial length. The one or more second portions have a second target dimension less than the first target dimension.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: March 31, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Dirk Breuer, Maik Liebau, Matthias Lehr
  • Patent number: 10600748
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a passivation layer disposed on the second interconnection member.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: March 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo Hwan Lee, Jong Rip Kim, Hyoung Joon Kim, Jin Yul Kim, Kyung Seob Oh
  • Patent number: 10600708
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes disposing on a carrier an electronic component having a plurality of conductors, encapsulating the electronic component with an encapsulant, and disposing an electronic device on the encapsulant. The electronic device and the carrier are electrically connected through the conductors, thereby reducing the overall thickness of the electronic package.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: March 24, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Wen-Shan Tsai, Chee-Key Chung, Chang-Fu Lin
  • Patent number: 10580727
    Abstract: A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planer view is smallest among a plurality of areas of the through-hole in a planer view, a filler arranged within the through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: March 3, 2020
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventors: Satoru Kuramochi, Sumio Koiwa, Hidenori Yoshioka
  • Patent number: 10578939
    Abstract: A display panel includes an array substrate, an opposite substrate facing the array substrate, and a liquid crystal layer disposed between the array substrate and the opposite substrate. The array substrate includes a display area and a non-display area surrounding the display area, and the non-display area includes a first non-display area disposed adjacent to a side portion of the display area and a second non-display area other than the first non-display area. The first non-display area overlaps the opposite substrate. The array substrate and the opposite substrate have the same or substantially the same area and a wire member is disposed under the array substrate to be connected to an external circuit module. Accordingly, the display panel does not need an extra space for the wire member, and thus the non-display area is reduced.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: March 3, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jin-Soo Jung, Young Gu Kim, Byoung-Hun Sung, Baekkyun Jeon
  • Patent number: 10553488
    Abstract: Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: February 4, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Shunqiang Gong, Juan Boon Tan, Shijie Wang, Mahesh Bhatkar, Daxiang Wang
  • Patent number: 10546779
    Abstract: A through substrate via (TSV) and method of forming the same are provided. The method of making the TSV may include etching a via opening into the backside of semiconductor substrate, the via opening exposing a surface of a metal landing structure. A conductive layer is deposited over the backside of semiconductor substrate, sidewalls of the via opening, and exposed surface of the metal landing structure. The conductive layer is coated with a polymer material, filling the via opening. The polymer material is developed to remove the polymer material from the backside of semiconductor substrate, leaving the via opening filled with undeveloped polymer material. A planar backside surface of semiconductor substrate is formed by removing the conductive layer.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: January 28, 2020
    Assignee: NXP USA, INC.
    Inventors: Qing Zhang, Lianjun Liu
  • Patent number: 10546802
    Abstract: A substrate contact plug which is connected to a wiring and a semiconductor substrate and does not form a circuit is formed in a seal ring region in a peripheral portion of a semiconductor chip region. The substrate contact plug is buried in a trench which is deeper than an element isolation trench.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: January 28, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroaki Sekikawa, Shigeo Tokumitsu, Asuka Komuro
  • Patent number: 10541207
    Abstract: At least one opening having a biconvex shape is formed into a dielectric material layer. A void-free metallization region (interconnect metallic region and/or metallic contact region) is provided to each of the openings. The void-free metallization region has the biconvex shape and exhibits a low wire resistance.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten
  • Patent number: 10515933
    Abstract: A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Pin Chang, Weng-Jin Wu, Wen-Chih Chiou, Chen-Hua Yu
  • Patent number: 10510672
    Abstract: A semiconductor package and a method manufacturing the same are disclosed. At least one semiconductor chip is mounted on a package substrate. An insulative mold layer is formed at sides of the semiconductor chip having at least one recess in a region in which conductive connection members are formed, the recess defining one or more protrusions within the mold layer. An interposer is positioned on the protrusions with the conductive connection members connecting and providing electrical connections between conductive pads on the upper surface of the package and conductive pads on the lower surface of the package substrate. The protrusions may position the interposer in the vertical direction by defining the vertical spacing between the lower surface of the interposer and the upper surface of the package substrate. The protrusions may also position the interposer in one or more horizontal directions and/or prevent substantial movement during connecting of the interposer to the package substrate.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: December 17, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uk Kim, Sunchul Kim, Jinkyeong Seol, Byoung Wook Jang
  • Patent number: 10497688
    Abstract: A semiconductor device according to an embodiment includes a first memory chip having a first front surface and a first back surface and having a first memory circuit provided on the first front surface side; a second memory chip having a second front surface and a second back surface facing the first front surface, having a second memory circuit provided on the second front surface side, and being electrically connected to the first memory chip; and a logic chip having the first memory chip provided between the logic chip and the second memory chip, having a third front surface and a third back surface, having a logic circuit provided on the third front surface side, and being electrically connected to the first memory chip.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: December 3, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Satoshi Tsukiyama, Yoichiro Kurita, Hideo Aoki, Kazushige Kawasaki
  • Patent number: 10476318
    Abstract: A battery-embedded device includes a substrate having a wiring, a coil fixed to the substrate, a battery fixed to the substrate, and a first temperature detecting element that is disposed on the substrate and configured to detect a temperature of the battery. An occupancy rate of the wiring in a first region of the substrate which is immediately below the first temperature detecting element is lower than an occupancy rate of the wiring in a second region of the substrate other than the first region.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: November 12, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Takashi Inoue, Hiroshi Yajima, Shinichiro Ito, Katsuya Hagiwara
  • Patent number: 10460921
    Abstract: A layer stack over a substrate is etched using a photoresist pattern deposited on the layer stack as a first mask. The photoresist pattern is in-situ cured using plasma. At least a portion of the photoresist pattern can be modified by curing. In one embodiment, silicon by-products are formed on the photoresist pattern from the plasma. In another embodiment, a carbon from the plasma is embedded into the photoresist pattern. In yet another embodiment, the plasma produces an ultraviolet light to cure the photoresist pattern. The cured photoresist pattern is slimmed. The layer stack is etched using the slimmed photoresist pattern as a second mask.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: October 29, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Kyeong Tae Lee, Sang Wook Kim, Daehee Weon, Sang-jun Choi, Sreekar Bhaviripudi, Jahyong Kuh
  • Patent number: 10460959
    Abstract: A manufacturing method of a package structure is provided. The method includes the following steps. A semiconductor chip is bonded on a carrier, wherein the semiconductor chip comprises a plurality of conductive pads. An insulating material layer is formed over the carrier and encapsulating the semiconductor chip, wherein a thickness of the insulating material layer is greater than a thickness of the semiconductor chip. A first surface of the insulating material layer is patterned to form first openings that expose the conductive pads of the semiconductor chip, and second openings that penetrate through the insulating material layer. A plurality of conductive posts is formed in the first openings, wherein the plurality of conductive posts is electrically connected to the plurality of conductive pads of the semiconductor chip. A plurality of conductive vias is formed in the second opening.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: October 29, 2019
    Assignee: Powertech Technology Inc.
    Inventors: Kun-Yung Huang, Yen-Ju Chen