With Electrical Contact In Hole In Semiconductor (e.g., Lead Extends Through Semiconductor Body) Patents (Class 257/621)
  • Patent number: 12087732
    Abstract: A semiconductor package including an improved isolation bonding film and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first die bonded to a package substrate, the first die including vias extending through a substrate, the vias extending above a top surface of the substrate; a first dielectric film extending along a top surface of the package substrate, along the top surface of the substrate, and along sidewalls of the first die, the vias extending through the first dielectric film; a second die bonded to the first dielectric film and the vias; and an encapsulant over the package substrate, the first die, the first dielectric film, and the second die.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: September 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Tsu Chung, Ku-Feng Yang, Yung-Chi Lin, Wen-Chih Chiou, Chen-Hua Yu
  • Patent number: 12033891
    Abstract: A method of forming a semiconductor device includes forming a material layer over a substrate and forming a first trench in the material layer, forming a conformal capping layer along sidewalls of the first trench, forming a second trench in the material layer while the capping layer is disposed along sidewalls of the first trench and forming a conductive feature within the first trench and the second trench.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: July 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 11990402
    Abstract: A semiconductor apparatus comprising a first substrate, a second substrate coupled with the first substrate via an insulating member, a third substrate coupled to the first substrate and disposed on the opposite side to the second substrate and a conductive layer including an electrode disposed between the first and second substrate is provided. A through via is disposed so as to pass through the second substrate and a part of the insulating member to reach the electrode. An opening is arranged overlapping the electrode in the first substrate and a part of the insulating member. First and second resin layers are disposed between the electrode and the third substrate, and the first resin layer is disposed within the opening, is disposed between the electrode and the second resin layer and has a different Young's modulus from the second resin layer.
    Type: Grant
    Filed: January 23, 2023
    Date of Patent: May 21, 2024
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yuichi Kazue
  • Patent number: 11984410
    Abstract: A method includes forming a reconstructed wafer including encapsulating a device die in an encapsulant, forming a dielectric layer over the device die and the encapsulant, forming a plurality of redistribution lines extending into the dielectric layer to electrically couple to the device die, and forming a metal ring in a common process for forming the plurality of redistribution lines. The metal ring encircles the plurality of redistribution lines, and the metal ring extends into scribe lines of the reconstructed wafer. A die-saw process is performed along scribe lines of the reconstructed wafer to separate a package from the reconstructed wafer. The package includes the device die and at least a portion of the metal ring.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Yu Lee, Chiang Lin, Yueh-Ting Lin, Hua-Wei Tseng, Li-Hsien Huang, Yu-Hsiang Hu
  • Patent number: 11984415
    Abstract: An interposer according to an embodiment of the present invention includes a base layer having opposite first and second surfaces, a wiring structure on the first surface of the base layer, an interposer protective layer disposed on the second surface of the base layer and having a pad recess with a lower surface of the interposer protective layer positioned at a first vertical level and a bottom surface of the pad recess positioned at a second vertical level that is higher than the first vertical level, an interposer pad of which a portion fills the pad recess of the interposer protective layer and the remaining portion protrudes from the interposer protective layer, and an interposer through electrode extending through the base layer and the interposer protective layer to the interposer pad, the interposer through electrode electrically connecting the wiring structure to the interposer pad.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: May 14, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yukyung Park, Ungcheon Kim, Wonil Lee
  • Patent number: 11967551
    Abstract: Various implementations described herein are directed to a device having a switch structure having an input and an output. The device may have a first thru-silicon via that couples a first backside signal to the input of the switch structure. The device may have a second thru-silicon via that couples a second backside signal to the output of the switch structure.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: April 23, 2024
    Assignee: Arm Limited
    Inventors: Ronald Paxton Preston, Sharath Koodali Edathil
  • Patent number: 11967519
    Abstract: An integrated semiconductor device includes a substrate, semiconductor circuit layers, a first insulating layer, a second insulating layer, and an interconnection layer. The semiconductor circuit layers are disposed above the substrate. The semiconductor circuit layers have device portions and isolating portions, and the isolating portions are located among the device portions. The first insulating layer is disposed on the semiconductor circuit layers, and the second insulating layer is disposed on the first insulating layer, and the interconnection layer is disposed on the semiconductor circuit layers. The interconnection layer penetrates the first and second insulating layers to electrically connect the device portions of the semiconductor circuit layers. The second insulating layer or the first and second insulating layers collectively form one or more isolating structures above the isolating portion of the semiconductor circuit layers.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: April 23, 2024
    Assignee: INNOSCIENCE (SUZHOU) SEMICONDUCTOR CO., LTD.
    Inventors: Kai Cao, Jianping Zhang, Lei Zhang, Weigang Yao, Chunhua Zhou
  • Patent number: 11961788
    Abstract: A semiconductor device includes: a semiconductor substrate having opposing first side and second sides; an active region and an isolation region on the first side; a circuit device on the active region; a front side interconnection structure on the first side and including front side interconnection layers disposed on different levels; first and second back side interconnection structures below the second side; a buried structure having a portion disposed in the isolation region and including a conductive line; a first through-electrode structure including a first through-electrode contacting the conductive line and penetrating the semiconductor substrate between the conductive line and the first back side interconnection structure; and a second through-electrode structure including a second through-electrode penetrating the semiconductor substrate between a first front side interconnection layer and the second back side interconnection structure.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: April 16, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyoukyung Cho, Hojin Lee, Kwangjin Moon
  • Patent number: 11955449
    Abstract: A semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on a top surface of the first semiconductor chip. The first semiconductor chip includes a conductive pattern disposed on the top surface of the first semiconductor chip and a first protective layer covering the top surface of the first semiconductor chip and at least partially surrounds the conductive pattern. The second semiconductor chip includes a first pad that contacts a first through electrode on a bottom surface of the second semiconductor chip. A second protective layer surrounds the first pad and covers the bottom surface of the second semiconductor chip. A third protection layer fills a first recess defined in the second protective layer to face the inside of the second protective layer. The first protective layer and the third protective layer contact each other.
    Type: Grant
    Filed: November 10, 2022
    Date of Patent: April 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO, LTD.
    Inventors: Jihwan Suh, Un-Byoung Kang, Taehun Kim, Hyuekjae Lee, Jihwan Hwang, Sang Cheon Park
  • Patent number: 11948920
    Abstract: Provided are a semiconductor device and a method for manufacturing the same, and a semiconductor package. The semiconductor device includes a die stack and a cap substrate. The die stack includes a first die, second dies stacked on the first die, and a third die stacked on the second dies. The first die includes first through semiconductor vias. Each of the second dies include second through semiconductor vias. The third die includes third through semiconductor vias. The cap substrate is disposed on the third die of the die stack. A sum of a thickness of the third die and a thickness of the cap substrate ranges from about 50 ?m to about 80 ?m.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Chun Hsu, Yan-Zuo Tsai, Chia-Yin Chen, Yang-Chih Hsueh, Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 11935873
    Abstract: A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad.
    Type: Grant
    Filed: February 28, 2023
    Date of Patent: March 19, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joonho Jun, Un-Byoung Kang, Sunkyoung Seo, Jongho Lee, Young Kun Jee
  • Patent number: 11923338
    Abstract: A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Ying Ho, Jeng-Shyan Lin, Wen-I Hsu, Feng-Chi Hung, Dun-Nian Yaung, Ying-Ling Tsai
  • Patent number: 11908808
    Abstract: A monolithic microwave integrated circuit (MMIC) with embedded transmission line (ETL) ground shielding is provided. In an exemplary aspect, an ETL MMIC according to this disclosure includes a MMIC substrate having an active side, an ETL dielectric layer covering the active side, and a topside ground plane over the ETL dielectric layer. The active side includes one or more transmission lines or other components which may undesirably couple to metal signal lines (e.g., package metal interconnects) in an external circuit assembly. The topside ground plane in the ETL MMIC provides shielding to reduce such electromagnetic coupling. The topside ground plane can also facilitate improved thermal paths for heat dissipation, such as through a redistribution layer (RDL) to a next higher assembly (NHA) and/or through a backside ground plane of the MMIC substrate.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: February 20, 2024
    Assignee: Qorvo US, Inc.
    Inventor: Andrew Arthur Ketterson
  • Patent number: 11901245
    Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The method includes: providing a package body includes a first semiconductor device, wherein the first semiconductor device includes a plurality of first electrical contacts disposed adjacent to an active surface of the first semiconductor device; measuring the actual positions of the first electrical contacts of the first semiconductor device; providing a plurality of second electrical contacts outside the first semiconductor device; and forming an interconnection structure based on the actual positions of the first electrical contacts of the first semiconductor device and the positions of the second electrical contacts satisfying a predetermined electrical performance criterion by a mask-less process, so as to connect the first electrical contacts and the second electrical contacts and maintain signal integrity during transmission.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: February 13, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chen-Chao Wang, Chih-Yi Huang, Keng-Tuan Chang
  • Patent number: 11894327
    Abstract: Semiconductor devices including one or more interfacing segments patterned within an outer protective layer and associated systems and methods are disclosed herein. The one or more interfacing segments may provide attachment interfaces/surfaces for connection pads. The one or more interfacing segments or a portion thereof may remain uncovered or exposed and provide warpage control for the corresponding semiconductor device.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: February 6, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Wei Zhou, Chien Wen Huang
  • Patent number: 11887913
    Abstract: An integrated circuit device includes a semiconductor substrate, first through-silicon-via (TSV) structures penetrating a first region of the semiconductor substrate and spaced apart from each other by a first pitch, a first individual device between the first TSV structures and spaced apart from the first TSV structures by a distance that is greater than a first keep-off distance, and second TSV structures penetrating a second region of the semiconductor substrate and spaced apart from each other by a second pitch that is less than the first pitch. The second region of the semiconductor device does not include an individual device that is homogeneous with the first individual device and between the second TSV structures.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: January 30, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chajea Jo, Ohguk Kwon, Namhoon Kim, Hyoeun Kim, Seunghoon Yeon
  • Patent number: 11869828
    Abstract: A semiconductor package includes a first die. The first die includes a semiconductor substrate. The semiconductor substrate has a first surface, a second surface opposite to the first surface, and a through hole between the first surface and the second surface and having an inner wall. The inner wall has a first lever arm. A length of the first lever arm is less than a thickness of the semiconductor substrate.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: January 9, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yi-Chi Chen, Ming-Han Wang
  • Patent number: 11848274
    Abstract: A semiconductor package includes: a base chip; a first semiconductor chip disposed on the base chip; a second semiconductor chip disposed on the first semiconductor chip; a first insulating layer disposed between the base chip and the first semiconductor chip; a second insulating layer disposed between the first semiconductor chip and the second semiconductor chip; a first connection bump penetrating through the first insulating layer and connecting the base chip and the first semiconductor chip to each other; and a second connection bump penetrating through the second insulating layer and connecting the first semiconductor chip and the second semiconductor chip to each other. The base chip has a width greater than a width of each of the first and second semiconductor chips. The first insulating layer and the second insulating layer include different materials from each other.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: December 19, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Geol Nam, Gunho Chang
  • Patent number: 11824023
    Abstract: A semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposite to the first surface. An active layer is disposed in a portion of the semiconductor substrate adjacent to the first surface. A through electrode extends in the semiconductor substrate in a vertical direction. The through electrode has a lower surface connected to the active layer and an upper surface positioned at a level lower than a level of the second surface of the semiconductor substrate. A passivation layer is disposed on the second surface of the semiconductor substrate. A bonding pad is arranged on a portion of the passivation layer and the upper surface of the through electrode. The bonding pad has a cross-section with a “T” shape in the vertical direction. The bonding pad is connected to the through electrode.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: November 21, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wonkyun Kwon, Chulyong Jang
  • Patent number: 11804459
    Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The semiconductor device includes a first dielectric layer including a first pad, a second dielectric layer on the first dielectric layer, a through electrode that penetrates the second dielectric layer and is electrically connected to the first pad, an upper passivation layer on the second dielectric layer, a second pad on the upper passivation layer, and an upper barrier layer between the upper passivation layer and the second pad. The first pad and the through electrode include a first material. The second pad includes a second material that is different from the first material of the first pad and the through electrode. The second pad includes a first part on the upper passivation layer, and a second part that extends from the first part into the upper passivation layer and is connected to the through electrode.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: October 31, 2023
    Inventors: Jinho Park, Chin Kim, Yongseung Bang, Jiyeon Baek, Jeong Hoon Ahn
  • Patent number: 11776898
    Abstract: Interconnect metallization of an integrated circuit device includes a sidewall contact between conductive features. In a stacked device, a terminal interconnect of one device layer may intersect a sidewall of a conductive feature in another device layer or between two devices layers. In some examples, a terminal interconnect coupled to a gate, source, or drain terminal of a finFET in a vertically-stacked device may extend to a depth below a plane of the fin and intersect a sidewall of another interconnect, or another device terminal, that is in another plane of the stacked device. A stop layer below a top surface of the conductive feature may allow for sidewall contact while avoiding interconnect shorts.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: October 3, 2023
    Assignee: Intel Corporation
    Inventors: Aaron Lilak, Anh Phan, Gilbert Dewey, Willy Rachmady, Patrick Morrow
  • Patent number: 11764129
    Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a shield structure blocks the migration of charge to a semiconductor device from proximate a through substrate via (TSV). In some embodiments, the IC comprises a substrate, an interconnect structure, the semiconductor device, the TSV, and the shield structure. The interconnect structure is on a frontside of the substrate and comprises a wire. The semiconductor device is on the frontside of the substrate, between the substrate and the interconnect structure. The TSV extends completely through the substrate, from a backside of the substrate to the wire, and comprises metal. The shield structure comprises a PN junction extending completely through the substrate and directly between the semiconductor device and the TSV.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: September 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Wei-Tao Tsai
  • Patent number: 11756890
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: September 12, 2023
    Assignee: Intel Corporation
    Inventors: Srinivas Pietambaram, Rahul Manepalli, Gang Duan
  • Patent number: 11728242
    Abstract: In some examples, a semiconductor package comprises a semiconductor die having a first surface and a second surface opposing the first surface. The package comprises an orifice extending through a thickness of the semiconductor die from the first surface to the second surface. The package comprises a set of metallic nanowires positioned within the orifice and extending through the thickness of the semiconductor die from the first surface to the second surface.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: August 15, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Stassen Cook, Ralf Jakobskrueger Muenster, Sreenivasan Kalyani Koduri
  • Patent number: 11728260
    Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a lower conductive structure, an upper conductive structure and a conductive via. The lower conductive structure includes a first dielectric layer and a first circuit layer in contact with the first dielectric layer. The upper conductive structure is attached to the lower conductive structure. The upper conductive structure includes a plurality of second dielectric layers, a plurality of second circuit layers in contact with the second dielectric layers, and defines an accommodating hole. An insulation material is disposed in the accommodating hole. The conductive via extends through the insulation material, and electrically connects the lower conductive structure.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: August 15, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Patent number: 11721666
    Abstract: A semiconductor package including an improved isolation bonding film and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first die bonded to a package substrate, the first die including vias extending through a substrate, the vias extending above a top surface of the substrate; a first dielectric film extending along a top surface of the package substrate, along the top surface of the substrate, and along sidewalls of the first die, the vias extending through the first dielectric film; a second die bonded to the first dielectric film and the vias; and an encapsulant over the package substrate, the first die, the first dielectric film, and the second die.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: August 8, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Tsu Chung, Ku-Feng Yang, Yung-Chi Lin, Wen-Chih Chiou, Chen-Hua Yu
  • Patent number: 11694941
    Abstract: A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate, an interposer substrate over the package substrate, semiconductor dies over the interposer substrate, and an underfill element over the interposer substrate and between the semiconductor dies and interposer substrate. The semiconductor die package also includes a ring structure and one or more lid structures separated from the ring structure. The ring structure is coupled to the package substrate to control warpage. The lid structures are coupled to the top surfaces of the semiconductor dies to control warpage and help heat dissipation. In addition, the lid structures define a gap to allow a portion of the underfill element between the adjacent semiconductor dies to be exposed, so that stress concentration on that portion can be avoided or reduced. Accordingly, the reliability of the semiconductor die package is improved.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: July 4, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Shen Yeh, Che-Chia Yang, Chia-Kuei Hsu, Ming-Chih Yew, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11688634
    Abstract: Embodiments disclosed herein include composite dies and methods of forming such composite dies. In an embodiment, a composite die comprises a base substrate, a first die over the base substrate, and a second die over the base substrate and adjacent to the first die. In an embodiment an underfill layer is between the first die and the base substrate, between the second die and the base substrate, and between the first die and the second die. In an embodiment, a trench into the underfill layer is between the first die and the second die. In an embodiment the composite die further comprises, a mold layer over the first die and the second die, wherein the mold layer fills the trench.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: June 27, 2023
    Assignee: Intel Corporation
    Inventors: Vipul Mehta, Yiqun Bai, Ziyin Lin, John Decker, Yan Li
  • Patent number: 11670661
    Abstract: An image sensor includes; a substrate having a first surface and an opposing second surface and including unit pixels respectively having photoelectric conversion regions, a semiconductor pattern disposed in a first trench defining the unit pixels, the semiconductor pattern including a first semiconductor layer provided on an inner surface of the first trench and a second semiconductor layer provided on the first semiconductor layer, and a first contact provided on the second surface and connected to the semiconductor pattern. A height of the first semiconductor layer from a bottom surface of the first trench is less than a height of the second semiconductor layer from the bottom surface of the first trench.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: June 6, 2023
    Inventors: Jinyoung Kim, Euiyeol Kim, Hyounmin Baek, Jeong-Ho Lee, Youngwoo Chung, Heegeun Jeong
  • Patent number: 11672111
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first hybrid bonding structure, a memory structure, and a control circuit structure. The first hybrid bonding layer includes a first surface and a second surface. The memory structure is in contact with the first surface. The control circuit structure is configured to control the memory structure. The control circuit structure is in contact with the second surface. A system in package (SiP) structure and a method for manufacturing a plurality of semiconductor structures are also provided.
    Type: Grant
    Filed: July 3, 2020
    Date of Patent: June 6, 2023
    Assignee: AP MEMORY TECHNOLOGY CORPORATION
    Inventors: Wenliang Chen, Lin Ma
  • Patent number: 11651132
    Abstract: A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: May 16, 2023
    Assignee: iCometrue Company Ltd.
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Patent number: 11638376
    Abstract: Electronic devices and methods of forming electronic devices using a reduced number of hardmask materials and reusing lithography reticles are described. Patterned substrates are formed using a combination of etch selective hardmask materials and reusing reticles to provide a pattern of repeating trapezoidal and rhomboidal openings.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: April 25, 2023
    Assignee: Applied Materials, Inc.
    Inventor: Russell Chin Yee Teo
  • Patent number: 11625523
    Abstract: A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.
    Type: Grant
    Filed: February 27, 2021
    Date of Patent: April 11, 2023
    Assignee: iCometrue Company Ltd.
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Patent number: 11621250
    Abstract: A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: April 4, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joonho Jun, Un-Byoung Kang, Sunkyoung Seo, Jongho Lee, Young Kun Jee
  • Patent number: 11600509
    Abstract: A micro pick-up array used to pick up a micro device is provided. The micro pick-up array includes a substrate, a pick-up structure, and a soft polymer layer. The pick-up structure is located on the substrate. The pick-up structure includes a cured photo sensitive material. The soft polymer layer covers the pick-up structure. A manufacturing method of a micro pick-up array is also provided.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: March 7, 2023
    Assignee: Au Optronics Corporation
    Inventors: Ze-Yu Yen, Yi-Fen Lan, Ho-Cheng Lee, Tsung-Tien Wu
  • Patent number: 11581289
    Abstract: A multi-chip package including a first integrated circuit and a second integrated circuit. The first integrated circuit includes a first side having a first conductive layer, a second side having a second conductive layer, and an edge, the first conductive layer coupled to the second conductive layer at a location adjacent to the edge. The second integrated circuit is coupled to the second conductive layer of the first integrated circuit.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: February 14, 2023
    Assignee: STMICROELECTRONICS PTE LTD
    Inventors: Yong Chen, David Gani
  • Patent number: 11574845
    Abstract: A method of manufacturing a 3D semiconductor device, the method including forming a first target structure, the first target structure including at least one upper gate, at least one bottom gate, and a dielectric separation layer disposed between and separating the at least one upper gate and the at least one bottom gate; removing material in a plurality of material removal areas in the first target structure, the plurality of material removal areas including at least one material removal area that extends through the at least one upper gate to a top of the dielectric separation layer; and forming a first contact establishing a first electrical connection to the upper gate and a second contact establishing a second electrical connection to the at least one bottom gate, such that the first contact and second contact are independent of each other.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: February 7, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Daniel Chanemougame, Lars Liebmann, Jeffrey Smith, Anton deVilliers
  • Patent number: 11570900
    Abstract: A circuit forming method, comprising: a coating step of applying a metal-containing liquid and a metal paste in an overlapping manner on a base, the metal-containing liquid containing fine metal particles and the metal paste containing a resin binder and metal particles larger than the fine metal particles in the metal-containing liquid; and a heating step of making the metal-containing liquid and the metal paste coated in the coating step conductive by heating the metal-containing liquid and the metal paste.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: January 31, 2023
    Assignee: FUJI CORPORATION
    Inventor: Kenji Tsukada
  • Patent number: 11557545
    Abstract: A monolithic microwave integrated circuit (MMIC) with embedded transmission line (ETL) ground shielding is provided. In an exemplary aspect, an ETL MMIC according to this disclosure includes a MMIC substrate having an active side, an ETL dielectric layer covering the active side, and a topside ground plane over the ETL dielectric layer. The active side includes one or more transmission lines or other components which may undesirably couple to metal signal lines (e.g., package metal interconnects) in an external circuit assembly. The topside ground plane in the ETL MMIC provides shielding to reduce such electromagnetic coupling. The topside ground plane can also facilitate improved thermal paths for heat dissipation, such as through a redistribution layer (RDL) to a next higher assembly (NHA) and/or through a backside ground plane of the MMIC substrate.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: January 17, 2023
    Assignee: Qorvo US, Inc.
    Inventor: Andrew Arthur Ketterson
  • Patent number: 11527627
    Abstract: A semiconductor Schottky rectifier built in an epitaxial semiconductor layer over a substrate has an anode structure and a cathode structure extending from the surface of the epitaxial layer. The cathode contact structure has a trench structure near the epi-layer and a vertical sidewall surface covered with a gate oxide layer. The cathode structure further comprises a polysilicon element adjacent to the gate oxide layer.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: December 13, 2022
    Assignee: Diodes Incorporated
    Inventors: Kolins Chao, John Huang
  • Patent number: 11521863
    Abstract: Disclosed is a method of fabricating a semiconductor package. The method may include providing a preliminary interposer substrate including connection terminals on a carrier substrate such that the connection terminals are oriented outward, preparing a release film including a base layer, an intermediate layer, and an adhesive layer, attaching the connection terminals to a first surface of the release film, detaching the carrier substrate from the preliminary interposer substrate, cutting the preliminary interposer substrate to form a plurality of interposer substrates separated from each other, irradiating a first light of a first wavelength onto the release film to form an air gap between the connection terminals and the release film, and detaching the interposer substrates from the release film. The intermediate substrate may include a light absorber absorbing the first light.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: December 6, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seon Ho Lee, Yeonseok Kim, Eunyeong Kim
  • Patent number: 11521915
    Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) chip comprising a front-end-of-line (FEOL) through semiconductor-on-substrate via (TSV), as well as a method for forming the IC chip. In some embodiments, a semiconductor layer overlies a substrate. The semiconductor layer may, for example, be or comprise a group III-V semiconductor and/or some other suitable semiconductor(s). A semiconductor device is on the semiconductor layer, and a FEOL layer overlies the semiconductor device. The FEOL TSV extends through the FEOL layer and the semiconductor layer to the substrate at a periphery of the IC chip. An intermetal dielectric (IMD) layer overlies the FEOL TSV and the FEOL layer, and an alternating stack of wires and vias is in the IMD layer.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: December 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Hsiang Wang, Chun Lin Tsai, Jiun-Lei Jerry Yu, Po-Chih Chen
  • Patent number: 11521934
    Abstract: A semiconductor package comprises a package substrate, a semiconductor chip on the package substrate, and an interposer substrate on the semiconductor chip. The interposer substrate comprises a first surface facing the semiconductor chip and a trench in the first surface, the trench vertically overlapping the semiconductor chip. An insulating filler is provided between the semiconductor chip and the interposer substrate, and at least partially fills the trench of the interposer substrate.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: December 6, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jongbo Shim, Jihwang Kim, Choongbin Yim
  • Patent number: 11515274
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die laterally covered by an insulating encapsulation, a first redistribution structure disposed on the semiconductor die and the insulating encapsulation, a second redistribution structure disposed opposite to the first redistribution structure, and a through insulating via (TIV) penetrating through the insulating encapsulation. The semiconductor die is electrically coupled to the first redistribution structure through the second redistribution structure and the TIV. The first redistribution structure includes a patterned conductive layer covered by a patterned dielectric layer, and under-ball metallurgy (UBM) pattern partially covered by the patterned dielectric layer.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: November 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang-Yu Liang, Hsiu-Jen Lin, Kai-Chiang Wu, Chih-Chiang Tsao
  • Patent number: 11476241
    Abstract: An interposer comprises a semiconductor material and includes cache memory under a location on the interposer for a host device. Memory interface circuitry may also be located under one or more locations on the interposer for memory devices. Microelectronic device assemblies incorporating such an interposer and comprising a host device and multiple memory devices are also disclosed, as are methods of fabricating such microelectronic device assemblies.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: October 18, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Chan H. Yoo, Owen R. Fay
  • Patent number: 11469200
    Abstract: A semiconductor device includes a substrate includes a first layer and a second layer over the first layer, a bump disposed over the second layer, a molding disposed over the second layer and surrounding the bump, and a retainer disposed over the second layer, wherein the retainer is disposed between the molding and a periphery of the substrate. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing several bumps on the substrate, disposing a retainer on the substrate and surrounding the bumps, and disposing a molding between the bumps and the retainer.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: October 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tung-Liang Shao, Yu-Chia Lai, Hsien-Ming Tu, Chang-Pin Huang, Ching-Jung Yang
  • Patent number: 11462479
    Abstract: A semiconductor package is provided including a package substrate, a first semiconductor chip on the substrate, with a first surface and a second surface opposite to each other; a plurality of first connection terminals disposed on the first surface contacting an upper surface of the substrate; a second semiconductor chip disposed on the second surface, with a third surface and a fourth surface opposite to each other; a plurality of second connection terminals disposed on the third surface contacting the second surface, wherein an absolute value between a first area, the sum of areas in which the plurality of first connection terminals contact the upper surface of the package substrate, and a second area, the sum of areas in which the plurality of second connection terminals contact the second surface of the first semiconductor chip, is equal to or less than about 0.3 of the first area.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: October 4, 2022
    Inventors: Geol Nam, Young Lyong Kim
  • Patent number: 11428946
    Abstract: According to various embodiments, a collimator includes a substrate defining a plurality of channels through the substrate. The substrate includes a first surface and a second surface opposite the first surface. Each of the channels includes a first aperture exposed from the first surface, a second aperture between the first surface and the second surface, and a third aperture exposed from the second surface. The first aperture and the third aperture are larger than the second aperture.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: August 30, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuan-Feng Chiang, Tsung-Tang Tsai, Min Lung Huang
  • Patent number: 11380726
    Abstract: A sensor device including an interposer including a first via and a lower pad, the lower pad being on a bottom surface of the interposer; an image sensor chip on a top surface of the interposer, the image sensor chip including a logic chip and a sensing chip on the logic chip, the logic chip including first wiring patterns and a second via, and the sensing chip including second wiring patterns; a conductive structure penetrating a portion of the logic chip and the sensing chip, the conductive structure being connected to at least one of the first wiring patterns and at least one of the second wiring patterns; and a passivation layer on an inner surface of the conductive structure, wherein a side surface of the interposer is coplanar with a side surface of the image sensor chip.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: July 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyunsu Jun
  • Patent number: 11355379
    Abstract: A method of fabricating a semiconductor structure includes forming a scissionable layer that is able to absorb infrared (IR) radiation, below a first carrier wafer. A first hard-dielectric layer is formed below the scissionable layer. A second hard-dielectric layer is formed on a top surface of a semiconductor wafer. The first dielectric layer is bonded with the second dielectric layer. Connectors on a bottom portion of the semiconductor wafer are formed to provide an electric connection to the semiconductor wafer. A second carrier wafer is connected to the connectors on the bottom portion of the semiconductor wafer. The first carrier wafer is separated from the semiconductor wafer by degrading the scissionable layer with an IR, by passing the IR through the first carrier wafer. A back end of line (BEOL) wiring passing from a top surface of the semiconductor wafer through the first and second dielectric layers is provided.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: June 7, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mukta Ghate Farooq, Dale Curtis McHerron, Spyridon Skordas