Abstract: Embodiments of a curved vehicle display including a display module having a display surface, a curved glass substrate disposed on the display surface having a first major surface, a second major surface having a second surface area, and a thickness in a range from 0.05 mm to 2 mm, wherein the second major surface comprises a first radius of curvature of 200 mm or greater, wherein, when the display module emits a light, the light transmitted through the glass substrate has a substantially uniform color along 75% or more of the second surface area, when viewed at a viewing angle at a distance of 0.5 meters from the second surface. Methods of forming a curved vehicle display are also disclosed.

Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

Abstract: A semiconductor structure, and a method of making the same, includes a semiconductor substrate having an uppermost surface and a fin structure on the uppermost surface of the semiconductor substrate including n first regions extending perpendicular to the uppermost surface of the semiconductor substrate and n?1 second regions extending between and connecting each of the n first regions and parallel to the uppermost surface of the semiconductor substrate, wherein n?3.

Abstract: A planar optical waveguide based on two-dimensional grating includes an optical waveguide substrate which is a transparent plane-parallel plate, and a functional grating element which includes a two-dimensional grating having two grating directions with an angle of 60° in between. The two-dimensional grating is either protruded or recessed into the top surface of the optical waveguide substrate. The output image from a micro-projector can enter the optical waveguide and then gets projected to cover the entire area of the functional grating element, enabling a human eye to view the output image across a large eye-box.

Abstract: A multi-LED structure comprises a first LED and a separate second LED disposed on a common multi-LED native substrate. The LEDs each comprise a common first layer having a cantilever portion and a base portion and a common second layer having a light-emitting emission portion disposed only over the base portion. An LED electrode electrically connects the first LED to the second LED. The cantilever portion extends in a direction different from the base portion or a length of the cantilever portion is less than a distance between the emission portions of the first and second LEDs.

Abstract: An embodiment includes a method of texturing a semiconductor substrate, a semiconductor substrate manufactured using the method, and a solar cell including the semiconductor substrate, the method including: forming metal nanoparticles on a semiconductor substrate, primarily etching the semiconductor substrate, removing the metal nanoparticles, and secondarily etching the primarily etched semiconductor substrate to form nanostructures.

Abstract: A semiconductor device package structure includes a substrate. The substrate has a circuit structure formed in a die region. The die region is defined by a plurality of scribe lines configured on the substrate. A seal ring is disposed in the substrate and located at a periphery region of the die region, and surrounds at least a portion of the circuit structure. A trench ring is disposed in the substrate between the seal ring and the scribe lines. A packaging passivation cap layer covers over the circuit structure and the seal ring, and covers at least the trench ring.

Abstract: A semiconductor stacking structure according to the present invention comprises: a monocrystalline substrate which is disparate from a nitride semiconductor; an inorganic thin film which is formed on a substrate to define a cavity between the inorganic thin film and the substrate, wherein at least a portion of the inorganic thin film is crystallized with a crystal structure that is the same as the substrate; and a nitride semiconductor layer which is grown from a crystallized inorganic thin film above the cavity. The method and apparatus for separating a nitride semiconductor layer according the present invention mechanically separate between the substrate and the nitride semiconductor layer. The mechanical separation can be performed by a method of separation of applying a vertical force to the substrate and the nitride semiconductor layer, a method of separation of applying a horizontal force, a method of separation of applying a force of a relative circular motion, and a combination thereof.

Abstract: Molecular-beam epitaxy (MBE) and more particularly suboxide MBE (S-MBE) and related structures are disclosed. S-MBE is disclosed that includes the use of a molecular beam of a suboxide that may be subsequently oxidized in a single step reaction to form an oxide film. By way of example, for a gallium oxide (Ga2O3) film, a molecular beam including a suboxide of gallium (Ga2O) may be provided. S-MBE may be performed in adsorption-controlled regimes where there is an excess of source material containing species in order to promote high growth rates for oxide films with improved crystallinity. Source mixtures for providing molecular beams of suboxides are disclosed that include mixtures of a particular element and an oxide of the element in ratios that promote such adsorption-controlled growth regimes. Related structures include oxide films having increased thickness with reduced crystal defects, including single polymorph films of gallium oxide.

Abstract: Provided is a solar cell including: a crystalline silicon semiconductor substrate having a specific radius of curvature; a plurality of microwire structures that extend from a first surface of the crystalline silicon semiconductor substrate in a vertical direction and are arranged spaced apart from each other; a first layer positioned on the first surface of the crystalline silicon semiconductor substrate and forming a P-N junction with the crystalline silicon semiconductor substrate; a first electrode part positioned on the first layer and connected to the first layer; a second layer positioned on a second surface of the crystalline silicon semiconductor substrate which is opposite the first surface; and a second electrode part positioned on the second layer and connected with the second layer.

Abstract: A wafer processing method includes a wafer providing step of placing a polyolefin or polyester sheet on an upper surface of a substrate for supporting a wafer and placing the wafer on an upper surface of the sheet in a condition where a back side of the wafer is exposed upward, a thermocompression bonding step of setting the wafer placed through the sheet on the substrate in an enclosed environment, next evacuating the enclosed environment, and next heating the sheet as applying a pressure to the wafer, thereby uniting the wafer through the sheet to the substrate by thermocompression bonding, a back processing step of processing the back side of the wafer supported through the sheet to the substrate, and a separating step of separating the wafer from the sheet bonded to the substrate.

Abstract: Embodiments of counter-stress structures and methods for forming the same are disclosed. The present disclosure describes a semiconductor wafer including a substrate having a dielectric layer formed thereon and a device region in the dielectric layer. The device region includes at least one semiconductor device. The semiconductor wafer further includes a sacrificial region adjacent to the device region, wherein the sacrificial region includes at least one counter-stress structure configured to counteract wafer stress formed in the device region.

Abstract: The present invention relates to a method for selective etching of a nanostructure (10). The method comprising: providing the nanostructure (10) having a main surface (12) delimited by, in relation to the main surface (12), inclined surfaces (14); and subjecting the nanostructure (10) for a dry etching, wherein the dry etching comprises: subjecting the nanostructure (10) for a low energy particle beam (20) having a direction perpendicular to the main surface (12); whereby a recess (16) in the nanostructure (10) is formed, the recess (16) having its opening at the main surface (12) of the nanostructure (10).

Abstract: Plasma etching processes for forming patterns in high refractive index glass substrates, such as for use as waveguides, are provided herein. The substrates may be formed of glass having a refractive index of greater than or equal to about 1.65 and having less than about 50 wt % SiO2. The plasma etching processes may include both chemical and physical etching components. In some embodiments, the plasma etching processes can include forming a patterned mask layer on at least a portion of the high refractive index glass substrate and exposing the mask layer and high refractive index glass substrate to a plasma to remove high refractive index glass from the exposed portions of the substrate. Any remaining mask layer is subsequently removed from the high refractive index glass substrate. The removal of the glass forms a desired patterned structure, such as a diffractive grating, in the high refractive index glass substrate.

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

Abstract: An approach provides a semiconductor structure with a semiconductor layer that has a plurality of metal lines on the semiconductor layer where a first line of the plurality of metal lines on the semiconductor layer has a different line width than a second line of the plurality of metal lines on the semiconductor layer and a low-k dielectric material covers the plurality of metal lines and the semiconductor layer between the plurality of metal lines.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a crack-stop structure disposed within a semiconductor substrate. The semiconductor substrate has a back-side surface and a front-side surface opposite the back-side surface. Photodetectors are disposed within the semiconductor substrate and are laterally spaced within a device region. An interconnect structure is disposed along the front-side surface. The interconnect structure includes a seal ring structure. A crack-stop structure is disposed within the semiconductor substrate and overlies the seal ring structure. The crack-stop structure continuously extends around the device region.

Abstract: A semiconductor device includes a semiconductor substrate having a cell region and a dummy region surrounding the cell region, a plurality of memory pillar structures, and a supporting layer. The memory pillar structures are on the cell region. The supporting layer is over the semiconductor substrate, interconnecting the memory pillar structures, and having a plurality of first and second opening patterns on the cell region. A first number of the memory pillar structures surround each of the first opening patterns, and a second number of the memory pillar structures surround each of the second opening patterns. The first opening patterns are different from the second opening patterns, the first number is different from the second number, and at least one of the first opening patterns and at least one of the second opening patterns are on a central portion of the cell region.

Abstract: A method includes etching a semiconductor substrate to form a trench, filling a dielectric layer into the trench, with a void being formed in the trench and between opposite portions of the dielectric layer, etching the dielectric layer to reveal the void, forming a diffusion barrier layer on the dielectric layer, and forming a high-reflectivity metal layer on the diffusion barrier layer. The high-reflectivity metal layer has a portion extending into the trench. A remaining portion of the void is enclosed by the high-reflectivity metal layer.

Abstract: A method for forming 3-dimensional vertical NOR-type memory string arrays uses damascene local bit lines is provided. The method of the present invention also avoids ribboning by etching local word lines in two steps. By etching the local word lines in two steps, the aspect ratio in the patterning and etching of stack of local word lines (“word line stacks”) is reduced, which improves the structural stability of the word line stacks.

Abstract: Embodiments of the invention include methods of forming a textile patterned hardmask. In an embodiment, a first hardmask and a second hardmask are formed over a top surface of an interconnect layer in an alternating pattern. A sacrificial cross-grating may then be formed over the first and second hardmasks. In an embodiment, portions of the first hardmask that are not covered by the sacrificial cross-grating are removed to form first openings and a third hardmask is disposed into the first openings. Embodiments may then include etching through portions of the second hardmask that are not covered by the sacrificial cross-grating to form second openings. The second openings may be filled with a fourth hardmask. According to an embodiment, the first, second, third, and fourth hardmasks are etch selective to each other. In an embodiment the sacrificial cross-grating may then be removed.

Abstract: Plasma etching processes for forming patterns in high refractive index glass substrates, such as for use as waveguides, are provided herein. The substrates may be formed of glass having a refractive index of greater than or equal to about 1.65 and having less than about 50 wt % SiO2. The plasma etching processes may include both chemical and physical etching components. In some embodiments, the plasma etching processes can include forming a patterned mask layer on at least a portion of the high refractive index glass substrate and exposing the mask layer and high refractive index glass substrate to a plasma to remove high refractive index glass from the exposed portions of the substrate. Any remaining mask layer is subsequently removed from the high refractive index glass substrate. The removal of the glass forms a desired patterned structure, such as a diffractive grating, in the high refractive index glass substrate.

Abstract: A semiconductor device package and a semiconductor apparatus are provided. The semiconductor device includes a first semiconductor package, a second semiconductor package, and an interposer between the first and second semiconductor packages. The first semiconductor package includes a first semiconductor package substrate and a first semiconductor chip. The second semiconductor package includes a second semiconductor package substrate and a second semiconductor chip. The interposer electrically connects the first semiconductor package to the second semiconductor package and includes a first interposer hole passing through the interposer. The first semiconductor chip includes a second portion which protrudes from a first portion, and the second portion is inserted into the first interposer hole.

Abstract: A semiconductor device includes a fin structure including a cylindrical shape, an inner gate formed inside the fin structure, and an outer gate formed outside the fin structure and connected to the inner gate.

Abstract: An integrated circuit device includes a substrate having a first intellectual property (IP) core including a cell region and a first edge dummy region, fin-type active regions protruding from the cell region, dummy fin-type active regions protruding from the first edge dummy region, gate lines extending, over the cell region of the substrate, the gate lines including two adjacent gate lines spaced apart from each other with a first pitch and two adjacent gate lines spaced apart with a second pitch greater than the first pitch, dummy gate lines over the first edge dummy region of the substrate and equally spaced apart from each other with the first pitch.

Abstract: A method of etching is described. The method includes treating at least a portion of a surface exposed on a substrate with an adsorption-promoting agent to alter a functionality of the exposed surface and cause subsequent adsorption of a carbon-containing precursor, and thereafter, adsorbing the organic precursor to the functionalized surface to form a carbon-containing film. Then, at least a portion of the surface of the carbon-containing film is exposed to an ion flux to remove the adsorbed carbon-containing film and at least a portion of the material of the underlying substrate.

Abstract: A semiconductor device includes a fin structure having a circular cylindrical shape, and including a first recess formed on a first side of the fin structure and a second recess formed on a second side of the fin structure opposite the first side, an inner gate formed inside the fin structure, and an inner gate insulating layer formed between the inner gate and an inner surface of the fin structure.

Abstract: Certain aspects of the present disclosure provide a structure for source or drain in a fin field-effect transistors (finFET) to increase a breakdown voltage between adjacent finFETs in a semiconductor device. One example semiconductor device generally includes a plurality of finFETs, each of the finFETs comprising a source and a drain, wherein at least the source or the drain in at least one finFET of the plurality of finFETs has a profile with at least one rounded tip to increase a breakdown voltage between the at least one finFET and an adjacent finFET in the plurality of finFETs.

Abstract: A semiconductor device includes a substrate, a fin structure protruding from the substrate, a gate insulating layer covering a channel region formed of the fin structure, a gate electrode layer covering the gate insulating layer, and isolation layers disposed on opposite sides of the fin structure. The fin structure includes a bottom portion, a neck portion, and a top portion sequentially disposed on the substrate. A width of the neck portion is less than a width of the bottom portion and a width of a portion of the top portion.

Abstract: Provided is a power semiconductor device that prevents element breakage, thus improving its reliability. The power semiconductor device includes a first main electrode. The first main electrode includes a first metal film, an intermediate film, and a second metal film. The first and second metal films are made of metal having an Al concentration greater than or equal to 95 wt %. The intermediate film contains primary-constituent phases each formed of a metal compound, and contains a secondary-constituent phase formed of an iron group element. The metal compound is that of at least one kind of element selected from a group consisting of a group 4A element, a group 5A element, and a group 6A element, and at least one kind of element selected from a group consisting of C and N. The intermediate film has a higher degree of hardness than the second metal film.

Abstract: Encapsulating a bonded wire with low profile encapsulation includes applying encapsulation over a bonded wire that is connected to a die on a first end and to a circuit component on a second end and truncating a shape of the encapsulation to form a truncated shape.

Abstract: A ceria composite particle dispersion has ceria composite particles having an average particle size of 50 to 350 nm and having the features described below. Each ceria composite particle has a mother particle, a cerium-containing silica layer on the surface thereof, and child particles dispersed inside the cerium-containing silica layer, the mother particles being amorphous silica-based and the child particles being crystalline ceria-based. The child particles have a coefficient of variation (CV value) in a particle size distribution of 14 to 40%. The ceria composite particles have a mass ratio of silica to ceria of 100:11-316. Only the crystal phase of ceria is detected when the ceria composite particles are subjected to X-ray diffraction. The average crystallite size of the crystalline ceria measured by subjecting the ceria composite particles to X-ray diffraction is 10 to 25 nm.

Abstract: A semiconductor apparatus in which are bonded a semiconductor substrate, in which a semiconductor element is arranged, and a supporting substrate is provided. A bonding layer for bonding the semiconductor substrate and the supporting substrate is arranged between the supporting substrate and a front side of the semiconductor substrate on the side of the supporting substrate. The bonding layer includes a first resin member arranged in a first region inside of an outer edge of the semiconductor substrate in an orthographic projection to the front side, and a second resin member arranged in a second region between the outer edge of the semiconductor substrate and the first region, in the orthographic projection to the front side. A linear expansion coefficient of the first resin member is less than a linear expansion coefficient of the second resin member.

Abstract: A FinFET having an asymmetric threshold voltage distribution is provided by forming a halo ion implantation region in a semiconductor fin, and in close proximity to a source region, of the FinFET. The halo ion implantation region is self-aligned to an outermost sidewall surface of the functional gate structure of the FinFET and it has a higher dopant concentration than the remaining portion of the channel region.

Abstract: A method for etching a layer of assembled block copolymer including first and second polymer phases, the etching method including a first step of etching by a first plasma formed from carbon monoxide or a first gas mixture including a fluorocarbon gas and a depolymerising gas, the first etching step being carried out so as to partially etch the first polymer phase and to deposit a carbon layer on the second polymer phase, and a second step of etching by a second plasma formed from a second gas mixture including a depolymerising gas and a gas selected among the carbon oxides and the fluorocarbon gases, the second etching step being carried out so as to etch the first polymer phase and the carbon layer on the second polymer phase.

Abstract: Provided are an epitaxial silicon wafer which can reduce metal contamination by exerting higher gettering capability and a method of manufacturing the same. In a method of manufacturing an epitaxial silicon wafer which includes a silicon wafer, a first silicon epitaxial layer formed on the silicon wafer, a first modifying layer in which carbon is implanted in a surface layer portion of the first silicon epitaxial layer, and a second silicon epitaxial layer on the first modifying layer, the peak concentration of the oxygen concentration profile in the first modifying layer after formation of the second silicon epitaxial layer is set to 2×1017 atoms/cm3 or less and the oxygen concentration of the second silicon epitaxial layer is set to be equal to or less than the SIMS detection lower limit value.

Abstract: An imprinting method and system in which, a template is imprinted onto formable material at a plurality of locations on a substrate. A template filling time varies among the plurality of locations. The template filling time for each of the locations is determined prior to applying the formable material to the substrate. The template is aligned to the substrate each time the template is imprinted onto the formable material during an alignment convergence period that is determined to have completed when real time alignment data indicates that alignment of the template and the substrate is within specified limits. The alignment convergence period and the template filing period overlap. Curing the formable material in the template at each of the plurality of locations after both the alignment convergence period has completed and the template filing period has expired.

Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure and a first antenna layer. The first antenna layer is formed on at least one of the first layer structure and the second layer structure. The first layer structure is formed between the first substrate and the second layer structure.

Abstract: According to an embodiment, a method of manufacturing a semiconductor device includes forming a first modified zone in a wafer by irradiating the wafer with a laser having transmissivity with respect to the wafer along a part of a dicing line on the wafer, and forming a second modified zone in the wafer by irradiating the wafer with the laser along the dicing line on the wafer. The first modified zone is partially formed between a surface of the wafer and the second modified zone, a semiconductor interconnect layer being formed on the surface of the wafer.

Abstract: A method is provided for fabricating an encapsulated emissive element. Beginning with a growth substrate, a plurality of emissive elements is formed. The growth substrate top surface is conformally coated with an encapsulation material. The encapsulation material may be photoresist, a polymer, a light reflective material, or a light absorbing material. The encapsulant is patterned to form fluidic assembly keys having a profile differing from the emissive element profiles. In one aspect, prior to separating the emissive elements from the handling substrate, a fluidic assembly keel or post is formed on each emissive element bottom surface. In one variation, the emissive elements have a horizontal profile. The fluidic assembly key has horizontal profile differing from the emissive element horizontal profile useful in selectively depositing different types of emissive elements during fluidic assembly.

Abstract: A substrate having a first area and a second area is provided. The substrate is patterned to form trenches in the substrate and semiconductor fins between the trenches, wherein the semiconductor fins comprises first semiconductor fins distributed in the first area and second semiconductor fins distributed in the second area. A first fin cut process is performed in the first area to remove portions of the first semiconductor fins. Insulators are formed in the trenches after the first fin cut process is performed. A second fin cut process is performed in the second area to remove portions of the second semiconductor fins until gaps are formed between the insulators in the second area. A gate stack is formed to partially cover the first semiconductor fins, the second semiconductor fins and the insulators.

Abstract: A processing method of a wafer includes a cut groove forming step of carrying out cutting with a cutting blade along streets from the back surface of the wafer to form cut grooves, a wafer dividing step of irradiating the wafer with a laser beam along the cut grooves and dividing the wafer into individual chips after the cut groove forming step is carried out, and a die bonding layer disposing step of applying a liquid die bonding agent on the back surface of the wafer and curing it to form the chips on which die bonding layers are formed on the back surface. According to the processing method of the present invention, the occurrence of clogging in the cutting blade and generation of a burr or the like in the die bonding layers can be prevented.

Abstract: To provide a method of producing a lithium niobate (LN) substrate which allows treatment conditions regarding a temperature, a time, and the like to be easily managed and in which an in-plane distribution of a volume resistance value is very small, and also variations in volume resistivity are small among substrates machined from the same ingot. A method of producing an LN substrate by using an LN single crystal grown by the Czochralski process, in which a lithium niobate single crystal having a Fe concentration of 50 mass ppm or more and 2000 mass ppm or less in the single crystal and being in a form of an ingot is buried in an Al powder or a mixed powder of Al and Al2O3, and heat-treated at a temperature of 450° C. or more and less than 660° C., which is a melting point of aluminum, to produce a lithium niobate single crystal substrate having a volume resistivity controlled to be within a range of 1×108 ?·cm or more to 2×1012 ?·cm or less.

Abstract: A method for fabricating a phase shift mask includes preparing a transmissive substrate on which a first mask region and a second mask region surrounding the first mask region are defined. In the first mask region, main patterns are formed having a first pitch in a first direction and a second direction perpendicular to the first direction. Each of the main patterns has a first area. In at least one row, assist patterns are formed at the first pitch to surround the main patterns. Each of the assist patterns has a second area less than the first area. In the second mask region, dummy patterns are formed in a plurality of rows. The dummy patterns surround the assist patterns at the first pitch. Each of the dummy patterns has a third area greater than the first area.

Abstract: Methods of forming semiconductor structures include providing a polymeric material over a carrier substrate, bonding another substrate to the polymeric material, and lowering a temperature of the polymeric material to below about 15° C. to separate the another substrate from the carrier substrate. Some methods include forming a polymeric material over a first substrate, securing a second substrate to the first substrate over the polymeric material, cooling the polymeric material to a temperature below a glass transition temperature of the polymeric material, and separating the second substrate from the first substrate. Semiconductor structures may include a polymeric material over at least a portion of a first substrate, an adhesive material over the polymeric material, and a second substrate over the adhesive material. The polymeric material may have a glass transition temperature of about 10° C. or lower and a melting point of about 100° C. or greater.

Abstract: A semiconductor light emitting device including a substrate, an electrode and a light emitting region is provided. The substrate may have protruding portions formed in a repeating pattern on substantially an entire surface of the substrate while the rest of the surface may be substantially flat. The cross sections of the protruding portions taken along planes orthogonal to the surface of the substrate may be semi-circular in shape. The cross sections of the protruding portions may in alternative be convex in shape. A buffer layer and a GaN layer may be formed on the substrate.

Abstract: Disclosed are a system and method, wherein, during manufacturing of integrated circuit chips on a semiconductor wafer, an in-line optical inspection is performed to acquire a two-dimensional (2D) image of an area of the semiconductor wafer and to confirm and classify a defect in the area. The 2D image is then converted into a virtual three-dimensional (3D) image. To ensure that the 3D image is accurate, techniques are employed to determine the topography of the surface shown in the 2D image based on material-specific image intensity information and, optionally, to filter out any edge effects that result in anomalies within the 3D image. The resulting 3D image is usable for performing an in-line failure analysis to determine a root cause of a defect. Such an in-line failure analysis can be performed significantly faster than any off-line failure analysis and, thus, allows for essentially real-time advanced process control (APC).

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a non-planar surface features and methods of manufacture. The structure includes a cavity formed in a substrate material. The cavity is covered with epitaxial material that has a non-planar surface topography which imparts a stress component on a transistor.

Abstract: Simplified methods of multiple-patterning photolithography using sequential infiltration synthesis to modify the photoresist such that it withstands plasma etching better than unmodified resist and replaces one or more hard masks and/or a freezing step in MPL processes including litho-etch-litho-etch photolithography or litho-freeze-litho-etch photolithography.

Abstract: The present teachings relate to compositions for forming a negative-tone photopatternable dielectric material, where the compositions include, among other components, an organic filler and one or more photoactive compounds, and where the presence of the organic filler enables the effective removal of such photoactive compounds (after curing, and during or after the development step) which, if allowed to remain in the photopatterned dielectric material, would lead to deleterious effects on its dielectric properties.