Abstract: Disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (IC) packages.

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

Abstract: The present disclosure discloses a pattern sheet, a semiconductor intermediate product, and a hole etching method. The pattern sheet includes a substrate, a dielectric layer, and a mask structure. The mask structure includes a multi-layer mask layer. An uppermost mask layer is a photoresist layer. A thickness of each layer of the mask layer and etching selectivity ratios between the layers below the mask layer satisfy that in each two neighboring layers of the mask layer, a lower layer of the mask layer is etched to form a through-hole penetrating a thickness of the lower layer of the mask layer, a remaining thickness of the upper layer of the mask layer is greater than or equal to zero.

Abstract: A substrate processing method includes providing a surface tension reducing agent as a gas onto a substrate, the substrate having an exposed photoresist layer and layer of developer on the exposed photoresist layer, and causing a bulk flow of the developer in order to remove the developer from the substrate.

Abstract: A semiconductor device includes lower electrodes, a first supporter structure including first supporter patterns interconnecting the lower electrodes, wherein side surfaces of the first supporter patterns and side surfaces of the lower electrodes that are exposed by the first supporter patterns at least partially define a first open region, the first supporter patterns being spaced apart from one another, the first open region extending among the first supporter patterns in a horizontal direction, a dielectric layer covering the first supporter structure and the lower electrodes, and an upper electrode on the dielectric layer. A distance between adjacent ones of the first supporter patterns is smaller than or equal to a pitch of the lower electrodes.

Abstract: A method of forming a semiconductor structure includes forming a first array of mandrels on a hardmask layer disposed on an uppermost surface of a semiconductor substrate. First sidewall image transfer spacers are formed on opposing longitudinal sidewalls of each mandrel in the first array of mandrels. A second array of mandrels is formed on the hardmask layer. Each mandrel in the second array of mandrels is laterally separated from each mandrel in the first array of mandrels by the first sidewall image transfer spacers. Second sidewall image transfer spacers are formed on opposing transversal sidewalls of the first array of mandrels and the second array of mandrels. Portions of the second sidewall image transfer spacers are selectively removed to define a crosslink fin pattern to be transferred to the semiconductor substrate.

Abstract: Embodiments of a curved vehicle display including a display module having a display surface, a curved glass substrate disposed on the display surface having a first major surface, a second major surface having a second surface area, and a thickness in a range from 0.05 mm to 2 mm, wherein the second major surface comprises a first radius of curvature of 200 mm or greater, wherein, when the display module emits a light, the light transmitted through the glass substrate has a substantially uniform color along 75% or more of the second surface area, when viewed at a viewing angle at a distance of 0.5 meters from the second surface. Methods of forming a curved vehicle display are also disclosed.

Abstract: A semiconductor memory device comprises a substrate, first and second lower electrode groups on the substrate and including a plurality of first and second lower electrodes, respectively, and first and second support patterns on side walls of and connecting each of the first and second lower electrodes, respectively. The first lower electrodes include a first center lower electrode arranged within a hexagonal shape defined by first edge lower electrodes. The second lower electrodes include a second center lower electrode arranged within a hexagonal shape defined by second edge lower electrodes. The first center lower electrode is spaced apart from each of the first edge lower electrodes in different first to third directions. The first support pattern is immediately adjacent to the second support pattern. The first center lower electrode is spaced apart from the second center lower electrode in a fourth direction different from the first to third directions.

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

Abstract: The present invention relates to a semiconductor device, wherein the semiconductor substrate includes: a semiconductor layer; and a well region, the semiconductor device includes: a surface electrode provided on a second main surface on a side opposite to a first main surface; a back surface electrode provided on the first main surface; and an upper surface film covering an end edge portion of the surface electrode and at least part of an outer side region outside an end surface of the surface electrode of the semiconductor substrate, the well region includes a portion extending to the outer side region and a portion extending to an inner side region inside the end surface of the surface electrode, and the upper surface film includes at least one outer peripheral opening part provided along an outer periphery of the surface electrode away from the surface electrode of the outer side region.

Abstract: A film formation method includes: providing a substrate including a first region in which a first material is exposed and a second region in which a second material different from the first material is exposed; forming an intermediate film selectively in the second region from the first region and the second region by supplying a processing gas to the substrate; forming a self-assembled monolayer in the first region and the second region after forming the intermediate film; removing the intermediate film and the self-assembled monolayer from the second region by heating the substrate to sublimate the intermediate film; and forming, after sublimation of the intermediate film, a target film selectively in the second region from the first region and the second region in a state in which the self-assembled monolayer is left in the first region.

Abstract: A low-stress packaging structure for a MEMS acceleration sensor chip includes a MEMS sensor chip and a chip carrier. Two sides of the bottom of the sensor chip are provided with a first metal layer and a second metal layer respectively. Two sides of a die attach area of the chip carrier are correspondingly provided with a third metal layer and a fourth metal layer. The first metal layer of the sensor chip and the third metal layer of the chip carrier are bonded together. The second metal layer of the sensor chip and the fourth metal layer of the chip carrier are only in contact but not bonded. A groove is arranged between the first metal layer and the second metal layer at the bottom of the sensor chip. A certain gap is defined between the sensor chip and cavity walls of chip carrier.

Abstract: A method of designing a semiconductor device including the operations of analyzing a vertical abutment between a first standard cell block and a second cell block and, if a mismatch is identified between the first standard cell block and the second cell block initiating the selection of a first modified cell block that reduces the mismatch and a spacing between the first modified cell block and the second cell block, the first modified cell block comprising a first abutment region having a continuous active region arranged along a first axis parallel to an edge of the vertical abutment, and replacing the first standard cell block with the first modified cell block to obtain a first modified layout design and devices manufactured according to the method.

Abstract: An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium.

Abstract: The present disclosure, in some embodiments, relates to a method of forming a semiconductor structure. The method includes forming a plurality of bulk micro defects within a handle substrate. Sizes of the plurality of bulk micro defects are increased to form a plurality of bulk macro defects (BMDs) within the handle substrate. Some of the plurality of BMDs are removed from within a first denuded region and a second denuded region arranged along opposing surfaces of the handle substrate. An insulating layer is formed onto the handle substrate. A device layer comprising a semiconductor material is formed onto the insulating layer. The first denuded region and the second denuded region vertically surround a central region of the handle substrate that has a higher concentration of the plurality of BMDs than both the first denuded region and the second denuded region.

Abstract: Embodiments of a curved vehicle display including a display module having a display surface, a curved glass substrate disposed on the display surface having a first major surface, a second major surface having a second surface area, and a thickness in a range from 0.05 mm to 2 mm, wherein the second major surface comprises a first radius of curvature of 200 mm or greater, wherein, when the display module emits a light, the light transmitted through the glass substrate has a substantially uniform color along 75% or more of the second surface area, when viewed at a viewing angle at a distance of 0.5 meters from the second surface. Methods of forming a curved vehicle display are also disclosed.

Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

Abstract: A semiconductor structure, and a method of making the same, includes a semiconductor substrate having an uppermost surface and a fin structure on the uppermost surface of the semiconductor substrate including n first regions extending perpendicular to the uppermost surface of the semiconductor substrate and n?1 second regions extending between and connecting each of the n first regions and parallel to the uppermost surface of the semiconductor substrate, wherein n?3.

Abstract: A planar optical waveguide based on two-dimensional grating includes an optical waveguide substrate which is a transparent plane-parallel plate, and a functional grating element which includes a two-dimensional grating having two grating directions with an angle of 60° in between. The two-dimensional grating is either protruded or recessed into the top surface of the optical waveguide substrate. The output image from a micro-projector can enter the optical waveguide and then gets projected to cover the entire area of the functional grating element, enabling a human eye to view the output image across a large eye-box.

Abstract: A multi-LED structure comprises a first LED and a separate second LED disposed on a common multi-LED native substrate. The LEDs each comprise a common first layer having a cantilever portion and a base portion and a common second layer having a light-emitting emission portion disposed only over the base portion. An LED electrode electrically connects the first LED to the second LED. The cantilever portion extends in a direction different from the base portion or a length of the cantilever portion is less than a distance between the emission portions of the first and second LEDs.

Abstract: An embodiment includes a method of texturing a semiconductor substrate, a semiconductor substrate manufactured using the method, and a solar cell including the semiconductor substrate, the method including: forming metal nanoparticles on a semiconductor substrate, primarily etching the semiconductor substrate, removing the metal nanoparticles, and secondarily etching the primarily etched semiconductor substrate to form nanostructures.

Abstract: A semiconductor device package structure includes a substrate. The substrate has a circuit structure formed in a die region. The die region is defined by a plurality of scribe lines configured on the substrate. A seal ring is disposed in the substrate and located at a periphery region of the die region, and surrounds at least a portion of the circuit structure. A trench ring is disposed in the substrate between the seal ring and the scribe lines. A packaging passivation cap layer covers over the circuit structure and the seal ring, and covers at least the trench ring.

Abstract: A semiconductor stacking structure according to the present invention comprises: a monocrystalline substrate which is disparate from a nitride semiconductor; an inorganic thin film which is formed on a substrate to define a cavity between the inorganic thin film and the substrate, wherein at least a portion of the inorganic thin film is crystallized with a crystal structure that is the same as the substrate; and a nitride semiconductor layer which is grown from a crystallized inorganic thin film above the cavity. The method and apparatus for separating a nitride semiconductor layer according the present invention mechanically separate between the substrate and the nitride semiconductor layer. The mechanical separation can be performed by a method of separation of applying a vertical force to the substrate and the nitride semiconductor layer, a method of separation of applying a horizontal force, a method of separation of applying a force of a relative circular motion, and a combination thereof.

Abstract: Provided is a solar cell including: a crystalline silicon semiconductor substrate having a specific radius of curvature; a plurality of microwire structures that extend from a first surface of the crystalline silicon semiconductor substrate in a vertical direction and are arranged spaced apart from each other; a first layer positioned on the first surface of the crystalline silicon semiconductor substrate and forming a P-N junction with the crystalline silicon semiconductor substrate; a first electrode part positioned on the first layer and connected to the first layer; a second layer positioned on a second surface of the crystalline silicon semiconductor substrate which is opposite the first surface; and a second electrode part positioned on the second layer and connected with the second layer.

Abstract: Molecular-beam epitaxy (MBE) and more particularly suboxide MBE (S-MBE) and related structures are disclosed. S-MBE is disclosed that includes the use of a molecular beam of a suboxide that may be subsequently oxidized in a single step reaction to form an oxide film. By way of example, for a gallium oxide (Ga2O3) film, a molecular beam including a suboxide of gallium (Ga2O) may be provided. S-MBE may be performed in adsorption-controlled regimes where there is an excess of source material containing species in order to promote high growth rates for oxide films with improved crystallinity. Source mixtures for providing molecular beams of suboxides are disclosed that include mixtures of a particular element and an oxide of the element in ratios that promote such adsorption-controlled growth regimes. Related structures include oxide films having increased thickness with reduced crystal defects, including single polymorph films of gallium oxide.

Abstract: A wafer processing method includes a wafer providing step of placing a polyolefin or polyester sheet on an upper surface of a substrate for supporting a wafer and placing the wafer on an upper surface of the sheet in a condition where a back side of the wafer is exposed upward, a thermocompression bonding step of setting the wafer placed through the sheet on the substrate in an enclosed environment, next evacuating the enclosed environment, and next heating the sheet as applying a pressure to the wafer, thereby uniting the wafer through the sheet to the substrate by thermocompression bonding, a back processing step of processing the back side of the wafer supported through the sheet to the substrate, and a separating step of separating the wafer from the sheet bonded to the substrate.

Abstract: Embodiments of counter-stress structures and methods for forming the same are disclosed. The present disclosure describes a semiconductor wafer including a substrate having a dielectric layer formed thereon and a device region in the dielectric layer. The device region includes at least one semiconductor device. The semiconductor wafer further includes a sacrificial region adjacent to the device region, wherein the sacrificial region includes at least one counter-stress structure configured to counteract wafer stress formed in the device region.

Abstract: The present invention relates to a method for selective etching of a nanostructure (10). The method comprising: providing the nanostructure (10) having a main surface (12) delimited by, in relation to the main surface (12), inclined surfaces (14); and subjecting the nanostructure (10) for a dry etching, wherein the dry etching comprises: subjecting the nanostructure (10) for a low energy particle beam (20) having a direction perpendicular to the main surface (12); whereby a recess (16) in the nanostructure (10) is formed, the recess (16) having its opening at the main surface (12) of the nanostructure (10).

Abstract: Plasma etching processes for forming patterns in high refractive index glass substrates, such as for use as waveguides, are provided herein. The substrates may be formed of glass having a refractive index of greater than or equal to about 1.65 and having less than about 50 wt % SiO2. The plasma etching processes may include both chemical and physical etching components. In some embodiments, the plasma etching processes can include forming a patterned mask layer on at least a portion of the high refractive index glass substrate and exposing the mask layer and high refractive index glass substrate to a plasma to remove high refractive index glass from the exposed portions of the substrate. Any remaining mask layer is subsequently removed from the high refractive index glass substrate. The removal of the glass forms a desired patterned structure, such as a diffractive grating, in the high refractive index glass substrate.

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

Abstract: An approach provides a semiconductor structure with a semiconductor layer that has a plurality of metal lines on the semiconductor layer where a first line of the plurality of metal lines on the semiconductor layer has a different line width than a second line of the plurality of metal lines on the semiconductor layer and a low-k dielectric material covers the plurality of metal lines and the semiconductor layer between the plurality of metal lines.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a crack-stop structure disposed within a semiconductor substrate. The semiconductor substrate has a back-side surface and a front-side surface opposite the back-side surface. Photodetectors are disposed within the semiconductor substrate and are laterally spaced within a device region. An interconnect structure is disposed along the front-side surface. The interconnect structure includes a seal ring structure. A crack-stop structure is disposed within the semiconductor substrate and overlies the seal ring structure. The crack-stop structure continuously extends around the device region.

Abstract: A semiconductor device includes a semiconductor substrate having a cell region and a dummy region surrounding the cell region, a plurality of memory pillar structures, and a supporting layer. The memory pillar structures are on the cell region. The supporting layer is over the semiconductor substrate, interconnecting the memory pillar structures, and having a plurality of first and second opening patterns on the cell region. A first number of the memory pillar structures surround each of the first opening patterns, and a second number of the memory pillar structures surround each of the second opening patterns. The first opening patterns are different from the second opening patterns, the first number is different from the second number, and at least one of the first opening patterns and at least one of the second opening patterns are on a central portion of the cell region.

Abstract: A method includes etching a semiconductor substrate to form a trench, filling a dielectric layer into the trench, with a void being formed in the trench and between opposite portions of the dielectric layer, etching the dielectric layer to reveal the void, forming a diffusion barrier layer on the dielectric layer, and forming a high-reflectivity metal layer on the diffusion barrier layer. The high-reflectivity metal layer has a portion extending into the trench. A remaining portion of the void is enclosed by the high-reflectivity metal layer.

Abstract: A method for forming 3-dimensional vertical NOR-type memory string arrays uses damascene local bit lines is provided. The method of the present invention also avoids ribboning by etching local word lines in two steps. By etching the local word lines in two steps, the aspect ratio in the patterning and etching of stack of local word lines (“word line stacks”) is reduced, which improves the structural stability of the word line stacks.

Abstract: Embodiments of the invention include methods of forming a textile patterned hardmask. In an embodiment, a first hardmask and a second hardmask are formed over a top surface of an interconnect layer in an alternating pattern. A sacrificial cross-grating may then be formed over the first and second hardmasks. In an embodiment, portions of the first hardmask that are not covered by the sacrificial cross-grating are removed to form first openings and a third hardmask is disposed into the first openings. Embodiments may then include etching through portions of the second hardmask that are not covered by the sacrificial cross-grating to form second openings. The second openings may be filled with a fourth hardmask. According to an embodiment, the first, second, third, and fourth hardmasks are etch selective to each other. In an embodiment the sacrificial cross-grating may then be removed.

Abstract: Plasma etching processes for forming patterns in high refractive index glass substrates, such as for use as waveguides, are provided herein. The substrates may be formed of glass having a refractive index of greater than or equal to about 1.65 and having less than about 50 wt % SiO2. The plasma etching processes may include both chemical and physical etching components. In some embodiments, the plasma etching processes can include forming a patterned mask layer on at least a portion of the high refractive index glass substrate and exposing the mask layer and high refractive index glass substrate to a plasma to remove high refractive index glass from the exposed portions of the substrate. Any remaining mask layer is subsequently removed from the high refractive index glass substrate. The removal of the glass forms a desired patterned structure, such as a diffractive grating, in the high refractive index glass substrate.

Abstract: A semiconductor device package and a semiconductor apparatus are provided. The semiconductor device includes a first semiconductor package, a second semiconductor package, and an interposer between the first and second semiconductor packages. The first semiconductor package includes a first semiconductor package substrate and a first semiconductor chip. The second semiconductor package includes a second semiconductor package substrate and a second semiconductor chip. The interposer electrically connects the first semiconductor package to the second semiconductor package and includes a first interposer hole passing through the interposer. The first semiconductor chip includes a second portion which protrudes from a first portion, and the second portion is inserted into the first interposer hole.

Abstract: A semiconductor device includes a fin structure including a cylindrical shape, an inner gate formed inside the fin structure, and an outer gate formed outside the fin structure and connected to the inner gate.

Abstract: An integrated circuit device includes a substrate having a first intellectual property (IP) core including a cell region and a first edge dummy region, fin-type active regions protruding from the cell region, dummy fin-type active regions protruding from the first edge dummy region, gate lines extending, over the cell region of the substrate, the gate lines including two adjacent gate lines spaced apart from each other with a first pitch and two adjacent gate lines spaced apart with a second pitch greater than the first pitch, dummy gate lines over the first edge dummy region of the substrate and equally spaced apart from each other with the first pitch.

Abstract: A method of etching is described. The method includes treating at least a portion of a surface exposed on a substrate with an adsorption-promoting agent to alter a functionality of the exposed surface and cause subsequent adsorption of a carbon-containing precursor, and thereafter, adsorbing the organic precursor to the functionalized surface to form a carbon-containing film. Then, at least a portion of the surface of the carbon-containing film is exposed to an ion flux to remove the adsorbed carbon-containing film and at least a portion of the material of the underlying substrate.

Abstract: A semiconductor device includes a fin structure having a circular cylindrical shape, and including a first recess formed on a first side of the fin structure and a second recess formed on a second side of the fin structure opposite the first side, an inner gate formed inside the fin structure, and an inner gate insulating layer formed between the inner gate and an inner surface of the fin structure.

Abstract: Certain aspects of the present disclosure provide a structure for source or drain in a fin field-effect transistors (finFET) to increase a breakdown voltage between adjacent finFETs in a semiconductor device. One example semiconductor device generally includes a plurality of finFETs, each of the finFETs comprising a source and a drain, wherein at least the source or the drain in at least one finFET of the plurality of finFETs has a profile with at least one rounded tip to increase a breakdown voltage between the at least one finFET and an adjacent finFET in the plurality of finFETs.

Abstract: A semiconductor device includes a substrate, a fin structure protruding from the substrate, a gate insulating layer covering a channel region formed of the fin structure, a gate electrode layer covering the gate insulating layer, and isolation layers disposed on opposite sides of the fin structure. The fin structure includes a bottom portion, a neck portion, and a top portion sequentially disposed on the substrate. A width of the neck portion is less than a width of the bottom portion and a width of a portion of the top portion.

Abstract: Provided is a power semiconductor device that prevents element breakage, thus improving its reliability. The power semiconductor device includes a first main electrode. The first main electrode includes a first metal film, an intermediate film, and a second metal film. The first and second metal films are made of metal having an Al concentration greater than or equal to 95 wt %. The intermediate film contains primary-constituent phases each formed of a metal compound, and contains a secondary-constituent phase formed of an iron group element. The metal compound is that of at least one kind of element selected from a group consisting of a group 4A element, a group 5A element, and a group 6A element, and at least one kind of element selected from a group consisting of C and N. The intermediate film has a higher degree of hardness than the second metal film.

Abstract: Encapsulating a bonded wire with low profile encapsulation includes applying encapsulation over a bonded wire that is connected to a die on a first end and to a circuit component on a second end and truncating a shape of the encapsulation to form a truncated shape.

Abstract: A ceria composite particle dispersion has ceria composite particles having an average particle size of 50 to 350 nm and having the features described below. Each ceria composite particle has a mother particle, a cerium-containing silica layer on the surface thereof, and child particles dispersed inside the cerium-containing silica layer, the mother particles being amorphous silica-based and the child particles being crystalline ceria-based. The child particles have a coefficient of variation (CV value) in a particle size distribution of 14 to 40%. The ceria composite particles have a mass ratio of silica to ceria of 100:11-316. Only the crystal phase of ceria is detected when the ceria composite particles are subjected to X-ray diffraction. The average crystallite size of the crystalline ceria measured by subjecting the ceria composite particles to X-ray diffraction is 10 to 25 nm.

Abstract: A semiconductor apparatus in which are bonded a semiconductor substrate, in which a semiconductor element is arranged, and a supporting substrate is provided. A bonding layer for bonding the semiconductor substrate and the supporting substrate is arranged between the supporting substrate and a front side of the semiconductor substrate on the side of the supporting substrate. The bonding layer includes a first resin member arranged in a first region inside of an outer edge of the semiconductor substrate in an orthographic projection to the front side, and a second resin member arranged in a second region between the outer edge of the semiconductor substrate and the first region, in the orthographic projection to the front side. A linear expansion coefficient of the first resin member is less than a linear expansion coefficient of the second resin member.

Abstract: A FinFET having an asymmetric threshold voltage distribution is provided by forming a halo ion implantation region in a semiconductor fin, and in close proximity to a source region, of the FinFET. The halo ion implantation region is self-aligned to an outermost sidewall surface of the functional gate structure of the FinFET and it has a higher dopant concentration than the remaining portion of the channel region.