Physical Configuration Of Semiconductor (e.g., Mesa, Bevel, Groove, Etc.) Patents (Class 257/618)
  • Patent number: 10788749
    Abstract: An imprinting method and system in which, a template is imprinted onto formable material at a plurality of locations on a substrate. A template filling time varies among the plurality of locations. The template filling time for each of the locations is determined prior to applying the formable material to the substrate. The template is aligned to the substrate each time the template is imprinted onto the formable material during an alignment convergence period that is determined to have completed when real time alignment data indicates that alignment of the template and the substrate is within specified limits. The alignment convergence period and the template filing period overlap. Curing the formable material in the template at each of the plurality of locations after both the alignment convergence period has completed and the template filing period has expired.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: September 29, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Craig William Cone
  • Patent number: 10784206
    Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure and a first antenna layer. The first antenna layer is formed on at least one of the first layer structure and the second layer structure. The first layer structure is formed between the first substrate and the second layer structure.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: September 22, 2020
    Assignee: MEDIATEK INC.
    Inventors: Wen-Sung Hsu, Tao Cheng, Nan-Cheng Chen, Che-Ya Chou, Wen-Chou Wu, Yen-Ju Lu, Chih-Ming Hung, Wei-Hsiu Hsu
  • Patent number: 10777459
    Abstract: According to an embodiment, a method of manufacturing a semiconductor device includes forming a first modified zone in a wafer by irradiating the wafer with a laser having transmissivity with respect to the wafer along a part of a dicing line on the wafer, and forming a second modified zone in the wafer by irradiating the wafer with the laser along the dicing line on the wafer. The first modified zone is partially formed between a surface of the wafer and the second modified zone, a semiconductor interconnect layer being formed on the surface of the wafer.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: September 15, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Takanobu Ono, Tsutomu Fujita
  • Patent number: 10749083
    Abstract: A method is provided for fabricating an encapsulated emissive element. Beginning with a growth substrate, a plurality of emissive elements is formed. The growth substrate top surface is conformally coated with an encapsulation material. The encapsulation material may be photoresist, a polymer, a light reflective material, or a light absorbing material. The encapsulant is patterned to form fluidic assembly keys having a profile differing from the emissive element profiles. In one aspect, prior to separating the emissive elements from the handling substrate, a fluidic assembly keel or post is formed on each emissive element bottom surface. In one variation, the emissive elements have a horizontal profile. The fluidic assembly key has horizontal profile differing from the emissive element horizontal profile useful in selectively depositing different types of emissive elements during fluidic assembly.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: August 18, 2020
    Assignee: eLux Inc.
    Inventors: Kenji Sasaki, Paul J. Schuele
  • Patent number: 10727132
    Abstract: A substrate having a first area and a second area is provided. The substrate is patterned to form trenches in the substrate and semiconductor fins between the trenches, wherein the semiconductor fins comprises first semiconductor fins distributed in the first area and second semiconductor fins distributed in the second area. A first fin cut process is performed in the first area to remove portions of the first semiconductor fins. Insulators are formed in the trenches after the first fin cut process is performed. A second fin cut process is performed in the second area to remove portions of the second semiconductor fins until gaps are formed between the insulators in the second area. A gate stack is formed to partially cover the first semiconductor fins, the second semiconductor fins and the insulators.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10707129
    Abstract: A processing method of a wafer includes a cut groove forming step of carrying out cutting with a cutting blade along streets from the back surface of the wafer to form cut grooves, a wafer dividing step of irradiating the wafer with a laser beam along the cut grooves and dividing the wafer into individual chips after the cut groove forming step is carried out, and a die bonding layer disposing step of applying a liquid die bonding agent on the back surface of the wafer and curing it to form the chips on which die bonding layers are formed on the back surface. According to the processing method of the present invention, the occurrence of clogging in the cutting blade and generation of a burr or the like in the die bonding layers can be prevented.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: July 7, 2020
    Assignee: DISCO CORPORATION
    Inventors: Tetsukazu Sugiya, Heidi Lan
  • Patent number: 10651818
    Abstract: To provide a method of producing a lithium niobate (LN) substrate which allows treatment conditions regarding a temperature, a time, and the like to be easily managed and in which an in-plane distribution of a volume resistance value is very small, and also variations in volume resistivity are small among substrates machined from the same ingot. A method of producing an LN substrate by using an LN single crystal grown by the Czochralski process, in which a lithium niobate single crystal having a Fe concentration of 50 mass ppm or more and 2000 mass ppm or less in the single crystal and being in a form of an ingot is buried in an Al powder or a mixed powder of Al and Al2O3, and heat-treated at a temperature of 450° C. or more and less than 660° C., which is a melting point of aluminum, to produce a lithium niobate single crystal substrate having a volume resistivity controlled to be within a range of 1×108 ?·cm or more to 2×1012 ?·cm or less.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: May 12, 2020
    Assignee: SUMITOMO METAL MINING CO., LTD.
    Inventor: Tomio Kajigaya
  • Patent number: 10620528
    Abstract: A method for fabricating a phase shift mask includes preparing a transmissive substrate on which a first mask region and a second mask region surrounding the first mask region are defined. In the first mask region, main patterns are formed having a first pitch in a first direction and a second direction perpendicular to the first direction. Each of the main patterns has a first area. In at least one row, assist patterns are formed at the first pitch to surround the main patterns. Each of the assist patterns has a second area less than the first area. In the second mask region, dummy patterns are formed in a plurality of rows. The dummy patterns surround the assist patterns at the first pitch. Each of the dummy patterns has a third area greater than the first area.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: April 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO. LTD.
    Inventors: Jae-hee Kim, Chan Hwang
  • Patent number: 10615069
    Abstract: Methods of forming semiconductor structures include providing a polymeric material over a carrier substrate, bonding another substrate to the polymeric material, and lowering a temperature of the polymeric material to below about 15° C. to separate the another substrate from the carrier substrate. Some methods include forming a polymeric material over a first substrate, securing a second substrate to the first substrate over the polymeric material, cooling the polymeric material to a temperature below a glass transition temperature of the polymeric material, and separating the second substrate from the first substrate. Semiconductor structures may include a polymeric material over at least a portion of a first substrate, an adhesive material over the polymeric material, and a second substrate over the adhesive material. The polymeric material may have a glass transition temperature of about 10° C. or lower and a melting point of about 100° C. or greater.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: April 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Sony Varghese
  • Patent number: 10593833
    Abstract: A semiconductor light emitting device including a substrate, an electrode and a light emitting region is provided. The substrate may have protruding portions formed in a repeating pattern on substantially an entire surface of the substrate while the rest of the surface may be substantially flat. The cross sections of the protruding portions taken along planes orthogonal to the surface of the substrate may be semi-circular in shape. The cross sections of the protruding portions may in alternative be convex in shape. A buffer layer and a GaN layer may be formed on the substrate.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: March 17, 2020
    Assignee: Nichia Corporation
    Inventors: Isamu Niki, Motokazu Yamada, Masahiko Sano, Shuji Shioji
  • Patent number: 10580893
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a non-planar surface features and methods of manufacture. The structure includes a cavity formed in a substrate material. The cavity is covered with epitaxial material that has a non-planar surface topography which imparts a stress component on a transistor.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Siva P. Adusumilli, Steven M. Shank, Anthony K. Stamper, John J. Ellis-Monaghan
  • Patent number: 10580615
    Abstract: Disclosed are a system and method, wherein, during manufacturing of integrated circuit chips on a semiconductor wafer, an in-line optical inspection is performed to acquire a two-dimensional (2D) image of an area of the semiconductor wafer and to confirm and classify a defect in the area. The 2D image is then converted into a virtual three-dimensional (3D) image. To ensure that the 3D image is accurate, techniques are employed to determine the topography of the surface shown in the 2D image based on material-specific image intensity information and, optionally, to filter out any edge effects that result in anomalies within the 3D image. The resulting 3D image is usable for performing an in-line failure analysis to determine a root cause of a defect. Such an in-line failure analysis can be performed significantly faster than any off-line failure analysis and, thus, allows for essentially real-time advanced process control (APC).
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kok Hin Teo, Jay A. Mody, Jeffrey B. Riendeau, Philip V. Kaszuba, Jian Qiu
  • Patent number: 10571803
    Abstract: Simplified methods of multiple-patterning photolithography using sequential infiltration synthesis to modify the photoresist such that it withstands plasma etching better than unmodified resist and replaces one or more hard masks and/or a freezing step in MPL processes including litho-etch-litho-etch photolithography or litho-freeze-litho-etch photolithography.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: February 25, 2020
    Assignee: UChicago Argonne, LLC
    Inventors: Seth B. Darling, Jeffrey W. Elam, Yu-Chih Tseng
  • Patent number: 10551745
    Abstract: The present teachings relate to compositions for forming a negative-tone photopatternable dielectric material, where the compositions include, among other components, an organic filler and one or more photoactive compounds, and where the presence of the organic filler enables the effective removal of such photoactive compounds (after curing, and during or after the development step) which, if allowed to remain in the photopatterned dielectric material, would lead to deleterious effects on its dielectric properties.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: February 4, 2020
    Assignee: Flexterra, Inc.
    Inventors: Yan Zheng, Yan Hu, Wei Zhao, Antonio Facchetti
  • Patent number: 10533960
    Abstract: In respective methods for manufacturing a high aspect ratio structure and an ultrasonic probe, a plurality of holes extending in a direction crossing a main surface of a substrate are formed, a plurality of first regions and second regions excluding the first regions from the main surface are periodically defined, and partition walls between the plurality of holes formed in the substrate corresponding to the first regions are removed by etching so that part of each of the partition walls within a predetermined range excluding a bottom portion is left. A high aspect ratio structure and an X-ray imaging apparatus include, over a side wall, a porous member including a plurality of holes extending in a direction crossing a grating surface within a predetermined range excluding a bottom portion in each of a plurality of recesses in a grating.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: January 14, 2020
    Assignee: KONICA MINOLTA, INC.
    Inventors: Mitsuru Yokoyama, Yuko Yamamoto
  • Patent number: 10522728
    Abstract: A chip-scale packaging (CSP) light-emitting device (LED), including a light-emitting semiconductor die, a photoluminescent layer, a chip-side-spacer structure, and a beveled chip reflective structure, is disclosed. The beveled reflective structure is disposed surrounding the chip-edge surfaces of the light-emitting semiconductor die, wherein the chip-side-spacer structure is disposed between the beveled reflective structure and the chip-edge surfaces of the light-emitting semiconductor die. A manufacturing method to fabricate the CSP LED is also disclosed. The CSP LED with a beveled chip reflector can effectively reflect the light radiated from the light-emitting semiconductor die toward the photoluminescent layer so that the light extraction efficiency is improved.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: December 31, 2019
    Assignee: MAVEN OPTRONICS CO., LTD.
    Inventors: Chieh Chen, Tsung-Hsi Wang
  • Patent number: 10522496
    Abstract: A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Li-Hui Cheng, Po-Hao Tsai, Jing-Cheng Lin
  • Patent number: 10516084
    Abstract: A method is provided for fabricating an encapsulated emissive element. Beginning with a growth substrate, a plurality of emissive elements is formed. The growth substrate top surface is conformally coated with an encapsulation material. The encapsulation material may be photoresist, a polymer, a light reflective material, or a light absorbing material. The encapsulant is patterned to form fluidic assembly keys having a profile differing from the emissive element profiles. In one aspect, prior to separating the emissive elements from the handling substrate, a fluidic assembly keel or post is formed on each emissive element bottom surface. In one variation, the emissive elements have a horizontal profile. The fluidic assembly key has horizontal profile differing from the emissive element horizontal profile useful in selectively depositing different types of emissive elements during fluidic assembly.
    Type: Grant
    Filed: September 8, 2018
    Date of Patent: December 24, 2019
    Assignee: eLux, Inc.
    Inventors: Kenji Sasaki, Paul J. Schuele
  • Patent number: 10510819
    Abstract: There is provided a method of forming a light source, the method comprising providing a backplane comprising a backplane substrate and a semiconductor particle formed separately from the backplane substrate and then fixed upon the backplane substrate at a predetermined position. The semiconductor particle can be planarized to remove a portion of the semiconductor particle and to expose at a cross-section of the semiconductor particle a planar surface. Moreover, the backplane may comprise a controllable gated electronic component on or directly beneath the planar surface. The controllable gated electronic component may be configured to control an LED emitter. The method further comprises providing the LED emitter comprising one or more LEDs electrically connected to the backplane such that at least one of the LEDs is electrically connected to the controllable gated electronic component.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: December 17, 2019
    Assignee: DIFTEK LASERS, INC.
    Inventor: Douglas R. Dykaar
  • Patent number: 10490665
    Abstract: A semiconductor device includes a semiconductor substrate having isolation regions formed therein and a fin-shaped semiconductor structure protruding vertically above the isolation regions and extending laterally in a first direction. The device additionally includes a gate dielectric wrapping a channel region of the fin-shaped semiconductor structure and a gate electrode wrapping the gate dielectric. The channel region is interposed in the first direction between a source region and a drain region and has sloped sidewalls and a width that continuously decreases from a base towards a peak of the channel region. The channel region comprises a volume inversion region having a height greater than about 25% of a total height of the channel region.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: November 26, 2019
    Inventor: Sang U. Kim
  • Patent number: 10490527
    Abstract: A method includes aligning a wire with a package body having a contact pad and moving the wire through the package body to form electrical contact with the contact pad.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: November 26, 2019
    Assignee: Intel IP Corporation
    Inventors: Christian Geissler, Sven Albers, Georg Seidemann, Andreas Wolter, Klaus Reingruber, Thomas Wagner, Marc Dittes
  • Patent number: 10475792
    Abstract: Provided is a power transistor device including a substrate structure, a first conductive layer, a second conductive layer and a third conductive layer. The substrate structure has a base portion and fin portions. The fin portions protrude from a surface of the base portion and extend along a first direction. The first conductive layer is disposed across the fin portions and extends along a second direction different from the first direction. The second conductive layer is disposed across the fin portions, is located at one side of the first conductive layer and extends along the second direction. The first spacer is disposed between and in physical contact with the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: November 12, 2019
    Assignee: UBIQ Semiconductor Corp.
    Inventor: Chin-Fu Chen
  • Patent number: 10453688
    Abstract: A method of manufacturing a semiconductor device includes forming a first metal layer on a semiconductor substrate and forming a second metal layer on the first metal layer. The second metal layer is formed of a different metal than the first metal layer. Microwave radiation is applied to the semiconductor substrate, first metal layer, and second metal layer to form an alloy including components of the first metal layer, second metal layer, and the semiconductor substrate.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: October 22, 2019
    Assignees: National Chiao Tung University, Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Hsin Chien, Chi-Wen Liu, Chung-Chun Hsu, Wei-Chun Chi
  • Patent number: 10445453
    Abstract: A cell layout includes a first cell having a plurality of first poly lines extending along a first direction, a second cell having a plurality of second poly lines extending along the first direction, and a boundary cell contiguous with the first cell. The first poly lines have a first uniform poly pitch and the second poly lines have a second uniform poly pitch. The second uniform poly pitch is smaller than the first uniform poly pitch. The boundary cell includes n stripes of first dummy poly lines and m stripes of second dummy poly lines extending along the first direction. The first dummy poly lines have the first uniform poly pitch and the second dummy poly lines have the second uniform pitch.
    Type: Grant
    Filed: March 27, 2016
    Date of Patent: October 15, 2019
    Assignee: MEDIATEK INC.
    Inventor: Jen-Hang Yang
  • Patent number: 10418285
    Abstract: Methods of forming a CT pillar with reduced width and increased distance from neighboring fins and the resulting devices are provided. Embodiments include providing a first pair of fins and a second pair of fins in an oxide layer, wherein the first and second pair of fins include Si; and forming a CT pillar including SiN between the first and second pair of fins and over a portion of the oxide layer, wherein width of the CT pillar and distance between the CT pillar and the first and second pair of fins are inversely proportional.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: September 17, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Chun Yu Wong, Laertis Economikos
  • Patent number: 10395938
    Abstract: A wafer element fabrication method is provided. The wafer element fabrication method includes forming a device element on a substrate such that the device element includes an upper surface and a sidewall extending from the upper surface to the substrate. The wafer element fabrication method further includes forming an adjusted print resolution assist feature (APRAF) on the substrate such that the APRAF is smaller than the device element in at least one dimension. In addition, the wafer element fabrication method includes depositing surrounding material, which is different from materials of the APRAF, to surround the APRAF and to lie on the upper surface in abutment with the sidewall of the device element.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yann A. Mignot, Muthumanickam Sankarapandian
  • Patent number: 10388723
    Abstract: To prevent an intermediate region from contacting a cathode electrode even if a cathode region is partially defective. There is provided a semiconductor device with a semiconductor substrate that has a field stop region where first impurities of a first conduction type are implanted, an intermediate region that is formed on a back surface side of the field stop region and where second impurities of a second conduction type are implanted, and a cathode region of the first conduction type that is formed on a back surface side of the intermediate region. In a back surface of the semiconductor substrate, a concentration of the first impurities is higher than a concentration of the second impurities.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: August 20, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroki Wakimoto, Yuichi Onozawa, Takahiro Tamura, Eri Ogawa
  • Patent number: 10354891
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes forming a filling material, such as an underfill, between a carrier and a plurality of electronic components and filling the filling material in a space between the electronic components to form a spacing portion. The spacing portion has a first segment and a second segment separated from each other to serve as a stress buffer zone. Therefore, when an encapsulation layer encapsulating the electronic components is subsequently ground, the present disclosure can effectively prevent the electronic components from being cracked due to stresses induced by the external grinding force.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: July 16, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Po-Hao Wang, Chih-Jen Yang, Yu-Chih Cheng, Chee-Key Chung, Chang-Fu Lin
  • Patent number: 10347491
    Abstract: Disclosed is a method. The method includes implanting recombination center particles into a semiconductor body via at least one contact hole in an insulation layer formed on top of the semiconductor body, forming a contact electrode electrically connected to the semiconductor body in the at least one contact hole, and annealing the semiconductor body to diffuse the recombination center particles in the semiconductor body. Forming the contact electrode includes forming a barrier layer on sections of the semiconductor body uncovered in the at least one contact hole, wherein the barrier layer is configured to inhibit the recombination center particles from diffusing out of the semiconductor body.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: July 9, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Wolfgang Jantscher, Alexander Binter, Oliver Blank, Petra Fischer, Ravi Keshav Joshi, Kurt Pekoll, Manfred Pippan, Andreas Riegler, Werner Schustereder, Juergen Steinbrenner, Waqas Mumtaz Syed
  • Patent number: 10338472
    Abstract: A mark forming method includes: a step of forming, on a device layer of a wafer, an intermediate layer to which a polymer layer containing a block copolymer is adherable, the device layer including a shot area and a scribe line area; a step of removing a portion, of the intermediate layer, formed in the scribe line area; a step of exposing an image of a mark on the scribe line area and forming, based on the image of the mark, a mark including recessed portion; and a step of applying the polymer layer containing the block copolymer on the device layer of the wafer. When a circuit pattern is formed by using the self-assembly of the block copolymer, it is possible to form the mark simultaneously with the formation of the circuit pattern.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: July 2, 2019
    Assignee: NIKON CORPORATION
    Inventor: Tomoharu Fujiwara
  • Patent number: 10325814
    Abstract: Directed self-assembly (DSA) material, or di-block co-polymer, to pattern features that ultimately define a channel region a gate electrode of a vertical nanowire transistor, potentially based on one lithographic operation. In embodiments, DSA material is confined within a guide opening patterned using convention lithography. In embodiments, channel regions and gate electrode materials are aligned to edges of segregated regions within the DSA material.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Paul A. Nyhus, Swaminathan Sivakumar
  • Patent number: 10309884
    Abstract: A method for predicting the electrical functionality of a semiconductor package, the method includes performing a first stiffness test for a first semiconductor package, receiving failure data for the first semiconductor package, the failure data includes results of an electrical test performed after the first semiconductor package is assembled on a printed circuit board, generating a database comprising results of the first stiffness test as a function of the failure data for the first semiconductor package, performing a second stiffness test for a second semiconductor package, identifying a unique result from the results of the first stiffness test in the database, the unique result aligns with a result of the second stiffness test, and predicting a failure data for the second semiconductor package based on the failure data for the first semiconductor package which corresponds to the unique result of the first stiffness test identified in the database.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: Stephen P. Ayotte, Eric G. Liniger, Travis S. Longenbach
  • Patent number: 10290737
    Abstract: A semiconductor arrangement comprises a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement comprises a second semiconductor column projecting from the substrate region. The second semiconductor column is separated a first distance from the first semiconductor column. The first distance is between about 10 nm to about 30 nm.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Jean-Pierre Colinge, Kuo-Cheng Ching, Ta-Pen Guo, Carlos H. Diaz
  • Patent number: 10263088
    Abstract: Embodiments of the present disclosure include contact structures and methods of forming the same. An embodiment is a method of forming a semiconductor device, the method including forming a contact region over a substrate, forming a dielectric layer over the contact region and the substrate, and forming an opening through the dielectric layer to expose a portion of the contact region. The method further includes forming a metal-silicide layer on the exposed portion of the contact region and along sidewalls of the opening; and filling the opening with a conductive material to form a conductive plug in the dielectric layer, the conductive plug being electrically coupled to the contact region.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: April 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou, Chia-Lin Hsu
  • Patent number: 10263095
    Abstract: A method of forming a semiconductor fin structure is provided. A substrate is provided, which has at least two sub regions and a dummy region disposed between the two sub regions. A recess is disposed in each sub region. A semiconductor layer is formed to fill the recesses. A patterned mask layer is formed on the semiconductor layer in the sub regions and on the substrate in the dummy region. The substrate and the semiconductor layer are removed by using the patterned mask layer as a mask, thereby forming a plurality of fin structures in the sub regions and a plurality of dummy fin structures in the dummy region.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: April 16, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Chih-Kai Hsu, Jyh-Shyang Jenq
  • Patent number: 10249740
    Abstract: An apparatus including a three-dimensional semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the three-dimensional semiconductor body including a plurality of nanowires including a germanium material disposed in respective planes separated in the junction regions by a second material, wherein a lattice constant of the second material is similar to a lattice constant of the germanium material; and a gate stack disposed on the channel region, the gate stack including a gate electrode disposed on a gate dielectric. A method of including forming a plurality of nanowires in separate planes on a substrate, each of the plurality of nanowires including a germanium material and separated from an adjacent nanowire by a sacrificial material; disposing a gate stack on the plurality of nanowires in a designated channel region, the gate stack including a dielectric material and a gate electrode.
    Type: Grant
    Filed: June 27, 2015
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Matthew V. Metz, Van H. Le, Jack T. Kavalieros, Sanaz K. Gardner
  • Patent number: 10249574
    Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate, forming a plurality of integrated circuit (IC) devices on the semiconductor substrate, and forming a seal ring structure surrounding each of the IC devices. Forming the seal ring structure includes forming a plurality of interlayer dielectric layers on the semiconductor substrate, and forming a plurality of hollow through-hole structures within each of the interlayer dielectric layers.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: April 2, 2019
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Long Ling
  • Patent number: 10236317
    Abstract: A method is provided for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer. The method includes selecting a periodicity for the second wafer to be manufactured that matches the periodicity of the first wafer. The method further includes manufacturing the second wafer in accordance with the selected periodicity. The method also includes placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer. The method additionally includes stacking the first wafer onto the second wafer, using a copper-to-copper bonding process to bond the first wafer to the second wafer.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Arvind Kumar, Mark Lamorey
  • Patent number: 10224230
    Abstract: A surface protective sheet is used when grinding the rear surface of a semiconductor wafer having a circuit formed on the front surface, and is provided with: a base material comprising a support film and an antistatic coating layer which includes an inorganic conductive filler and a cured product of a curable resin (A); and an adhesive layer. The stress relaxation percentage of the base material after 1 minute at 10% elongation is at least 60%. The Young's modulus of the base material is 100-2000 MPa.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: March 5, 2019
    Assignee: LINTEC Corporation
    Inventors: Kazuyuki Tamura, Shigeto Okuji
  • Patent number: 10217941
    Abstract: A method for producing an organic light-emitting diode and an organic light-emitting diode are disclosed. In an embodiment, the method includes providing a substrate with a continuous application surface, generating multiple adhesion regions on the application surface, the adhesion regions being completely surrounded by the application surface, applying metal nanowires over the entire surface of the application surface, removing the metal nanowires outside of the adhesion regions by a washing process using a solvent such that the remaining metal nanowires completely or partly form a light-permeable electrode of the organic light-emitting diode, and applying an organic layer sequence onto the light-permeable electrode.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: February 26, 2019
    Assignee: OSRAM OLED GmbH
    Inventors: Silke Scharner, Thomas Wehlus, Nina Riegel, Arne Fleißner, Johannes Rosenberger, Daniel Riedel
  • Patent number: 10211053
    Abstract: Provided is a staircase-shaped connection structure of a three-dimensional semiconductor device. The device includes an electrode structure on a substrate, the electrode structure including an upper staircase region, a lower staircase region, and a buffer region therebetween. The electrode structure includes horizontal electrodes sequentially stacked on the substrate, the horizontal electrodes include a plurality of pad regions constituting a staircase structure of each of the upper and lower staircase regions, and the buffer region has a width that is larger than that of each of the pad regions.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: February 19, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Ik Oh, Daehyun Jang, Ha-Na Kim, Kyoungsub Shin
  • Patent number: 10205009
    Abstract: A superjunction semiconductor device includes a first semiconductor layer doped with a first conductivity type; an active region formed on the first semiconductor layer, the active region including a drift layer; and a termination region disposed to surround the active region, the termination region including a lower edge region disposed on a side surface of the drift layer and an upper edge region disposed on the lower edge region, wherein the upper edge region includes a lower charge balance region disposed on the lower edge region, the lower charge balance region having a second conductivity type different from the first conductivity type, and an upper charge balance region disposed on the lower charge balance region, the upper charge balance region having the first conductivity type.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: February 12, 2019
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Kwang-won Lee, Hye-min Kang, Jae-gil Lee
  • Patent number: 10192868
    Abstract: A semiconductor device and its operation method, relating to semiconductor technology. The semiconductor device comprises a substrate and an active area on the substrate, wherein the active area comprises a first active area and a second active area positioned along an extension direction of the first active area, the first active area comprises a first component, a second component, and a connection component, wherein the first component and the second component each directly contact a side of the connection component, wherein the second active area comprises a third component and a fourth component being separated by a groove isolation, the groove isolation in the second active area corresponds to the connection component in the first active area. The semiconductor device further comprises a first pseudo gate covering the connection component and the groove isolation. This inventive concept reduces over-etching when forming contact components.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: January 29, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Yan Lin Sun, Shou Zhu Guo
  • Patent number: 10189117
    Abstract: A embodiment of the invention includes providing a system and method in accordance with an embodiment of the invention including processing a target surface of interest to adjust interfacial material characteristics such as increasing surface area and/or chemical interaction properties via laser texturizing such as via increasing porosity. An embodiment can include an ultrashort pulse laser (USPL), wherein laser pulses are of a duration of femtoseconds, and adapting the USPL's laser energy output irradiance to athermally convert the target surface of interest's material into a plasma state for re-deposition on the target surface; applying the exemplary embodiment's laser beam energy in a raster pattern across the target surface, wherein the USPL is adapted to nano-structure or texturize the target surface to produce a region having a surface covered by texturized structures that can include nano structures increasing adhesion or chemical reaction properties of the target surface.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: January 29, 2019
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Steve Seghi, Jason Kalishek
  • Patent number: 10177113
    Abstract: A method of mass transferring electronic devices includes following steps. A wafer is provided. The wafer includes a substrate and a plurality of electronic devices. The electronic devices are arranged in a matrix on a surface of the substrate. The wafer is attached to a temporary fixing film. The wafer is cut so that the wafer is divided into a plurality of blocks. Each of the blocks includes at least a part of the electronic devices and a sub-substrate. The temporary fixing film is stretched so that the blocks on the temporary fixing film are separated from each other as the temporary fixing film is stretched. At least a part of the blocks is selected as a predetermined bonding portion, and each of the blocks in the predetermined bonding portion is transferred to a carrying substrate in sequence, so that the electronic devices in the predetermined bonding portion arc bonded to the carrying substrate. The sub-substrates of the blocks are removed.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: January 8, 2019
    Assignee: Genesis Photonics Inc.
    Inventors: Shao-Ying Ting, Yan-Ting Lan, Jing-En Huang, Yi-Ru Huang
  • Patent number: 10170326
    Abstract: A wafer element fabrication method is provided. The wafer element fabrication method includes forming a device element on a substrate such that the device element includes an upper surface and a sidewall extending from the upper surface to the substrate. The wafer element fabrication method further includes forming an adjusted print resolution assist feature (APRAF) on the substrate such that the APRAF is smaller than the device element in at least one dimension. In addition, the wafer element fabrication method includes depositing surrounding material, which is different from materials of the APRAF, to surround the APRAF and to lie on the upper surface in abutment with the sidewall of the device element.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yann A. Mignot, Muthumanickam Sankarapandian
  • Patent number: 10165686
    Abstract: An electrical component having a first package part of a first plastic compound. The first package part has a first trench-shaped formation. A first semiconductor body with an integrated circuit is disposed in the first trench-shaped formation. At least two traces, which run on an outer side of the first package part, are provided on a surface of the first trench-shaped formation, wherein the at least two traces are connected to the integrated circuit. The first trench-shaped formation is filled at least partially with a filling material of a second plastic compound to cover the first semiconductor body.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: December 25, 2018
    Assignee: TDK-Micronas GmbH
    Inventors: Joerg Franke, Klaus Heberle, Oliver Breitwieser, Timo Kaufmann
  • Patent number: 10163709
    Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor device and a second semiconductor device are formed within a semiconductor wafer and a scribe region between the first semiconductor device and the second semiconductor device is patterned. A singulation process is then utilized within the scribe region to singulate the first semiconductor device from the second semiconductor device. The first semiconductor device and the second semiconductor device are then bonded to a second semiconductor substrate and thinned in order to remove extension regions from the first semiconductor device and the second semiconductor device.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hung-Pin Chang, Yi-Hsiu Chen, Ku-Feng Yang, Wen-Chih Chiou
  • Patent number: 10134599
    Abstract: A method of metal-assisted chemical etching comprises forming an array of discrete metal features on a surface of a semiconductor structure, where each discrete metal feature comprises a porous metal body with a plurality of pores extending therethrough and terminating at the surface of the semiconductor structure. The semiconductor structure is exposed to an etchant, and the discrete metal features sink into the semiconductor structure as metal-covered surface regions are etched. Simultaneously, uncovered surface regions are extruded through the pores to form anchoring structures for the discrete metal features. The anchoring structures inhibit detouring or delamination of the discrete metal features during etching. During continued exposure to the etchant, the anchoring structures are gradually removed, leaving an array of holes in the semiconductor structure.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: November 20, 2018
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Xiuling Li, Jeong Dong Kim, Munho Kim, Lingyu Kong
  • Patent number: 10115578
    Abstract: A method of processing a wafer having on a face side thereof a device area with a plurality of devices formed therein and an outer circumferential excess area surrounding the device area includes a grinding step for grinding a reverse side of the wafer corresponding to the device area with a grinding wheel that is smaller in diameter than the wafer, thereby forming a first portion corresponding to the device area and an annular second portion surrounding the first portion, the annular second portion being thicker and more protrusive toward a reverse side thereof than the first portion. In the grinding step, the grinding wheel and the wafer are moved relatively to each other so that the angle formed between the reverse side of the first portion and an inner side surface of the annular second portion is larger than 45° and smaller than 75°.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: October 30, 2018
    Assignee: Disco Corporation
    Inventors: Ryosuke Nishihara, Jun Koide, Kohei Tsujimoto, Minoru Matsuzawa