Physical Configuration Of Semiconductor (e.g., Mesa, Bevel, Groove, Etc.) Patents (Class 257/618)
  • Patent number: 11302734
    Abstract: A method includes etching a semiconductor substrate to form a trench, filling a dielectric layer into the trench, with a void being formed in the trench and between opposite portions of the dielectric layer, etching the dielectric layer to reveal the void, forming a diffusion barrier layer on the dielectric layer, and forming a high-reflectivity metal layer on the diffusion barrier layer. The high-reflectivity metal layer has a portion extending into the trench. A remaining portion of the void is enclosed by the high-reflectivity metal layer.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: April 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chi Wu, Chun-Chieh Fang, Bo-Chang Su, Chien Nan Tu, Yu-Lung Yeh, Kun-Yu Lin, Shih-Shiung Chen
  • Patent number: 11282855
    Abstract: A method for forming 3-dimensional vertical NOR-type memory string arrays uses damascene local bit lines is provided. The method of the present invention also avoids ribboning by etching local word lines in two steps. By etching the local word lines in two steps, the aspect ratio in the patterning and etching of stack of local word lines (“word line stacks”) is reduced, which improves the structural stability of the word line stacks.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: March 22, 2022
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Scott Brad Herner, Wu-Yi Henry Chien, Jie Zhou, Eli Harari
  • Patent number: 11276581
    Abstract: Embodiments of the invention include methods of forming a textile patterned hardmask. In an embodiment, a first hardmask and a second hardmask are formed over a top surface of an interconnect layer in an alternating pattern. A sacrificial cross-grating may then be formed over the first and second hardmasks. In an embodiment, portions of the first hardmask that are not covered by the sacrificial cross-grating are removed to form first openings and a third hardmask is disposed into the first openings. Embodiments may then include etching through portions of the second hardmask that are not covered by the sacrificial cross-grating to form second openings. The second openings may be filled with a fourth hardmask. According to an embodiment, the first, second, third, and fourth hardmasks are etch selective to each other. In an embodiment the sacrificial cross-grating may then be removed.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Kevin Lin, Robert Lindsey Bristol, Alan M. Myers
  • Patent number: 11254606
    Abstract: Plasma etching processes for forming patterns in high refractive index glass substrates, such as for use as waveguides, are provided herein. The substrates may be formed of glass having a refractive index of greater than or equal to about 1.65 and having less than about 50 wt % SiO2. The plasma etching processes may include both chemical and physical etching components. In some embodiments, the plasma etching processes can include forming a patterned mask layer on at least a portion of the high refractive index glass substrate and exposing the mask layer and high refractive index glass substrate to a plasma to remove high refractive index glass from the exposed portions of the substrate. Any remaining mask layer is subsequently removed from the high refractive index glass substrate. The removal of the glass forms a desired patterned structure, such as a diffractive grating, in the high refractive index glass substrate.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: February 22, 2022
    Assignee: Magic Leap, Inc.
    Inventors: Mauro Melli, Christophe Peroz, Vikramjit Singh
  • Patent number: 11244936
    Abstract: A semiconductor device package and a semiconductor apparatus are provided. The semiconductor device includes a first semiconductor package, a second semiconductor package, and an interposer between the first and second semiconductor packages. The first semiconductor package includes a first semiconductor package substrate and a first semiconductor chip. The second semiconductor package includes a second semiconductor package substrate and a second semiconductor chip. The interposer electrically connects the first semiconductor package to the second semiconductor package and includes a first interposer hole passing through the interposer. The first semiconductor chip includes a second portion which protrudes from a first portion, and the second portion is inserted into the first interposer hole.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: February 8, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yun Hyeok Im, Hee Seok Lee, Taek Kyun Shin, Cha Jea Jo
  • Patent number: 11239316
    Abstract: A semiconductor device includes a fin structure including a cylindrical shape, an inner gate formed inside the fin structure, and an outer gate formed outside the fin structure and connected to the inner gate.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: February 1, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc Adam Bergendahl, Gauri Karve, Fee Li Lie, Eric R. Miller, Robert Russell Robison, John Ryan Sporre, Sean Teehan
  • Patent number: 11211375
    Abstract: An integrated circuit device includes a substrate having a first intellectual property (IP) core including a cell region and a first edge dummy region, fin-type active regions protruding from the cell region, dummy fin-type active regions protruding from the first edge dummy region, gate lines extending, over the cell region of the substrate, the gate lines including two adjacent gate lines spaced apart from each other with a first pitch and two adjacent gate lines spaced apart with a second pitch greater than the first pitch, dummy gate lines over the first edge dummy region of the substrate and equally spaced apart from each other with the first pitch.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: December 28, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jina Lee, Hyungjoo Youn
  • Patent number: 11205576
    Abstract: A method of etching is described. The method includes treating at least a portion of a surface exposed on a substrate with an adsorption-promoting agent to alter a functionality of the exposed surface and cause subsequent adsorption of a carbon-containing precursor, and thereafter, adsorbing the organic precursor to the functionalized surface to form a carbon-containing film. Then, at least a portion of the surface of the carbon-containing film is exposed to an ion flux to remove the adsorbed carbon-containing film and at least a portion of the material of the underlying substrate.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: December 21, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Alok Ranjan, Peter Ventzek
  • Patent number: 11127815
    Abstract: A semiconductor device includes a fin structure having a circular cylindrical shape, and including a first recess formed on a first side of the fin structure and a second recess formed on a second side of the fin structure opposite the first side, an inner gate formed inside the fin structure, and an inner gate insulating layer formed between the inner gate and an inner surface of the fin structure.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: September 21, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc Adam Bergendahl, Gauri Karve, Fee Li Lie, Eric R. Miller, Robert Russell Robison, John Ryan Sporre, Sean Teehan
  • Patent number: 11075206
    Abstract: Certain aspects of the present disclosure provide a structure for source or drain in a fin field-effect transistors (finFET) to increase a breakdown voltage between adjacent finFETs in a semiconductor device. One example semiconductor device generally includes a plurality of finFETs, each of the finFETs comprising a source and a drain, wherein at least the source or the drain in at least one finFET of the plurality of finFETs has a profile with at least one rounded tip to increase a breakdown voltage between the at least one finFET and an adjacent finFET in the plurality of finFETs.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: July 27, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Kwanyong Lim, Youn Sung Choi, Ukjin Roh
  • Patent number: 10998427
    Abstract: A semiconductor device includes a substrate, a fin structure protruding from the substrate, a gate insulating layer covering a channel region formed of the fin structure, a gate electrode layer covering the gate insulating layer, and isolation layers disposed on opposite sides of the fin structure. The fin structure includes a bottom portion, a neck portion, and a top portion sequentially disposed on the substrate. A width of the neck portion is less than a width of the bottom portion and a width of a portion of the top portion.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Wei Chang, Chiung Wen Hsu, Yu-Ting Weng
  • Patent number: 10971591
    Abstract: Provided is a power semiconductor device that prevents element breakage, thus improving its reliability. The power semiconductor device includes a first main electrode. The first main electrode includes a first metal film, an intermediate film, and a second metal film. The first and second metal films are made of metal having an Al concentration greater than or equal to 95 wt %. The intermediate film contains primary-constituent phases each formed of a metal compound, and contains a secondary-constituent phase formed of an iron group element. The metal compound is that of at least one kind of element selected from a group consisting of a group 4A element, a group 5A element, and a group 6A element, and at least one kind of element selected from a group consisting of C and N. The intermediate film has a higher degree of hardness than the second metal film.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: April 6, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Dai Kitano
  • Patent number: 10946658
    Abstract: Encapsulating a bonded wire with low profile encapsulation includes applying encapsulation over a bonded wire that is connected to a die on a first end and to a circuit component on a second end and truncating a shape of the encapsulation to form a truncated shape.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: March 16, 2021
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chien-Hua Chen, Michael W. Cumbie, Zhuqing Zhang
  • Patent number: 10920120
    Abstract: A ceria composite particle dispersion has ceria composite particles having an average particle size of 50 to 350 nm and having the features described below. Each ceria composite particle has a mother particle, a cerium-containing silica layer on the surface thereof, and child particles dispersed inside the cerium-containing silica layer, the mother particles being amorphous silica-based and the child particles being crystalline ceria-based. The child particles have a coefficient of variation (CV value) in a particle size distribution of 14 to 40%. The ceria composite particles have a mass ratio of silica to ceria of 100:11-316. Only the crystal phase of ceria is detected when the ceria composite particles are subjected to X-ray diffraction. The average crystallite size of the crystalline ceria measured by subjecting the ceria composite particles to X-ray diffraction is 10 to 25 nm.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: February 16, 2021
    Assignee: JGC CATALYSTS AND CHEMICALS LTD.
    Inventors: Michio Komatsu, Yuji Tawarazako, Shinya Usuda, Kazuhiro Nakayama, Shota Kawakami
  • Patent number: 10916659
    Abstract: A FinFET having an asymmetric threshold voltage distribution is provided by forming a halo ion implantation region in a semiconductor fin, and in close proximity to a source region, of the FinFET. The halo ion implantation region is self-aligned to an outermost sidewall surface of the functional gate structure of the FinFET and it has a higher dopant concentration than the remaining portion of the channel region.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: February 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Choonghyun Lee, Pouya Hashemi, Takashi Ando, Jingyun Zhang
  • Patent number: 10916578
    Abstract: A semiconductor apparatus in which are bonded a semiconductor substrate, in which a semiconductor element is arranged, and a supporting substrate is provided. A bonding layer for bonding the semiconductor substrate and the supporting substrate is arranged between the supporting substrate and a front side of the semiconductor substrate on the side of the supporting substrate. The bonding layer includes a first resin member arranged in a first region inside of an outer edge of the semiconductor substrate in an orthographic projection to the front side, and a second resin member arranged in a second region between the outer edge of the semiconductor substrate and the first region, in the orthographic projection to the front side. A linear expansion coefficient of the first resin member is less than a linear expansion coefficient of the second resin member.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: February 9, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Takahiro Hachisu
  • Patent number: 10875236
    Abstract: A method for etching a layer of assembled block copolymer including first and second polymer phases, the etching method including a first step of etching by a first plasma formed from carbon monoxide or a first gas mixture including a fluorocarbon gas and a depolymerising gas, the first etching step being carried out so as to partially etch the first polymer phase and to deposit a carbon layer on the second polymer phase, and a second step of etching by a second plasma formed from a second gas mixture including a depolymerising gas and a gas selected among the carbon oxides and the fluorocarbon gases, the second etching step being carried out so as to etch the first polymer phase and the carbon layer on the second polymer phase.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: December 29, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas Posseme, Sébastien Barnola, Patricia Pimenta Barros, Aurélien Sarrazin
  • Patent number: 10872768
    Abstract: Provided are an epitaxial silicon wafer which can reduce metal contamination by exerting higher gettering capability and a method of manufacturing the same. In a method of manufacturing an epitaxial silicon wafer which includes a silicon wafer, a first silicon epitaxial layer formed on the silicon wafer, a first modifying layer in which carbon is implanted in a surface layer portion of the first silicon epitaxial layer, and a second silicon epitaxial layer on the first modifying layer, the peak concentration of the oxygen concentration profile in the first modifying layer after formation of the second silicon epitaxial layer is set to 2×1017 atoms/cm3 or less and the oxygen concentration of the second silicon epitaxial layer is set to be equal to or less than the SIMS detection lower limit value.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: December 22, 2020
    Assignee: SUMCO CORPORATION
    Inventor: Ayumi Masada
  • Patent number: 10788749
    Abstract: An imprinting method and system in which, a template is imprinted onto formable material at a plurality of locations on a substrate. A template filling time varies among the plurality of locations. The template filling time for each of the locations is determined prior to applying the formable material to the substrate. The template is aligned to the substrate each time the template is imprinted onto the formable material during an alignment convergence period that is determined to have completed when real time alignment data indicates that alignment of the template and the substrate is within specified limits. The alignment convergence period and the template filing period overlap. Curing the formable material in the template at each of the plurality of locations after both the alignment convergence period has completed and the template filing period has expired.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: September 29, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Craig William Cone
  • Patent number: 10784206
    Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure and a first antenna layer. The first antenna layer is formed on at least one of the first layer structure and the second layer structure. The first layer structure is formed between the first substrate and the second layer structure.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: September 22, 2020
    Assignee: MEDIATEK INC.
    Inventors: Wen-Sung Hsu, Tao Cheng, Nan-Cheng Chen, Che-Ya Chou, Wen-Chou Wu, Yen-Ju Lu, Chih-Ming Hung, Wei-Hsiu Hsu
  • Patent number: 10777459
    Abstract: According to an embodiment, a method of manufacturing a semiconductor device includes forming a first modified zone in a wafer by irradiating the wafer with a laser having transmissivity with respect to the wafer along a part of a dicing line on the wafer, and forming a second modified zone in the wafer by irradiating the wafer with the laser along the dicing line on the wafer. The first modified zone is partially formed between a surface of the wafer and the second modified zone, a semiconductor interconnect layer being formed on the surface of the wafer.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: September 15, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Takanobu Ono, Tsutomu Fujita
  • Patent number: 10749083
    Abstract: A method is provided for fabricating an encapsulated emissive element. Beginning with a growth substrate, a plurality of emissive elements is formed. The growth substrate top surface is conformally coated with an encapsulation material. The encapsulation material may be photoresist, a polymer, a light reflective material, or a light absorbing material. The encapsulant is patterned to form fluidic assembly keys having a profile differing from the emissive element profiles. In one aspect, prior to separating the emissive elements from the handling substrate, a fluidic assembly keel or post is formed on each emissive element bottom surface. In one variation, the emissive elements have a horizontal profile. The fluidic assembly key has horizontal profile differing from the emissive element horizontal profile useful in selectively depositing different types of emissive elements during fluidic assembly.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: August 18, 2020
    Assignee: eLux Inc.
    Inventors: Kenji Sasaki, Paul J. Schuele
  • Patent number: 10727132
    Abstract: A substrate having a first area and a second area is provided. The substrate is patterned to form trenches in the substrate and semiconductor fins between the trenches, wherein the semiconductor fins comprises first semiconductor fins distributed in the first area and second semiconductor fins distributed in the second area. A first fin cut process is performed in the first area to remove portions of the first semiconductor fins. Insulators are formed in the trenches after the first fin cut process is performed. A second fin cut process is performed in the second area to remove portions of the second semiconductor fins until gaps are formed between the insulators in the second area. A gate stack is formed to partially cover the first semiconductor fins, the second semiconductor fins and the insulators.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10707129
    Abstract: A processing method of a wafer includes a cut groove forming step of carrying out cutting with a cutting blade along streets from the back surface of the wafer to form cut grooves, a wafer dividing step of irradiating the wafer with a laser beam along the cut grooves and dividing the wafer into individual chips after the cut groove forming step is carried out, and a die bonding layer disposing step of applying a liquid die bonding agent on the back surface of the wafer and curing it to form the chips on which die bonding layers are formed on the back surface. According to the processing method of the present invention, the occurrence of clogging in the cutting blade and generation of a burr or the like in the die bonding layers can be prevented.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: July 7, 2020
    Assignee: DISCO CORPORATION
    Inventors: Tetsukazu Sugiya, Heidi Lan
  • Patent number: 10651818
    Abstract: To provide a method of producing a lithium niobate (LN) substrate which allows treatment conditions regarding a temperature, a time, and the like to be easily managed and in which an in-plane distribution of a volume resistance value is very small, and also variations in volume resistivity are small among substrates machined from the same ingot. A method of producing an LN substrate by using an LN single crystal grown by the Czochralski process, in which a lithium niobate single crystal having a Fe concentration of 50 mass ppm or more and 2000 mass ppm or less in the single crystal and being in a form of an ingot is buried in an Al powder or a mixed powder of Al and Al2O3, and heat-treated at a temperature of 450° C. or more and less than 660° C., which is a melting point of aluminum, to produce a lithium niobate single crystal substrate having a volume resistivity controlled to be within a range of 1×108 ?·cm or more to 2×1012 ?·cm or less.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: May 12, 2020
    Assignee: SUMITOMO METAL MINING CO., LTD.
    Inventor: Tomio Kajigaya
  • Patent number: 10620528
    Abstract: A method for fabricating a phase shift mask includes preparing a transmissive substrate on which a first mask region and a second mask region surrounding the first mask region are defined. In the first mask region, main patterns are formed having a first pitch in a first direction and a second direction perpendicular to the first direction. Each of the main patterns has a first area. In at least one row, assist patterns are formed at the first pitch to surround the main patterns. Each of the assist patterns has a second area less than the first area. In the second mask region, dummy patterns are formed in a plurality of rows. The dummy patterns surround the assist patterns at the first pitch. Each of the dummy patterns has a third area greater than the first area.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: April 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO. LTD.
    Inventors: Jae-hee Kim, Chan Hwang
  • Patent number: 10615069
    Abstract: Methods of forming semiconductor structures include providing a polymeric material over a carrier substrate, bonding another substrate to the polymeric material, and lowering a temperature of the polymeric material to below about 15° C. to separate the another substrate from the carrier substrate. Some methods include forming a polymeric material over a first substrate, securing a second substrate to the first substrate over the polymeric material, cooling the polymeric material to a temperature below a glass transition temperature of the polymeric material, and separating the second substrate from the first substrate. Semiconductor structures may include a polymeric material over at least a portion of a first substrate, an adhesive material over the polymeric material, and a second substrate over the adhesive material. The polymeric material may have a glass transition temperature of about 10° C. or lower and a melting point of about 100° C. or greater.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: April 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Sony Varghese
  • Patent number: 10593833
    Abstract: A semiconductor light emitting device including a substrate, an electrode and a light emitting region is provided. The substrate may have protruding portions formed in a repeating pattern on substantially an entire surface of the substrate while the rest of the surface may be substantially flat. The cross sections of the protruding portions taken along planes orthogonal to the surface of the substrate may be semi-circular in shape. The cross sections of the protruding portions may in alternative be convex in shape. A buffer layer and a GaN layer may be formed on the substrate.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: March 17, 2020
    Assignee: Nichia Corporation
    Inventors: Isamu Niki, Motokazu Yamada, Masahiko Sano, Shuji Shioji
  • Patent number: 10580615
    Abstract: Disclosed are a system and method, wherein, during manufacturing of integrated circuit chips on a semiconductor wafer, an in-line optical inspection is performed to acquire a two-dimensional (2D) image of an area of the semiconductor wafer and to confirm and classify a defect in the area. The 2D image is then converted into a virtual three-dimensional (3D) image. To ensure that the 3D image is accurate, techniques are employed to determine the topography of the surface shown in the 2D image based on material-specific image intensity information and, optionally, to filter out any edge effects that result in anomalies within the 3D image. The resulting 3D image is usable for performing an in-line failure analysis to determine a root cause of a defect. Such an in-line failure analysis can be performed significantly faster than any off-line failure analysis and, thus, allows for essentially real-time advanced process control (APC).
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kok Hin Teo, Jay A. Mody, Jeffrey B. Riendeau, Philip V. Kaszuba, Jian Qiu
  • Patent number: 10580893
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a non-planar surface features and methods of manufacture. The structure includes a cavity formed in a substrate material. The cavity is covered with epitaxial material that has a non-planar surface topography which imparts a stress component on a transistor.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Siva P. Adusumilli, Steven M. Shank, Anthony K. Stamper, John J. Ellis-Monaghan
  • Patent number: 10571803
    Abstract: Simplified methods of multiple-patterning photolithography using sequential infiltration synthesis to modify the photoresist such that it withstands plasma etching better than unmodified resist and replaces one or more hard masks and/or a freezing step in MPL processes including litho-etch-litho-etch photolithography or litho-freeze-litho-etch photolithography.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: February 25, 2020
    Assignee: UChicago Argonne, LLC
    Inventors: Seth B. Darling, Jeffrey W. Elam, Yu-Chih Tseng
  • Patent number: 10551745
    Abstract: The present teachings relate to compositions for forming a negative-tone photopatternable dielectric material, where the compositions include, among other components, an organic filler and one or more photoactive compounds, and where the presence of the organic filler enables the effective removal of such photoactive compounds (after curing, and during or after the development step) which, if allowed to remain in the photopatterned dielectric material, would lead to deleterious effects on its dielectric properties.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: February 4, 2020
    Assignee: Flexterra, Inc.
    Inventors: Yan Zheng, Yan Hu, Wei Zhao, Antonio Facchetti
  • Patent number: 10533960
    Abstract: In respective methods for manufacturing a high aspect ratio structure and an ultrasonic probe, a plurality of holes extending in a direction crossing a main surface of a substrate are formed, a plurality of first regions and second regions excluding the first regions from the main surface are periodically defined, and partition walls between the plurality of holes formed in the substrate corresponding to the first regions are removed by etching so that part of each of the partition walls within a predetermined range excluding a bottom portion is left. A high aspect ratio structure and an X-ray imaging apparatus include, over a side wall, a porous member including a plurality of holes extending in a direction crossing a grating surface within a predetermined range excluding a bottom portion in each of a plurality of recesses in a grating.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: January 14, 2020
    Assignee: KONICA MINOLTA, INC.
    Inventors: Mitsuru Yokoyama, Yuko Yamamoto
  • Patent number: 10522496
    Abstract: A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Li-Hui Cheng, Po-Hao Tsai, Jing-Cheng Lin
  • Patent number: 10522728
    Abstract: A chip-scale packaging (CSP) light-emitting device (LED), including a light-emitting semiconductor die, a photoluminescent layer, a chip-side-spacer structure, and a beveled chip reflective structure, is disclosed. The beveled reflective structure is disposed surrounding the chip-edge surfaces of the light-emitting semiconductor die, wherein the chip-side-spacer structure is disposed between the beveled reflective structure and the chip-edge surfaces of the light-emitting semiconductor die. A manufacturing method to fabricate the CSP LED is also disclosed. The CSP LED with a beveled chip reflector can effectively reflect the light radiated from the light-emitting semiconductor die toward the photoluminescent layer so that the light extraction efficiency is improved.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: December 31, 2019
    Assignee: MAVEN OPTRONICS CO., LTD.
    Inventors: Chieh Chen, Tsung-Hsi Wang
  • Patent number: 10516084
    Abstract: A method is provided for fabricating an encapsulated emissive element. Beginning with a growth substrate, a plurality of emissive elements is formed. The growth substrate top surface is conformally coated with an encapsulation material. The encapsulation material may be photoresist, a polymer, a light reflective material, or a light absorbing material. The encapsulant is patterned to form fluidic assembly keys having a profile differing from the emissive element profiles. In one aspect, prior to separating the emissive elements from the handling substrate, a fluidic assembly keel or post is formed on each emissive element bottom surface. In one variation, the emissive elements have a horizontal profile. The fluidic assembly key has horizontal profile differing from the emissive element horizontal profile useful in selectively depositing different types of emissive elements during fluidic assembly.
    Type: Grant
    Filed: September 8, 2018
    Date of Patent: December 24, 2019
    Assignee: eLux, Inc.
    Inventors: Kenji Sasaki, Paul J. Schuele
  • Patent number: 10510819
    Abstract: There is provided a method of forming a light source, the method comprising providing a backplane comprising a backplane substrate and a semiconductor particle formed separately from the backplane substrate and then fixed upon the backplane substrate at a predetermined position. The semiconductor particle can be planarized to remove a portion of the semiconductor particle and to expose at a cross-section of the semiconductor particle a planar surface. Moreover, the backplane may comprise a controllable gated electronic component on or directly beneath the planar surface. The controllable gated electronic component may be configured to control an LED emitter. The method further comprises providing the LED emitter comprising one or more LEDs electrically connected to the backplane such that at least one of the LEDs is electrically connected to the controllable gated electronic component.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: December 17, 2019
    Assignee: DIFTEK LASERS, INC.
    Inventor: Douglas R. Dykaar
  • Patent number: 10490665
    Abstract: A semiconductor device includes a semiconductor substrate having isolation regions formed therein and a fin-shaped semiconductor structure protruding vertically above the isolation regions and extending laterally in a first direction. The device additionally includes a gate dielectric wrapping a channel region of the fin-shaped semiconductor structure and a gate electrode wrapping the gate dielectric. The channel region is interposed in the first direction between a source region and a drain region and has sloped sidewalls and a width that continuously decreases from a base towards a peak of the channel region. The channel region comprises a volume inversion region having a height greater than about 25% of a total height of the channel region.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: November 26, 2019
    Inventor: Sang U. Kim
  • Patent number: 10490527
    Abstract: A method includes aligning a wire with a package body having a contact pad and moving the wire through the package body to form electrical contact with the contact pad.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: November 26, 2019
    Assignee: Intel IP Corporation
    Inventors: Christian Geissler, Sven Albers, Georg Seidemann, Andreas Wolter, Klaus Reingruber, Thomas Wagner, Marc Dittes
  • Patent number: 10475792
    Abstract: Provided is a power transistor device including a substrate structure, a first conductive layer, a second conductive layer and a third conductive layer. The substrate structure has a base portion and fin portions. The fin portions protrude from a surface of the base portion and extend along a first direction. The first conductive layer is disposed across the fin portions and extends along a second direction different from the first direction. The second conductive layer is disposed across the fin portions, is located at one side of the first conductive layer and extends along the second direction. The first spacer is disposed between and in physical contact with the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: November 12, 2019
    Assignee: UBIQ Semiconductor Corp.
    Inventor: Chin-Fu Chen
  • Patent number: 10453688
    Abstract: A method of manufacturing a semiconductor device includes forming a first metal layer on a semiconductor substrate and forming a second metal layer on the first metal layer. The second metal layer is formed of a different metal than the first metal layer. Microwave radiation is applied to the semiconductor substrate, first metal layer, and second metal layer to form an alloy including components of the first metal layer, second metal layer, and the semiconductor substrate.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: October 22, 2019
    Assignees: National Chiao Tung University, Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Hsin Chien, Chi-Wen Liu, Chung-Chun Hsu, Wei-Chun Chi
  • Patent number: 10445453
    Abstract: A cell layout includes a first cell having a plurality of first poly lines extending along a first direction, a second cell having a plurality of second poly lines extending along the first direction, and a boundary cell contiguous with the first cell. The first poly lines have a first uniform poly pitch and the second poly lines have a second uniform poly pitch. The second uniform poly pitch is smaller than the first uniform poly pitch. The boundary cell includes n stripes of first dummy poly lines and m stripes of second dummy poly lines extending along the first direction. The first dummy poly lines have the first uniform poly pitch and the second dummy poly lines have the second uniform pitch.
    Type: Grant
    Filed: March 27, 2016
    Date of Patent: October 15, 2019
    Assignee: MEDIATEK INC.
    Inventor: Jen-Hang Yang
  • Patent number: 10418285
    Abstract: Methods of forming a CT pillar with reduced width and increased distance from neighboring fins and the resulting devices are provided. Embodiments include providing a first pair of fins and a second pair of fins in an oxide layer, wherein the first and second pair of fins include Si; and forming a CT pillar including SiN between the first and second pair of fins and over a portion of the oxide layer, wherein width of the CT pillar and distance between the CT pillar and the first and second pair of fins are inversely proportional.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: September 17, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Chun Yu Wong, Laertis Economikos
  • Patent number: 10395938
    Abstract: A wafer element fabrication method is provided. The wafer element fabrication method includes forming a device element on a substrate such that the device element includes an upper surface and a sidewall extending from the upper surface to the substrate. The wafer element fabrication method further includes forming an adjusted print resolution assist feature (APRAF) on the substrate such that the APRAF is smaller than the device element in at least one dimension. In addition, the wafer element fabrication method includes depositing surrounding material, which is different from materials of the APRAF, to surround the APRAF and to lie on the upper surface in abutment with the sidewall of the device element.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yann A. Mignot, Muthumanickam Sankarapandian
  • Patent number: 10388723
    Abstract: To prevent an intermediate region from contacting a cathode electrode even if a cathode region is partially defective. There is provided a semiconductor device with a semiconductor substrate that has a field stop region where first impurities of a first conduction type are implanted, an intermediate region that is formed on a back surface side of the field stop region and where second impurities of a second conduction type are implanted, and a cathode region of the first conduction type that is formed on a back surface side of the intermediate region. In a back surface of the semiconductor substrate, a concentration of the first impurities is higher than a concentration of the second impurities.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: August 20, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroki Wakimoto, Yuichi Onozawa, Takahiro Tamura, Eri Ogawa
  • Patent number: 10354891
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes forming a filling material, such as an underfill, between a carrier and a plurality of electronic components and filling the filling material in a space between the electronic components to form a spacing portion. The spacing portion has a first segment and a second segment separated from each other to serve as a stress buffer zone. Therefore, when an encapsulation layer encapsulating the electronic components is subsequently ground, the present disclosure can effectively prevent the electronic components from being cracked due to stresses induced by the external grinding force.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: July 16, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Po-Hao Wang, Chih-Jen Yang, Yu-Chih Cheng, Chee-Key Chung, Chang-Fu Lin
  • Patent number: 10347491
    Abstract: Disclosed is a method. The method includes implanting recombination center particles into a semiconductor body via at least one contact hole in an insulation layer formed on top of the semiconductor body, forming a contact electrode electrically connected to the semiconductor body in the at least one contact hole, and annealing the semiconductor body to diffuse the recombination center particles in the semiconductor body. Forming the contact electrode includes forming a barrier layer on sections of the semiconductor body uncovered in the at least one contact hole, wherein the barrier layer is configured to inhibit the recombination center particles from diffusing out of the semiconductor body.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: July 9, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Wolfgang Jantscher, Alexander Binter, Oliver Blank, Petra Fischer, Ravi Keshav Joshi, Kurt Pekoll, Manfred Pippan, Andreas Riegler, Werner Schustereder, Juergen Steinbrenner, Waqas Mumtaz Syed
  • Patent number: 10338472
    Abstract: A mark forming method includes: a step of forming, on a device layer of a wafer, an intermediate layer to which a polymer layer containing a block copolymer is adherable, the device layer including a shot area and a scribe line area; a step of removing a portion, of the intermediate layer, formed in the scribe line area; a step of exposing an image of a mark on the scribe line area and forming, based on the image of the mark, a mark including recessed portion; and a step of applying the polymer layer containing the block copolymer on the device layer of the wafer. When a circuit pattern is formed by using the self-assembly of the block copolymer, it is possible to form the mark simultaneously with the formation of the circuit pattern.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: July 2, 2019
    Assignee: NIKON CORPORATION
    Inventor: Tomoharu Fujiwara
  • Patent number: 10325814
    Abstract: Directed self-assembly (DSA) material, or di-block co-polymer, to pattern features that ultimately define a channel region a gate electrode of a vertical nanowire transistor, potentially based on one lithographic operation. In embodiments, DSA material is confined within a guide opening patterned using convention lithography. In embodiments, channel regions and gate electrode materials are aligned to edges of segregated regions within the DSA material.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Paul A. Nyhus, Swaminathan Sivakumar
  • Patent number: 10309884
    Abstract: A method for predicting the electrical functionality of a semiconductor package, the method includes performing a first stiffness test for a first semiconductor package, receiving failure data for the first semiconductor package, the failure data includes results of an electrical test performed after the first semiconductor package is assembled on a printed circuit board, generating a database comprising results of the first stiffness test as a function of the failure data for the first semiconductor package, performing a second stiffness test for a second semiconductor package, identifying a unique result from the results of the first stiffness test in the database, the unique result aligns with a result of the second stiffness test, and predicting a failure data for the second semiconductor package based on the failure data for the first semiconductor package which corresponds to the unique result of the first stiffness test identified in the database.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: Stephen P. Ayotte, Eric G. Liniger, Travis S. Longenbach