Physical Configuration Of Semiconductor (e.g., Mesa, Bevel, Groove, Etc.) Patents (Class 257/618)
  • Patent number: 10325814
    Abstract: Directed self-assembly (DSA) material, or di-block co-polymer, to pattern features that ultimately define a channel region a gate electrode of a vertical nanowire transistor, potentially based on one lithographic operation. In embodiments, DSA material is confined within a guide opening patterned using convention lithography. In embodiments, channel regions and gate electrode materials are aligned to edges of segregated regions within the DSA material.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Paul A. Nyhus, Swaminathan Sivakumar
  • Patent number: 10309884
    Abstract: A method for predicting the electrical functionality of a semiconductor package, the method includes performing a first stiffness test for a first semiconductor package, receiving failure data for the first semiconductor package, the failure data includes results of an electrical test performed after the first semiconductor package is assembled on a printed circuit board, generating a database comprising results of the first stiffness test as a function of the failure data for the first semiconductor package, performing a second stiffness test for a second semiconductor package, identifying a unique result from the results of the first stiffness test in the database, the unique result aligns with a result of the second stiffness test, and predicting a failure data for the second semiconductor package based on the failure data for the first semiconductor package which corresponds to the unique result of the first stiffness test identified in the database.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: Stephen P. Ayotte, Eric G. Liniger, Travis S. Longenbach
  • Patent number: 10290737
    Abstract: A semiconductor arrangement comprises a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement comprises a second semiconductor column projecting from the substrate region. The second semiconductor column is separated a first distance from the first semiconductor column. The first distance is between about 10 nm to about 30 nm.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Jean-Pierre Colinge, Kuo-Cheng Ching, Ta-Pen Guo, Carlos H. Diaz
  • Patent number: 10263088
    Abstract: Embodiments of the present disclosure include contact structures and methods of forming the same. An embodiment is a method of forming a semiconductor device, the method including forming a contact region over a substrate, forming a dielectric layer over the contact region and the substrate, and forming an opening through the dielectric layer to expose a portion of the contact region. The method further includes forming a metal-silicide layer on the exposed portion of the contact region and along sidewalls of the opening; and filling the opening with a conductive material to form a conductive plug in the dielectric layer, the conductive plug being electrically coupled to the contact region.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: April 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou, Chia-Lin Hsu
  • Patent number: 10263095
    Abstract: A method of forming a semiconductor fin structure is provided. A substrate is provided, which has at least two sub regions and a dummy region disposed between the two sub regions. A recess is disposed in each sub region. A semiconductor layer is formed to fill the recesses. A patterned mask layer is formed on the semiconductor layer in the sub regions and on the substrate in the dummy region. The substrate and the semiconductor layer are removed by using the patterned mask layer as a mask, thereby forming a plurality of fin structures in the sub regions and a plurality of dummy fin structures in the dummy region.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: April 16, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Chih-Kai Hsu, Jyh-Shyang Jenq
  • Patent number: 10249740
    Abstract: An apparatus including a three-dimensional semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the three-dimensional semiconductor body including a plurality of nanowires including a germanium material disposed in respective planes separated in the junction regions by a second material, wherein a lattice constant of the second material is similar to a lattice constant of the germanium material; and a gate stack disposed on the channel region, the gate stack including a gate electrode disposed on a gate dielectric. A method of including forming a plurality of nanowires in separate planes on a substrate, each of the plurality of nanowires including a germanium material and separated from an adjacent nanowire by a sacrificial material; disposing a gate stack on the plurality of nanowires in a designated channel region, the gate stack including a dielectric material and a gate electrode.
    Type: Grant
    Filed: June 27, 2015
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Matthew V. Metz, Van H. Le, Jack T. Kavalieros, Sanaz K. Gardner
  • Patent number: 10249574
    Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate, forming a plurality of integrated circuit (IC) devices on the semiconductor substrate, and forming a seal ring structure surrounding each of the IC devices. Forming the seal ring structure includes forming a plurality of interlayer dielectric layers on the semiconductor substrate, and forming a plurality of hollow through-hole structures within each of the interlayer dielectric layers.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: April 2, 2019
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Long Ling
  • Patent number: 10236317
    Abstract: A method is provided for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer. The method includes selecting a periodicity for the second wafer to be manufactured that matches the periodicity of the first wafer. The method further includes manufacturing the second wafer in accordance with the selected periodicity. The method also includes placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer. The method additionally includes stacking the first wafer onto the second wafer, using a copper-to-copper bonding process to bond the first wafer to the second wafer.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Arvind Kumar, Mark Lamorey
  • Patent number: 10224230
    Abstract: A surface protective sheet is used when grinding the rear surface of a semiconductor wafer having a circuit formed on the front surface, and is provided with: a base material comprising a support film and an antistatic coating layer which includes an inorganic conductive filler and a cured product of a curable resin (A); and an adhesive layer. The stress relaxation percentage of the base material after 1 minute at 10% elongation is at least 60%. The Young's modulus of the base material is 100-2000 MPa.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: March 5, 2019
    Assignee: LINTEC Corporation
    Inventors: Kazuyuki Tamura, Shigeto Okuji
  • Patent number: 10217941
    Abstract: A method for producing an organic light-emitting diode and an organic light-emitting diode are disclosed. In an embodiment, the method includes providing a substrate with a continuous application surface, generating multiple adhesion regions on the application surface, the adhesion regions being completely surrounded by the application surface, applying metal nanowires over the entire surface of the application surface, removing the metal nanowires outside of the adhesion regions by a washing process using a solvent such that the remaining metal nanowires completely or partly form a light-permeable electrode of the organic light-emitting diode, and applying an organic layer sequence onto the light-permeable electrode.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: February 26, 2019
    Assignee: OSRAM OLED GmbH
    Inventors: Silke Scharner, Thomas Wehlus, Nina Riegel, Arne Fleißner, Johannes Rosenberger, Daniel Riedel
  • Patent number: 10211053
    Abstract: Provided is a staircase-shaped connection structure of a three-dimensional semiconductor device. The device includes an electrode structure on a substrate, the electrode structure including an upper staircase region, a lower staircase region, and a buffer region therebetween. The electrode structure includes horizontal electrodes sequentially stacked on the substrate, the horizontal electrodes include a plurality of pad regions constituting a staircase structure of each of the upper and lower staircase regions, and the buffer region has a width that is larger than that of each of the pad regions.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: February 19, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Ik Oh, Daehyun Jang, Ha-Na Kim, Kyoungsub Shin
  • Patent number: 10205009
    Abstract: A superjunction semiconductor device includes a first semiconductor layer doped with a first conductivity type; an active region formed on the first semiconductor layer, the active region including a drift layer; and a termination region disposed to surround the active region, the termination region including a lower edge region disposed on a side surface of the drift layer and an upper edge region disposed on the lower edge region, wherein the upper edge region includes a lower charge balance region disposed on the lower edge region, the lower charge balance region having a second conductivity type different from the first conductivity type, and an upper charge balance region disposed on the lower charge balance region, the upper charge balance region having the first conductivity type.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: February 12, 2019
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Kwang-won Lee, Hye-min Kang, Jae-gil Lee
  • Patent number: 10192868
    Abstract: A semiconductor device and its operation method, relating to semiconductor technology. The semiconductor device comprises a substrate and an active area on the substrate, wherein the active area comprises a first active area and a second active area positioned along an extension direction of the first active area, the first active area comprises a first component, a second component, and a connection component, wherein the first component and the second component each directly contact a side of the connection component, wherein the second active area comprises a third component and a fourth component being separated by a groove isolation, the groove isolation in the second active area corresponds to the connection component in the first active area. The semiconductor device further comprises a first pseudo gate covering the connection component and the groove isolation. This inventive concept reduces over-etching when forming contact components.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: January 29, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Yan Lin Sun, Shou Zhu Guo
  • Patent number: 10189117
    Abstract: A embodiment of the invention includes providing a system and method in accordance with an embodiment of the invention including processing a target surface of interest to adjust interfacial material characteristics such as increasing surface area and/or chemical interaction properties via laser texturizing such as via increasing porosity. An embodiment can include an ultrashort pulse laser (USPL), wherein laser pulses are of a duration of femtoseconds, and adapting the USPL's laser energy output irradiance to athermally convert the target surface of interest's material into a plasma state for re-deposition on the target surface; applying the exemplary embodiment's laser beam energy in a raster pattern across the target surface, wherein the USPL is adapted to nano-structure or texturize the target surface to produce a region having a surface covered by texturized structures that can include nano structures increasing adhesion or chemical reaction properties of the target surface.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: January 29, 2019
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Steve Seghi, Jason Kalishek
  • Patent number: 10177113
    Abstract: A method of mass transferring electronic devices includes following steps. A wafer is provided. The wafer includes a substrate and a plurality of electronic devices. The electronic devices are arranged in a matrix on a surface of the substrate. The wafer is attached to a temporary fixing film. The wafer is cut so that the wafer is divided into a plurality of blocks. Each of the blocks includes at least a part of the electronic devices and a sub-substrate. The temporary fixing film is stretched so that the blocks on the temporary fixing film are separated from each other as the temporary fixing film is stretched. At least a part of the blocks is selected as a predetermined bonding portion, and each of the blocks in the predetermined bonding portion is transferred to a carrying substrate in sequence, so that the electronic devices in the predetermined bonding portion arc bonded to the carrying substrate. The sub-substrates of the blocks are removed.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: January 8, 2019
    Assignee: Genesis Photonics Inc.
    Inventors: Shao-Ying Ting, Yan-Ting Lan, Jing-En Huang, Yi-Ru Huang
  • Patent number: 10170326
    Abstract: A wafer element fabrication method is provided. The wafer element fabrication method includes forming a device element on a substrate such that the device element includes an upper surface and a sidewall extending from the upper surface to the substrate. The wafer element fabrication method further includes forming an adjusted print resolution assist feature (APRAF) on the substrate such that the APRAF is smaller than the device element in at least one dimension. In addition, the wafer element fabrication method includes depositing surrounding material, which is different from materials of the APRAF, to surround the APRAF and to lie on the upper surface in abutment with the sidewall of the device element.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yann A. Mignot, Muthumanickam Sankarapandian
  • Patent number: 10165686
    Abstract: An electrical component having a first package part of a first plastic compound. The first package part has a first trench-shaped formation. A first semiconductor body with an integrated circuit is disposed in the first trench-shaped formation. At least two traces, which run on an outer side of the first package part, are provided on a surface of the first trench-shaped formation, wherein the at least two traces are connected to the integrated circuit. The first trench-shaped formation is filled at least partially with a filling material of a second plastic compound to cover the first semiconductor body.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: December 25, 2018
    Assignee: TDK-Micronas GmbH
    Inventors: Joerg Franke, Klaus Heberle, Oliver Breitwieser, Timo Kaufmann
  • Patent number: 10163709
    Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor device and a second semiconductor device are formed within a semiconductor wafer and a scribe region between the first semiconductor device and the second semiconductor device is patterned. A singulation process is then utilized within the scribe region to singulate the first semiconductor device from the second semiconductor device. The first semiconductor device and the second semiconductor device are then bonded to a second semiconductor substrate and thinned in order to remove extension regions from the first semiconductor device and the second semiconductor device.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hung-Pin Chang, Yi-Hsiu Chen, Ku-Feng Yang, Wen-Chih Chiou
  • Patent number: 10134599
    Abstract: A method of metal-assisted chemical etching comprises forming an array of discrete metal features on a surface of a semiconductor structure, where each discrete metal feature comprises a porous metal body with a plurality of pores extending therethrough and terminating at the surface of the semiconductor structure. The semiconductor structure is exposed to an etchant, and the discrete metal features sink into the semiconductor structure as metal-covered surface regions are etched. Simultaneously, uncovered surface regions are extruded through the pores to form anchoring structures for the discrete metal features. The anchoring structures inhibit detouring or delamination of the discrete metal features during etching. During continued exposure to the etchant, the anchoring structures are gradually removed, leaving an array of holes in the semiconductor structure.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: November 20, 2018
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Xiuling Li, Jeong Dong Kim, Munho Kim, Lingyu Kong
  • Patent number: 10115578
    Abstract: A method of processing a wafer having on a face side thereof a device area with a plurality of devices formed therein and an outer circumferential excess area surrounding the device area includes a grinding step for grinding a reverse side of the wafer corresponding to the device area with a grinding wheel that is smaller in diameter than the wafer, thereby forming a first portion corresponding to the device area and an annular second portion surrounding the first portion, the annular second portion being thicker and more protrusive toward a reverse side thereof than the first portion. In the grinding step, the grinding wheel and the wafer are moved relatively to each other so that the angle formed between the reverse side of the first portion and an inner side surface of the annular second portion is larger than 45° and smaller than 75°.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: October 30, 2018
    Assignee: Disco Corporation
    Inventors: Ryosuke Nishihara, Jun Koide, Kohei Tsujimoto, Minoru Matsuzawa
  • Patent number: 10090296
    Abstract: A semiconductor device includes a wiring layer that includes at least one low-dielectric rate interlayer insulating film layer; a guard ring that is formed by placing in series a wire and a via so as to be in contact with a through electrode, in a portion in which the through electrode passing through the wiring layer is formed; and the through electrode that is formed by being buried inside the guard ring.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: October 2, 2018
    Assignee: Sony Corporation
    Inventor: Takushi Shigetoshi
  • Patent number: 10068764
    Abstract: Embodiments of the invention provide methods for selective film deposition using a surface pretreatment. According to one embodiment, the method includes providing a substrate containing a dielectric layer and a metal layer, exposing the substrate to a reactant gas containing a molecule that forms self-assembled monolayers (SAMs) on the substrate, and thereafter, selectively depositing a metal oxide film on a surface of the dielectric layer relative to a surface of the metal layer by exposing the substrate to a deposition gas.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: September 4, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Kandabara N. Tapily, Gerrit J. Leusink, Cory Wajda, Hoyoung Kang
  • Patent number: 10056510
    Abstract: A photovoltaic device includes a substrate having a plurality of hole shapes formed therein. The plurality of hole shapes each have a hole opening extending from a first surface and narrowing with depth into the substrate. The plurality of hole shapes form a hole pattern on the first surface, and the hole pattern includes flat areas separating the hole shapes on the first surface. A photovoltaic device stack is formed on the first surface and extends into the hole shapes. Methods are also provided.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: August 21, 2018
    Assignee: International Business Machines Corporation
    Inventors: Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana
  • Patent number: 10050006
    Abstract: A method for forming a chip package is provided. The method includes providing a first substrate and a second substrate. The first substrate is attached onto the second substrate by an adhesive layer. A first opening is formed to penetrate the first substrate and the adhesive layer and separate the first substrate and the adhesive layer into portions. A chip package formed by the method is also provided.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: August 14, 2018
    Assignee: XINTEC INC.
    Inventors: Chia-Lun Shen, Yi-Ming Chang, Tsang-Yu Liu, Yen-Shih Ho
  • Patent number: 10037945
    Abstract: A package structure is disclosed. The package structure includes at least a lead, for delivering at least a signal; at least a routing layer, connected to the at least a lead, where at least a first hole is formed through the at least a routing layer; a die, disposed on the at least a routing layer, where at least a second hole is formed through the die, and the die generates or receives the at least a signal; and a molding cap, for covering the at least a routing layer and the die; where the at least a signal is delivered through the at least a first hole and the at least a second hole.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: July 31, 2018
    Assignee: WIN Semiconductors Corp.
    Inventors: Chih-Wen Huang, Jui-Chieh Chiu, Fan-Hsiu Huang
  • Patent number: 10002900
    Abstract: A method is provided for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer. The method includes selecting a periodicity for the second wafer to be manufactured that matches the periodicity of the first wafer. The method further includes manufacturing the second wafer in accordance with the selected periodicity. The method also includes placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer. The method additionally includes stacking the first wafer onto the second wafer, using a copper-to-copper bonding process to bond the first wafer to the second wafer.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: June 19, 2018
    Assignee: International Business Machines Corporation
    Inventors: Arvind Kumar, Mark Lamorey
  • Patent number: 9997582
    Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a substrate, a scan line disposed over the substrate and configured to transmit a scan signal, a data line crossing the scan line and configured to transmit a data voltage and a driving voltage line crossing the scan line and configured to transmit a driving voltage. The OLED display also includes a switching transistor connected to the scan line and the data line, a driving transistor connected to the switching transistor and including a driving gate electrode, a driving source electrode, and a driving drain electrode and an OLED electrically connected to the driving transistor. The driving source electrode at least partially overlaps the driving voltage line in the depth dimension of the OLED display so as to form an assistance capacitor.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: June 12, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dong Sun Lee, Seon I Jeong
  • Patent number: 9997363
    Abstract: A method for producing a semiconductor piece includes forming a first groove portion of a front-surface-side groove by anisotropic dry etching from a front surface of a substrate, forming a second groove portion of the front-surface-side groove, the second groove portion being located below and in communication with the first groove portion and having a width wider than a width of the first groove portion, and thinning the substrate from a back surface of the substrate up to the second groove portion. The second groove portion is formed by changing an etching condition of the anisotropic dry etching during the formation of the front-surface-side groove so that the width of the second groove portion is wider than the width of the first groove portion.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: June 12, 2018
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Kenichi Ono, Hideyuki Ikoma, Shogo Komagata, Michiaki Murata, Tsutomu Otsuka
  • Patent number: 9941175
    Abstract: A method for forming fins on a semiconductor device includes etching trenches into a monocrystalline substrate to form first fins and forming a first dielectric layer at bottoms of the trenches. Second fins of a material having a different composition than the substrate are grown on sidewalls of the trenches. A second dielectric layer is formed over the second fins. The first fins are removed by etching. The second fins are processed to form fin field effect transistor devices.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: April 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Huiming Bu, Shogo Mochizuki, Tenko Yamashita
  • Patent number: 9935042
    Abstract: A semiconductor package includes a chip, a layer which is thermally coupled to the chip and which is formed from a material having a triggering temperature of greater than or equal to 200° C., starting from which an exothermic reaction takes place, and encapsulating material which at least partly covers the chip and the layer. The layer is configured in such a way and is arranged relative to the chip in such a way that, in the case of a triggered exothermic reaction of the material of the layer, at least one component of the chip is damaged on account of the temperature increase caused by the exothermic reaction.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: April 3, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Spoettl, Frank Pueschner, Guenther Ruhl, Peter Stampka
  • Patent number: 9935022
    Abstract: Systems and methods of characterizing wafer shape using coherent gradient sensing (CGS) interferometry are disclosed. The method includes measuring at least 3×106 data points on a wafer surface using a CGS system to obtain a topography map of the wafer surface. The data are collected on a wafer for pre-processing and post-processing of the wafer, and the difference calculated to obtain a measurement of the effect of the process on wafer surface shape. The process steps for processing the same wafer or subsequent wafers are controlled based on measured process-induced change in the wafer surface shape in order to improve the quality of the wafer processing.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: April 3, 2018
    Assignee: Ultratech, Inc.
    Inventor: David M. Owen
  • Patent number: 9913374
    Abstract: Printed electronic device comprising a substrate onto at least one surface of which has been applied a layer of an electrically conductive ink comprising functionalized graphene sheets and at least one binder. A method of preparing printed electronic devices is further disclosed.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: March 6, 2018
    Assignees: THE TRUSTEES OF PRINCETON UNIVERSITY, VORBECK MATERIALS CORPORATION
    Inventors: John M. Crain, John S. Lettow, Ilhan A. Aksay, Sibel Korkut, Katherine S. Chiang, Chuan-Hua Chen, Robert K. Prud'Homme
  • Patent number: 9910201
    Abstract: A manufacturing method of a mother substrate assembly includes forming a metal layer on substantially an entire surface of a transparent substrate including a cell area including a non-display area and a display area, an align key area, and a substrate area surrounding the cell area and the align key area, etching the metal layer to form an align key in the align key area, etching the metal layer to form a reflection part in the non-display area, and etching the metal layer in the display area to form a metal nanowire in the display area.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: March 6, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung-Won Park, Taewoo Kim, Moongyu Lee, Minhyuck Kang
  • Patent number: 9899309
    Abstract: A semiconductor substrate is provided, including a substrate body having a lateral surface, and a protruding structure extending outward from the lateral surface. The semiconductor substrate distributes stresses generated during a manufacturing process through the protruding structure, and is thus prevented from delamination or being cracked. An electronic package having the semiconductor substrate is also provided.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: February 20, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shih-Ching Chen, Shih-Liang Peng, Chieh-Lung Lai, Jia-Wei Pan, Chang-Lun Lu
  • Patent number: 9887280
    Abstract: A superjunction semiconductor device includes a first semiconductor layer doped with a first conductivity type; an active region formed on the first semiconductor layer, the active region including a drift layer; and a termination region disposed to surround the active region, the termination region including a lower edge region disposed on a side surface of the drift layer and an upper edge region disposed on the lower edge region, wherein the upper edge region includes a lower charge balance region disposed on the lower edge region, the lower charge balance region having a second conductivity type different from the first conductivity type, and an upper charge balance region disposed on the lower charge balance region, the upper charge balance region having the first conductivity type.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: February 6, 2018
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Kwang-won Lee, Hye-min Kang, Jae-gil Lee
  • Patent number: 9881801
    Abstract: A polishing liquid includes abrasive grains, an additive and water, wherein the abrasive grains include a tetravalent metal element hydroxide, and produce a liquid phase with a nonvolatile content of 500 ppm or greater when an aqueous dispersion with a content of the abrasive grains adjusted to 1.0 mass % has been centrifuged for 50 minutes at a centrifugal acceleration of 1.59×105 G.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: January 30, 2018
    Assignee: HITACHI CHEMICAL COMPANY, LTD.
    Inventor: Tomohiro Iwano
  • Patent number: 9842763
    Abstract: A method for manufacturing a bonded wafer using a base wafer which is an epitaxial wafer produced by a method including at least one of: (1) setting a chamfer width of a wafer for epitaxial growth to be 0.20 mm or less on an epitaxial growth side; (2) preparing a wafer for epitaxial growth having a rise shape on an epitaxial growth side periphery, thereby adjusting the wafer to have an amount of sag within a range of ?30 nm/mm2 to +10 nm/mm2 on a bonding surface side periphery; and (3) adjusting epitaxial growth conditions so a change in amount of sag before and after growth becomes a positive value, thereby adjusting the wafer to have sag within a range of ?30 nm/mm2 to +10 nm/mm2. The method can manufacture a bonded wafer with a small terrace width even when an epitaxial wafer is used as the base wafer.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: December 12, 2017
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Toru Ishizuka, Yuta Tamba, Eiichi Yamazaki
  • Patent number: 9824937
    Abstract: A method for semiconductor processing includes forming a first dielectric layer comprising an N-type dopant over a first plurality of fins extending above a first region of a substrate, forming a second dielectric layer comprising a P-type dopant over the first plurality of fins and a second plurality of fins extending above a second region of the substrate, the second dielectric layer overlying the first dielectric layer, and forming an isolation layer between adjacent ones of the first plurality of fins, and between adjacent ones of the second plurality of fins. The method further includes performing an implantation process using a first dopant, the implantation process changing an etching rate of the isolation layer, and recessing the isolation layer, the first dielectric layer, and the second dielectric layer, where after the recessing, the first and the second plurality of fins extend above an upper surface of the isolation layer.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: November 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsan-Chun Wang, Liang-Yin Chen
  • Patent number: 9823315
    Abstract: In a magnetic sensor, a pinned layer covers a wiring layer on a side opposite to a substrate with respect to the wiring layer and includes a bent portion having a bent shape in cross section. Free layers are arranged on a side opposite to the substrate with respect to the pinned layer. The size of the free layers in a planar direction is set to a size smaller than the size of the pinned layer in the planar direction. A magnetic field leaking from the pinned layer may form a closed loop adjacent to the substrate, that is, on a side opposite to the free layers with respect to the substrate. Therefore, influence of the magnetic field leaking from the pinned layer on the free layers can be restricted.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: November 21, 2017
    Assignee: DENSO CORPORATION
    Inventors: Toshifumi Yano, Takamoto Furuichi
  • Patent number: 9799570
    Abstract: Semiconductor devices are fabricated with vertical field effect transistor (FET) devices having uniform structural profiles. Semiconductor fabrication methods for vertical FET devices implement a process flow to fabricate dummy fins within isolation regions to enable the formation of vertical FET devices with uniform structural profiles within device regions. Sacrificial semiconductor fins are formed in the isolation regions concurrently with semiconductor fins in the device regions, to minimize/eliminate micro-loading effects from an etch process used for fin patterning and, thereby, form uniform profile semiconductor fins. The sacrificial semiconductor fins within the isolation regions also serve to minimize/eliminate non-uniform topography and micro-loading effects when planarizing and recessing conductive gate layers and, thereby. form conductive gate structures for vertical FET devices with uniform gate lengths in the device regions.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: October 24, 2017
    Assignee: International Business Machines Corporation
    Inventor: Kangguo Cheng
  • Patent number: 9755078
    Abstract: A semiconductor structure includes a first fin structure having a first strain located on a surface of a first insulator layer portion. The first fin structure includes a first doped silicon germanium alloy fin portion having a first germanium content and a silicon germanium alloy fin portion having a third germanium content. A second fin structure having a second strain is located on a surface of a second insulator layer portion. The second fin structure includes a second doped silicon germanium alloy fin portion having a second germanium content and a silicon germanium alloy fin portion having the third germanium content, wherein the first germanium content differs from the second germanium content and the third germanium content is greater than the first and second germanium contents, and wherein the first strain differs from the second strain.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: September 5, 2017
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Pranita Kerber, Christine Q. Ouyang, Alexander Reznicek
  • Patent number: 9748450
    Abstract: A method of producing an optoelectronic component includes providing an optoelectronic semiconductor chip having a mask layer arranged on an upper side of the optoelectronic semiconductor chip; providing a carrier having walls arranged on a surface of the carrier, the walls laterally limiting a receiving region; arranging an optoelectronic semiconductor chip in the receiving region, wherein a bottom side of the optoelectronic semiconductor chip faces the surface of the carrier; filling a region of the receiving region surrounding the optoelectronic semiconductor chip with an optically reflective material up to a height that lies between the upper side of the optoelectronic semiconductor chip and an upper side of the mask layer; removing the mask layer to create a free space in the optically reflective material; and introducing a wavelength-converting material into the free space.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: August 29, 2017
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Martin Brandl, Markus Burger
  • Patent number: 9701902
    Abstract: An etching method according to an embodiment includes forming a catalyst layer made of a noble metal on a structure made of a semiconductor, and dipping the structure in an etching solution containing hydrofluoric acid, an oxidizer, and an organic additive to remove a portion of the structure that is in contact with the catalyst layer.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: July 11, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yusaku Asano
  • Patent number: 9653268
    Abstract: A method of manufacturing a vitreous silica crucible includes an inspection method comprising: a measurement step of measuring an infrared absorption spectrum or a Raman shift of a measurement point on an inner surface of the vitreous silica crucible; a determining step of predicting whether a surface defect region is generated or not in the measurement point based on an obtained spectrum to determine a quality of the vitreous silica crucible.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: May 16, 2017
    Assignee: SUMCO CORPORATION
    Inventors: Toshiaki Sudo, Tadahiro Sato, Ken Kitahara, Masami Ohara
  • Patent number: 9627581
    Abstract: A nitride semiconductor structure includes a nitride semiconductor layer having a principal plane and including a nitride semiconductor. The normal to the principal plane of the nitride semiconductor layer is inclined at 5 degrees or more and 17 degrees or less with respect to the [11-22] axis of the nitride semiconductor constituting the nitride semiconductor layer in the direction of the +c-axis of the nitride semiconductor. The nitride semiconductor structure may further include a substrate having a principal plane which supports the nitride semiconductor layer on the principal plane. The substrate may include any one selected from the group consisting of a nitride semiconductor, sapphire, and Si.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: April 18, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Songbaek Choe
  • Patent number: 9613888
    Abstract: A semiconductor device in the preferred embodiment includes: a lead frame comprising a die pad and an electrode terminal; and at least one semiconductor chip bonded to a surface of the die pad, wherein the lead frame excluding a bottom surface thereof and the semiconductor chip are sealed by a sealing resin, and an unevenness is introduced on a bonding interface between the surface of the die pad and the semiconductor chip.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: April 4, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Rei Yoneyama, Hiroyuki Okabe, Nobuya Nishida, Taichi Obara
  • Patent number: 9595440
    Abstract: A method of semiconductor device fabrication including placing a substrate having a first and second features disposed thereon in a vaporizing spray deposition system. An atomizing spray head of the vaporizing spray deposition system is used to deposit a conformal polymer layer on the first and second features. The first feature having the layer of the polymer disposed thereon and having a first width. A spray trim process is performed on the first and second features having the polymer layer disposed thereon using the atomizing spray head.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: March 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yu Chang, Kuei-Liang Lu, Ming-Feng Shieh
  • Patent number: 9583673
    Abstract: A semiconductor light emitting device including: a substrate made of GaAs; and a semiconductor layer formed on the substrate, in which part of the substrate on a side opposite to the semiconductor layer is removed by etching so that the semiconductor light emitting device has a thickness of not more than 60 ?m.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: February 28, 2017
    Assignee: ROHM CO., LTD.
    Inventors: Tadahiro Hosomi, Kentaro Mineshita
  • Patent number: 9576796
    Abstract: A method of manufacturing a semiconductor device may include: forming an opening in an insulating layer to expose a portion of a major surface of a substrate, the substrate comprising a first semiconductor material; forming a protrusion in the opening using a first epitaxial growth process, the protrusion comprising a first portion disposed in the opening and a second portion extending out of the opening, the protrusion comprising a second semiconductor material different from the first semiconductor material; and forming the second semiconductor material on sidewalls of the second portion of the protrusion using a second epitaxial growth process different from the first epitaxial growth process.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Martin Christopher Holland, Georgios Vellianitis
  • Patent number: 9570412
    Abstract: A semiconductor device includes a first metal wiring formed on a semiconductor substrate, a first organic insulating film formed on the first metal wiring, and a second metal wiring formed to cover the first organic insulating film and having a via connected to the first metal wiring. The semiconductor device further includes a second organic insulating film formed on the first organic insulating film and having an opening to expose the second metal wiring, a bump formed on an exposed portion of the second metal wiring in the opening, and a tunnel portion formed in contact with the second metal wiring or the first organic insulating film. The tunnel portion overlaps with the second metal wiring in planar view.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: February 14, 2017
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Yoshimasa Yoshioka