In Compound Semiconductor Material (e.g., Gaas) Patents (Class 257/631)
  • Patent number: 9882100
    Abstract: A light-emitting device includes: a photoluminescent layer that emits light; and a light-transmissive layer on which the emitted light is to be incident. At least one of the photoluminescent layer and the light-transmissive layer defines a surface structure. The surface structure has projections and/or recesses to limit a directional angle of the emitted light. The photoluminescent layer and the light-transmissive layer are curved.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: January 30, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Akira Hashiya, Taku Hirasawa, Yasuhisa Inada
  • Patent number: 9444126
    Abstract: A high-frequency signal line includes a base layer including first and second principal surfaces, a signal line provided on the first principal surface, a ground conductor provided on the first principal surface along the signal line, and a plurality of high-permittivity portions arranged along the signal line and in contact with a portion of both the signal line and the ground conductor, each of the high-permittivity portions having a higher specific permittivity than the base layer.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: September 13, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Noboru Kato, Satoshi Ishino, Jun Sasaki
  • Patent number: 9082742
    Abstract: A semiconductor device includes: a substrate comprised by gallium arsenide; an active layer provided on the substrate; a first nickel-plated layer provided on a lower face of the substrate facing the active layer; a copper-plated layer provided on a lower face of the first nickel-plated layer; and a second nickel-plated layer provided on a lower face of the copper-plated layer.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: July 14, 2015
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Hiroshi Kawakubo
  • Publication number: 20150108617
    Abstract: A method for chemically passivating a surface of a product made of a III-V semiconductor material in which a) a P(N) polymer film is formed by deposition in a solvent comprising liquid ammonia. The film is formed by deposition, without electrochemical assistance, in the solvent, in the presence of an oxidizing chemical additive comprising phosphorous and generating electrical charge carriers in said surface.
    Type: Application
    Filed: June 12, 2012
    Publication date: April 23, 2015
    Applicants: Centre National de la Recherche Scientifique-CNRS, Universite de Versailles Saint-Quentin-En-Yvelines, Ecole Polytechnique
    Inventors: Francoise Hervagault, Elaine Le Floch, Clemence Le Floch, Paul Le Floch
  • Patent number: 8753961
    Abstract: A method of nucleating and growing oxygen precipitates during a pad oxidation process. The nucleating is performed during in the oxidation furnace prior to the pad oxide growth. At least a portion of the growth of the oxygen precipitates occurs during the pad oxide growth. The oxygen precipitates are of sufficient concentration and size in lightly doped p-type wafers for effective gettering of heavy metals is deep submicron transistor, integrated circuit manufacturing flows.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: June 17, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Bradley David Sucher
  • Publication number: 20140008771
    Abstract: The present invention is to provide a method for forming a compound epitaxial layer by chemical bonding, which comprises the steps of forming a contact layer on a substrate; chemically reacting atoms on a surface of the contact layer with non-metal atoms, such that the non-metal atoms form non-metal ions for chemically bonding to the atoms on the surface of the contact layer; exciting the non-metal ions by energy excitation, such that unpaired electrons of the non-metal ions not yet bound to the atoms on the surface of the contact layer become dangling bonds; and conducting chemical vapor deposition by introducing an organic metal compound and a reactant gas, wherein metal ions of the organic metal compound are bound to the dangling bonds by electric dipole attraction, and anions of the reactant gas are bound to the metal ions by ionic bonding, such that the compound epitaxial layer is formed.
    Type: Application
    Filed: July 5, 2012
    Publication date: January 9, 2014
    Applicant: Huey-Jean LIN
    Inventor: Kuo-Wei SHYU
  • Publication number: 20130168702
    Abstract: A method is provided for preparing a surface of a GaAs substrate (001) such that it can receive a ferromagnetic semiconductor deposited by epitaxy, as well as a substrate thus prepared, method for manufacturing one such semiconductor deposited on the substrate, the resulting semiconductor, and uses thereof. The preparation method renders the surface capable of receiving an epitaxially deposited ferromagnetic semiconductor which may include semiconductors from groups III-V, IV and II-VI of the periodic table, with the exception of GaAs, and which also includes at least one magnetic element of manganese, iron, cobalt, nickel and chromium. The method includes vacuum deoxidation of the surface under a reduced germanium-based flux such that, following desorption of the arsenic and gallium oxide from the said surface, the latter has a single-domain 2×1 reconstruction and is sufficiently planar and arsenic-depleted to prevent any diffusion of arsenic from the substrate to the subsequently deposited semiconductor.
    Type: Application
    Filed: July 15, 2011
    Publication date: July 4, 2013
    Inventors: André Barski, Matthieu Jamet
  • Publication number: 20130168834
    Abstract: The present disclosure reduces and, in some instances, eliminates the density of interface states in III-V compound semiconductor materials by providing a thin crystalline interlayer onto an upper surface of a single crystal III-V compound semiconductor material layer to protect the crystallinity of the single crystal III-V compound semiconductor material layer's surface atoms prior to further processing of the structure.
    Type: Application
    Filed: February 25, 2013
    Publication date: July 4, 2013
    Applicant: International Business Machines Corporation
    Inventor: International Business Machines Corporation
  • Patent number: 8415772
    Abstract: A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 ? to 400 ? on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: April 9, 2013
    Assignee: International Business Machines Corporation
    Inventors: Joel P. de Souza, Keith E. Fogel, Edward W. Kiewra, Steven J. Koester, Christopher C. Parks, Devendra K. Sadana, Shahab Siddiqui
  • Patent number: 8217407
    Abstract: A method of manufacturing a light emitting device, including the steps of: (A) sequentially forming a first compound semiconductor layer of a first conduction type, an active layer, and a second compound semiconductor layer of a second conduction type different from said first conduction type, over a substrate; and (B) exposing a part of said first compound semiconductor layer, forming a first electrode over said exposed part of said first compound semiconductor layer and forming a second electrode over said second compound semiconductor layer, wherein said method further includes, subsequent to said step (B), the step of: (C) covering at least said exposed part of said first compound semiconductor layer, an exposed part of said active layer, an exposed part of said second compound semiconductor layer, and a part of said second electrode with an SOG layer.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: July 10, 2012
    Assignee: Sony Corporation
    Inventors: Yoshiaki Watanabe, Tomonori Hino, Nobukata Okano, Hisayoshi Kuramochi, Yuichiro Kikuchi, Tatsuo Ohashi
  • Patent number: 8178951
    Abstract: There is provided a compound semiconductor substrate prepared by forming a point defect in an inside structure thereof by implanting an electrically-neutral impurity with energy of 0.1 to 10 MeV on a surface of the substrate. When the compound semiconductor is undoped, electrical resistance increases to increase insulating properties, and when the compound semiconductor is doped with an n-type dopant, the impurity is implanted and charge concentration of the substrate increases to increase conductive properties. In accordance with the present invention, the various electrical properties needed for the compound semiconductor can be effectively controlled by increasing the insulating properties of the undoped compound semiconductor or by increasing the charge concentration of the n-type compound semiconductor, and the application range to various devices can be expanded.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: May 15, 2012
    Assignee: Samsung Corning Precision Materials Co., Ltd.
    Inventors: Young Zo Yoo, Hyun Min Shin, Jun Sung Choi
  • Patent number: 8148802
    Abstract: The present invention provides methods of protecting a surface of an aluminum nitride substrate. The substrate with the protected surface can be stored for a period of time and easily activated to be in a condition ready for thin film growth or other processing. In certain embodiments, the method of protecting the substrate surface comprises forming a passivating layer on at least a portion of the substrate surface by performing a wet etch, which can comprise the use of one or more organic compounds and one or more acids. The invention also provides aluminum nitride substrates having passivated surfaces.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: April 3, 2012
    Assignee: North Carolina State University
    Inventors: Ramon R. Collazo, Zlatko Sitar, Rafael Dalmau
  • Patent number: 8143686
    Abstract: In one aspect, the present invention provides a method of processing a substrate, e.g., a semiconductor substrate, by irradiating a surface of the substrate (or at least a portion of the surface) with a first set of polarized short laser pulses while exposing the surface to a fluid to generate a plurality of structures on the surface, e.g., within a top layer of the surface. Subsequently, the structured surface can be irradiated with another set of polarized short laser pulses having a different polarization than that of the initial set while exposing the structured surface to a fluid, e.g., the same fluid initially utilized to form the structured surface or a different fluid. In many embodiments, the second set of polarized laser pulses cause the surface structures formed by the first set to break up into smaller-sized structures, e.g., nano-sized features such as nano-sized rods.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: March 27, 2012
    Assignee: President and Fellows of Harvard College
    Inventors: Eric Mazur, Mengyan Shen
  • Patent number: 8143147
    Abstract: A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided, including systems and methods for forming binary compound epitaxial thin films. Methods and systems of embodiments of the invention may be used to form direct bandgap semiconducting binary compound epitaxial thin films, such as, for example, GaN, InN and AlN, and the mixed alloys of these compounds, e.g., (In, Ga)N, (Al, Ga)N, (In, Ga, Al)N. Methods and apparatuses include a multistage deposition process and system which enables rapid repetition of sub-monolayer deposition of thin films.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: March 27, 2012
    Assignee: Intermolecular, Inc.
    Inventors: Philip A. Kraus, Sandeep Nijhawan, Thai Cheng Chua
  • Patent number: 8129260
    Abstract: A semiconductor substrate includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is formed of II-VI-group semiconductor material, III-V-group semiconductor material, or II-VI-group semiconductor material and III-V-group semiconductor material. At least one amorphous region and at least one crystalloid region are formed in the first semiconductor layer. The second semiconductor layer is formed on the first semiconductor layer and is crystal-grown from the at least one crystalloid region. A method of manufacturing a semiconductor substrate includes preparing a growth substrate; crystal-growing the first semiconductor layer on the growth substrate; forming the at least one amorphous region and the at least one crystalloid region in the first semiconductor layer; and forming a second semiconductor layer on the first semiconductor layer using the at least one amorphous region as a mask and the at least one crystalloid region as a seed.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: March 6, 2012
    Assignee: Samsung LED Co., Ltd.
    Inventors: Ho-sun Paek, Youn-joon Sung, Kyoung-ho Ha, Joong-kon Son, Sung-nam Lee
  • Patent number: 8022412
    Abstract: An epitaxial structure having a low defect density includes: a base layer; a first epitaxial layer having a plurality of concentrated defect groups, and an epitaxial surface that has a plurality of first recesses corresponding in position to the concentrated defect groups, the sizes of the first recesses being close to each other; and a plurality of defect-termination blocks respectively and filling the first recesses and having polished surfaces. The defect-termination blocks are made of a material which is different in removal rate from that of the first epitaxial layer.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: September 20, 2011
    Assignee: National Chung-Hsien University
    Inventors: Dong-Sing Wuu, Ray-Hua Horng, Shih-Ting Chen, Tshung-Han Tsai, Hsueh-Wei Wu
  • Patent number: 7919815
    Abstract: Wafer suitable for semiconductor deposition application can be fabricated to have low bow, warp, total thickness variation, taper, and total indicated reading properties. The wafers can be fabricated by cutting a boule to produce rough-cut wafers, lapping the rough-cut wafers, etching the lapped wafers to remove a defect, deformation zone and relieve residual stress, and chemically mechanically polishing the etched wafers to desired finish properties. Etching can be performed by immersion in a heated etching solution comprising sulfuric acid or a mixture of sulfuric and phosphoric acids. A low pH slurry utilized in chemical mechanical polishing of the spinel wafer can comprise ?-Al2O3 and an organic phosphate.
    Type: Grant
    Filed: March 1, 2006
    Date of Patent: April 5, 2011
    Assignee: Saint-Gobain Ceramics & Plastics, Inc.
    Inventors: Brahmanandam Tanikella, Elizabeth Thomas, Frank L. Csillag, Palaniappan Chinnakaruppan, Jadwiga Jaroniec, Eric Virey, Robert A. Rizzuto
  • Patent number: 7858418
    Abstract: Herein disclosed a method of manufacturing a light emitting device, including the steps of: (A) sequentially forming a first compound semiconductor layer of a first conduction type, an active layer, and a second compound semiconductor layer of a second conduction type different from said first conduction type, over a substrate; and (B) exposing a part of said first compound semiconductor layer, forming a first electrode over said exposed part of said first compound semiconductor layer and forming a second electrode over said second compound semiconductor layer, wherein said method further includes, subsequent to said step (B), the step of: (C) covering at least said exposed part of said first compound semiconductor layer, an exposed part of said active layer, an exposed part of said second compound semiconductor layer, and a part of said second electrode with an SOG layer.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: December 28, 2010
    Assignee: Sony Corporation
    Inventors: Yoshiaki Watanabe, Tomonori Hino, Nobukata Okano, Hisayoshi Kuramochi, Yuichiro Kikuchi, Tatsuo Ohashi
  • Publication number: 20100200963
    Abstract: The present invention relates to a process for preparing a functionalized Si/Ge-surface, wherein an unfunctionalised Si/Ge-surface is contacted in the presence of ultraviolet radiation with a C2-C50 alkene and/or a C2-C50 alkyne, and/or alkyne being optionally substituted and/or being optionally interrupted by one or more heteroatoms. The present invention further relates to articles or substrates comprising the functionalized Si/Ge-surface and the use of the functionalised Si/Ge-surface to prevent or to reduce adsorption of a biomolecule to an article or a substrate.
    Type: Application
    Filed: July 31, 2008
    Publication date: August 12, 2010
    Inventors: Catharina Gerarda Petronella Henrica Schroën, Michel Rosso, Johannes Teunis Zuilhof
  • Publication number: 20100032684
    Abstract: A method for fabricating substantially relaxed SiGe alloy layers with a reduced planar defect density is disclosed The method of the present invention includes forming a strained Ge-containing layer on a surface of a Si-containing substrate; implanting ions at or below the Ge-containing layer/Si-containing substrate interface and heating to form a substantially relaxed SiGe alloy layer that has a reduced planar defect density. A substantially relaxed SiGe-on-insulator substrate material having a SiGe layer with a reduced planar defect density as well as heterostructures containing the same are also provided.
    Type: Application
    Filed: August 11, 2009
    Publication date: February 11, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Huajie Chen, Keith E. Fogel, Devendra K. Sadana, Ghavam G. Shahidi
  • Publication number: 20100032812
    Abstract: A method is provided for controlling the average stress and the strain gradient in structural silicon germanium layers as used in micromachined devices. The method comprises depositing a single silicon germanium layer on a substrate and annealing a predetermined part of the deposited silicon germanium layer. The process parameters of the depositing and/or annealing steps are selected such that a predetermined average stress and a predetermined strain gradient are obtained in the predetermined part of the silicon germanium layer. Preferably a plasma assisted deposition technique is used for depositing the silicon germanium layer, and a pulsed excimer laser is used for local annealing, with a limited thermal penetration depth. Structural silicon germanium layers for surface micromachined structures can be formed at temperatures substantially below 400° C., which offers the possibility of post-processing micromachined structures on top of a substrate comprising electronic circuitry such as CMOS circuitry.
    Type: Application
    Filed: December 21, 2006
    Publication date: February 11, 2010
    Applicants: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC), AMERICAN UNIVERSITY CAIRO
    Inventors: Sherif Sedky, Ann Witvrouw
  • Patent number: 7619301
    Abstract: A GaAs semiconductor substrate includes a surface layer. When an atomic ratio is to be calculated using a 3d electron spectrum of Ga atoms and As atoms measured at the condition of 10° for the photoelectron take-off angle ? by X-ray photoelectron spectroscopy, the structural atomic ratio of all Ga atoms to all As atoms (Ga)/(As) at the surface layer is at least 0.5 and not more than 0.9, the ratio of As atoms bound with O atoms to all Ga atoms and all As atoms (As—O)/{(Ga)+(As)} at the surface layer is at least 0.15 and not more than 0.35, and the ratio of Ga atoms bound with O atoms to all Ga atoms and all As atoms (Ga—O)/{(Ga)+(As)} at the surface layer is at least 0.15 and not more than 0.35. Accordingly, there is provided a GaAs semiconductor substrate having a surface cleaned to an extent allowing removal of impurities and oxides at the surface by at least thermal cleaning of the substrate.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: November 17, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takayuki Nishiura, Yoshio Mezaki, Yusuke Horie, Yasuaki Higuchi
  • Patent number: 7592629
    Abstract: A gallium nitride thin film on sapphire substrate having reduced bending deformation and a method for manufacturing the same. An etching trench structure is formed on a sapphire substrate by primary nitradation and HCl treatment and a gallium nitride film is grown thereon by secondary nitradation. The gallium nitride thin film on sapphire substrate comprises an etching trench structure formed on a sapphire substrate, wherein a function graph of a curvature radius Y according to a thickness X of a gallium nitride film satisfies Equation 1 below, and corresponds to or is located above a function graph drawn when Y0 is 6.23±1.15, A is 70.04 ±1.92, and T is 1.59±0.12: Y=Y0+A·e?(X?1)/T,??[Equation 1] where Y is the curvature radius m, X is the thickness of the gallium nitride film, and Y0, A, and T are positive numbers.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: September 22, 2009
    Assignee: Samsung Corning Co., Ltd.
    Inventors: Chang Ho Lee, Sun Hwan Kong
  • Patent number: 7550782
    Abstract: In a semiconductor device in which a group III nitride compound semiconductor layer is formed without a low temperature grown buffer layer provided on an undercoat layer formed by a metal nitride layer, the metal nitride layer is formed of reddish brown titanium nitride. The reddish brown titanium nitride can be obtained by causing nitrogen to be rich in the titanium nitride.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: June 23, 2009
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masanori Murakami, Teppei Watanabe, Susumu Tsukimoto, Kazuhiro Ito, Jun Ito, Miki Moriyama, Naoki Shibata
  • Patent number: 7518151
    Abstract: The present invention relates to a gallium nitride/sapphire thin film, wherein a curvature radius thereof is positioned on the right side of a curve plotted from the following functional formula (I): Y=Y0+A·e?(x1?1)/T1+B·(1?e?x2/T2)??(I) wherein Y is the curvature radius (m) of a gallium nitride/sapphire thin film, x1 is the thickness (?m) of a gallium nitride layer, x2 is the thickness (mm) of a sapphire substrate, Y0 is ?107±2.5, A is 24.13±0.50, B is 141±4.5, T1 is 0.56±0.04, and T2 is 0.265±0.5.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: April 14, 2009
    Assignee: Samsung Corning Co., Ltd.
    Inventors: Chang Ho Lee, Hae Yong Lee, Choon Kon Kim, Kisoo Lee
  • Publication number: 20080296738
    Abstract: A GaAs semiconductor substrate includes a surface layer. When an atomic ratio is to be calculated using a 3d electron spectrum of Ga atoms and As atoms measured at the condition of 10° for the photoelectron take-off angle ? by X-ray photoelectron spectroscopy, the structural atomic ratio of all Ga atoms to all As atoms (Ga)/(As) at the surface layer is at least 0.5 and not more than 0.9, the ratio of As atoms bound with O atoms to all Ga atoms and all As atoms (As—O)/{(Ga)+(As)} at the surface layer is at least 0.15 and not more than 0.35, and the ratio of Ga atoms bound with O atoms to all Ga atoms and all As atoms (Ga—O)/{(Ga)+(As)} at the surface layer is at least 0.15 and not more than 0.35. Accordingly, there is provided a GaAs semiconductor substrate having a surface cleaned to an extent allowing removal of impurities and oxides at the surface by at least thermal cleaning of the substrate.
    Type: Application
    Filed: October 9, 2007
    Publication date: December 4, 2008
    Inventors: Takayuki Nishiura, Yoshio Mezaki, Yusuke Horie, Yasuaki Higuchi
  • Patent number: 7442628
    Abstract: A method for manufacturing a semiconductor laser. As a preparative step for coating an end face of a resonator with a dielectric film, a cleavage plane of a semiconductor laminated structure that is to be the end face is subjected to a plasma cleaning to prevent a conductive film, which absorbs laser light, from attaching to the cleavage plane. During the plasma cleaning, a first process gas containing argon gas and nitrogen gas is introduced into a vacuumed ECR sputtering apparatus. After the cleavage plane is exposed to the first process gas in the plasma state for a certain time period without application of a voltage, a second process gas containing argon gas and oxygen gas is introduced, and the cleavage plane is exposed to the second process gas in the plasma state while a voltage is applied to the silicon target.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: October 28, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Keiji Yamane, Tetsuo Ueda, Isao Kidoguchi, Toshiya Kawata
  • Publication number: 20080164580
    Abstract: A chemical vapor deposition (CVD) method for depositing materials including germanium (Ge), antimony (Sb) and nitrogen (N) which, in some embodiments, has the ability to fill high aspect ratio openings is provided. The CVD method of the instant invention permits for the control of nitrogen-doped GeSb stoichiometry over a wide range of values and the inventive method is performed at a substrate temperature of less than 400° C., which makes the inventive method compatible with existing interconnect processes and materials. In some embodiments, the inventive method is a non-selective CVD process, which means that the nitrogen-doped GeSb materials are deposited equally well on insulating and non-insulating materials. In other embodiments, a selective CVD process is provided in which the nitrogen-doped GeSb materials are deposited only on regions of a substrate in a metal which is capable of forming an eutectic alloy with germanium.
    Type: Application
    Filed: January 9, 2007
    Publication date: July 10, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jennifer L. Gardner, Fenton R. Mc Feely, John J. Yurkas
  • Publication number: 20080164579
    Abstract: A chemical vapor deposition (CVD) method for depositing materials including germanium (Ge) and antimony (Sb) which, in some embodiments, has the ability to fill high aspect ratio openings is provided. The CVD method of the instant invention permits for the control of GeSb stoichiometry over a wide range of values and the inventive method is performed at a substrate temperature of less than 400° C., which makes the inventive method compatible with existing interconnect processes and materials. In addition to the above, the inventive method is a non-selective CVD process, which means that the GeSb materials are deposited equally well on insulating and non-insulating materials.
    Type: Application
    Filed: January 9, 2007
    Publication date: July 10, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fenton R. McFeely, Alejandro G. Schrott, John J. Yurkas
  • Publication number: 20080076235
    Abstract: Various embodiments proved a buffer layer that is grown over a silicon substrate that provides desirable isolation for devices formed relative to III-V material device layers, such as InSb-based devices, as well as bulk thin film grown on a silicon substrate. In addition, the buffer layer can mitigate parallel conduction issues between transistor devices and the silicon substrate. In addition, the buffer layer addresses and mitigates lattice mismatches between the film relative to which the transistor is formed and the silicon substrate.
    Type: Application
    Filed: September 27, 2006
    Publication date: March 27, 2008
    Inventors: Mantu K. Hudait, Mohamad A. Shaheen, Loren A. Chow, Peter G. Tolchinsky, Joel M. Fastenau, Dmitri Loubychev, Amy W. K. Liu
  • Patent number: 7315045
    Abstract: The present invention relates to a sapphire/gallium nitride laminate, wherein a curvature radius thereof is positioned on the right side of a first curve plotted from the following functional formula (I): Y=Y0+A·e?(x?1)/T??(I) wherein Y is the curvature radius (m) of a sapphire/gallium nitride laminate, X is the thickness (?m) of a gallium nitride film, Y0 is 5.47±0.34, A is 24.13±0.50, and T is 0.56±0.04. The inventive laminate can be advantageously used in the manufacture of a high quality electronic device.
    Type: Grant
    Filed: January 28, 2005
    Date of Patent: January 1, 2008
    Assignee: Samsung Corning Co., Ltd.
    Inventors: Chang Ho Lee, Hae Yong Lee, Choon Kon Kim
  • Patent number: 7291874
    Abstract: The present invention discloses a laser dicing apparatus for a gallium arsenide wafer and a method thereof, wherein firstly, a gallium arsenide wafer is stuck onto a holding film; next, the gallium arsenide wafer together with the holding film is disposed on a working table; the gallium arsenide wafer has multiple chips or dice with a scribed line drawn between every two chips; a control device and an object lens are used to position the working table and a laser, and two video devices are used to observe whether the laser has been precisely aimed at one of the scribed lines; after parameters have been input into the control device, the laser is used to cut the gallium arsenide wafer, and the gallium arsenide wafer is then separated into multiple discrete chips or dice. The present invention can precisely cut gallium arsenide wafers, reduce the cost and accelerate the fabrication process.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: November 6, 2007
    Assignee: Arima Optoelectronics Corp.
    Inventor: Chih-Ming Hsu
  • Patent number: 7192851
    Abstract: A method for manufacturing a semiconductor laser. As a preparative step for coating an end face of a resonator with a dielectric film, a cleavage plane of a semiconductor laminated structure that is to be the end face is subjected to a plasma cleaning to prevent a conductive film, which absorbs laser light, from attaching to the cleavage plane. During the plasma cleaning, a first process gas containing argon gas and nitrogen gas is introduced into a vacuumed ECR sputtering apparatus. After the cleavage plane is exposed to the first process gas in the plasma state for a certain time period without application of a voltage, a second process gas containing argon gas and oxygen gas is introduced, and the cleavage plane is exposed to the second process gas in the plasma state while a voltage is applied to the silicon target.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: March 20, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Keiji Yamane, Tetsuo Ueda, Isao Kidoguchi, Toshiya Kawata
  • Patent number: 7187058
    Abstract: The invention relates to a semiconductor component having a semiconductor body (100) and at least one pn junction present in the semiconductor body (100) and an amorphous passivation layer (70) arranged at least in sections on a surface (101) of the semiconductor body (100), the following holding true for the minimum Ds,min of an interface state density Ds at the junction between the passivation layer (70) and the semiconductor body (100): D s , min ? N S , Bd E g where NS,Bd is the breakdown charge and Eg is the band gap of the semiconductor material used for the semiconductor body (100).
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: March 6, 2007
    Assignee: Infineon Technologies AG
    Inventor: Gerhard Schmidt
  • Patent number: 7109530
    Abstract: A nitride-based semiconductor element having excellent element characteristics is obtained by fabricating a nitride-based semiconductor layer having excellent crystallinity without performing extended etching. The nitride-based semiconductor element comprises a mask layer, having a recess portion, formed on a substantially flat upper surface of an underlayer to partially expose the upper surface of the underlayer, a nitride-based semiconductor layer formed on the exposed part of the underlayer and the mask layer while forming a void on the recess portion of the mask layer, and a nitride-based semiconductor element layer, formed on the nitride-based semiconductor layer, having an element region. During laterally growth, strain is relaxed thereby improving crystallinity. The underlayer is formed in a substantially flat shape, thereby avoiding extended etching.
    Type: Grant
    Filed: March 10, 2004
    Date of Patent: September 19, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Nobuhiko Hayashi, Tatsuya Kunisato, Hiroki Ohbo, Tsutomu Yamaguchi
  • Patent number: 7030462
    Abstract: A Heterojunction Bipolar Transistor, HBT, (100) containing a collector layer (104), a base layer (105) and an emitter layer (106) is constructed such that the collector layer (104), the base layer (105) and the emitter layer (106) have different lattice constants of ac, ab and ae respectively, and a value of ab between values of ac and ae (in other words, the values of ac, ab and ae satisfy a relationship of ac>ab>ae or ac<ab<ae). According to the present invention, the HBT having a high reliability can be realized without altering the existing apparatus and steps for producing the HBT extensively.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: April 18, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Motoji Yagura
  • Patent number: 6963090
    Abstract: An implant-free enhancement mode metal-oxide semiconductor field effect transistor (EMOSFET) is provided. The EMOSFET has a III-V compound semiconductor substrate and an epitaxial layer structure overlying the III-V compound semiconductor substrate. The epitaxial material layer has a channel layer and at least one doped layer. A gate oxide layer overlies the epitaxial layer structure. The EMOSFET further includes a metal gate electrode overlying the gate oxide layer and source and drain ohmic contacts overlying the epitaxial layer structure.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: November 8, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Matthias Passlack, Olin L. Hartin, Marcus Ray, Nicholas Medendorp
  • Patent number: 6906350
    Abstract: The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a delta doped silicon carbide MESFET having a source, a drain and a gate. The gate is situated between the source and the drain and extends into a doped channel layer of a first conductivity type. Regions of silicon carbide adjacent to the source and the drain extend between the source and the gate and the drain and the gate, respectively. The regions of silicon carbide have carrier concentrations that are greater than a carrier concentration of the doped channel layer and are spaced apart from the gate.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: June 14, 2005
    Assignee: Cree, Inc.
    Inventor: Saptharishi Sriram
  • Patent number: 6841409
    Abstract: An AlGaInP layer is formed on a substrate made of GaAs, and an AlGaAs layer is formed on the AlGaInP layer via a buffer layer therebetween. The buffer layer has a thickness of about 1.1 nm and is made of AlGaInP whose Ga content is smaller than that of the AlGaInP layer. The buffer layer may alternatively be made of AlGaAs whose Al content is smaller than that of the AlGaAs layer.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: January 11, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Toshikazu Onishi
  • Patent number: 6797991
    Abstract: The nitride semiconductor device includes: a substrate made of a III-V group compound semiconductor containing nitride; and a function region made of a III-V group compound semiconductor layer containing nitride formed on a main surface of the substrate. The main surface of the substrate is tilted from a {0001} surface by an angle in an range of 13° to 90° inclusive.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: September 28, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Masahiro Ishida
  • Patent number: 6759139
    Abstract: A nitride-based semiconductor element enabling formation of a nitride-based semiconductor layer having low dislocation density, consisting of a material different from that of an underlayer, on the underlayer with a small thickness is obtained. This nitride-based semiconductor element comprises a plurality of mask layers formed at a prescribed interval to be in contact with the upper surface of the underlayer while partially exposing the underlayer and the nitride-based semiconductor layer, formed on the upper surface of the underlayer and the mask layers, consisting of the material different from that of the underlayer. The minimum distance between adjacent mask layers is smaller than the width of an exposed part of the underlayer located between the adjacent mask layers.
    Type: Grant
    Filed: February 25, 2002
    Date of Patent: July 6, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tatsuya Kunisato, Nobuhiko Hayashi, Hiroki Ohbo, Masayuki Hata, Tsutomu Yamaguchi
  • Patent number: 6756611
    Abstract: A method of growing a nitride semiconductor crystal which has very few crystal defects and can be used as a substrate is disclosed. This invention includes the step of forming a first selective growth mask on a support member including a dissimilar substrate having a major surface and made of a material different from a nitride semiconductor, the first selective growth mask having a plurality of first windows for selectively exposing the upper surface of the support member, and the step of growing nitride semiconductor portions from the upper surface, of the support member, which is exposed from the windows, by using a gaseous Group 3 element source and a gaseous nitrogen source, until the nitride semiconductor portions grown in the adjacent windows combine with each other on the upper surface of the selective growth mask.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: June 29, 2004
    Assignee: Nichia Chemical Industries, Ltd.
    Inventors: Hiroyuki Kiyoku, Shuji Nakamura, Tokuya Kozaki, Naruhito Iwasa, Kazuyuki Chocho
  • Patent number: 6727559
    Abstract: A local oscillation FET has a source connecting pad, a drain connecting pad and a gate connecting pad. The source connecting pad occupies one corner of a substrate, and the drain and gate connecting pads are placed at the neighboring corners so that the three connecting pads form an L shape on the substrate. As a modification to this configuration, another source connecting pad is placed at the remaining corner of the substrate so that the drain and gate connecting pads are shielded from each other by the two source connecting pads. These device configurations contribute to size reduction of the local oscillation FET.
    Type: Grant
    Filed: June 24, 2002
    Date of Patent: April 27, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Asano, Masahiro Uekawa, Koichi Hirata, Mikito Sakakibara
  • Patent number: 6713845
    Abstract: A nitride-based semiconductor element having excellent element characteristics is obtained by obtaining a nitride-based semiconductor layer having excellent crystallinity without performing a long-time etching process. This nitride-based semiconductor element comprises a mask layer, having a recess portion, formed on a substantially flat upper surface of an underlayer to partially expose the upper surface of the underlayer, a nitride-based semiconductor layer formed on the exposed part of the underlayer and the mask layer while forming a void on the recess portion of the mask layer, and a nitride-based semiconductor element layer, formed on the nitride-based semiconductor layer, having an element region.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: March 30, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Nobuhiko Hayashi, Tatsuya Kunisato, Hiroki Ohbo, Tsutomu Yamaguchi
  • Patent number: 6653663
    Abstract: The nitride semiconductor device includes: a substrate made of a III-V group compound semiconductor containing nitride; and a function region made of a III-V group compound semiconductor layer containing nitride formed on a main surface of the substrate. The main surface of the substrate is tilted from a {0001} plane by an angle in a range of 13° to 90° inclusive.
    Type: Grant
    Filed: December 5, 2000
    Date of Patent: November 25, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Masahiro Ishida
  • Patent number: 6653660
    Abstract: A vertical cavity-type semiconductor light-emitting device comprises a first semiconductor distributed Bragg reflector type mirror formed on a substrate, a first semiconductor layer formed on the first semiconductor distributed Bragg reflector type mirror and including at least an active layer which becomes an emission layer, a second semiconductor distributed Bragg reflector type mirror formed on the first semiconductor layer and including Al as a configuration element, and a second semiconductor layer including InxGa1−xP (0≦x≦1) layer provided on the second semiconductor distributed Bragg reflector type mirror.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: November 25, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keiji Takaoka
  • Patent number: 6573528
    Abstract: This patent is generally directed towards a method and device for providing a diode structure that has a barrier height that may be readily engineered with a series resistance that may be independently varied while simultaneously providing for the complete characterization and discernment of the barrier height in a microwave and millimeter-wave rectifying diode without the need for device fabrication and electrical measurement. The present invention generally relates to microwave and millimeterwave diodes, and more particularly to low barrier structures within these diodes that are capable of rectification of microwave and millimeterwave radiation.
    Type: Grant
    Filed: October 12, 2001
    Date of Patent: June 3, 2003
    Inventor: Walter David Braddock
  • Publication number: 20030057437
    Abstract: Selenium (or tellurium or sulfur) is doped as an n-type dopant by homogeneous doping or planar doping in a compound semiconductor epitaxial wafer to form a selenium-doped layer. Thus, an epitaxial wafer having high carrier density can be prepared. The use of this epitaxial wafer can lower parasitic resistance and can provide HEMT having high gm. Further, the lowered resistance can significantly increase the freedom of device design.
    Type: Application
    Filed: September 21, 2001
    Publication date: March 27, 2003
    Inventors: Tatsushi Hashimoto, Mineo Washima, Takeshi Tanaka
  • Publication number: 20030034541
    Abstract: Fault remediation functions are embodied in a semiconductor structure in which high quality epitaxial layers of monocrystalline materials are made to overlie monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Fault remediation is carried out in one instance by recognizing the presence of a fault and in another instance by providing fault correction.
    Type: Application
    Filed: August 16, 2001
    Publication date: February 20, 2003
    Applicant: MOTOROLA, INC.
    Inventors: Raymond B. Essick, Mihir A. Pandya
  • Patent number: 6504185
    Abstract: A compound semiconductor device is formed having a plurality of FETs exhibiting the same electrode ratio of a difference between a surface area of the active region and the combined overlapping surface area of the source and drain ohmic electrodes to the combined overlapping surface area of the source and drain ohmic electrodes. As such, precise control of a threshold voltage of the FETs is achieved. The compound semiconductor device is also formed so as to include a plurality of resistors having the same ratio of a difference between a surface area of the resistivity region and the combined overlapping surface area of the pair electrodes to the combined overlapping surface area of the pair electrodes. In this manner, a resistivity of the resistor is precisely controlled.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: January 7, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Nobusuke Yamamoto