Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include an obstructive element bonded to the semiconductor element along a bond interface, the obstructive element including an obstructive material disposed over the active circuitry, the obstructive material configured to obstruct external access to the active circuitry. The bonded element can include an artifact structure indicative of a wafer-level bond in which the semiconductor element and the obstructive element formed part of respective wafers directly bonded prior to singulation.

Abstract: A thin film heterostructure of a topological insulator (TI) with a normal metal (NM) is used as a highly energy efficient and low power dissipation spin Hall Material (SHM). The TI material is sputter deposited onto a substrate and cooled in high vacuum, and an NM material is sputter deposited onto the TI film. The structure and method is compatible with complementary metal oxide (CMOS) processes, and with growth of large-area TI films for wafer-level device fabrication.

Abstract: When III-V semiconductor material is bonded to an oxide material, water molecules can degrade the bonding if they become trapped at the interface between the III-V material and the oxide material. Because water molecules can diffuse readily through oxide material, and may not diffuse as readily through III-V material or through silicon, forcing the III-V material against the oxide material can force water molecules at the interface into the oxide material and away from the interface. Water molecules present at the interface can be forced during manufacturing through vertical channels in a silicon layer into a buried oxide layer thereby to enhance bonding between the III-V material and the oxide material. Water molecules can be also forced through lateral channels in the oxide material, past a periphery of the III-V material, and, through diffusion, out of the oxide material into the atmosphere.

Abstract: A semiconductor structure includes a semiconductor element and a first bonding structure. The semiconductor element has a first surface and a second surface opposite to the first surface. The first bonding structure is disposed adjacent to the first surface of the semiconductor element, and includes a first electrical connector, a first insulation layer surrounding the first electrical connector and a first conductive layer surrounding the first insulation layer.

Abstract: An apparatus for detecting the presence of assembly related defects on a semiconductor device including an edge ring having a resistance value and including one or more layers configured to at least partially cover the semiconductor device in a first direction. The one or more layers are divided into a first section and a second section. Each layer of the one or more layers are in electrical communication with one another. The resistance value of the edge ring is at a first resistance value associated with the first and second sections being intact. At least one of the first section and second section is configured to break in response to an assembly related defect, and the resistance value of the edge ring is configured to change from the first resistance value to a second resistance value in response to at least one of the first and second sections being broken.

Abstract: An electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. Chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. A lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.

Abstract: A microelectromechanical (MEMS) microphone with membrane trench reinforcements and method of fabrication is provided. The MEMS microphone includes a flexible plate and a rigid plate mechanically coupled to the flexible plate. The MEMS microphone includes a stoppage member affixed to the rigid plate and extending perpendicular relative to a surface of the rigid plate opposite the surface of the flexible plate. The stoppage member limits motion of the flexible plate. The rigid plate includes a reverse bending edge that include a first lateral etch stop that includes a first corner radius and a second lateral etch stop that includes a second corner radius. The first corner radius is more than 100 nanometers and the second corner radius is more than 25 nanometers. Further, a lateral step width between the first corner radius and the second corner radius is less than around 4 micrometers.

Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include an obstructive element bonded to the semiconductor element along a bond interface, the obstructive element including an obstructive material disposed over the active circuitry, the obstructive material configured to obstruct external access to the active circuitry. The bonded element can include an artifact structure indicative of a wafer-level bond in which the semiconductor element and the obstructive element formed part of respective wafers directly bonded prior to singulation.

Abstract: A method of manufacturing a semiconductor device includes forming a stack in which first material layers and second material layers are alternately stacked, forming a channel structure passing through the stack, forming openings by removing the first material layers, forming an amorphous blocking layer in the openings, and performing a first heat treatment process to supply deuterium through the openings and substitute hydrogen in the channel structure with the deuterium.

Abstract: In some examples, a device includes a dielectric material, a ferromagnetic material, and a topological material positioned between the dielectric material and the ferromagnetic material. The device is configured to trap electric charge inside the dielectric material or at an interface of the dielectric material and the topological material. The device is configured to switch a magnetization state of the ferromagnetic material based on a current through the topological material or based on a voltage in the topological material.

Abstract: The present invention provides a wearable device, a system for manufacturing a wearable device and a method of neural activity control. The device for temporal interference simulation includes a pair of electrodes at penalizable location. The electrodes each send out a high frequency electromagnetic fields with a very slight difference in the two frequencies. The fields superimpose at a specified region of the brain, which is customized depending on the location of neural activity control, to create a low frequency refractory wave envelope. The low frequency wave inhibits or stimulates local neurons to control electrical activity within that region.

Abstract: A thermal management package for a semiconductor device includes a high dielectric constant material substrate, a high thermal conductivity slug disposed in a first window in the high dielectric constant material substrate and held therein by a first bonding material, an outer substrate formed from a material having a low dielectric constant and having a second window formed therein, the high dielectric constant material substrate disposed in the second window in the low dielectric constant outer substrate and held therein by a second bonding material.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device is disclosed. The method of manufacturing a semiconductor device, includes forming an organic film containing polyacrylonitrile on a target film on a semiconductor substrate; applying a metal compound to the organic film to form a composite film; removing the composite film partially to form a pattern; heating the pattern-formed composite film; and processing the target film by using the heated composite film as a mask.

Abstract: Methods of depositing a carbon film are discussed. Some embodiments selectively deposit a carbon film on a metal surface over a dielectric surface. Some embodiments form carbon pillars on metal surfaces selectively over dielectric surfaces. Some embodiments utilize carbon pillars in forming self-aligned vias.

Abstract: A display panel and a display device are provided. The display panel includes: a first substrate including a display area and a wiring area, wherein a plurality of active switches and a plurality of pixel units are disposed in the display area of the first substrate, and the pixel units are respectively coupled to the active switches; a second substrate disposed opposite the first substrate; a first drive line portion disposed in the wiring area of the first substrate; a second drive line portion disposed in the wiring area of the first substrate; a flexible circuit board including a first wire; and a first interface unit respectively connecting the first wire to the first drive line portion and the second drive line portion. The flexible circuit board comprises a second wire, and the second wire is connected to the first wire in parallel to form parallel circuits.

Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first portion and a vertically conductive structure. The first portion includes a first dielectric layer and a first guard ring in the first dielectric layer. The first guard ring includes, in the first dielectric layer, a first metal layer coupled to a first via. The first portion includes a vertical conductive structure passing through the first dielectric layer and proximate by the first guard ring.

Abstract: A bonding structure and a method for manufacturing the same. First edge trimming is performed from the bonding surface of an n-th wafer in bonding the n-th wafer and an (n?1)th wafer, and a width of the first edge trimming is Wn. As n increases, the width of the first edge trimming is gradually increased. In the trimming, a portion that is not even at the edge of the n-th wafer can be removed. The bonding surface of the n-th wafer faces the bonding surface of the (n?1)-th wafer, so as to bond the n-th wafer and the (n?1)-th wafer. Afterwards the substrate of the n-th wafer is thinned, so as to form the (n?1)-th wafer stack. There is a reduced possibility that a gap exists between the bonding interfaces of the wafers, a bonding strength between the wafers is improved, and a risk of cracking is reduced.

Abstract: A method for manufacturing a substrate includes the following steps: (a) providing a support substrate with a first coefficient of thermal expansion, having on one of its faces a first plurality of trenches parallel to each other in a first direction, and a second plurality of trenches parallel to each other in a second direction; (b) transferring a useful layer from a donor substrate to the support substrate, the useful layer having a second coefficient of thermal expansion; wherein an intermediate layer is inserted between the front face of the support substrate and the useful layer, the intermediate layer having a coefficient of thermal expansion between the first and second coefficients of thermal expansion.

Abstract: An integrated circuit device is provided. The integrated circuit device includes a semiconductor substrate having a circuit area and a guarding area surrounding the circuit area. A guarding structure is formed in the guarding area, and includes a diffusion region in the semiconductor substrate. The guarding structure also includes a gate stack disposed on the semiconductor substrate and positioned adjacent to the diffusion region. The guarding structure further includes a guarding layer disposed on the gate stack. The gate stack extends in a first direction while the guarding layer extends in a second direction that is different from the first direction. The guarding layer is electrically insulated from the diffusion region. Thus, an integrated circuit device including a guarding structure with several capacitors is provided.

Abstract: In a touch sensor in which a touch sensor body is attached to a cover member, the cover member includes: a first member made of a glass plate and having a first surface and a second surface that is an opposite surface of the first member from the first surface; and a resin film made of polyvinyl butyral (PVB) and formed on the second surface. The resin film is located between the first member and the touch sensor body.

Abstract: A glass element having a thickness from 25 ?m to 125 ?m, a first primary surface, a second primary surface, and a compressive stress region extending from the first primary surface to a first depth, the region defined by a compressive stress ?I of at least about 100 MPa at the first primary surface. Further, the glass element has a stress profile such that it does not fail when it is subject to 200,000 cycles of bending to a target bend radius of from 1 mm to 20 mm, by the parallel plate method. Still further, the glass element has a puncture resistance of greater than about 1.5 kgf when the first primary surface of the glass element is loaded with a tungsten carbide ball having a diameter of 1.5 mm.

Abstract: A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure having PMOS and NMOS regions. The PMOS region includes a first region, a first gate structure on the first region, and first source and drain regions on opposite sides of the first gate structure. The NMOS region includes a second region and a second gate structure on the second region. The method also includes introducing a p-type dopant into the first source and drain regions, performing a first annealing, forming second source and drain regions on opposite sides of the second gate structure, introducing an n-type dopant into the second source and drain regions, and performing a second annealing. The method satisfies thermal budget requirements of forming PMOS and NMOS devices, thereby enabling a better diffusion of the p-type dopant into the source and drain regions of the PMOS device without affecting the performance of the NMOS device.

Abstract: A semiconductor device includes a plurality of semiconductor switching elements disposed on a single semiconductor substrate comprising a semiconductor having a bandgap that is wider than that of silicon; and a plurality of electrode pads that are disposed in a predetermined planar layout on a front surface of the semiconductor substrate, the plurality of electrode pads each being electrically connected to the plurality of semiconductor switching elements. A plurality of terminal pins to externally carry out voltage of the electrode pads is bonded through a plated film to all of the plurality of electrode pads by solder.

Abstract: Silicon-based or other electronic circuitry is dissolved or otherwise disabled by reactive materials within a semiconductor chip should the chip or a device containing the chip be subjected to tampering. Triggering circuits containing normally-OFF heterojunction field-effect photo-transistors are configured to cause reactions of the reactive materials within the chips upon exposure to light. The normally-OFF heterojunction field-effect photo-transistors can be fabricated during back-end-of-line processing through the use of polysilicon channel material, amorphous hydrogenated silicon gate contacts, hydrogenated crystalline silicon source/drain contacts, or other materials that allow processing at low temperatures.

Abstract: A semiconductor structure including a semiconductor layer made of a crystalline semiconductor compound, a portion of the semiconductor layer which forms a suspended membrane above a carrier layer, the suspended membrane being formed from a tensilely stressed central segment and a plurality of lateral segments forming tensioning arms. The central segment includes at least one zone of thinned thickness.

Abstract: A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.

Abstract: An electronic device includes a substrate, a functional element that is arranged on the substrate, a terminal that is arranged on the substrate and that is electrically connected to the functional element, and a bonding wire that is connected to the terminal. The terminal has an alloy portion that is alloyed to the bonding wire at a connection portion between the terminal and the bonding wire, and the thickness of the terminal is larger than the thickness of the alloy portion. Moreover, the terminal is formed of the same material (silicon) as the functional element.

Abstract: A method of restricting diffusion of miscible materials across a barrier, including, forming a 2-dimensional material on a substrate surface, wherein the 2-dimensional material includes one or more defects through which a portion of the substrate surface is exposed, forming a plug selectively on the exposed substrate surface, and forming a cover layer on the plug and 2-dimensional material, wherein the cover layer material is miscible in the substrate material.

Abstract: A process for the manufacture of a semiconductor element includes a stage of rapid heat treatment of a substrate comprising a charge-trapping layer, which is capable of damaging an RF characteristic of the substrate. The rapid heat treatment stage is followed by a healing heat treatment of the substrate between 700° C. and 1,100° C., for a period of time of at least 15 seconds.

Abstract: Included are a first cover base including an alkali glass layer, a first alkali-free glass layer provided on one face of the alkali glass layer, and a second alkali-free glass layer provided on another face of the alkali glass layer and a sensor that is provided on the first alkali-free glass layer of the first cover base and includes a plurality of first electrodes configured to detect the unevenness of a surface of an object to be detected that comes into contact with or close to the first cover base and a switching element. At least the first electrodes are formed above the first alkali-free glass layer and in a transmissive area that passes an image.

Abstract: A semiconductor device includes a semiconductor substrate comprising a group III element and a group V element, and a gate structure on the semiconductor substrate. The semiconductor substrate includes a first region which contacts a bottom surface of the gate structure and a second region which is disposed under the first region. The concentration of the group III element in the first region is lower than that of the group V element in the first region, and the concentration of the group III element in the second region is substantially equal to that of the group V element in the second region.

Abstract: Implementations described herein generally relate to processes for the fabrication of semiconductor devices in which a self-assembled monolayer (SAM) is used to achieve selective area deposition. Methods described herein relate to alternating SAM molecule and hydroxyl moiety exposure operations which may be utilized to form SAM layers suitable for blocking deposition of subsequently deposited materials.

Abstract: A semiconductor device, including a substrate, a deposition layer deposited on the substrate, a semiconductor region selectively provided in the deposition layer, a semiconductor layer provided on the deposition layer and the semiconductor region, a first region and a second region selectively provided in the semiconductor layer, a gate electrode provided on the second region and the semiconductor layer via a gate insulating film, a source electrode in contact with the semiconductor layer and the second region, an interlayer insulating film covering the gate electrode, a drain electrode provided on the substrate, a plating film selectively provided on the source electrode at portions thereof on which the protective film is not provided, and a pin-shaped electrode connected to the plating film via solder. The second region is not formed directly beneath a portion where the plating film, the protective film and the source electrode are in contact with one another.

Abstract: Silicon-based or other electronic circuitry is dissolved or otherwise disabled by reactive materials within a semiconductor chip should the chip or a device containing the chip be subjected to tampering. Triggering circuits containing normally-OFF heterojunction field-effect photo-transistors are configured to cause reactions of the reactive materials within the chips upon exposure to light. The normally-OFF heterojunction field-effect photo-transistors can be fabricated during back-end-of-line processing through the use of polysilicon channel material, amorphous hydrogenated silicon gate contacts, hydrogenated crystalline silicon source/drain contacts, or other materials that allow processing at low temperatures.

Abstract: In a semiconductor device, an interlayer insulating film electrically insulating a gate electrode and a source electrode has a structure in which a BPSG film and a NSG film are sequentially stacked. Further, the interlayer insulating film has a structure in which the BPSG film, the NSG film, and a SiN film are sequentially stacked, or a structure in which the BPSG film, the SiN film, and the NSG film are sequentially stacked. Such a structure enables the reliability of the semiconductor device in which a pin-shaped electrode is bonded by solder to be improved.

Abstract: In an aspect of the disclosure, a process for forming nanostructuring on a silicon-containing substrate is provided. The process comprises (a) performing metal-assisted chemical etching on the substrate, (b) performing a clean, including partial or total removal of the metal used to assist the chemical etch, and (c) performing an isotropic or substantially isotropic chemical etch subsequently to the metal-assisted chemical etch of step (a). In an alternative aspect of the disclosure, the process comprises (a) performing metal-assisted chemical etching on the substrate, (b) cleaning the substrate, including removal of some or all of the assisting metal, and (c) performing a chemical etch which results in regularized openings in the silicon substrate.

Abstract: The present invention relates to ruggedized downhole tools and sensors, as well as uses thereof. In particular, these tools can operate under extreme conditions and, therefore, allow for real-time measurements in geothermal reservoirs or other potentially harsh environments. One exemplary sensor includes a ruggedized ion selective electrode (ISE) for detecting tracer concentrations in real-time. In one embodiment, the ISE includes a solid, non-conductive potting material and an ion selective material, which are disposed in a temperature-resistant electrode body. Other electrode configurations, tools, and methods are also described.

Abstract: Provided are an electrode active material having a plurality of pores and a secondary battery including the same, and more particularly, a porous electrode active material including silicon-based oxide expressed by SiOx (0.5?x?1.2) and having a Brunauer, Emmett, and Teller (BET) specific surface area ranging from 2 m2/g to 100 m2/g, and a secondary battery including a cathode including a cathode active material, a separator, an anode including an anode active material, and an electrolyte, in which the anode active material includes a porous electrode active material including silicon-based oxide expressed by SiOx (0.5?x?1.2) and having a BET specific surface area ranging from 2 m2/g to 100 m2/g.

Abstract: A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, and a surface insulating film disposed in a manner extending across the cell portion and the outer peripheral portion, and in the cell portion, formed to be thinner than a part in the outer peripheral portion.

Abstract: A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.

Abstract: An article includes a support substrate bonded to heterostructure epitaxial layers that include one or more electronic devices. The support substrate has a bonding surface and the heterostructure epitaxial layers have a surface with the epitaxial growth direction of the heterostructure epitaxial layers towards the surface. The surface of the heterostructure epitaxial layers is bonded at the bonding surface of the support substrate by ion exchange between the surface of the heterostructure epitaxial layers and the bonding surface of the support substrate.

Abstract: A chip packaging method using a hydrophobic surface includes forming superhydrophobic surfaces forming hydrophilic surfaces on predetermined positions of the superhydrophobic surfaces formed on the one of a first chip or the first board and the one of a second chip or a second board, respectively, generating liquid metal balls on the hydrophilic surfaces formed on the one of the first chip or the first board and the one of the second chip or the second board, respectively, and packaging the one of the first chip or the first board and the one of the second chip or the second board by combing the liquid metal ball of the one of the first chip or the first board and the liquid metal ball of the one of the second chip or the second board with each other.

Abstract: A first semiconductor substrate having at least one integrated semiconductor device is provided. A lift-off layer is formed on a main surface of the first semiconductor substrate. The lift-off layer is patterned so as to form openings in the lift-off layer that are arranged on either side of a first portion of the lift-off layer. The first substrate is connected together with a second substrate by an interconnect structure to form an assembly with the main surface of the first semiconductor substrate being exposed. Exposed surfaces of the assembly are coated with a parylene coating, with a first portion of the parylene coating being supported by the first portion of the lift-off layer. The first portion of the parylene coating is selectively removed using a lift-off technique that removes the first portion of the lift-off layer. The lift-off technique is performed after connecting the first substrate and second substrates together.

Abstract: Silicon-based or other electronic circuitry is dissolved or otherwise disabled by reactive materials within a semiconductor chip should the chip or a device containing the chip be subjected to tampering. Triggering circuits containing normally-OFF heterojunction field-effect photo-transistors are configured to cause reactions of the reactive materials within the chips upon exposure to light. The normally-OFF heterojunction field-effect photo-transistors can be fabricated during back-end-of-line processing through the use of polysilicon channel material, amorphous hydrogenated silicon gate contacts, hydrogenated crystalline silicon source/drain contacts, or other materials that allow processing at low temperatures.

Abstract: Damascene templates have two-dimensionally patterned raised metal features disposed on an underlying conductive layer extending across a substrate. The templates are topographically flat overall, and the patterned conductive features establish micron-scale and nanometer-scale patterns for the assembly of nanoelements into nanoscale circuits and sensors. The templates are made using microfabrication techniques together with chemical mechanical polishing. These templates are compatible with various directed assembly techniques, including electrophoresis, and offer essentially 100% efficient assembly and transfer of nanoelements in a continuous operation cycle. The templates can be repeatedly used for transfer of patterned nanoelements thousands of times with minimal or no damage, and the transfer process involves no intermediate processes between cycles. The assembly and transfer processes employed are carried out at room temperature and pressure and are thus amenable to low cost, high-rate device production.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a routable distribution layer on a leadframe; mounting an integrated circuit over the routable distribution layer; encapsulating with an encapsulation over the routable distribution layer; peeling the leadframe away from the routable distribution layer with a bottom distribution side of the routable distribution layer exposed from the encapsulation; and mounting an external interconnect on the routable distribution layer.

Abstract: A solar cell is discussed. The solar cell includes a semiconductor substrate, a p-type conductive region formed at the semiconductor substrate and including a p-type impurity, and a passivation film formed on the p-type conductive region and including aluminum oxide. The passivation film has a thickness of 7 to 17 ?.

Abstract: Methods for detecting the physical layout of an integrated circuit are provided. The methods of the present disclosure allow large area imaging of the circuit layout without requiring tedious sample preparation techniques. The imaging can be performed utilizing low-energy beam techniques such as scanning electron microscopy; however, more sophisticated imaging techniques can also be employed. In the methods of the present disclosure, spalling is used to remove a portion of a semiconductor layer including at least one semiconductor device formed thereon or therein from a base substrate. In some cases, a buried insulator layer that is located beneath a semiconductor layer including the at least one semiconductor device can be completely or partially removed. In some cases, the semiconductor layer including the at least one semiconductor device can be thinned. The methods improve the detection quality that the buried insulator layer and a thick semiconductor layer can reduce.

Abstract: Embodiments of mechanisms for forming a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate having a first device region and a second device region. The semiconductor device structure further includes first devices in the first device region and second devices in the second device region. The semiconductor device structure also includes a first annular structure continuously surrounding the first device region and a second annular structure continuously surrounding the second device region. The first annular structure has a first thermal diffusion coefficient less than a second thermal diffusion coefficient of the second annular structure.