Non-single Crystal, Or Recrystallized, Material With Specified Crystal Structure (e.g., Specified Crystal Size Or Orientation) Patents (Class 257/64)
  • Patent number: 10351431
    Abstract: Provided are methods for growing large-size, uniform graphene layers on planarized substrates using Chemical Vapor Deposition (CVD) at atmospheric pressure; graphene produced according to these methods may have a single layer content exceeding 95%. Field effect transistors fabricated by the inventive process have room temperature hole mobilities that are a factor of 2-5 larger than those measured for samples grown on commercially-available copper foil substrates.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: July 16, 2019
    Assignee: The Trustees of the University of Pennsylvania
    Inventors: Alan T. Johnson, Zhengtang Luo
  • Patent number: 10301743
    Abstract: A new GaN single crystal is provided. A GaN single crystal according to the present embodiment comprises a gallium polar surface which is a main surface on one side and a nitrogen polar surface which is a main surface on the opposite side, wherein on the gallium polar surface is found at least one square area, an outer periphery of which is constituted by four sides each with a length of 2 mm or more, and, when the at least one square are is divided into a plurality of sub-areas each of which is a square of 100 ?m×100 ?m, pit-free areas account for 80% or more of the sub-areas.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: May 28, 2019
    Assignee: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Hideo Fujisawa, Yutaka Mikawa, Shinichiro Kawabata, Hideo Namita, Tae Mochizuki
  • Patent number: 10217882
    Abstract: A quantum rod, a synthesis method of the quantum rod and a quantum rod display device are discussed. The quantum rod according to an embodiment includes a core, a first shell covering the core, and a second shell covering a side of the first shell. In the quantum rod, a first thickness of the first shell is greater than a second thickness of the second shell, and a first length of the first shell is smaller than a second length of the second shell.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: February 26, 2019
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Kyung-Kook Jang, Byung-Geol Kim, Wy-Yong Kim, Kyu-Nam Kim, Sung-Il Woo
  • Patent number: 10090638
    Abstract: A monolithically integrated optical device. The device has a gallium and nitrogen containing substrate member having a surface region configured on either a non-polar or semi-polar orientation. The device also has a first waveguide structure configured in a first direction overlying a first portion of the surface region. The device also has a second waveguide structure integrally configured with the first waveguide structure. The first direction is substantially perpendicular to the second direction.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: October 2, 2018
    Assignee: Soraa Laser Diode, Inc.
    Inventor: James W. Raring
  • Patent number: 10083996
    Abstract: An object of the present invention is to provide a semiconductor device having a novel structure in which in a data storing time, stored data can be stored even when power is not supplied, and there is no limitation on the number of writing. A semiconductor device includes a first transistor including a first source electrode and a first drain electrode; a first channel formation region for which an oxide semiconductor material is used and to which the first source electrode and the first drain electrode are electrically connected; a first gate insulating layer over the first channel formation region; and a first gate electrode over the first gate insulating layer. One of the first source electrode and the first drain electrode of the first transistor and one electrode of a capacitor are electrically connected to each other.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: September 25, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kiyoshi Kato
  • Patent number: 10083921
    Abstract: Some embodiments relate to a die that has been formed by improved dicing techniques. The die includes a substrate which includes upper and lower substrate surfaces with a vertical substrate sidewall extending therebetween. The vertical substrate sidewall corresponds to an outermost edge of the substrate. A device layer is arranged over the upper substrate surface. A crack stop is arranged over an upper surface of the device layer and has an outer perimeter that is spaced apart laterally from the vertical substrate sidewall. The die exhibits a tapered sidewall extending downward through at least a portion of the device layer to meet the vertical substrate sidewall.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: September 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Syuan Lin, Jiun-Lei Jerry Yu, Ming-Cheng Lin, Hsin-Chieh Huang, Chao-Hsiung Wang
  • Patent number: 10032933
    Abstract: Provided is a thin film transistor including an active layer including a first silicon active layer, a second silicon active layer, and an oxide active layer in a space between the first silicon active layer and the second silicon active layer, a gate electrode on the active layer with a gate insulating layer disposed therebetween, and a source electrode and a drain electrode with an interlayer insulating layer disposed between the gate electrode and the source and drain electrodes, the source and drain electrodes being in contact with the first silicon active layer and the second silicon active layer, respectively.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: July 24, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jung-Bae Kim
  • Patent number: 9991257
    Abstract: A semiconductor device may include fin active regions extending parallel to each other on a substrate, an isolation region between the fin active regions, gate patterns intersecting the fin active regions and extending parallel to each other, source/drain areas on the fin active regions between the gate patterns and fin active region spacers contacting side surfaces of the fin active regions and formed over a surface of the isolation region between the fin active regions. Uppermost levels of the fin active region spacers may be higher than interfaces between the fin active regions and the source/drain areas. The upper surface of the isolation region may be lower than bottom surfaces of the source/drain areas.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: June 5, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Miseon Park, Jongryeol Yoo, Hyunjung Lee, Yong-Suk Tak, Bonyoung Koo, Sunjung Kim
  • Patent number: 9966470
    Abstract: A FinFET device includes a substrate and a fin structure having a semiconductor material layer over the substrate and recessed regions on side walls of the fin structure. The recessed regions have openings facing away from the fin structure. The fin structure has a bottom portion below the recessed regions that is wider than a top portion.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: May 8, 2018
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Meng Zhao
  • Patent number: 9843024
    Abstract: Systems and methods for fabricating an OLED are provided, which include dispensing a substrate material onto a substrate carrier, the substrate carrier being rotated by one or more drums, curing the substrate material to form a substrate, depositing at least one OLED onto the substrate, and separating the substrate from the substrate carrier.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: December 12, 2017
    Assignee: Universal Display Corporation
    Inventors: Ruiqing Ma, John Felts, Jeffrey Silvernail, Zhaoqun Zhoi, Emory Krall, Julia J. Brown
  • Patent number: 9443984
    Abstract: A semiconductor device capable of high speed operation is provided. Further, a highly reliable semiconductor device is provided. An oxide semiconductor having crystallinity is used for a semiconductor layer of a transistor. A channel formation region, a source region, and a drain region are formed in the semiconductor layer. The source region and the drain region are formed in such a manner that one or more of elements selected from rare gases and hydrogen are added to the semiconductor layer by an ion doping method or an ion implantation method with the use of a channel protective layer as a mask.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: September 13, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Shunpei Yamazaki
  • Patent number: 9419146
    Abstract: A region containing a high proportion of crystal components and a region containing a high proportion of amorphous components are formed separately in one oxide semiconductor film. The region containing a high proportion of crystal components is formed so as to serve as a channel formation region and the other region is formed so as to contain a high proportion of amorphous components. It is preferable that an oxide semiconductor film in which a region containing a high proportion of crystal components and a region containing a high proportion of amorphous components are mixed in a self-aligned manner be formed. To separately form the regions which differ in crystallinity in the oxide semiconductor film, first, an oxide semiconductor film containing a high proportion of crystal components is formed and then process for performing amorphization on part of the oxide semiconductor film is conducted.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: August 16, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Shunpei Yamazaki
  • Patent number: 9343306
    Abstract: A thin film transistor array substrate includes a substrate, a plurality of poly-silicon islands and a plurality of gates. The substrate has a display region, a gate driver region and a source driver region. Each poly-silicon island disposed on the substrate has a source region, a drain region and a channel region disposed therebetween. The poly-silicon islands include several first poly-silicon islands and several second poly-silicon islands. The first poly-silicon islands having main grain boundaries and sub grain boundaries are only disposed within the display region and the gate driver region. The main grain boundaries of the first poly-silicon islands are only disposed within the source regions and/or the drain regions. The second poly-silicon islands are disposed in the source driver region. Grain sizes of the first poly-silicon islands are substantially different from those of the second poly-silicon islands. Gates corresponding to the channel regions are disposed on the substrate.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: May 17, 2016
    Assignee: Au Optronics Corporation
    Inventors: Ming-Wei Sun, Chih-Wei Chao
  • Patent number: 9299568
    Abstract: A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.
    Type: Grant
    Filed: July 1, 2012
    Date of Patent: March 29, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Fredrick Jenne, Sagy Levy, Krishnaswamy Ramkumar
  • Patent number: 9281305
    Abstract: A transistor device structure includes a substrate, a first transistor layer and a second transistor layer. The second transistor layer is disposed between the substrate and the first transistor layer. The first transistor layer includes an insulating structure and a first transistor unit. The insulating structure is disposed on the second transistor layer and has a protruding portion. The first transistor unit includes a gate structure, a source/drain structure, an embedded source/drain structure and a channel. The source/drain structure is disposed beside the gate structure and over the insulating structure. The embedded source/drain structure is disposed underneath the source/drain structure and in the insulating structure. The channel is defined between the protruding portion and the gate structure.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: March 8, 2016
    Assignee: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Chih-Chao Yang, Jia-Min Shieh, Wen-Hsien Huang, Tung-Ying Hsieh, Chang-Hong Shen, Szu-Hung Chen
  • Patent number: 9269825
    Abstract: A semiconductor device which is miniaturized and has sufficient electrical characteristics to function as a transistor is provided. In a semiconductor device including a transistor in which a semiconductor layer, a gate insulating layer, and a gate electrode layer are stacked in that order, an oxide semiconductor film which contains at least four kinds of elements of indium, gallium, zinc, and oxygen, and in which the percentage of the indium is twice or more as large as each of the percentage of the gallium and the percentage of the zinc when the composition of the four elements is expressed in atomic percentage is used as the semiconductor layer. In the semiconductor device, the oxide semiconductor film is a film to which oxygen is introduced in the manufacturing process and contains a large amount of oxygen, and an insulating layer including an aluminum oxide film is provided to cover the transistor.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: February 23, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Naoto Yamade, Junichi Koezuka
  • Patent number: 9196616
    Abstract: It is an object to provide a memory device where an area occupied by a memory cell is small, and moreover, a memory device where an area occupied by a memory cell is small and a data holding period is long. A memory device includes a bit line, a capacitor, a first insulating layer provided over the bit line and including a groove portion, a semiconductor layer, a second insulating layer in contact with the semiconductor layer, and a word line in contact with the second insulating layer. Part of the semiconductor layer is electrically connected to the bit line in a bottom portion of the groove portion, and another part of the semiconductor layer is electrically connected to one electrode of the capacitor in a top surface of the first insulating layer.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: November 24, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Toshihiko Saito
  • Patent number: 9196543
    Abstract: A method of forming a fin field effect transistor (FinFET) structure including forming a plurality of shallow trench isolation (STI) features in a semiconductor substrate, thereby defining a plurality of bulk-semiconductor areas separated from each other by the STI features. The method then forms a first hard mask layer on the semiconductor substrate, the first hard mask layer being patterned to have a plurality of openings over one of the bulk-semiconductor areas. A second semiconductor material is then grown on the semiconductor substrate within the plurality of openings of the first hard mask layer, thereby forming a multi-fin active region having multiple fin features within the one of the bulk-semiconductor areas.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: November 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 9178042
    Abstract: A method for forming a thin film transistor includes joining a crystalline substrate to an insulating substrate. A doped layer is deposited on the crystalline substrate, and the doped layer is patterned to form source and drain regions. The crystalline substrate is patterned to form an active area such that a conductive channel is formed in the crystalline substrate between the source and drain regions. A gate stack is formed between the source and drain regions, and contacts are formed to the source and drain regions and the gate stack through a passivation layer.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: November 3, 2015
    Assignee: GLOBALFOUNDRIES INC
    Inventors: Bahman Hekmatshoartabari, Ning Li, Devendra K. Sadana, Davood Shahrjerdi
  • Patent number: 9035429
    Abstract: There is provided a method of processing a surface of a group III nitride crystal, that includes the steps of: polishing a surface of a group III nitride crystal with a polishing slurry containing abrasive grains; and thereafter polishing the surface of the group III nitride crystal with a polishing liquid at least once, and each step of polishing with the polishing liquid employs a basic polishing liquid or an acidic polishing liquid as the polishing liquid. The step of polishing with the basic or acidic polishing liquid allows removal of impurity such as abrasive grains remaining on the surface of the group III nitride crystal after it is polished with the slurry containing the abrasive grains.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: May 19, 2015
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takayuki Nishiura, Keiji Ishibashi
  • Patent number: 9035311
    Abstract: An organic light emitting diode (OLED) display device and a method of fabricating the same are provided. The OLED display device includes a substrate having a thin film transistor region and a capacitor region, a buffer layer disposed on the substrate, a gate insulating layer disposed on the substrate, a lower capacitor electrode disposed on the gate insulating layer in the capacitor region, an interlayer insulating layer disposed on the substrate, and an upper capacitor electrode disposed on the interlayer insulating layer and facing the lower capacitor electrode, wherein regions of each of the buffer layer, the gate insulating layer, the interlayer insulating layer, the lower capacitor electrode, and the upper capacitor electrode have surfaces in which protrusions having the same shape as grain boundaries of the semiconductor layer are formed. The resultant capacitor has an increased surface area, and therefore, an increased capacitance.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 19, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byoung-Keon Park, Tae-Hoon Yang, Jin-Wook Seo, Soo-Beom Jo, Dong-Hyun Lee, Kil-Won Lee, Maxim Lisachenko, Yun-Mo Chung, Bo-Kyung Choi, Jong-Ryuk Park, Ki-Yong Lee
  • Patent number: 9006728
    Abstract: It is an object to provide a semiconductor device having a new productive semiconductor material and a new structure. The semiconductor device includes a first conductive layer over a substrate, a first insulating layer which covers the first conductive layer, an oxide semiconductor layer over the first insulating layer that overlaps with part of the first conductive layer and has a crystal region in a surface part, second and third conductive layers formed in contact with the oxide semiconductor layer, an insulating layer which covers the oxide semiconductor layer and the second and third conductive layers, and a fourth conductive layer over the insulating layer that overlaps with part of the oxide semiconductor layer.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kei Takahashi, Yoshiaki Ito
  • Publication number: 20150060859
    Abstract: In accordance with an embodiment, an evaluation sample includes a substrate and a polycrystalline film on the substrate. The polycrystalline film has crystal grains. A specific orientation plane is exposed on the surface of each crystal grain. The orientation planes exhibit random angles to the surface of the substrate.
    Type: Application
    Filed: January 6, 2014
    Publication date: March 5, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Ryota NIHEI
  • Patent number: 8969878
    Abstract: A semiconductor device includes a N-type field effect transistor comprising a N-channel region in a substrate. A high dielectric constant (high-k) layer is disposed on the N-channel region. A diffusion layer including a metal oxide is disposed on the high-k layer. A passivation layer is disposed on the diffusion layer, and a first metal gate is disposed on the passivation layer. The first high-k layer and the N-channel region include metal atoms of a metal element of the metal oxide.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ju-Youn Kim
  • Patent number: 8969182
    Abstract: A semiconductor device using an oxide semiconductor is provided with stable electric characteristics to improve the reliability. In a manufacturing process of a transistor including an oxide semiconductor film, an oxide semiconductor film containing a crystal having a c-axis which is substantially perpendicular to a top surface thereof (also called a first crystalline oxide semiconductor film) is formed; oxygen is added to the oxide semiconductor film to amorphize at least part of the oxide semiconductor film, so that an amorphous oxide semiconductor film containing an excess of oxygen is formed; an aluminum oxide film is formed over the amorphous oxide semiconductor film; and heat treatment is performed thereon to crystallize at least part of the amorphous oxide semiconductor film, so that an oxide semiconductor film containing a crystal having a c-axis which is substantially perpendicular to a top surface thereof (also called a second crystalline oxide semiconductor film) is formed.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: March 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Naoto Yamade, Yuhei Sato, Yutaka Okazaki, Shunpei Yamazaki
  • Patent number: 8963124
    Abstract: At least first and second Si1-xGex (0?x?1) layers are formed on an insulating film. At least first and second material layers are formed correspondingly to the at least first and second Si1-xGex (0?x?1) layers. A lattice constant of the first Si1-xGex (0?x?1) layer is matched with a lattice constant of the first material layer. A lattice constant of the second Si1-xGex (0?x?1) layer is matched with a lattice constant of the second material layer.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: February 24, 2015
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Masanobu Miyao, Hiroshi Nakashima, Taizoh Sadoh, Ichiro Mizushima, Masaki Yoshimaru
  • Patent number: 8952876
    Abstract: A display substrate includes a base substrate, a first insulating layer formed on a base substrate, a pixel including a pixel electrode having the first insulating layer, and a circuit including a circuit transistor disposed on a peripheral area to drive the pixel. The pixel includes a first channel formed on the base substrate having the first insulating layer formed thereon. The first channel includes a poly-silicon layer, a first source electrode and a first drain electrode formed on the first channel that are spaced apart from each other, and a first gate electrode formed on the first source electrode and the first drain electrode corresponding to the first channel which is formed of the transparent conductive material. The poly-silicon layer is formed at a front channel portion of the first channel proximal to the first gate electrode through the first gate electrode.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: February 10, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyung-Jun Kim, Sung-Haeng Cho, Yong-Mo Choi
  • Patent number: 8933456
    Abstract: A germanium-containing layer is deposited on a single crystalline bulk silicon substrate in an ambient including a level of oxygen partial pressure sufficient to incorporate 1%-50% of oxygen in atomic concentration. The thickness of the germanium-containing layer is preferably limited to maintain some degree of epitaxial alignment with the underlying silicon substrate. Optionally, a graded germanium-containing layer can be grown on, or replace, the germanium-containing layer. An at least partially crystalline silicon layer is subsequently deposited on the germanium-containing layer. A handle substrate is bonded to the at least partially crystalline silicon layer. The assembly of the bulk silicon substrate, the germanium-containing layer, the at least partially crystalline silicon layer, and the handle substrate is cleaved within the germanium-containing layer to provide a composite substrate including the handle substrate and the at least partially crystalline silicon layer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Daniel A. Inns, Jeehwan Kim, Devendra K. Sadana, Katherine L. Saenger
  • Patent number: 8912545
    Abstract: A method is provided for fabricating a nanowire-based semiconductor structure. The method includes forming a first nanowire with a first polygon-shaped cross-section having a first number of sides. The method also includes forming a semiconductor layer on surface of the first nanowire to form a second nanowire with a second polygon-shaped cross-section having a second number of sides, the second number being greater than the first number. Further, the method includes annealing the second nanowire to remove a substantial number of vertexes of the second polygon-shaped cross-section to form the nanowire with a non-polygon-shaped cross-section corresponding to the second polygon-shaped cross-section.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 16, 2014
    Assignee: Semiconductor Manufacturing International Corp.
    Inventors: Deyuan Xiao, James Hong
  • Patent number: 8906769
    Abstract: An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film. Then, the sidewall spacers over the side surfaces of the insulating films corresponding to the sidewalls of the first and second gate electrodes are removed to leave the sidewall spacers over the side surfaces of the insulating film corresponding to the sidewalls of the third gate electrode. Then, the sidewall spacers and the insulating films are etched back, so that the sidewall spacers are formed of the insulating film over the sidewalls of the first, second, and third gate electrodes.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: December 9, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Koji Maekawa, Tatsuyoshi Mihara
  • Patent number: 8907346
    Abstract: An imprint apparatus according to embodiments includes a stage, a dropping unit that drops resist, an imprinting unit that presses a circuit pattern of a template against the resist on a transfer target substrate, an underlying position detecting unit, a correcting unit, and a dropping position control unit. The underlying position detecting unit detects a position of an underlying pattern on the transfer target substrate. The correcting unit corrects a dropping position of the resist on a basis of a position of the underlying pattern. The dropping position control unit causes the resist to be dropped onto a dropping position after correction on the transfer target substrate on the basis of corrected dropping position.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: December 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Koshiba, Nobuhiro Komine
  • Patent number: 8884295
    Abstract: A thin film transistor (TFT) having an active layer pattern, the active layer pattern including a first active layer pattern extending in a first direction; a second active layer pattern extending in the first direction and parallel to the first active layer pattern; and a third active layer pattern connecting a first end of the first active layer pattern to a first end of the second active layer pattern.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: November 11, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byoung-Kwon Choo, Hyun-Been Hwang, Kwon-Hyung Lee, Cheol-Ho Park
  • Patent number: 8859381
    Abstract: A field-effect transistor (FET) and methods for fabricating such. The FET includes a substrate having a crystalline orientation, a source region in the substrate, and a drain region in the substrate. Gate spacers are positioned over the source region and the drain region. The gate spacers include a gate spacer height. A source contact physically and electrically contacts the source region and extends beyond the gate spacer height. A drain contact physically and electrically contacts the drain region and extends beyond the gate spacer height. The source and drain contacts have the same crystalline orientation as the substrate.
    Type: Grant
    Filed: June 29, 2013
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Wilfried E. Haensch, Effendi Leobandung, Min Yang
  • Patent number: 8860168
    Abstract: An integrated circuit structure includes a substrate, a semiconductor device supported by the substrate, and a guard ring structure disposed around the semiconductor device, the guard ring structure forming a Schottky junction. In an embodiment, the Schottky junction is formed from a p-type metal contact and an n-type guard ring. In an embodiment, the guard ring structure is electrically coupled to a positive or negative supply voltage.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: October 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Feng Chang, Jam-Wem Lee
  • Publication number: 20140252362
    Abstract: A thin film apparatus having a plurality of thin film cells is disclosed. Each thin film cell includes a crystalline layer and a surrounding layer. The crystalline layer has a shape of polygon. The surrounding layer is partially located on the crystalline layer. The crystalline layer is surrounded by the surrounding layer.
    Type: Application
    Filed: March 7, 2014
    Publication date: September 11, 2014
    Applicant: SenseTech Co., Ltd
    Inventors: Po-Wei LU, Mao-Chen LIU, Wen-Chieh CHOU, Chun-Chieh WANG, Shu-Yi WENG
  • Patent number: 8816430
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a gate electrode, source/drain regions, and a gate insulating film. The substrate is made of monocrystalline silicon, an upper surface of the substrate is a (100) plane, and a trench is made in the upper surface. The gate electrode is provided in at least an interior of the trench. The source/drain regions are formed in regions of the substrate having the trench interposed. The gate insulating film is provided between the substrate and the gate electrode. The trench includes a bottom surface made of a (100) plane, a pair of oblique surfaces made of (111) planes contacting the bottom surface, and a pair of side surfaces made of (110) planes contacting the oblique surfaces. The source/drain regions are in contact with the side and oblique surfaces and are apart from a central portion of the bottom surface.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Yanagisawa
  • Patent number: 8795440
    Abstract: A method of growing non-polar m-plane III-nitride film, such as GaN, AlN, AlGaN or InGaN, wherein the non-polar m-plane III-nitride film is grown on a suitable substrate, such as an m-SiC, m-GaN, LiGaO2 or LiAlO2 substrate, using metalorganic chemical vapor deposition (MOCVD). The method includes performing a solvent clean and acid dip of the substrate to remove oxide from the surface, annealing the substrate, growing a nucleation layer, such as aluminum nitride (AlN), on the annealed substrate, and growing the non-polar m-plane III-nitride film on the nucleation layer using MOCVD.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: August 5, 2014
    Assignees: The Regents of the University of California, Japan Science and Technology Agency
    Inventors: Bilge M. Imer, James S. Speck, Steven P. DenBaars, Shuji Nakamura
  • Patent number: 8796122
    Abstract: A method of fabricating a display device is provided. The method includes providing a substrate having a pixel region and a circuit region located at the periphery of the pixel region. A first semiconductor layer and a second semiconductor layer are formed on the pixel region and on the circuit region, respectively. The first semiconductor layer may be selectively surface treated to increase the density of lattice defects in a surface of the first semiconductor layer.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: August 5, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Eui-Hoon Hwang, Deuk-Jong Kim
  • Patent number: 8796681
    Abstract: A semiconductor device which is miniaturized and has sufficient electrical characteristics to function as a transistor is provided. In a semiconductor device including a transistor in which a semiconductor layer, a gate insulating layer, and a gate electrode layer are stacked in that order, an oxide semiconductor film which contains at least four kinds of elements of indium, gallium, zinc, and oxygen, and in which the percentage of the indium is twice or more as large as each of the percentage of the gallium and the percentage of the zinc when the composition of the four elements is expressed in atomic percentage is used as the semiconductor layer. In the semiconductor device, the oxide semiconductor film is a film to which oxygen is introduced in the manufacturing process and contains a large amount of oxygen, and an insulating layer including an aluminum oxide film is provided to cover the transistor.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: August 5, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Naoto Yamade, Junichi Koezuka
  • Patent number: 8796730
    Abstract: Disclosed herein is a power semiconductor module including: a circuit board having gate, emitter, and collector patterns formed thereon; a first semiconductor chip mounted on the circuit board, having gate and emitter terminals each formed on one surface thereof, and having a collector terminal formed on the other surface thereof; a second semiconductor chip mounted on the first semiconductor chip, having a cathode terminal formed on one surface thereof, and having an anode terminal formed on the other surface thereof; a first conductive connection member having one end disposed between the collector terminal of the first semiconductor chip and the cathode terminal of the second semiconductor chip and the other end contacting the collector pattern of the circuit board; and a second conductive connection member having one end contacting the anode terminal of the second semiconductor chip and the other end contacting the emitter pattern of the circuit board.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: August 5, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young Ki Lee, Dong Soo Seo, Kwang Soo Kim, Young Hoon Kwak
  • Patent number: 8796687
    Abstract: A method of treating a sheet of semiconducting material comprises forming a sinterable first layer over each major surface of a sheet of semiconducting material, forming a second layer over each of the first layers to form a particle-coated semiconductor sheet, placing the particle-coated sheet between end members, heating the particle-coated sheet to a temperature effective to at least partially sinter the first layer and at least partially melt the semiconducting material, and cooling the particle-coated sheet to solidify the semiconducting material and form a treated sheet of semiconducting material.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: August 5, 2014
    Assignee: Corning Incorporated
    Inventors: Glen Bennett Cook, Prantik Mazumder, Mallanagouda Dyamanagouda Patil, Lili Tian, Natesan Venkataraman
  • Patent number: 8795854
    Abstract: Novel articles and methods to fabricate the same resulting in flexible, oriented, semiconductor-based, electronic devices on {110}<100> textured substrates are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: August 5, 2014
    Inventor: Amit Goyal
  • Patent number: 8778719
    Abstract: The linear semiconductor substrate 1 or 2 of the present invention comprises at least one desired thin film 4 formed on a linear substrate 3 having a length ten or more times greater than a width, thickness, or diameter of the linear substrate itself. Adopting semiconductor as the thin film 4 forms a linear semiconductor thin film. The linear semiconductor substrate 1 or 2 of the present invention is produced by utilizing a fiber-drawing technique which is a fabricating technique of optical fibers.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: July 15, 2014
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Toshihiro Nakamura, Nobuaki Orita, Hisashi Koaizawa, Kenkichi Suzuki, Hiroshi Kuraseko, Michio Kondo
  • Patent number: 8766273
    Abstract: It is possible to manufacture a large-size, high-accuracy organic EL display using a plastic substrate and an organic EL display using a roll-shaped long plastic substrate. The organic EL display includes an organic EL device A having at least a lower electrode 300, an organic layer including at least a light emitting layer, and an upper electrode 305 and a thin film transistor B on a transparent plastic substrate 100, a source electrode or drain electrode of the thin film transistor B is connected to the lower electrode 300, the plastic substrate 100 has a gas barrier layer 101a, the thin film transistor B is formed on the gas barrier layer 101a, the thin film transistor B includes an active layer 203 containing a non-metallic element which a mixture of oxygen (O) and nitrogen (N) and has a ratio of N to O (N number density/O number density) from 0 to 2, and the organic EL device A is formed at least on the gas barrier layer 101a or one the thin film transistor B.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: July 1, 2014
    Assignees: Sumitomo Chemical Company, Limited, Sumitomo Bakelite Co., Ltd.
    Inventors: Shigeyoshi Otsuki, Toshimasa Eguchi, Shinya Yamaguchi, Mamoru Okamoto
  • Patent number: 8754418
    Abstract: Disclosed is a semiconductor device 100A that has first lightly doped drain regions 31A1 and 32A1 between a source region 34A1 and a channel region 33A1 of a first conductive-type driver circuit TFT 10A1 and/or between a drain region 35A1 and the channel region 33A1 of the first conductive-type driver circuit TFT 10A1, and second lightly doped drain regions 31C and 32C between a source region 34C and a channel region 33C of a first conductive-type pixel TFT 10C and/or between a drain region 35C and the channel region 33C of the first conductive-type pixel TFT 10C, in which the first lightly doped drain regions 31A1 and 32A1 have first conductive-type impurities n1 at a first impurity concentration C1, and the second lightly doped drain regions 31C and 32C have first conductive-type impurities n1 at the first impurity concentration C1 and second conductive-type impurities p2 at a second impurity concentration C2.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: June 17, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kazushige Hotta
  • Publication number: 20140151706
    Abstract: Silicon nanoparticle inks provide a basis for the formation of desirable materials. Specifically, composites have been formed in thin layers comprising silicon nanoparticles embedded in an amorphous silicon matrix, which can be formed at relatively low temperatures. The composite material can be heated to form a nanocrystalline material having crystals that are non-rod shaped. The nanocrystalline material can have desirable electrical conductive properties, and the materials can be formed with a high dopant level. Also, nanocrystalline silicon pellets can be formed from silicon nanoparticles deposited form an ink in which the pellets can be relatively dense although less dense than bulk silicon. The pellets can be formed from the application of pressure and heat to a silicon nanoparticle layer.
    Type: Application
    Filed: February 7, 2014
    Publication date: June 5, 2014
    Applicant: NanoGram Corporation
    Inventors: Guojun Liu, Shivkumar Chiruvolu, Weidong Li, Uma Srinivasan
  • Publication number: 20140151705
    Abstract: A method is provided for fabricating a nanowire-based semiconductor structure. The method includes forming a first nanowire with a first polygon-shaped cross-section having a first number of sides. The method also includes forming a semiconductor layer on surface of the first nanowire to form a second nanowire with a second polygon-shaped cross-section having a second number of sides, the second number being greater than the first number. Further, the method includes annealing the second nanowire to remove a substantial number of vertexes of the second polygon-shaped cross-section to form the nanowire with a non-polygon-shaped cross-section corresponding to the second polygon-shaped cross-section.
    Type: Application
    Filed: March 15, 2013
    Publication date: June 5, 2014
    Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP.
    Inventors: DEYUAN XIAO, JAMES HONG
  • Patent number: 8736952
    Abstract: A photonic crystal device comprising: a photonic crystal material having an initial ordered structure and a viewing surface, the initial ordered structure giving rise to a first optical effect detectable from the viewing surface; and a removal layer removably attached with the viewing surface or an opposing surface of the photonic crystal material opposite to the viewing surface; wherein mechanical removal of at least a portion of the removal layer results in a structural change in at least a portion of the initial ordered structure of at least a portion of the photonic crystal material respective to the portion of the removed removal layer, thereby resulting in a changed portion different from the initial ordered structure, the changed portion giving rise to a second optical effect detectable from the viewing surface and detectably different from the first optical effect.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: May 27, 2014
    Assignee: Opalux Incorporated
    Inventor: Andre Arsenault
  • Patent number: 8730419
    Abstract: To provide a display device which has a narrower frame region and which includes a driver circuit not affected by variation in transistor characteristics. A base substrate having an insulating surface to which a single-crystal semiconductor layer is attached is divided into strips and is used for a driver circuit of a display device. Alternatively, a base substrate having an insulating surface to which a plurality of single-crystal semiconductor layers is attached is divided into strips and is used for a driver circuit of a display device. Accordingly, a driver circuit corresponding to a size of a display device can be used for the display device, and a display device which has a narrower frame region and which includes a driver circuit not affected by variation in transistor characteristics can be provided.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: May 20, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Publication number: 20140117366
    Abstract: According to an embodiment, a semiconductor device includes an underlying layer and a plurality of transistors. The underlying layer includes a first region and a second region provided adjacently to the first region. The transistors are arranged in a plane parallel to an upper surface of the underlying layer. Each transistor includes a channel allowing a current to flow in a first direction intersecting the plane. The plurality of transistors includes a first transistor provided on the first region and a second transistor provided on the second region, a first channel of the first transistor having a first crystal orientation, and a second channel of the second transistor having a second crystal orientation different from the first crystal orientation.
    Type: Application
    Filed: September 13, 2013
    Publication date: May 1, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Masumi SAITOH