Abstract: A semiconductor device includes first and second antenna connection electrodes placed on the periphery of a semiconductor chip, an on-chip antenna connection electrode placed in the inner area of the semiconductor chip compared to the first and second antenna connection electrodes, and an internal circuit formed in the semiconductor chip. The first and second antenna connection electrodes are connected to the internal circuit by internal lines. The on-chip antenna connection electrode is connected to the internal circuit and the second antenna connection electrode by internal lines. An on-chip antenna is connected to the second antenna connection electrode and the on-chip antenna connection electrode. An external antenna is connected to the first and second antenna connection electrodes.

Abstract: A semiconductor device has a mounting substrate and a semiconductor package mounted on the mounting substrate. The mounting substrate has a substrate body, input/output line conductors on the upper surface of the substrate body, a front-face grounding conductor on the upper surface of the substrate body, spaced from the input/output line conductors, and a lower surface grounding conductor formed on the lower surface of the substrate body and electrically connected to the front-face grounding conductor. The semiconductor package has input/output terminals electrically connected to end portions of the input/output line conductors, a grounding terminal electrically connected to the front-face grounding conductor, and a semiconductor element die-bonded on the grounding terminal and electrically connected to the input/output terminals.

Abstract: A direct-connect signaling system including a printed circuit board and first and second integrated circuit packages disposed on the printed circuit board. A plurality of electric signal conductors extend between the first and second integrated circuit packages suspended above the printed circuit board.

Abstract: A packaged device is obtained using an innovative package approach that allows integration of miniature planar magnetics into standard low-cost semiconductor packages (BGA, PDIP, SOIC, etc.) with electronic and electrical components, where those components can be C&W and/or SMD types. The packaged device includes a planar magnetic substrate having first and second dielectric layers, the first dielectric layer having a first winding defined thereon, the second dielectric layer having a second winding defined thereon. A magnetic component is provided in the substrate. A package material provided at least partly around the substrate and the magnetic component to protect the substrate and magnetic component. The magnetic component is an inductor or transformer. The packaged device further includes at least one semiconductor component provided on the first dielectric layer.

Abstract: At least one semiconductor die is equipped with at least one RF transmitter, RF receiver and/or RF transceiver. This enables one or more RF links to be established with the die, enabling communications with the die to be effected with reduced or no wirebond or other physical connections. In another aspect of the invention, a source die with RF communication capability communicates with a target die by establishing an RF link with an intermediate RF device. The intermediate RF device has a physical connection, either directly to the target die, or to the substrate which they share, which allows the source die to communicate with the target die. The source and target dies may be on the same or on different substrates. This enables the use of multiple semiconductor dies and substrates in a manner which reduces the required physical connections between them.

Abstract: A semiconductor device package comprises a first semiconductor die having a first source region, a first gate region, and a first drain region attached on a first leadframe, a second semiconductor die having a second source region, a second gate region, and a second drain region attached on a second leadframe, and several pins electrically connected to the leadframes and source and gate regions. The second leadframe is electrically connected to the first source region. The pins connected to the first leadframe and second source region are on a side of the package, and the pins connected to the first gate region, second leadframe, and second gate region are on another side of the package.

Abstract: A bottom unit including a bottom unit semiconductor chip is mounted to a circuit board and one or more top elements such as packaged semiconductor chips are mounted to the bottom unit. Both mounting operations can be performed using the same techniques as commonly employed for mounting components to a circuit board. Ordinary packaged chips can be employed as the top elements, thereby reducing the cost of the assembly and allowing customization of the assembly by selecting packaged chips. The assembly achieves benefits similar to those obtained with a preassembled stacked chip unit, but without the expense of special handling of the bare dies included in the packaged chips.

Abstract: A packaged integrated circuit includes an integrated circuit and a package substrate. A trace in the package substrate includes a first portion and a second, high-inductance, portion. The high-inductance portion of the trace is proximate to a port of the integrated circuit and provides a selected inductance operating in cooperation with the capacitance of the port to reduce return loss from the port.

Abstract: The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.

Abstract: A package substrate includes signal pads provided on a main surface of the package substrate, footpads provided on a backside of the package substrate, and a sealing electrode provided on the main surface to surround the signal pads, the signal pads being electrically coupled to the footpads, the sealing electrode being insulated from the footpads.

Abstract: A high frequency module and a manufacturing method thereof In the module, a substrate has a ground. A plurality of surface mounted devices are mounted on the substrate. A metal wall is connected to the ground of the substrate. A resin molding hermetically seals the surface mounted devices and the metal wall, the resin molding formed to expose a top surface of the metal wall. Also, a metal film is formed on the resin molding to contact the top surface of the exposed metal wall.

Abstract: An RF power transistor with a metal design (70) comprises a drain pad (72) and a plurality of metal drain fingers (74) extending from the drain pad, wherein at least one metal drain finger comprises one or more sections of metal (74-1, 74-2, 100-1, 100-2, 100-3), each section of metal including of one or more branch (54-1, 54-2, 116-1, 116-2, 116-11, 116-21, 116-41) of metal having a metal width maintained within a bamboo regime.

Abstract: A semiconductor chip packaging structure comprising a dielectric film having one or more through holes aligned with the one or more contact pads of at least one power semiconductor chip. A patterned electrically conductive layer adjacent to the dielectric film has one or more electrically conductive posts which extend through the one or more though holes aligned with the contact pads to electrically couple the conductive layer to the contact pads. In certain embodiments, one or more air gaps may be formed between the dielectric film and the active surface of the at least one power semiconductor chip. Methods for fabricating the semiconductor chip packaging structure are also disclosed.

Abstract: An assembly includes a substrate, a device coupled to the substrate; a ring formed on the substrate; and one or more bonding pads formed on the substrate, wherein the ring and bonding pads are formed of a same material.

Abstract: A tunable element in the microwave frequency range is described that may include one or more tunable elements that are directly digitally controlled by a digital bus connecting a digital control circuit to each controlled element. In particular, each digital signal is filtered by a digital isolation technique so that the signal reaches the tunable elements with very low noise. The low noise digital signals are then converted to analog control voltages. The direct D/A conversion is accomplished by a special D/A converter which is manufactured as an integral part of a substrate. This D/A converter in accordance with the invention may consist of a resistor ladder or a directly digitally controlled capacitor. The direct digitally controlled capacitor may be a cantilevered type capacitor having multiple separate electrodes or sub-plates representing binary bits that may be used to control the capacitor.

Abstract: Aspects of the invention recite wire bonding on thinned portions of a lead-frame that is configured for use in an IC package. A harder lead-frame material, improved adhesive tape, and various structural features of the lead-frame itself, in various combinations or subcombinations, facilitate the attachment of wire bonds to thinned areas of the lead-frame. This eliminates the need for supports placed directly under the bond sites, removing unwanted conductive areas on the outer surface of an IC package.

Abstract: An apparatus includes a circuit having first, second and third circuit portions, the first and third circuit portions each including at least one semiconductor circuit component. The second circuit portion includes at least one non-semiconductor circuit component, and is free of semiconductor circuit components. A first substrate has the first and second circuit portions disposed adjacent one side thereof. A second substrate is physically separate from the first substrate, and has the third circuit portion disposed adjacent a side thereof which faces the one side of the first substrate. The second and third circuit portions have electrically conductive parts which are coupled by thermo-formed bonds.

Abstract: A switch device includes a semiconductor chip, and at least two switches formed on the semiconductor chip. Ground parts of the at least two switches are arranged between said at least two switches.

Abstract: A chip package having a lead frame, a chip, a plurality of bonding wires, and an insulation material is provided. The lead frame comprises a die pad, a plurality of leads, a plurality of signal pads and a plurality of non-signal pads. The signal pads and non-signal pads are underneath the signal leads and non-signal leads respectively. The non-signal pad is directly connected to a non-signal plane in the circuit board through its own vias. The signal pad has a structure which extends toward its adjacent non-signal pads. With the signal pad size enlarged, the capacitance between the non-signal plane in the circuit board and the signal pad is increased. The increased capacitance compensates the inductance induced from the bonding wires and improves the response of the signal propagation path for RF applications.

Abstract: By securing a fatigue life of a connection portion with a semiconductor package and a mount board, a semiconductor device having a high reliability is provided. The semiconductor device consists of a semiconductor element, a mount board in which said semiconductor element is mounted, and a support member in which said mount board is supported through a connection member, wherein the connection member consists of a first mount board connection portion with the mount board at a first side of the element in a direction along a main surface of the mount board in which the semiconductor element is mounted, and consists of a first support member connection portion with the support member at a second side in opposition to the first side through the semiconductor element.

Abstract: The present invention provides a high frequency module having a base substrate unit (2) which has its uppermost layer planarized to form a buildup-forming surface (16), a high frequency circuit unit (3) having multiple wiring layers which are formed on the base substrate unit (2), each of which layers has a wiring pattern and film elements formed on a dielectric insulating layer thereof, whose uppermost wiring layer (17) has plural lands (22) and ground patterns (20) formed thereon together with the wiring pattern and inductor elements (19), and a semiconductor chip (4) mounted on the wiring layer (17) of the high frequency circuit unit (3). Transmission lines (24) to connect the inductor elements (19) and lands (22) which are formed on the wiring layer (17) are directed within hollowed pattern regions (20c) formed at the ground pattern (20) to constitute coplanar type transmission lines.

Abstract: A semiconductor device includes a semiconductor chip, electrodes pads, an insulating layer, first and second conductive patterns and external terminals. The electrode pads are formed on a first area of a main surface of the semiconductor chip. The insulating layer is formed on a second area of the semiconductor chip so as to expose the electrode pads. The first conductive pattern provides a ground potential and is formed on the insulating layer. The second conductive pattern transfers a signal. The second conductive pattern is formed on the insulating layer and located to partially surround the first conductive pattern. The external terminals are formed on the first and second patterns at the second area.

Abstract: In an electronic circuit device including a substrate including a front surface on which an electronic circuit element is mounted and a reverse surface opposite to the front surface in a thickness direction of the substrate, an electrically conductive terminal member electrically connected to the electronic circuit element, a lead frame extending perpendicular to the thickness direction to face the reverse surface in the thickness direction, and a sealing resin covering at least partially the electronic circuit element, substrate and lead frame while at least a part of the electrically conductive terminal member is prevented from being covered by the sealing resin, the substrate extends to project outward from an end of the lead frame in a transverse direction perpendicular to the thickness direction while the end of the lead frame is covered by the sealing resin.

Abstract: A semiconductor device having an active region is formed in a layer provided on a semiconductor substrate. At least a portion of the semiconductor substrate below at least a portion of the active region is removed such that the portion of the active region is provided in a membrane defined by that portion of the layer below which the semiconductor substrate has been removed. A heat conducting and electrically insulating layer is applied to the bottom surface of the membrane. The heat conducting and electrically insulating layer has a thermal conductivity that is higher than the thermal conductivity of the membrane so that the heat conducting and electrically insulating layer allows heat to pass from the active region into the heat conducting and electrically insulating layer during normal operation of the device.

Abstract: A three-dimensional stacked semiconductor package includes first and second chips, first and second adhesives, first and second wire bonds, a lead and an encapsulant. The chips are disposed on opposite sides of the lead, and the wire bonds contact the same side of the lead.

Abstract: A semiconductor package that includes two power semiconductor dies, such as power MOSFET dies, including vertical conduction MOSFETs, arranged in a half-bridge configuration is disclosed. The package may be mounted on a split conductive pad including two isolated die pads, each die pad being electrically connected to the second power electrode of the die that is on it. The split pad may include several conductive leads, including at least one output lead electrically connected to a first electrode of the first semiconductor die on the same side of the die as the control electrode and to the second electrode of the second die located on the opposite side of the second die from the control electrode.

Abstract: A semiconductor device (10) includes a semiconductor die (20) and an inductor (30, 50) formed with a bonding wire (80) attached to a top surface (21) of the semiconductor die. The bonding wire is extended laterally a distance (L30, L150) greater than its height (H30, H50) to define an insulating core (31, 57). In one embodiment, the inductor is extended beyond an edge (35, 39) of the semiconductor die to reduce loading.

Abstract: A semiconductor device is formed by laminating two semiconductor chips with the rear surfaces thereof provided face to face. Each semiconductor chip is provided with an outer lead for clock enable to which the clock enable signal and chip select signal are individually input. On the occasion of making access to one semiconductor chip, the other semiconductor chip is set to the low power consumption mode by setting the clock enable signal and chip select signal to the non-active condition.

Abstract: A bump-less chip package is provided. The bump-less chip package includes a chip, an interconnection structure and a panel-shaped component. The panel-shaped component has a plurality of electrical terminals on a first surface thereof. The back surface of the chip is disposed on the first surface of the panel-shaped component, and the chip has a plurality of first pads on the active surface thereof away from the panel-shaped component. The interconnection structure is disposed on the first surface of the panel-shaped component and the active surface of the chip. The first pads of the chip may electrically connect with the electrical terminals of the panel-shaped component through the interconnection structure. Furthermore, the interconnection structure has a plurality of second pads on the surface away from the chip.

Abstract: A semiconductor device which integrates a plurality of semiconductor chips into a single package includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a plurality of first bonding pads outputting first signals having a first level. The second semiconductor chip includes a plurality of second bonding pads and a plurality of third bonding pads. The plurality of second bonding pads is electrically coupled to a part of the plurality of first bonding pads to receive the first signals having the first level from the first semiconductor chip through the part of the plurality of first bonding pads. The plurality of third bonding pads converts the first signals received through the plurality of second bonding pad into second signals having a second level different from the first level and outputs the second signals through the plurality of third bonding pads.

Abstract: An exemplary system and method for providing differential adjustment of the height of a multilayer substrate in localized areas for improved Q-factor performance of RF devices is disclosed as comprising inter alia: a multilayer substrate (200); an RF component (210) embedded in the substrate (200); a surface mounted component (220); and an RF shield (260) disposed next to the surface mounted component (220), wherein the height of the shield (260) does not extend substantially beyond the height of the surface mounted component (220). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize Q, RF performance and/or material characteristics.

Abstract: A connection arrangement for a micro lead frame plastic (MLP) package is provided that includes a paddle configured to be connected to a circuit board and a first ground pad and a second ground pad each connected to the paddle. The first and second ground pads together with the paddle are configured to provide continuity of ground between the circuit board and a chip mounted to the paddle.

Abstract: The cost of a semiconductor device is to be reduced. An electrical connection between a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip is made through an inner lead portion of a lead disposed at a position around the first semiconductor chip and two bonding wires.

Abstract: A semiconductor processing system utilizing transport speed monitoring of a wafer boat. The semiconductor processing comprises a process chamber, loading device, and transport speed monitoring device. The loading device transports a boat of wafers into and out of the process chamber where the wafers experience particular treatment. The transport speed monitoring device is responsible for detecting the movement of the wafer boat and asserting an abnormality signal when the transport speed of the wafer boat falls beyond a limit.

Abstract: A high frequency integrated circuit includes a die, a package and capacitive bond. The die includes a circuit that processes a high frequency signal and also includes at least one bonding pad coupled to the circuit. The package includes a plurality of bonding posts, at least one of the bonding posts is allocated to the at least one bond pad of the die. A bonding capacitor couples the at least one bond pad on the die to the at least one bond post of the package.

Abstract: A modular power semiconductor module for mounting on a heat sink comprises a plurality of partial modules, each having a base plate and a framelike housing as well as terminal elements for load terminals and auxiliary terminals. Adjacent partial modules are assembled into a complete power semiconductor module by means of a cap that fixes the partial modules relative to one another and/or by means of connections that fix the various partial modules relative to one another.

Abstract: A high-frequency wiring structure includes a microstrip line having a ground conductor, a dielectric disposed on the ground conductor, and a transmission conductor that is at least partially disposed in the dielectric. The transmission conductor is defined by a flat bottom parallel to the ground conductor, a pair of flat sides that are perpendicular to the ground conductor and are positioned on both sides of the flat bottom in the wiring width direction, and curved parts that continuously join the flat bottom and the pair of flat sides. The curved parts have a radius of curvature within the range of 5% to 50% of the thickness of the transmission conductor.

Abstract: A bottom die and a top die stacked on the bottom die are configured to provide a daisy chain function. Both die include an input/output function control bonding pad (20G), a first bonding pad (20C) controllable to function as either an input or an output, and a second bonding pad (20E) controllable to function as either an output or an electrically floating pad in response to a corresponding input/output function control signal. The top die (30) is stacked on the bottom die (20) and the first bonding pad (20C) of the bottom die (20) is wire bonded to the first bonding pad (30C) of the top die (30). A first reference voltage (VDD) on the function control bonding pad of the bottom die configures its first bonding pad as an output and its second bonding pad as electrically floating, and a second reference voltage (VSS) on the function control bonding pad of the top die configures its first bonding pad as an input and its second bonding pad as an output, to thereby provide the daisy chain function.

Abstract: An apparatus and method to provide a micro-electromechanical systems (MEMS) radio frequency (RF) switch module with a vertical via. The MEMS RF switch module includes a MEMS die coupled to a cap section. The vertical via passes through the cap section to electrically couple an RF switch array of the MEMS die to a printed circuit board (PCB). In one embodiment, the MEMS die includes a trace ring surrounding at least a portion of the RF switch array so that a signal may enter or exit the MEMS RF switch module using the vertical via without crossing the trace ring.

Abstract: An integrated circuit ground system includes an integrated circuit (IC) ground connection, first and second IC package pins, first and second printed circuit board (PCB) pads, a PCB ground connection, and a resonant circuit. The IC ground connection is fabricated on a substrate of an integrated circuit. The first IC package pin is operably coupled to the IC ground connection via a first bond wire. The second IC package pin is operably coupled to the IC ground connection via a second bond wire. The second PCB pad is operably coupled to the second IC package pin to provide a low impedance DC ground connection for the integrated circuit to the printed circuit board. The resonant circuit is operably coupling the first IC package pin to the first PCB pad, wherein the resonant circuit is tuned to resonant with the first bond wire at high frequency range to provide a low impedance AC ground connection for the integrated circuit to the printed circuit board within the high frequency range.

Abstract: Techniques that enable the transitioning of high frequency signals on a printed wiring board processed in accordance with industry standards (such as the IPC specifications) are disclosed. One embodiment provides a high frequency via structure for a printed wiring board, where the via structure includes a via pad configured in accordance with IPC standards. A printed microwave transmission line having an inductive section is connected to the via pad, wherein the inductive section has dimensions to compensate for transition discontinuity.

Abstract: Power transistor devices and techniques for reducing bowing in such devices are provided. In one aspect, a power transistor device is provided. The power transistor device comprises a substrate, a device film formed on the substrate and an adhesion layer formed on a side of the substrate opposite the device film, wherein at least a portion of the adhesion layer is at least partially segmented. The power transistor device thereby exhibits a reduced amount of bowing relative to an amount of bowing expected without the segmenting of the adhesion layer. The power transistor device may be part of an integrated circuit.

Abstract: A multi-layer board includes a ceramic layer and plural resin layers which are stacked together. The ceramic layer is provided with an impedance element formed thereon, and the uppermost resin layer is provided with an electronic component mounted thereon. The multi-layer board is stable against a temperature change.

Abstract: The present invention relates to a microwave device for at least one of dissipating and attenuating power, the device comprising: an insulating substrate; at least one conductive strip of a microwave transmission line on a face of the substrate; at least one ground zone; and at least one resistive layer placed on said face of the substrate, the resistive layer having at least a first region to which the conductive strip(s) is connected and a second region connected to the ground zone, the resistive layer presenting a longitudinal axis; in which device: the resistive layer is covered at least in part by a ground plane connected to the ground zone and insulated from the resistive layer by an insulating layer; wherein said ground plane comprises a conductive material silkscreen printed on the insulating layer.

Abstract: A semiconductor device includes a semiconductor substrate having a main surface, the main surface including a first area formed with a high-frequency circuit element and a second area located around the first area and formed with a low-frequency circuit element. The semiconductor device also includes a sealing resin which covers the main surface; a plurality of first external terminals which are formed above the second area and which are electrically connected to the high-frequency circuit element, the first external terminals protruding from the surface of the sealing resin. The semiconductor device further includes a plurality of second external terminals which are formed above the second area and which are electrically connected to the low-frequency circuit element, the second external terminals protruding from the surface of the sealing resin.

Abstract: An insulating sheet consisting of a metal layer and an unhardened insulating resin layer is formed. The insulating resin layer contains a filler having grains of, e.g., scale-like shape and has thixotropy, and its outer size is larger than that of a bottom surface of a metal plate. The insulating sheet is disposed on a bottom surface of a cavity of a mold die and the metal plate is disposed on an upper surface of the insulating resin layer. On a main surface of the metal plate, a power semiconductor chip connected to a frame and another frame through a wire is mounted. The cavity is fully filled with a liquid mold resin in this state. After that, the insulating resin layer is hardened at the same timing as the hardening of the mold resin, and the insulating resin and the metal plate are fixed to each other. An interface between the insulating resin layer and the metal plate is included in the upper surface of the insulating resin layer.

Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.

Abstract: An electronic component arrangement includes a discrete electronic component having first and second terminals and a centre-exposed pad. A substrate has a first electrical conductor electrically connected to the first terminal, a second electrical conductor electrically connected to the second terminal, and a third electrical conductor. A thermally conductive element is in direct thermal communication with both the centre-exposed pad of the electronic component and the third electrical conductor of the substrate.

Abstract: The present invention provides a semiconductor device comprising a semiconductor substrate, and transistors formed on the semiconductor substrate, wherein control electrode terminals constituting external electrode terminals of the transistors, and first electrode terminals which transmit output signals, are provided on a main surface of the semiconductor substrate, wherein the control electrode terminals are provided at least one, and a plurality of the first electrode terminals are arranged on one side and a plurality of the first electrode terminals are arranged on the other side with the control electrode terminals being interposed therebetween, wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on one side of the control electrode terminals constitute a first transistor portion, and wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on the other side of the control electrode

Abstract: Devices having one or more of the following: an input/output (I/O) interconnect system, an optical I/O interconnect, an electrical I/O interconnect, a radio frequency I/O interconnect, are disclosed. A representative I/O interconnect system includes a first substrate and a second substrate. The first substrate includes a compliant pillar vertically extending from the first substrate. The compliant pillar is constructed a first material. The second substrate includes a compliant socket adapted to receive the compliant pillar. The compliant socket is constructed of a second material.