Abstract: A semiconductor structure includes a semiconductor substrate, a semiconductor device and a heating structure. The semiconductor substrate includes a device region and a heating region surrounding the device region. The semiconductor device is located on the device region. The heating structure is located on the heating region and includes an intrinsic semiconductor area, at least one heating element and at least one heating pad. The intrinsic semiconductor area is surrounding the semiconductor device. The at least one heating element is located at a periphery of the intrinsic semiconductor area. The at least one heating pad is joined with the at least one heating element, wherein the at least one heating pad includes a plurality of contact structures, and a voltage is supplied from the plurality of contact structures to control a temperature of the at least one heating element.

Abstract: A semiconductor device has a first substrate and a first electrical component disposed over the first substrate. A first support frame is disposed over the first substrate. The first support frame has a horizontal support channel extending across the first substrate and a vertical support brace extending from the horizontal support channel to the first substrate. The first support frame can have a vertical shielding partition extending from the horizontal support channel to the first substrate. An encapsulant is deposited over the first electrical component and first substrate and around the first support frame. A second electrical component is disposed over the first electrical component. A second substrate is disposed over the first support frame. A second electrical component is disposed over the second substrate. A third substrate is disposed over the second substrate. A second support frame is disposed over the second substrate.

Abstract: An electronic card (e.g., an electronic payment card) or another device (e.g., a wireless telephonic device) is provided that may communicate dynamic magnetic stripe data to a magnetic stripe reader. Information may be embedded into a magnetic track of data representative of additional information such as, for example, a unique identification number or an additional track of magnetic stripe data.

Abstract: Provided is an electromagnetic wave absorber capable of further expanding applicable objects while reducing a size of a unit structure, and at the same time, improving the degree of freedom in arrangement.

Abstract: A semiconductor package includes a first chip package including a plurality of first semiconductor dies and a first insulating encapsulant, a second semiconductor die, a third semiconductor die, and a second insulating encapsulant. The plurality of first semiconductor dies are electrically connected to each other, and the first insulating encapsulant encapsulates the plurality of first semiconductor dies. The second semiconductor die and the third semiconductor die are electrically communicated to each other by connecting to the first chip package, wherein the first chip package is stacked on the second semiconductor die and the third semiconductor die. The second insulating encapsulant encapsulates the first chip package, the second semiconductor die, and the third semiconductor die.

Abstract: A three-dimensional stacked integrated circuit (3D SIC) that can have at least a first 3D XPoint (3DXP) die and, in some examples, can have at least a second 3DXP die too. In such examples, the first 3DXP die and the second 3DXP die can be stacked. The 3D SIC can be partitioned into a plurality of columns that are perpendicular to each of the stacked dies. In such examples, when a first column of the plurality of columns is determined as failing, data stored in the first column can be replicated to a second column of the plurality of columns. Also, for example, when a part of a first column of the plurality of columns is determined as failing, data stored in the part of the first column can be replicated to a corresponding part of a second column of the plurality of columns.

Abstract: An interposer subassembly that is suitable for an electronic system having at least one integrated circuit (1C) component. The interposer subassembly includes a flexible base layer, having a first surface and an opposing second surface, at least one active electronic circuit component, operatively integrated within the flexible base layer, and at least one first patterned contact layer, provided on any one of the first surface and the second surface of the flexible base layer and which is configured to operably interface with the at least one active electronic circuit component and the at least one 1C component.

Abstract: A semiconductor device includes a semiconductor element, a heat sink on which the semiconductor element is mounted, and a case made of resin, the case being mounted on the heat sink and containing the semiconductor element. A fastening hole is formed passing through the case and the heat sink. The case includes a surface pressure absorbing member on a portion including the fastening hole in plan view, the surface pressure absorbing member having a plate shape and being higher in rigidity than the resin.

Abstract: A SPAD-type photodiode comprising a depletion area in a first portion of a semiconductor substrate of a first conductivity type and further comprising a gate electrically-insulated from the substrate, extending into the substrate from an upper surface of the substrate, and separating the first portion of the substrate from a second portion. The photodiode further comprises a first region of the second conductivity type extending from the upper surface of the substrate into the second portion.

Abstract: A MEMS device is formed by applying a lower polymer film to top surfaces of a common substrate containing a plurality of MEMS devices, and patterning the lower polymer film to form a headspace wall surrounding components of each MEMS device. Subsequently an upper polymer dry film is applied to top surfaces of the headspace walls and patterned to form headspace caps which isolate the components of each MEMS device. Subsequently, the MEMS devices are singulated to provide separate MEMS devices.

Abstract: The present application provides a method for forming a chip package and a chip package. The method comprises mounting at least one chipset including at least first and second chips on a carrier with front surface of the chips face away from the carrier; attaching an interconnection device to the front surfaces of the first and second chips to enable electrically connections between the chips; forming a molded encapsulation layer whereby the first chip, the second chip and the interconnection device are embedded or partially embedded in the molded encapsulation layer; thinning one side of the molded encapsulation layer away from the carrier to expose first bumps on the first and second chips; forming second bumps on a surface of one side of the molded encapsulation layer where the first bumps are exposed; and removing the carrier. Thus, a flexible, efficient and low-cost packaging scheme is provided for multi-chip connection.

Abstract: A method includes forming a plurality of dielectric layers, forming a lower portion of a seal ring including a plurality of metal layers, each extending into one of the plurality of dielectric layers, depositing a first passivation layer over the plurality of dielectric layers, forming an opening in the first passivation layer, forming a via ring in the opening and physically contacting the lower portion of the seal ring, and forming a metal ring over the first passivation layer and joined to the via ring. The via ring and the metal ring form an upper portion of the seal ring. The metal ring includes an edge portion having a zigzag pattern. The method further includes forming a second passivation layer on the metal ring, and performing a singulation process to form a device die, with the seal ring being proximate edges of the device die.

Abstract: A method for forming a semiconductor die package is provided, including disposing a first semiconductor die and a second semiconductor die over an interposer substrate, forming an underfill element over the interposer substrate to surround the first and second semiconductor dies, wherein a portion of the underfill element is between the semiconductor dies, stacking the interposer substrate over a package substrate, and installing a ring structure on the package substrate through an adhesive layer to surround the semiconductor dies. The ring structure has recessed parts recessed from its bottom surface. The recessed parts include first recessed parts arranged in at least one corner area of the ring structure and two second recessed parts arranged in two opposite side areas of the ring structure. The portion of the underfill element between the first and the second semiconductor dies is disposed between the two second recessed parts.

Abstract: A chip packaging structure includes a chip module and a main body, wherein the main body has a first portion, a second portion, and a holding portion. The second portion protrudes from the first portion, and a size of the second portion is less than a size of the first portion. The holding portion is located at the second portion, and the chip module is placed at the holding portion to be engaged with the main body.

Abstract: A method of forming a packaged semiconductor device according to some embodiments includes providing a leadframe blank including a first package blank, a second package blank and a tie bar between the first package blank and the second package blank, forming a recessed cavity in the tie bar, and separating the first and second package blanks by sawing through the leadframe blank along the tie bar.

Abstract: Generally described, one or more embodiments are directed to a leadframe package having a plurality of leads, a die pad, a semiconductor die coupled to the die pad, and encapsulation material. An inner portion of the die pad includes a perimeter portion that includes a plurality of protrusions that are spaced apart from each other. The protrusions aid in locking the die pad in the encapsulation material. The plurality of leads includes upper portions and base portions. The base portion of the plurality of leads are offset (or staggered) relative to the plurality of protrusions of the die pad. In particular, the base portions extend longitudinally toward the die pad and are located between respective protrusions. The upper portions of the leads include lead locks that extend beyond the base portions in a direction of adjacent leads. The lead locks and the protrusion in the die pad aid in locking the leads and the die pad in the encapsulation material.

Abstract: A three-dimensional device structure includes a first die including a first semiconductor substrate, a second die disposed on the first die and including a second semiconductor substrate, a dielectric encapsulation (DE) layer disposed on the first die and surrounding the second die, a redistribution layer structure disposed on the second die and the DE layer, and an integrated passive device (IPD) embedded in the DE layer and electrically connected to the first die and the redistribution layer structure.

Abstract: An electronic component includes a device die and a substrate. The device die includes conductive contacts with conductive pillars conductively affixed to conductive contact. The conductive pillars include a cavity formed in an end of the conductive pillar opposite the conductive contact. The substrate includes of conductive pads that are each associated with one of the conductive contacts. The conductive pads include a conductive pad conductively affixed to the substrate, and a conductive ring situated within a cavity in the end conductive rings have a capillary formed along an axis of the conductive ring. A solder material fills the capillary of each of the conductive rings and the cavity formed in the end of the associated conductive pillars to form a conductive joint between the pillars and the conductive pads.

Abstract: A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate.

Abstract: A semiconductor device package is provided. The semiconductor device package includes providing a first substrate, a computing unit and a power module. The first substrate has a first surface and a second surface opposite to the first surface. The computing unit is adjacent to the first surface. The computing unit includes a semiconductor die. The power module is adjacent to the second surface. The power module includes a power element and a passive element. Each of the semiconductor die, the power element, and the passive element is vertically arranged with respect to each other, and the passive elements are assembled between the semiconductor die and the power element.

Abstract: A semiconductor device package having stress isolation is provided. The semiconductor device package includes a package substrate and a sensor attached to the package substrate. A first isolation material is formed around a perimeter of the sensor. An encapsulant encapsulates at least a portion of the first isolation material and the package substrate.

Abstract: Provided is a semiconductor package including: a first substrate comprising a specific pattern formed thereon to enable electrical connection; a second substrate, which is spaced apart from and faces the first substrate, comprising a specific pattern formed thereon to enable electrical connection; at least one semiconductor chip attached to the first substrate; at least one metal post formed in a non-vertical structure between the first substrate and the second substrate for dispersing a coefficient of thermal expansion (CTE) stress directly generated from the second substrate, wherein the metal post comprises one end attached on the at least one semiconductor chip, and the other end attached on the pattern of the first substrate or the second substrate; at least one terminal lead electrically connected to the first substrate or the second substrate; and a package housing covering the first and second substrates and exposing the terminal leads to the outside.

Abstract: An electronic device package and a method for manufacturing an electronic device package are provided. The electronic device package includes electronic device structure which includes a first electronic device and a first encapsulant, a second electronic device, and a second encapsulant. The first encapsulant encapsulates the first electronic device. The second electronic device is adjacent to the electronic device structure. The second encapsulant encapsulates the electronic device structure and the second electronic device. A first extension line along a lateral surface of the first electronic device and a second extension line along a lateral surface of the first encapsulant define a first angle, the second extension line along the lateral surface of the first encapsulant and a third extension line along a lateral surface of the second electronic device define a second angle, and the first angle is different from the second angle.

Abstract: Embodiments herein describe techniques for a semiconductor device including a package substrate having a core layer. An inductor may include a first coaxial line and a second coaxial line vertically through the core layer, and an interconnect within the package substrate coupling the first coaxial line and the second coaxial line. A first magnetic segment may surround the first coaxial line within the core layer, and a second magnetic segment may surround the second coaxial line within the core layer. In addition, a third magnetic segment may surround the interconnect and be coupled to the first magnetic segment and the second magnetic segment. Other embodiments may be described and/or claimed.

Abstract: A package device includes a first device die and second device die bonded thereto. When the area of the second device die is less than half the area of the first device die, one or more inactive structures having a semiconductor substrate is also bonded to the first device die so that the combined area of the second device die and the one or more inactive structures is greater than half the area of the first device die.

Abstract: A semiconductor package includes a first chip package including a plurality of first semiconductor dies and a first insulating encapsulant, a second semiconductor die, a third semiconductor die, and a second insulating encapsulant. The plurality of first semiconductor dies are electrically connected to each other, and the first insulating encapsulant encapsulates the plurality of first semiconductor dies. The second semiconductor die and the third semiconductor die are electrically communicated to each other by connecting to the first chip package, wherein the first chip package is stacked on the second semiconductor die and the third semiconductor die. The second insulating encapsulant encapsulates the first chip package, the second semiconductor die, and the third semiconductor die.

Abstract: A leadframe for electronic systems comprising a first sub-leadframe connected by links to a second sub-leadframe, the first and second sub-leadframe connected by tiebars to a frame; and each link having a neck suitable for bending the link, the necks arrayed in a line operable as the axis for bending the second sub-leadframe towards the first sub-leadframe with the necks operable as rotation pivots.

Abstract: A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate, an interposer substrate over the package substrate, two semiconductor dies over the interposer substrate, and an underfill element formed over the interposer substrate and surrounding the semiconductor dies. A ring structure is disposed over the package substrate and surrounds the semiconductor dies. Recessed parts are recessed from the bottom surface of the ring structure. The recessed parts include multiple first recessed parts arranged in each corner area of the ring structure and two second recessed parts arranged in opposite side areas of the ring structure and aligned with a portion of the underfill element between the semiconductor dies. An adhesive layer is interposed between the bottom surface of the ring structure and the package substrate.

Abstract: Provided is a solid-state imaging unit that includes a stacked structure including a sensor substrate and a circuit board. The sensor board has an effective pixel region where an imaging device is disposed. The imaging device includes a plurality of pixels and is configured to receive external light in each of the pixels to generate a pixel signal. The circuit board includes a chip including a first portion and a second portion that are integrated with each other. The first portion includes a signal processing circuit that performs signal processing of the pixel signal. The second portion is disposed at a position different from a position of the first portion in an in-plane direction. Here, both the first portion and the second portion are disposed to overlap the effective pixel region in a stacking direction of the sensor board and the circuit board.

Abstract: One or more chip-embedded integrated voltage regulators (“CEIVR's”) are configured to provide power to a circuit or chip such as a CPU or GPU and meet power delivery specifications. The CEIVR's, circuit or chip, and power delivery pathways can be included within the same package. The CEIVR's can be separate from the circuit or chip.

Abstract: A vapor chamber device adapted to be thermally coupled to a heat source includes a first casing and a second casing. The first casing includes a first plate, a first capillary structure at an inner surface of the first plate, and a first lateral wall protruding from the inner surface and surrounding the first capillary structure. The heat source is adapted to contact an outer surface of the first plate. The second casing is stacked on the first casing and includes a second plate, a plurality of supporting posts protruding from the second plate, and a second lateral wall protruding from the second plate and surrounding the supporting posts. The supporting posts face towards the first capillary structure, and the first lateral wall is connected to the second lateral wall.

Abstract: Provided is a semiconductor device including: a circuit board; a wiring pattern; a first semiconductor chip and a second semiconductor chip; a first lead frame; and a second lead frame; wherein the first lead frame and the second lead frame each comprises: a chip joining portion provided above at least a part of the semiconductor chip; a wiring joining portion provided above at least a part of the wiring pattern; and a bridging portion for connecting the chip joining portion and the wiring joining portion; and in the first direction, a space between the bridging portion of the first lead frame and the bridging portion of the second lead frame is smaller than a space between the chip joining portion of the first lead frame and the chip joining portion of the second lead frame.

Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package is provided that includes a package substrate that has a first edge and a second edge opposite to the first edge. A semiconductor chip is mounted on the package substrate. A thermal interface material is positioned on the semiconductor chip. A lid is positioned over the thermal interface material. A spring biasing mechanism is included that is operable to bias the lid away from the package substrate so that the lid, when subjected to a compressive force, can translate toward the package substrate and impart a compressive force on the thermal interface material.

Abstract: A method of processing a workpiece with a disk-shaped blade containing abrasive grains includes the steps of placing an auxiliary plate made of a material having a modulus of elasticity higher than a material of which a front surface side of the workpiece is made, on the front surface side of the workpiece, causing the blade rotated to cut into the front surface side of the workpiece to cut the workpiece as well as the auxiliary plate, and removing the auxiliary plate from the workpiece that has been cut by the blade.

Abstract: An antenna module includes an antenna substrate, a first semiconductor package, disposed on the antenna substrate, including a first connection member including one or more first redistribution layers, electrically connected to the antenna substrate, and a first semiconductor chip disposed on the first connection member, and a second semiconductor package, disposed on the antenna substrate to be spaced apart from the first semiconductor package, including a second connection member including one or more second redistribution layers, electrically connected to the antenna substrate, and a second semiconductor chip disposed on the second connection member. The first semiconductor chip and the second semiconductor chip are different types of semiconductor chips.

Abstract: A substrate for a display includes a substrate section on which a flexible substrate and a driver are mounted, a flexible substrate side terminal area, disposed in a mounting area on the substrate section for the flexible substrate, to which a signal is inputted from the flexible substrate, a driver side terminal area, disposed in a mounting area on the substrate section for the driver, through which at least a part of the signal is inputted and outputted to the driver, a wire, disposed to extend from the mounting area on the substrate section for the flexible substrate to the mounting area for the driver and connected to the flexible substrate side terminal area and the driver side terminal area, through which the signal is transmitted, and a shield section, disposed to overlap the wire via an insulating film on the substrate section, that is kept at a constant potential.

Abstract: A semiconductor device includes: a case having an opening; a semiconductor element contained in the case; a control substrate which is disposed above the semiconductor element in the case and on which a control circuit to control the semiconductor element is disposed; a lid to cover the opening of the case; and a control terminal having one end portion connected to the control circuit disposed on the control substrate and the other end portion protruding out of the case. The control terminal has a bend in the case, and a side portion of the case or the lid is provided with a support capable of supporting the bend.

Abstract: A method is disclosed herein. The method includes dicing a wafer and applying a mask. The method includes spraying die bond material, at a first temperature, to a surface of the wafer and cooling the die bond material at a second temperature to at least partially solidify the die bond material. The method also includes removing the mask from the wafer through the die bond material. After the removing of the mask, the method includes curing the die bond material to form a die attach film layer on the wafer.

Abstract: The present disclosure relates to an embedded packaging module comprising a first semiconductor device, a first packaging layer and a first wiring layer, the first semiconductor device having a first and a second face, at least two positioning bulges and at least one bonding pad being provided on the first face of the first semiconductor device; the first packaging layer being formed on both the first face and a surface adjacent to the first face, the positioning bulges being positioned in the first packaging layer, at least one first via hole being provided in the first packaging layer, the bottom of the first via hole being positioned in the bonding pad and contacting with the bonding pad; the first wiring layer being positioned on the side of the first packaging layer away from the first semiconductor device and being electrically connected with the bonding pad through the first via hole.

Abstract: An actuating breathable material structure is disclosed and includes a supporting main body, a plurality of actuating breathable units and a plurality of micro processing chips. The supporting main body is made of a supporting matrix. The plurality of actuating breathable units and the plurality of micro processing chips are compounded and are integrally formed with the supporting matrix into one piece. By controlling the actuation of the plurality of actuating breathable units through the plurality of micro processing chips, a breathing effect resulting from gas transportation in a specific direction is performed.

Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, a heat sink lid and conductive balls. The die is disposed on a front surface of the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the front surface of the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies. The conductive balls are disposed on the opposite surface of the circuit substrate and electrically connected with the die through the circuit substrate.

Abstract: A semiconductor device, having a first semiconductor chip including a first side portion at a front surface thereof and a first control electrode formed in the first side portion, a second semiconductor chip including a second side portion at a front surface thereof and a second control electrode formed in the second side portion, a first circuit pattern, on which the first semiconductor chip and the second semiconductor chip are disposed, a second circuit pattern, and a first control wire electrically connecting the first control electrode, the second control electrode, and the second circuit pattern. The first side portion and the second side portion are aligned. The first control electrode and the second control electrode are aligned. The second circuit pattern are aligned with the first control electrode and the second control electrode.

Abstract: A semiconductor packaging structure includes: a substrate, a redistribution layer having one conductive plugs, metal bumps disposed on the redistribution layer, and electrically connected with the redistribution layer including the conductive plug; a semiconductor chip over the redistribution layer and aligned to and electrically connected with the conductive plug; an underfill layer filling a gap between the redistribution layer and the semiconductor chip and the conductive plugs; a polymer layer on the redistribution layer, over the plurality of metal bumps, the underfill layer and the semiconductor chip, exposing only top parts of the plurality of metal bumps and top part of the semiconductor chip; and an antenna module disposed on the second surface of the substrate.

Abstract: Interposer printed circuit boards for power modules and associated methods are disclosed. In at least one illustrative embodiment, a printed circuit board assembly may comprise a printed circuit board, an electrical component mounted on a surface of the printed circuit board, and an interposer printed circuit board mounted on the surface of the printed circuit board. The interposer printed circuit board may comprise a first signal path to transmit a first electrical signal and a second signal path to transmit a second electrical signal that is different from the first electrical signal. The interposer printed circuit board may be configured to provide a standoff to prevent the electrical component from contacting a motherboard when the printed circuit board assembly is mounted to the motherboard.

Abstract: A three-dimensional stacked integrated circuit (3D SIC) that can have at least a first 3D XPoint (3DXP) die and, in some examples, can have at least a second 3DXP die too. In such examples, the first 3DXP die and the second 3DXP die can be stacked. The 3D SIC can be partitioned into a plurality of columns that are perpendicular to each of the stacked dies. In such examples, when a first column of the plurality of columns is determined as failing, data stored in the first column can be replicated to a second column of the plurality of columns. Also, for example, when a part of a first column of the plurality of columns is determined as failing, data stored in the part of the first column can be replicated to a corresponding part of a second column of the plurality of columns.

Abstract: Embodiments described herein provide techniques for forming a solder mask having a repeating pattern of features formed therein. The repeating pattern of features can be conceptually understood as a plurality of groove structures formed in the solder mask. The solder mask can be included in a semiconductor package that comprises the solder mask over a substrate and a molding compound over the solder mask that conforms to the repeating pattern of features. Several advantages are attributable to embodiments of the solder mask described herein. One advantage is that the repeating pattern of features formed in the solder mask increase the contact area between the solder mask and the molding compound. Increasing the contact area can assist with increasing adherence and conformance of the molding compound to the solder mask. This increased adherence and conformance assists with minimizing or eliminating interfacial delamination.

Abstract: Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.

Abstract: In a described example, an apparatus includes a package substrate with a split die pad having a slot between a die mount portion and a wire bonding portion; a first end of the wire bonding portion coupled to the die mount portion at one end of the slot; a second end of the wire bonding portion coupled to a first lead on the package substrate. At least one semiconductor die is mounted on the die mount portion; a first end of a first wire bond is bonded to a first bond pad on the at least one semiconductor die; a second end of the first wire bond is bonded to the wire bonding portion; and mold compound covers the at least one semiconductor die, the die mount portion, the wire bonding portion, and fills the slot.

Abstract: Methods of forming an image sensor chip scale package. Implementations may include providing a semiconductor wafer having a pixel array, forming a first cavity through the wafer and/or one or more layers coupled over the wafer, filling the first cavity with a fill material, planarizing the fill material and/or the one or more layers to form a first surface of the fill material coplanar with a first surface of the one or more layers, and bonding a transparent cover over the fill material and the one or more layers. The bond may be a fusion bond between the transparent cover and a passivation oxide; a fusion bond between the transparent cover and an anti-reflective coating; a bond between the transparent cover and an organic adhesive coupled over the fill material, and/or; a bond between a first metallized surface of the transparent cover and a metallized layer coupled over the wafer.

Abstract: Implementations of a semiconductor device may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be formed by at least two semiconductor die. The warpage of one of the first largest planar surface or the second largest planar surface may be less than 200 microns.