Housing Or Package Patents (Class 257/678)
  • Patent number: 12009286
    Abstract: A method of forming a packaged semiconductor device according to some embodiments includes providing a leadframe blank including a first package blank, a second package blank and a tie bar between the first package blank and the second package blank, forming a recessed cavity in the tie bar, and separating the first and second package blanks by sawing through the leadframe blank along the tie bar.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: June 11, 2024
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: Soon Lee Liew, Eng Wah Woo, Alexander Komposch
  • Patent number: 11948868
    Abstract: Generally described, one or more embodiments are directed to a leadframe package having a plurality of leads, a die pad, a semiconductor die coupled to the die pad, and encapsulation material. An inner portion of the die pad includes a perimeter portion that includes a plurality of protrusions that are spaced apart from each other. The protrusions aid in locking the die pad in the encapsulation material. The plurality of leads includes upper portions and base portions. The base portion of the plurality of leads are offset (or staggered) relative to the plurality of protrusions of the die pad. In particular, the base portions extend longitudinally toward the die pad and are located between respective protrusions. The upper portions of the leads include lead locks that extend beyond the base portions in a direction of adjacent leads. The lead locks and the protrusion in the die pad aid in locking the leads and the die pad in the encapsulation material.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: April 2, 2024
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Jefferson Talledo
  • Patent number: 11908838
    Abstract: A three-dimensional device structure includes a first die including a first semiconductor substrate, a second die disposed on the first die and including a second semiconductor substrate, a dielectric encapsulation (DE) layer disposed on the first die and surrounding the second die, a redistribution layer structure disposed on the second die and the DE layer, and an integrated passive device (IPD) embedded in the DE layer and electrically connected to the first die and the redistribution layer structure.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jen-Yuan Chang, Chien-Chang Lee, Chia-Ping Lai, Tzu-Chung Tsai
  • Patent number: 11875988
    Abstract: An electronic component includes a device die and a substrate. The device die includes conductive contacts with conductive pillars conductively affixed to conductive contact. The conductive pillars include a cavity formed in an end of the conductive pillar opposite the conductive contact. The substrate includes of conductive pads that are each associated with one of the conductive contacts. The conductive pads include a conductive pad conductively affixed to the substrate, and a conductive ring situated within a cavity in the end conductive rings have a capillary formed along an axis of the conductive ring. A solder material fills the capillary of each of the conductive rings and the cavity formed in the end of the associated conductive pillars to form a conductive joint between the pillars and the conductive pads.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: January 16, 2024
    Assignee: NXP USA, INC.
    Inventor: Kabir Mirpuri
  • Patent number: 11854988
    Abstract: A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jiun Yi Wu, Chen-Hua Yu, Chung-Shi Liu, Chien-Hsun Lee
  • Patent number: 11848296
    Abstract: A semiconductor device package is provided. The semiconductor device package includes providing a first substrate, a computing unit and a power module. The first substrate has a first surface and a second surface opposite to the first surface. The computing unit is adjacent to the first surface. The computing unit includes a semiconductor die. The power module is adjacent to the second surface. The power module includes a power element and a passive element. Each of the semiconductor die, the power element, and the passive element is vertically arranged with respect to each other, and the passive elements are assembled between the semiconductor die and the power element.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: December 19, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Han-Chee Yen, Ying-Nan Liu, Min-Yao Cheng
  • Patent number: 11823968
    Abstract: A semiconductor device package having stress isolation is provided. The semiconductor device package includes a package substrate and a sensor attached to the package substrate. A first isolation material is formed around a perimeter of the sensor. An encapsulant encapsulates at least a portion of the first isolation material and the package substrate.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: November 21, 2023
    Assignee: NXP USA, INC.
    Inventors: Michael B. Vincent, Scott M. Hayes, Stephen Ryan Hooper
  • Patent number: 11798864
    Abstract: Provided is a semiconductor package including: a first substrate comprising a specific pattern formed thereon to enable electrical connection; a second substrate, which is spaced apart from and faces the first substrate, comprising a specific pattern formed thereon to enable electrical connection; at least one semiconductor chip attached to the first substrate; at least one metal post formed in a non-vertical structure between the first substrate and the second substrate for dispersing a coefficient of thermal expansion (CTE) stress directly generated from the second substrate, wherein the metal post comprises one end attached on the at least one semiconductor chip, and the other end attached on the pattern of the first substrate or the second substrate; at least one terminal lead electrically connected to the first substrate or the second substrate; and a package housing covering the first and second substrates and exposing the terminal leads to the outside.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: October 24, 2023
    Assignee: JMJ Korea Co., Ltd.
    Inventor: Yun Hwa Choi
  • Patent number: 11791227
    Abstract: An electronic device package and a method for manufacturing an electronic device package are provided. The electronic device package includes electronic device structure which includes a first electronic device and a first encapsulant, a second electronic device, and a second encapsulant. The first encapsulant encapsulates the first electronic device. The second electronic device is adjacent to the electronic device structure. The second encapsulant encapsulates the electronic device structure and the second electronic device. A first extension line along a lateral surface of the first electronic device and a second extension line along a lateral surface of the first encapsulant define a first angle, the second extension line along the lateral surface of the first encapsulant and a third extension line along a lateral surface of the second electronic device define a second angle, and the first angle is different from the second angle.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: October 17, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Kuoching Cheng, Yuan-Feng Chiang, Ya Fang Chan, Wen-Long Lu, Shih-Yu Wang
  • Patent number: 11764150
    Abstract: Embodiments herein describe techniques for a semiconductor device including a package substrate having a core layer. An inductor may include a first coaxial line and a second coaxial line vertically through the core layer, and an interconnect within the package substrate coupling the first coaxial line and the second coaxial line. A first magnetic segment may surround the first coaxial line within the core layer, and a second magnetic segment may surround the second coaxial line within the core layer. In addition, a third magnetic segment may surround the interconnect and be coupled to the first magnetic segment and the second magnetic segment. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: September 19, 2023
    Assignee: Intel Corporation
    Inventors: Sri Chaitra Jyotsna Chavali, Tarek Ibrahim, Wei-Lun Jen
  • Patent number: 11756933
    Abstract: A package device includes a first device die and second device die bonded thereto. When the area of the second device die is less than half the area of the first device die, one or more inactive structures having a semiconductor substrate is also bonded to the first device die so that the combined area of the second device die and the one or more inactive structures is greater than half the area of the first device die.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Hsien-Wei Chen
  • Patent number: 11749651
    Abstract: A semiconductor package includes a first chip package including a plurality of first semiconductor dies and a first insulating encapsulant, a second semiconductor die, a third semiconductor die, and a second insulating encapsulant. The plurality of first semiconductor dies are electrically connected to each other, and the first insulating encapsulant encapsulates the plurality of first semiconductor dies. The second semiconductor die and the third semiconductor die are electrically communicated to each other by connecting to the first chip package, wherein the first chip package is stacked on the second semiconductor die and the third semiconductor die. The second insulating encapsulant encapsulates the first chip package, the second semiconductor die, and the third semiconductor die.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: September 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen
  • Patent number: 11742263
    Abstract: A leadframe for electronic systems comprising a first sub-leadframe connected by links to a second sub-leadframe, the first and second sub-leadframe connected by tiebars to a frame; and each link having a neck suitable for bending the link, the necks arrayed in a line operable as the axis for bending the second sub-leadframe towards the first sub-leadframe with the necks operable as rotation pivots.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: August 29, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Lee Han Meng@ Eugene Lee, Anis Fauzi Bin Abdul Aziz, Wei Fen Sueann Lim
  • Patent number: 11676826
    Abstract: A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate, an interposer substrate over the package substrate, two semiconductor dies over the interposer substrate, and an underfill element formed over the interposer substrate and surrounding the semiconductor dies. A ring structure is disposed over the package substrate and surrounds the semiconductor dies. Recessed parts are recessed from the bottom surface of the ring structure. The recessed parts include multiple first recessed parts arranged in each corner area of the ring structure and two second recessed parts arranged in opposite side areas of the ring structure and aligned with a portion of the underfill element between the semiconductor dies. An adhesive layer is interposed between the bottom surface of the ring structure and the package substrate.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Sheng Lin, Shu-Shen Yeh, Chin-Hua Wang, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11670625
    Abstract: Provided is a solid-state imaging unit that includes a stacked structure including a sensor substrate and a circuit board. The sensor board has an effective pixel region where an imaging device is disposed. The imaging device includes a plurality of pixels and is configured to receive external light in each of the pixels to generate a pixel signal. The circuit board includes a chip including a first portion and a second portion that are integrated with each other. The first portion includes a signal processing circuit that performs signal processing of the pixel signal. The second portion is disposed at a position different from a position of the first portion in an in-plane direction. Here, both the first portion and the second portion are disposed to overlap the effective pixel region in a stacking direction of the sensor board and the circuit board.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: June 6, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Masahiko Yukawa
  • Patent number: 11652062
    Abstract: One or more chip-embedded integrated voltage regulators (“CEIVR's”) are configured to provide power to a circuit or chip such as a CPU or GPU and meet power delivery specifications. The CEIVR's, circuit or chip, and power delivery pathways can be included within the same package. The CEIVR's can be separate from the circuit or chip.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: May 16, 2023
    Assignee: Faraday Semi, Inc.
    Inventor: Parviz Parto
  • Patent number: 11644250
    Abstract: A vapor chamber device adapted to be thermally coupled to a heat source includes a first casing and a second casing. The first casing includes a first plate, a first capillary structure at an inner surface of the first plate, and a first lateral wall protruding from the inner surface and surrounding the first capillary structure. The heat source is adapted to contact an outer surface of the first plate. The second casing is stacked on the first casing and includes a second plate, a plurality of supporting posts protruding from the second plate, and a second lateral wall protruding from the second plate and surrounding the supporting posts. The supporting posts face towards the first capillary structure, and the first lateral wall is connected to the second lateral wall.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: May 9, 2023
    Assignee: National Tsing Hua University
    Inventor: Shwin-Chung Wong
  • Patent number: 11631641
    Abstract: Provided is a semiconductor device including: a circuit board; a wiring pattern; a first semiconductor chip and a second semiconductor chip; a first lead frame; and a second lead frame; wherein the first lead frame and the second lead frame each comprises: a chip joining portion provided above at least a part of the semiconductor chip; a wiring joining portion provided above at least a part of the wiring pattern; and a bridging portion for connecting the chip joining portion and the wiring joining portion; and in the first direction, a space between the bridging portion of the first lead frame and the bridging portion of the second lead frame is smaller than a space between the chip joining portion of the first lead frame and the chip joining portion of the second lead frame.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: April 18, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tomoya Nakayama, Akihiro Osawa
  • Patent number: 11631624
    Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package is provided that includes a package substrate that has a first edge and a second edge opposite to the first edge. A semiconductor chip is mounted on the package substrate. A thermal interface material is positioned on the semiconductor chip. A lid is positioned over the thermal interface material. A spring biasing mechanism is included that is operable to bias the lid away from the package substrate so that the lid, when subjected to a compressive force, can translate toward the package substrate and impart a compressive force on the thermal interface material.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: April 18, 2023
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Kaushik Mysore Srinivasa Setty, William J. Maxwell
  • Patent number: 11615979
    Abstract: A method of processing a workpiece with a disk-shaped blade containing abrasive grains includes the steps of placing an auxiliary plate made of a material having a modulus of elasticity higher than a material of which a front surface side of the workpiece is made, on the front surface side of the workpiece, causing the blade rotated to cut into the front surface side of the workpiece to cut the workpiece as well as the auxiliary plate, and removing the auxiliary plate from the workpiece that has been cut by the blade.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: March 28, 2023
    Assignee: DISCO CORPORATION
    Inventor: Steve Latina
  • Patent number: 11581275
    Abstract: An antenna module includes an antenna substrate, a first semiconductor package, disposed on the antenna substrate, including a first connection member including one or more first redistribution layers, electrically connected to the antenna substrate, and a first semiconductor chip disposed on the first connection member, and a second semiconductor package, disposed on the antenna substrate to be spaced apart from the first semiconductor package, including a second connection member including one or more second redistribution layers, electrically connected to the antenna substrate, and a second semiconductor chip disposed on the second connection member. The first semiconductor chip and the second semiconductor chip are different types of semiconductor chips.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: February 14, 2023
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Doo Il Kim, Won Wook So, Young Sik Hur, Jung Chul Gong
  • Patent number: 11579497
    Abstract: A substrate for a display includes a substrate section on which a flexible substrate and a driver are mounted, a flexible substrate side terminal area, disposed in a mounting area on the substrate section for the flexible substrate, to which a signal is inputted from the flexible substrate, a driver side terminal area, disposed in a mounting area on the substrate section for the driver, through which at least a part of the signal is inputted and outputted to the driver, a wire, disposed to extend from the mounting area on the substrate section for the flexible substrate to the mounting area for the driver and connected to the flexible substrate side terminal area and the driver side terminal area, through which the signal is transmitted, and a shield section, disposed to overlap the wire via an insulating film on the substrate section, that is kept at a constant potential.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: February 14, 2023
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yukio Shimizu, Shinzoh Murakami
  • Patent number: 11552039
    Abstract: The present disclosure relates to an embedded packaging module comprising a first semiconductor device, a first packaging layer and a first wiring layer, the first semiconductor device having a first and a second face, at least two positioning bulges and at least one bonding pad being provided on the first face of the first semiconductor device; the first packaging layer being formed on both the first face and a surface adjacent to the first face, the positioning bulges being positioned in the first packaging layer, at least one first via hole being provided in the first packaging layer, the bottom of the first via hole being positioned in the bonding pad and contacting with the bonding pad; the first wiring layer being positioned on the side of the first packaging layer away from the first semiconductor device and being electrically connected with the bonding pad through the first via hole.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: January 10, 2023
    Assignee: Delta Electronics (Shanghai) CO., LTD
    Inventors: Zengsheng Wang, Xuetao Guo, Kai Lu, Hui Li
  • Patent number: 11552040
    Abstract: A method is disclosed herein. The method includes dicing a wafer and applying a mask. The method includes spraying die bond material, at a first temperature, to a surface of the wafer and cooling the die bond material at a second temperature to at least partially solidify the die bond material. The method also includes removing the mask from the wafer through the die bond material. After the removing of the mask, the method includes curing the die bond material to form a die attach film layer on the wafer.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: January 10, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Siqi Zhang, Xu Wang, Pradeep Rai, Shrikar Bhagath
  • Patent number: 11551983
    Abstract: A semiconductor device includes: a case having an opening; a semiconductor element contained in the case; a control substrate which is disposed above the semiconductor element in the case and on which a control circuit to control the semiconductor element is disposed; a lid to cover the opening of the case; and a control terminal having one end portion connected to the control circuit disposed on the control substrate and the other end portion protruding out of the case. The control terminal has a bend in the case, and a side portion of the case or the lid is provided with a support capable of supporting the bend.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: January 10, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventor: Shin Suzuki
  • Patent number: 11540416
    Abstract: An actuating breathable material structure is disclosed and includes a supporting main body, a plurality of actuating breathable units and a plurality of micro processing chips. The supporting main body is made of a supporting matrix. The plurality of actuating breathable units and the plurality of micro processing chips are compounded and are integrally formed with the supporting matrix into one piece. By controlling the actuation of the plurality of actuating breathable units through the plurality of micro processing chips, a breathing effect resulting from gas transportation in a specific direction is performed.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: December 27, 2022
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Ta-Wei Hsueh, Yung-Lung Han, Chi-Feng Huang, Chun-Yi Kuo, Chang-Yen Tsai
  • Patent number: 11515292
    Abstract: A semiconductor device, having a first semiconductor chip including a first side portion at a front surface thereof and a first control electrode formed in the first side portion, a second semiconductor chip including a second side portion at a front surface thereof and a second control electrode formed in the second side portion, a first circuit pattern, on which the first semiconductor chip and the second semiconductor chip are disposed, a second circuit pattern, and a first control wire electrically connecting the first control electrode, the second control electrode, and the second circuit pattern. The first side portion and the second side portion are aligned. The first control electrode and the second control electrode are aligned. The second circuit pattern are aligned with the first control electrode and the second control electrode.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: November 29, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Mitsuhiro Kakefu, Hiroaki Ichikawa
  • Patent number: 11515269
    Abstract: A semiconductor packaging structure includes: a substrate, a redistribution layer having one conductive plugs, metal bumps disposed on the redistribution layer, and electrically connected with the redistribution layer including the conductive plug; a semiconductor chip over the redistribution layer and aligned to and electrically connected with the conductive plug; an underfill layer filling a gap between the redistribution layer and the semiconductor chip and the conductive plugs; a polymer layer on the redistribution layer, over the plurality of metal bumps, the underfill layer and the semiconductor chip, exposing only top parts of the plurality of metal bumps and top part of the semiconductor chip; and an antenna module disposed on the second surface of the substrate.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: November 29, 2022
    Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
    Inventors: Yenheng Chen, Chengchung Lin, Chengtar Wu, Jangshen Lin
  • Patent number: 11515229
    Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, a heat sink lid and conductive balls. The die is disposed on a front surface of the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the front surface of the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies. The conductive balls are disposed on the opposite surface of the circuit substrate and electrically connected with the die through the circuit substrate.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: November 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Lai, Chien-Chia Chiu, Chen-Hua Yu, Der-Chyang Yeh, Cheng-Hsien Hsieh, Li-Han Hsu, Tsung-Shu Lin, Wei-Cheng Wu, Yu-Chen Hsu
  • Patent number: 11488945
    Abstract: A three-dimensional stacked integrated circuit (3D SIC) that can have at least a first 3D XPoint (3DXP) die and, in some examples, can have at least a second 3DXP die too. In such examples, the first 3DXP die and the second 3DXP die can be stacked. The 3D SIC can be partitioned into a plurality of columns that are perpendicular to each of the stacked dies. In such examples, when a first column of the plurality of columns is determined as failing, data stored in the first column can be replicated to a second column of the plurality of columns. Also, for example, when a part of a first column of the plurality of columns is determined as failing, data stored in the part of the first column can be replicated to a corresponding part of a second column of the plurality of columns.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: November 1, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Tony M. Brewer
  • Patent number: 11490517
    Abstract: Interposer printed circuit boards for power modules and associated methods are disclosed. In at least one illustrative embodiment, a printed circuit board assembly may comprise a printed circuit board, an electrical component mounted on a surface of the printed circuit board, and an interposer printed circuit board mounted on the surface of the printed circuit board. The interposer printed circuit board may comprise a first signal path to transmit a first electrical signal and a second signal path to transmit a second electrical signal that is different from the first electrical signal. The interposer printed circuit board may be configured to provide a standoff to prevent the electrical component from contacting a motherboard when the printed circuit board assembly is mounted to the motherboard.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: November 1, 2022
    Assignee: ABB POWER ELECTRONICS, INC.
    Inventors: John Andrew Trelford, Richard John Yeager, Alok Kumar Lohia, Thang Danh Truong
  • Patent number: 11476174
    Abstract: Embodiments described herein provide techniques for forming a solder mask having a repeating pattern of features formed therein. The repeating pattern of features can be conceptually understood as a plurality of groove structures formed in the solder mask. The solder mask can be included in a semiconductor package that comprises the solder mask over a substrate and a molding compound over the solder mask that conforms to the repeating pattern of features. Several advantages are attributable to embodiments of the solder mask described herein. One advantage is that the repeating pattern of features formed in the solder mask increase the contact area between the solder mask and the molding compound. Increasing the contact area can assist with increasing adherence and conformance of the molding compound to the solder mask. This increased adherence and conformance assists with minimizing or eliminating interfacial delamination.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: October 18, 2022
    Assignee: Intel Corporation
    Inventors: James Zhang, Yi Xu, Yuhong Cai
  • Patent number: 11462515
    Abstract: Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: October 4, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Chee Hiong Chew, Atapol Prajuckamol, Stephen St. Germain, Yusheng Lin
  • Patent number: 11444012
    Abstract: In a described example, an apparatus includes a package substrate with a split die pad having a slot between a die mount portion and a wire bonding portion; a first end of the wire bonding portion coupled to the die mount portion at one end of the slot; a second end of the wire bonding portion coupled to a first lead on the package substrate. At least one semiconductor die is mounted on the die mount portion; a first end of a first wire bond is bonded to a first bond pad on the at least one semiconductor die; a second end of the first wire bond is bonded to the wire bonding portion; and mold compound covers the at least one semiconductor die, the die mount portion, the wire bonding portion, and fills the slot.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: September 13, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yuh-Harng Chien, Chang-Yen Ko, Chih-Chien Ho
  • Patent number: 11437426
    Abstract: Methods of forming an image sensor chip scale package. Implementations may include providing a semiconductor wafer having a pixel array, forming a first cavity through the wafer and/or one or more layers coupled over the wafer, filling the first cavity with a fill material, planarizing the fill material and/or the one or more layers to form a first surface of the fill material coplanar with a first surface of the one or more layers, and bonding a transparent cover over the fill material and the one or more layers. The bond may be a fusion bond between the transparent cover and a passivation oxide; a fusion bond between the transparent cover and an anti-reflective coating; a bond between the transparent cover and an organic adhesive coupled over the fill material, and/or; a bond between a first metallized surface of the transparent cover and a metallized layer coupled over the wafer.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: September 6, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Swarnal Borthakur
  • Patent number: 11432419
    Abstract: A semiconductor module includes a first power semiconductor element having a first surface and a second surface. The semiconductor module also includes a second power semiconductor element having a first surface and a second surface. The semiconductor module also includes first, second, third, and fourth conductor plates, and a connecting part. The connecting part is integrally formed with the second conductor plate, extends toward the third conductor plate, and is connected to the third conductor plate.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: August 30, 2022
    Assignee: Hitachi Astemo, Ltd.
    Inventors: Tokihito Suwa, Yujiro Kaneko, Yusuke Takagi, Shinichi Fujino, Takahiro Shimura
  • Patent number: 11430746
    Abstract: Implementations of a semiconductor device may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be formed by at least two semiconductor die. The warpage of one of the first largest planar surface or the second largest planar surface may be less than 200 microns.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: August 30, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Francis J. Carney
  • Patent number: 11424221
    Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a first die and a second die boned face-to-face. The first die includes first transistors formed on a face side of the first die in a semiconductor portion and at least a contact structure disposed in an insulating portion outside the semiconductor portion. The second die includes a substrate and second transistors formed on a face side of the second die. Further, the semiconductor device includes a first pad structure disposed on a back side of the first die and the first pad structure is conductively coupled with the contact structure. An end of the contact structure protrudes from the insulating portion into the first pad structure. Further, in some embodiments, the semiconductor device includes a connection structure disposed on the back side of the first die and conductively connected with the semiconductor portion.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: August 23, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Liang Xiao, Shu Wu
  • Patent number: 11424215
    Abstract: A nucleation suppression layer including a self-assembly material can be formed on a surface of a bonding dielectric layer without depositing the self-assembly material on physically exposed surfaces of first metal bonding pads of a first semiconductor die. Metallic liners including a second metal can be formed on the physically exposed surfaces of the metal bonding pads without depositing the second metal on the nucleation suppression layer. The first semiconductor die is bonded to a second semiconductor die by inducing metal-to-metal bonding between mating pairs of the first metal bonding pads and second metal bonding pads of the second semiconductor die.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: August 23, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Lin Hou, Peter Rabkin, Yangyin Chen, Masaaki Higashitani
  • Patent number: 11410923
    Abstract: A semiconductor device, an integrated fan-out package and a method of forming the same are disclosed. In some embodiments, a semiconductor device includes a substrate, a conductive layer, a passivation layer and a bump structure. The substrate has at least one electronic component therein. The conductive layer has a plurality of lines patterns over and electrically connected to the at least one electronic component. The passivation layer is over the conductive layer. The bump structure has a plurality of protruding parts penetrating through the passivation layer and electrically connected to the lines patterns of the conductive layer.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: August 9, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang, Wei-Ting Chen
  • Patent number: 11399438
    Abstract: The present disclosure provides a power module, a chip-embedded package module and a manufacturing method of the chip-embedded package module. The chip-embedded package module includes: a chip having a first surface and a second surface that are disposed oppositely; a first plastic member including a first cover portion and a first protrusion; and a second plastic member including a second cover portion and a second protrusion. A height difference discontinuous interface structure is formed between the top surface of the second protrusion and the second surface of the chip, which cuts off a passage for expansion of delamination at an edge position of the chip, thereby effectively suppressing generation of the delamination.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: July 26, 2022
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Shouyu Hong, Qingdong Chen, Ganyu Zhou, Yan Chen, Xiaoni Xin, Pengkai Ji
  • Patent number: 11393744
    Abstract: Provided is a semiconductor package in which a bonding structure is formed using metal grains included in metal powder layers having a coefficient of thermal expansion (CTE) similar with those of a substrate and a conductor so as to minimize generation of cracks and to improve reliability of bonded parts.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: July 19, 2022
    Assignee: JMJ Korea Co., Ltd.
    Inventor: Yun Hwa Choi
  • Patent number: 11387096
    Abstract: A method for forming sequencing flow cells can include providing a semiconductor wafer covered with a dielectric layer, and forming a patterned layer on the dielectric layer. The patterned layer has a differential surface that includes alternating first surface regions and second surface regions. The method can also include attaching a cover wafer to the semiconductor wafer to form a composite wafer structure including a plurality of flow cells. The composite wafer structure can then be singulated to form a plurality of dies. Each die forms a sequencing flow cell. The sequencing flow cell can include a flow channel between a portion of the patterned layer and a portion of the cover wafer, an inlet, and an outlet. Further, the method can include functionalizing the sequencing flow cell to create differential surfaces.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: July 12, 2022
    Assignee: MGI Tech Co., Ltd.
    Inventors: Shifeng Li, Jian Gong, Yan-You Lin, Cheng Frank Zhong
  • Patent number: 11387178
    Abstract: An example of a printable electronic component includes a component substrate having a connection post side and an opposing contact pad side. The component can include one or more non-planar, electrically conductive connection posts protruding from the connection post side of the component substrate. Each of the one or more connection posts can have a peak area smaller than a base area. The component can include one or more non-planar, electrically conductive exposed component contact pads disposed on (e.g., directly on, indirectly on, or in) the contact pad side of the component substrate. Multiple components can be stacked such that connection post(s) of one are in contact with non-planar contact(s) of one or more others.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: July 12, 2022
    Assignee: X-Celeprint Limited
    Inventors: Kevin G. Oswalt, Ronald S. Cok
  • Patent number: 11365115
    Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a first dielectric structure disposed over a first semiconductor substrate, where the first dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the first dielectric structure and includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. A first piezoelectric anti-stiction structure is disposed between the movable mass and the first dielectric structure, wherein the first piezoelectric anti-stiction structure includes a first piezoelectric structure and a first electrode disposed between the first piezoelectric structure and the first dielectric structure.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: June 21, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fan Hu, Chun-Ren Cheng, Hsiang-Fu Chen, Wen-Chuan Tai
  • Patent number: 11362019
    Abstract: According to an aspect of the present disclosure, a semiconductor device includes a base plate, a first semiconductor chip provided above the base plate, a bonding wire joined with the first semiconductor chip at a first joint part and having a curved part above the first joint part, a first sealing member provided from an upper surface of the base plate up to a height higher than the first joint part and lower than the curved part, the first sealing member covering the first joint part and a second sealing member provided on the first sealing member, covering the curved part, and having an elastic modulus lower than an elastic modulus of the first sealing member.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: June 14, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Daisuke Murata
  • Patent number: 11363723
    Abstract: A printed circuit board for an electric component contains an electrically insulating substrate which has a surface and at least one electrically conductive conductor track formed within the substrate. The surface of the substrate has a sealing region which is arranged and/or configured such that the sealing region is flat and/or the substrate has a homogenous substrate thickness in the sealing region. An overmolding which adjoins the sealing region is arranged on the surface of the substrate.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: June 14, 2022
    Assignee: Vitesco Technologies Germany GmbH
    Inventor: Johannes Bock
  • Patent number: 11348855
    Abstract: A semiconductor component includes: a semiconductor device; an insulating molded portion configured to encapsulate the semiconductor device; a terminal connected to the semiconductor device, the terminal being configured to project out from the insulating molded portion; and a cooler mounted with the insulating molded portion such that the semiconductor device is cooled; wherein a recessed portion is formed in a surface of the cooler on which the insulating molded portion is mounted so as to extend from a position facing the terminal to a position at inner side of an end portion of the insulating molded portion.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: May 31, 2022
    Assignee: CALSONIC KANSEI CORPORATION
    Inventors: Yutaka Satou, Yasuyuki Ooi
  • Patent number: 11342249
    Abstract: The semiconductor device of the present embodiment includes a lead frame having a projection portion, the projection portion having an upper face and a side face, a semiconductor chip provided above the projection portion, and a bonding material provided between the projection portion and the semiconductor chip, the bonding material being in contact with the upper face and the side face, the bonding material bonding the lead frame and the semiconductor chip.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: May 24, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Masanari Seki, Daisuke Koike, Masahiko Hori
  • Patent number: 11340667
    Abstract: An electronic device includes a substrate including an input terminal arranged a plurality of terminals, a wiring substrate having a flexibility connected to the input terminal part. The wiring substrate includes a base film, a cover film covering the base film, a plurality of wirings between the base film and the cover film, a connection part, and a first region bent in a first the one side and a second region adjacent to the first region. The second region of the connection part includes a first connection terminal group connected to the plurality of wirings, a second connection terminal group, and a dummy terminal group between the first connection terminal group. The first region is provided with an opening through the base film and the cover film, the second region overlaps the input terminal part, and the dummy terminal group and the opening are adjacent to each other.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: May 24, 2022
    Assignee: Japan Display Inc.
    Inventors: Keisuke Asada, Hideaki Abe, Kota Uogishi, Kazuyuki Yamada