Housing Or Package Patents (Class 257/678)
  • Patent number: 11031341
    Abstract: A device and method of utilizing an interconnect bridge to electrically couple two semiconductor dies located on different surfaces. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a substrate to a semiconductor die on a motherboard are shown. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a top surface of a substrate to a semiconductor die on a bottom surface of a substrate are shown. Methods of electrically coupling semiconductor dies on different surfaces using interconnect bridges are shown.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Md Altai Hossain, Kevin J Doran, Yu Amos Zhang, Zhiguo Qian
  • Patent number: 11031313
    Abstract: A semiconductor device includes: a semiconductor module including a module main body having first and second main surfaces which are opposite to each other, and a terminal protruding from a side surface of the module main body and bent toward the first main surface; a mounting board placed on the first main surface side and connected to the terminal; a heat radiation fin placed on the second main surface side; and a screw fitting a fitting portion of the module main body from the first main surface side to the heat radiation fin, wherein the mounting board is provided with an opening at a portion facing the fitting portion, and a type of a product is printed on the first main surface and exposed from the opening of the mounting board.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: June 8, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Takuya Shiraishi
  • Patent number: 11031322
    Abstract: There is provided a semiconductor device, including: a semiconductor element which includes an element main surface and an element rear surface that face opposite sides in a thickness direction and in which a first electrode and a second electrode are formed on the element main surface; a first conductive member electrically connected to the first electrode; a second conductive member electrically connected to the second electrode; and a sealing resin configured to cover part of the first conductive member, part of the second conductive member, and the semiconductor element.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: June 8, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Yoshikatsu Miura
  • Patent number: 11032953
    Abstract: An electronic assembly includes a first printed circuit board (PCB), a second PCB, and a grounding shield. The first PCB includes a first plurality of electronic components and a first conductive layer. The second PCB includes a second plurality of electronic components and a second conductive layer. The grounding shield is electrically connected between the first conductive layer of the first PCB and the second conductive layer of the second PCB to electrically connect the first PCB and the second PCB. The first PCB and the second PCB are arranged in a stack such that the first conductive layer and the second conductive layer mutually shield at least one of the first plurality of electronic components and at least one of the second plurality of electronic components from electromagnetic interference.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: June 8, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Jason Allen Harrigan
  • Patent number: 11018109
    Abstract: A power semiconductor module, including a housing; a power semiconductor chip within the housing; power terminals protruding from the housing and electrically interconnected with power electrodes of the semiconductor chip; and auxiliary terminals protruding from the housing and electrically interconnected with a gate electrode and one of the power electrodes; wherein three auxiliary terminals are arranged in a coaxial auxiliary terminal arrangement, which comprises an inner and two outer auxiliary terminals, which are arranged on opposing sides of the inner auxiliary terminal. The inner auxiliary terminal is electrically interconnected with the gate electrode or one of the power electrodes and the two outer auxiliary terminals are electrically connected with the other one of the gate electrode and the one of the power electrodes.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: May 25, 2021
    Assignees: ABB Power Grids Switzerland AG, Audi AG
    Inventors: Didier Cottet, Felix Traub, Jürgen Schuderer, Andreas Apelsmeier, Johann Asam
  • Patent number: 11011690
    Abstract: An LED chip module includes a first electrode plate and a second electrode plate. A first set of LED chip and a second set of LED chip are respectively set on the first electrode plate and the second electrode plate. The second set of LED chip is electrically connected to the first set of LED chip. A plastic shell is fixedly connected to the first electrode plate and the second electrode plate by injection molding to make the first electrode plate and the second electrode plate keep a predetermined space between each other and make a lower surface of the first electrode plate and a lower surface of the second electrode plate be respectively connected to two different polarity terminals of the power supply to drive the first set of LED chip and the second set of LED chip to emit light.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: May 18, 2021
    Assignee: XIAMEN ECO LIGHTING CO. LTD.
    Inventors: Liangliang Cao, Huiwu Chen, Qiyuan Wang
  • Patent number: 10991684
    Abstract: A three-dimensional stacked integrated circuit (3D SIC) that can have at least a first 3D XPoint (3DXP) die and, in some examples, can have at least a second 3DXP die too. In such examples, the first 3DXP die and the second 3DXP die can be stacked. The 3D SIC can be partitioned into a plurality of columns that are perpendicular to each of the stacked dies. In such examples, when a first column of the plurality of columns is determined as failing, data stored in the first column can be replicated to a second column of the plurality of columns. Also, for example, when a part of a first column of the plurality of columns is determined as failing, data stored in the part of the first column can be replicated to a corresponding part of a second column of the plurality of columns.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: April 27, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Tony M. Brewer
  • Patent number: 10989396
    Abstract: An illumination device includes a supporting base, and a light-emitting element inserted in the supporting base. The light-emitting element includes a substrate having a supporting surface and a side surface, a light-emitting chip disposed on the supporting surface, and a first wavelength conversion layer covering the light-emitting chip and only a portion of the supporting surface without covering the side surface.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: April 27, 2021
    Assignee: EPISTAR CORPORATION
    Inventors: Chih-Ping Ho, Chih-Wei Liao, Shyi-Ming Pan
  • Patent number: 10991645
    Abstract: A wiring substrate includes: a substrate; an oxide film including an oxide of one or both of Ti and Zr, the oxide film being formed on a surface of the substrate; an alloy film including an alloy of one or any combination of Ni, Co, and W with Cu, the alloy film being formed on the oxide film; and a Cu layer formed on the alloy film.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: April 27, 2021
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Yoko Nakabayashi
  • Patent number: 10991665
    Abstract: A semiconductor package and a packaged electronic device are described. The semiconductor package has a foundation layer and a planar filtering circuit. The circuit is formed in the foundation layer to provide EMI/RFI mitigation. The circuit has one or more conductive traces that are patterned to form an equivalent circuit of inductors and capacitors. The one or more conductive traces include planar metal shapes, such as meanders, loops, inter-digital fingers, and patterned shapes, to reduce the z-height of the package. The packaged electronic device has a semiconductor die, a foundation layer, a motherboard, a package, and the circuit. The circuit removes undesirable interferences generated from the semiconductor die. The circuit has a z-height that is less than a z-height of solder balls used to attach the foundation layer to the motherboard. A method of forming a planar filtering circuit in a foundation layer is also described.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: April 27, 2021
    Assignee: Intel Corporation
    Inventors: Hao-Han Hsu, Dong-Ho Han, Steven C. Wachtman, Ryan K. Kuhlmann
  • Patent number: 10985032
    Abstract: A power MOSFET includes a substrate, a dielectric layer, solder balls, first and second patterned-metal layers. The substrate includes an active surface, a back surface, a source region and a gate region on the active surface, and a drain region on the back surface. The first patterned-metal layer disposed on the active surface includes a source electrode, a gate electrode, a drain electrode and a connecting trace. The source and gate electrodes electrically connect the source and gate regions. The connecting trace located at an edge of the substrate electrically connects the drain electrode. The dielectric layer disposed on the active surface exposes the first patterned-metal layer. The second patterned-metal layer includes UBM layers covering the source, gate and drain electrodes and a connecting metal layer covering the connecting trace and extending to the edge to electrically connect the drain region. The solder balls are disposed on the UBM layers.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: April 20, 2021
    Assignee: Excelliance MOS Corporation
    Inventor: Yi-Chi Chang
  • Patent number: 10985087
    Abstract: A wiring board has a metal-made base having a front surface and a back surface, an insulating frame body bonded to the front surface of the base through a bonding layer made of bonding material, a mounting area where a component is supposed to be mounted on the front surface of the base, and a restriction portion formed by a groove or a protrusion that is provided on the front surface of the base or by a combination of the groove and the protrusion. The restriction portion is arranged in at least a part of an area between the mounting area and the frame body on the front surface in plan view.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: April 20, 2021
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventors: Yosuke Imoto, Shinichiro Haneishi, Kenji Suzuki, Norihiko Kawai, Naoki Kito
  • Patent number: 10971477
    Abstract: A device is provided, including: a first device package including: a first redistribution structure including a first redistribution line and a second redistribution line; a die on the first redistribution structure; a first via coupled to a first side of the first redistribution line; a second via coupled to a first side of the second redistribution line and extending through the second redistribution line; an encapsulant surrounding the die, the first via, and the second via; and a second redistribution structure over the encapsulant, the second redistribution structure electrically connected to the die, the first via, and the second via; a first conductive connector coupled to a second side of the first redistribution line, the first conductive connector disposed along a different axis than a longitudinal axis of the first via; and a second conductive connector coupled to a second side of the second redistribution line, the second conductive connector disposed along a longitudinal axis of the second via.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Ming Hung Tseng, Yen-Liang Lin, Tzu-Sung Huang, Tin-Hao Kuo, Hao-Yi Tsai
  • Patent number: 10971483
    Abstract: A semiconductor package and method of manufacturing the same are provided. A semiconductor package includes an interconnect layer comprising first conductive pads configured as bond pads and second conductive pads configured as test pads, a plurality of conductive pillars over the interconnect layer, and a first semiconductor die bonded to the interconnect layer through the first conductive pads. The semiconductor package also includes an integrated passive device bonded to the interconnect layer through the first conductive pads, wherein the integrated passive device and the first semiconductor die are disposed on a same side of the interconnect layer, a second semiconductor die electrically coupled to the conductive pillars, and an encapsulating material surrounding the first semiconductor die, the integrated passive device and the conductive pillars.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shin-Puu Jeng, Jui-Pin Hung, Feng-Cheng Hsu
  • Patent number: 10964670
    Abstract: Disclosed are semiconductor packages and methods of manufacturing the same. The method of manufacturing a semiconductor package may include providing a carrier substrate having a trench formed on a first top surface of the carrier substrate, providing a first semiconductor chip on the carrier substrate, mounting at least one second semiconductor chip on a second top surface of the first semiconductor chip, coating a mold member to surround a first lateral surface of the first semiconductor chip and a second lateral surface of the at least one second semiconductor chip, and curing the mold member to form a mold layer. The trench may be provided along a first edge of the first semiconductor chip. The mold member may cover a second edge of a bottom surface the first semiconductor chip.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: March 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Taehyeong Kim, Young Lyong Kim, Geol Nam
  • Patent number: 10966336
    Abstract: The invention relates to an electrical equipment, in particular for electrical or hybrid vehicles, comprising a casing, said casing comprising a casing element comprising a side wall and defining an inner space. The side wall of the casing element comprises a material offset towards the inner space thereof forming a zone for connecting the positive terminal and the negative terminal of the electrical energy source such that said material offset overlaps the first electrical conductor and the second electrical conductor only making visible, from the outside of said side wall, the positive visible terminal and the negative visible terminal.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: March 30, 2021
    Assignee: VALEO SIEMENS EAUTOMOTIVE FRANCE SAS
    Inventors: Guillaume Tramet, Roger Deniot
  • Patent number: 10956645
    Abstract: The place and route stage for a hard macro is modified to assign a more robust power-grid tier to a critical path for a hard macro and to assign a less robust power-grid tier to a remainder of the hard macro.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: March 23, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Joon Hyung Chung, Mikhail Popovich, Gudoor Reddy
  • Patent number: 10957618
    Abstract: Disclosed herein are apparatuses and methods for configuring a circuit board to have a plurality of die having different bottom-side electrical potential. An apparatus comprises a circuit board comprising a metallic base plate, a thermally conductive dielectric, and a plurality of metallic pads. Each of a plurality of die of the apparatus is coupled to a respective one of the plurality of metallic pads, and the plurality of die comprises a first die and a second die. Based on each of the plurality of die being coupled to a respective one of the plurality of metallic foil pads, the first die is configured to exhibit a first bottom-side electrical potential and the second die is configured to exhibit a second bottom-side electrical potential. The apparatus is further configured to conduct heat from the plurality of die away from the plurality of die via at least the metallic base plate, the thermally conductive dielectric, and the plurality of metallic pads.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: March 23, 2021
    Assignee: Apex Microtechnology, Inc.
    Inventors: Kirby Gaulin, Emily Sataua, Alan Varner
  • Patent number: 10957661
    Abstract: An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. The post includes a conductor member. An upper portion of the post extends above an upper surface of the substrate. An exterior surface of the post associated with the upper portion is in contact with a dielectric layer. The dielectric layer is disposed on the upper surface of the substrate and adjacent to the post to provide a dielectric collar for the post. An exterior surface of the dielectric collar is in contact with a conductor layer. The conductor layer is disposed adjacent to the dielectric collar to provide a metal collar for the post, where a top surface of each of the conductor member, the dielectric collar and the metal collar have formed thereon a bond structure for interconnection of the metal collar and the conductor member.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: March 23, 2021
    Assignee: Invensas Corporation
    Inventor: Cyprian Emeka Uzoh
  • Patent number: 10959322
    Abstract: A printed circuit board comprises a board main body, a sensor, an external connection pad, and a hollow-structured electrical conductor. The board main body has a top face and a bottom face opposite the top face. The sensor is mounted on one of the top face and the bottom face of the board main body. The external connection pad is provided on the top face or the bottom face of the board main body opposite the sensor. The hollow-structured electrical conductor extends through the board main body and electrically connects the sensor to the external connection pad.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: March 23, 2021
    Assignee: Tyco Electronics Japan G.K.
    Inventors: Kenta Sato, Heewon Jeong
  • Patent number: 10951798
    Abstract: A small-scale camera device with heat-dissipating properties includes a pedestal bracket and a camera module mounted on the pedestal bracket. The pedestal bracket includes a top plate and a side plate extending perpendicularly from edges of the top plate. The side plate includes an inner side surface and an outer side surface opposite to the inner side surface. The bottom of the side plate defines a plurality of first receiving recesses, each of the first receiving recesses carries a heat dissipation member.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: March 16, 2021
    Assignee: TRIPLE WIN TECHNOLOGY(SHENZHEN) CO. LTD.
    Inventors: Xiao-Mei Ma, Shin-Wen Chen, Sheng-Jie Ding
  • Patent number: 10937666
    Abstract: A method for manufacturing a lead frame including: punching a metal plate disposed on a die with a punch in a direction from the metal plate toward a die side to form a punched metal, the punched metal including at least one electrode, at least one hanger lead separated from the at least one electrode, and an outer frame connected to the at least one electrode and the at least one hanger lead; and stamping at least part of a corner of an end of the at least one hanger lead, the corner being on a side corresponding to the die side, with a vertically split mold to form at least one chamfered surface.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: March 2, 2021
    Assignee: NICHIA CORPORATION
    Inventor: Mayumi Fukuda
  • Patent number: 10937771
    Abstract: A semiconductor package is provided which includes a redistribution substrate, an interconnect substrate on the redistribution substrate, a metal layer on the semiconductor chip, a semiconductor chip on the redistribution substrate and in the hole of the interconnect substrate, and a mold layer in a gap between the semiconductor chip and the interconnect substrate. The interconnect substrate includes a hole penetrating thereinside. The interconnect substrate includes base layers and a conductive member extending through the base layers. A top surface of the interconnect substrate is positioned either above or below the level of the top surface of the metal layer.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: March 2, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jichul Kim, Jae Choon Kim, Hansung Ryu, KyongSoon Cho, YoungSang Cho, Yeo-Hoon Yoon
  • Patent number: 10930576
    Abstract: A micro-electromechanical system (MEMS) device includes a support structure comprising a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic core, a conductive layer coupled to the first adhesion layer, a second adhesion layer coupled to the conductive layer, and a barrier layer coupled to the second adhesion layer. The support structure defines a cavity. The MEMS device also includes a III-V membrane coupled to a portion of the support structure. A portion of the III-V membrane is suspended over the cavity defined by the support structure and defines a MEMS structure.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: February 23, 2021
    Assignee: QROMIS, INC.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Shari Farrens, Ozgur Aktas
  • Patent number: 10930586
    Abstract: An integrated fan-out package includes a die, an insulating encapsulation, a redistribution circuit structure, conductive terminals, and barrier layers. The insulating encapsulation encapsulates the die. The redistribution circuit structure includes a first redistribution conductive layer on the insulating encapsulation, a first inter-dielectric layer covering the first redistribution conductive layer, and a second redistribution conductive layer on the first inter-dielectric layer. The first redistribution conductive layer includes conductive through vias extending from a first surface of the insulating encapsulation to a second surface of the insulating encapsulation. The first inter-dielectric layer includes contact openings, portions of the second redistribution conductive layer filled in the contact openings are in contact with the first redistribution conductive layer and offset from the conductive through vias.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Wen Wu, Hung-Jui Kuo, Ming-Che Ho
  • Patent number: 10920140
    Abstract: Provided is a method for producing a fluorescent material, including: preparing a raw material mixture including a compound containing at least one rare earth element Ln selected from the group consisting of Y, Gd, La, Lu, Sc and Sm, a compound containing at least one Group 13 element selected from Al and Ga, a compound containing Tb, a compound containing Ce and a compound containing Eu, wherein the raw material mixture contains each compound such that each element satisfies a composition represented by the following formula (I): (Ln1-a-b-cTbaCebEUc)3(Al1-dGad)5O12 (I), wherein a, b, c and d satisfy 0.25?a<1, 0.008×10?2?b?1.5×10?2, 0.012×10?2?c?2×10?2, and 0?d?0.85, and heat-treating the raw material mixture to obtain the fluorescent material.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: February 16, 2021
    Assignee: NICHIA CORPORATION
    Inventor: Tomokazu Suzuki
  • Patent number: 10916829
    Abstract: A semiconductor package structure having an antenna module includes: a substrate, having at least one via hole running through the substrate; a rewiring layer, disposed on a surface of the substrate; a metal bump, disposed on and electrically connected to the rewiring layer; a semiconductor chip, disposed on and electrically connected to the rewiring layer; a conductive column, filling the via hole; a plastic packaging material layer, surrounding the metal bump and the semiconductor chip; and an antenna module, electrically connected to the metal bump through the conductive column and the rewiring layer.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: February 9, 2021
    Assignee: SJ Semiconductor (Jiangyin) Corporation
    Inventors: Yenheng Chen, Chengtar Wu, Chengchung Lin
  • Patent number: 10910299
    Abstract: Provided are a method of manufacturing a semiconductor package substrate, a semiconductor package substrate manufactured using the method of manufacturing a semiconductor package substrate, a method of manufacturing a semiconductor package, and a semiconductor package manufactured using the method of manufacturing a semiconductor package. The method of manufacturing a semiconductor package substrate includes forming first grooves or first trenches in a bottom surface of a base substrate having a top surface and the bottom surface and formed of a conductive material; filling the first grooves or trenches with resin; curing the resin; removing exposed portions of the resin overfilled in the first grooves or trenches; etching the top surface of the base substrate to expose at least portions of the resin filled in the first grooves or trenches; and forming a second groove or a second trench in the bottom surface of the base substrate.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: February 2, 2021
    Assignee: HAESUNG DS CO., LTD.
    Inventors: In Seob Bae, Sung Il Kang, Dong Jin Yoon
  • Patent number: 10893623
    Abstract: The invention relates to a method for obtaining a leaktight electronic device according to which provision is made for steps consisting in: a) placing an electronic module (3) inside a mould (100), b) holding said electronic module away from the walls (101) of said mould with the aid of holding claws (200) each exhibiting an end which protrudes towards the interior of the mould, c) injecting into said mould a thermoplastic material able to harden so as to form a leaktight shell, said holding claws retracting towards the exterior of the mould during the injection of said thermoplastic material.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: January 12, 2021
    Assignee: VALEO COMFORT AND DRIVING ASSISTANCE
    Inventor: Marc David
  • Patent number: 10892216
    Abstract: A first insulation layer includes a concave portion formed in a lower surface thereof. A first wiring layer is formed in the concave portion. A protective insulation layer has an opening configured to expose a part of the first wiring layer and is stacked on the lower surface of the first insulation layer. An adhesion layer is interposed between the first wiring layer and the protective insulation layer and has higher adhesiveness with the protective insulation layer than the first wiring layer. The first wiring layer includes a pad portion formed in the concave portion and a protrusion protruding from a portion of a lower surface of the pad portion into the opening. The adhesion layer is formed to cover the lower surface of the pad portion and a side surface of the protrusion and to expose a lower end face of the protrusion.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: January 12, 2021
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Jun Furuichi
  • Patent number: 10886242
    Abstract: An antenna module includes an antenna substrate, a first semiconductor package, disposed on the antenna substrate, including a first connection member including one or more first redistribution layers, electrically connected to the antenna substrate, and a first semiconductor chip disposed on the first connection member, and a second semiconductor package, disposed on the antenna substrate to be spaced apart from the first semiconductor package, including a second connection member including one or more second redistribution layers, electrically connected to the antenna substrate, and a second semiconductor chip disposed on the second connection member. The first semiconductor chip and the second semiconductor chip are different types of semiconductor chips.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: January 5, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Doo Il Kim, Won Wook So, Young Sik Hur, Jung Chul Gong
  • Patent number: 10880994
    Abstract: An apparatus is provided which comprises: a processor die; a processor substrate having a region extended away from the processor die, wherein the processor die is mounted on the processor substrate, wherein the extended region has at least one signal interface which is connectable to a top-side connector; and an interposer coupled to the processor substrate and a motherboard.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Russell S. Aoki, Jeffory L. Smalley, Jonathan W. Thibado
  • Patent number: 10879207
    Abstract: A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: December 29, 2020
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Liang Wang, Rajesh Katkar, Javier A. DeLaCruz, Arkalgud R. Sitaram
  • Patent number: 10881024
    Abstract: An electronic device that includes a printed board with a surface over which a heating element is mounted, and a hermetically sealed housing that has thermal conductivity and accommodates the printed board therein. The printed board has a through hole therein, and a projection on a surface of the housing is thermally coupled to the heating element through the through hole.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: December 29, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Taku Ogura
  • Patent number: 10865102
    Abstract: The present disclosure relates to a MEMS package having different trench depths, and a method of fabricating the MEMS package. In some embodiments, a cap substrate is bonded to a device substrate. The cap substrate comprises a first trench, a second trench, and an edge trench recessed from at a front-side surface of the cap substrate. A stopper is disposed within the first trench and raised from a bottom surface of the first trench. The stopper has a top surface lower than the front-side surface of the cap substrate.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Chuan Tai, Fan Hu
  • Patent number: 10865329
    Abstract: The present invention relates to an adhesive film for a semiconductor that can more easily bury unevenness such as through wires of a semiconductor substrate or a wire attached to a semiconductor chip and the like, and yet can be applied to various cutting methods without specific limitations to realize excellent cuttability, thus improving reliability and efficiency of a semiconductor packaging process.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: December 15, 2020
    Assignee: LG CHEM, LTD.
    Inventors: Hee Jung Kim, Se Ra Kim, Jung Hak Kim, Seung Hee Nam, Jung Ho Jo, Kwang Joo Lee, Young Kook Kim
  • Patent number: 10861803
    Abstract: LTCC structure extends between top and bottom surfaces, with at least one cavity being formed within the structure and extending from the top surface inwardly in the direction of the bottom surface. A die is disposed within the cavity a top surface of the die is positioned flush with the top surface of the package, resulted in the shortest length of the wire box connecting the die with the LTCC structure and ultimately reducing the inductance.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: December 8, 2020
    Assignee: Scientific Components Corporation
    Inventor: Aaron Vaisman
  • Patent number: 10861709
    Abstract: Provided is a method of evaluating the impurity gettering capability of an epitaxial silicon wafer, which allows for very precise evaluation of the impurity gettering behavior of a modified layer formed immediately under an epitaxial layer, the modified layer containing carbon in solid solution. In this method, a modified layer located immediately under an epitaxial layer, the modified layer containing carbon in solid solution, is analyzed by three-dimensional atom probe microscopy, and the impurity gettering capability of the modified layer is evaluated based on a three-dimensional map of carbon in the modified layer, obtained by the analysis.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: December 8, 2020
    Assignee: SUMCO CORPORATION
    Inventors: Satoshi Shigematsu, Ryosuke Okuyama, Kazunari Kurita
  • Patent number: 10859814
    Abstract: In an electro-optical device, a mirror that is formed on an element substrate is sealed by a frame shaped spacer and a plate-like light-transmitting cover which is adhered to the spacer. An inorganic barrier layer is formed on an outer face of the spacer and a side face of the light-transmitting cover, and the boundary of the spacer and the light-transmitting cover is covered by the inorganic barrier layer.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: December 8, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Terunao Hanaoka, Shuhei Yamada
  • Patent number: 10856450
    Abstract: Technology leading to a size reduction in a power conversion apparatus comprising a cooling function and technology relating to enhancing productivity and enhancing reliability necessary for commercial production are provided. Series circuits comprising an upper arm and lower arm of an inverter circuit are built in a single semiconductor module 500. The semiconductor module has cooling metal on two sides. An upper arm semiconductor chip and lower arm semiconductor chip are wedged between the cooling metals. The semiconductor module is inserted inside a channel case main unit 214. A DC positive electrode terminal 532, a DC negative electrode terminal 572, and an alternating current terminal 582 of a semiconductor chip are disposed in the semiconductor module. The DC terminals 532 and 572 are electrically connected with a terminal of a capacitor module. The alternating current terminal 582 is electrically connected with a motor generator via an AC connector.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: December 1, 2020
    Assignee: HITACHI, LTD.
    Inventors: Takeshi Tokuyama, Kinya Nakatsu, Ryuichi Saito
  • Patent number: 10854552
    Abstract: A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun Yi Wu, Chen-Hua Yu, Chung-Shi Liu, Chien-Hsun Lee
  • Patent number: 10845387
    Abstract: A probe card device includes an upper die unit, a lower die unit, a spacer sandwiched between the upper and lower die units, an impedance adjusting member, and conductive probes. The upper die unit includes a first die and a second die spaced apart from the first die. The first die has a penetrating hole, and the second die has a circuit layer. The impedance adjusting member is disposed on the second die and is electrically coupled to the circuit layer. Each of the conductive probes passes through the upper die unit, the spacer, and the lower die unit. At least one of the conductive probes includes an upper contacting segment protruding from the upper die unit and an extending arm connected to the upper contacting segment. The extending arm is abutted against the circuit layer by passing through the penetrating hole.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: November 24, 2020
    Assignee: CHUNGHWA PRECISION TEST TECH. CO., LTD.
    Inventors: Wen-Tsung Lee, Kai-Chieh Hsieh, Chao-Hui Tseng, Hsien-Yu Wang
  • Patent number: 10840172
    Abstract: A leadframe, that is to be incorporated into a semiconductor housing is provided. The leadframe may include a first die pad, a second die pad and a plurality of contact pads. A lower surface of the contact pads and a lower surface of the first die pad are arranged in a first plane. An upper surface of the second die pad is arranged in a second plane distant from the first plane by an overall thickness of the semiconductor package.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: November 17, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Bemmerl, Azlina Kassim, Nurfarena Othman
  • Patent number: 10840407
    Abstract: A method for manufacturing an electronic device comprises providing a substrate, applying a first bonding material on the substrate, bonding a plurality of light emitting units to the substrate through the first bonding material, identifying a defective light emitting unit from the plurality of light emitting units, removing the defective light emitting unit from a corresponding position on the substrate, applying a second bonding material, and bonding a repairing light emitting unit to the corresponding position through the second bonding material.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: November 17, 2020
    Assignee: InnoLux Corporation
    Inventors: Jia-Yuan Chen, Tsung-Han Tsai
  • Patent number: 10840210
    Abstract: A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Wei Zhou, Bret K. Street, Benjamin L. McClain, Mark E. Tuttle
  • Patent number: 10840229
    Abstract: A semiconductor device assembly that includes first and second semiconductor devices connected directly to a first side of a substrate and a plurality of interconnects connected to a second side of the substrate. The substrate is configured to enable the first and second semiconductor devices to communicate with each other through the substrate. The substrate may be a silicon substrate that includes complementary metal-oxide-semiconductor (CMOS) circuits. The first semiconductor device may be a processing unit and the second semiconductor device may be a memory device, which may be a high bandwidth memory device. A method of making a semiconductor device assembly includes applying CMOS processing to a silicon substrate, forming back end of line (BEOL) layers on a first side of the substrate, attaching a memory device and a processing unit directly to the BEOL layers, and forming a redistribution layer on the second side of the substrate.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: November 17, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Chan H. Yoo, Owen R. Fay
  • Patent number: 10832790
    Abstract: A storage device may include a controller performing non data word line (NDWL) maintenance in sub block mode (SBM). The NDWL maintenance in SBM can include proactive select gate drain (SGD) detection and phased SGD correction. For example, when a block reaches a PE cycle threshold value, SGD phased correction occurs upon detection of an error, by determining whether a sister sub block of the selected block contains data. If the sister sub block contains data, the data is transferred from the sister sub block, and then the block and sister sub block undergo correction for NDLW maintenance.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: November 10, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Shakti Bhatnagar, Shivam Mishra, Hitesh Golechchha
  • Patent number: 10833024
    Abstract: A substrate structure includes a substrate body, at least one first mold area and at least one second mold area. The substrate body has a first surface and a second surface opposite to the first surface, and defines at least one first through hole extending through the substrate body. The first mold area is disposed on the first surface of the substrate body. The second mold area is disposed on the second surface of the substrate body, wherein the first mold area is in communication with the second mold area through the first through hole.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: November 10, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chang Yi Yang
  • Patent number: 10825786
    Abstract: A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: November 3, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng Lin, Soon Wei Wang, Chee Hiong Chew, Francis J. Carney
  • Patent number: 10825821
    Abstract: A computing device includes a wafer having multiple layers, the wafer including a top layer and sublayers disposed below it, the sublayers including one or more memory devices. The computing device also includes two or more shaped retainer elements shaped to mate with and at least partially surround at least the top of the wafer and in electrical contact with one or more chips disposed on a top of the top layer and a holding device that mates with the retainer elements to provide at least power to the retaining elements. So arranged, the wafer may be cooled.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: November 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Babar A. Khan, Arvind Kumar, Kamal K. Sikka