Housing Or Package Patents (Class 257/678)
  • Patent number: 11365115
    Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a first dielectric structure disposed over a first semiconductor substrate, where the first dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the first dielectric structure and includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. A first piezoelectric anti-stiction structure is disposed between the movable mass and the first dielectric structure, wherein the first piezoelectric anti-stiction structure includes a first piezoelectric structure and a first electrode disposed between the first piezoelectric structure and the first dielectric structure.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: June 21, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fan Hu, Chun-Ren Cheng, Hsiang-Fu Chen, Wen-Chuan Tai
  • Patent number: 11362019
    Abstract: According to an aspect of the present disclosure, a semiconductor device includes a base plate, a first semiconductor chip provided above the base plate, a bonding wire joined with the first semiconductor chip at a first joint part and having a curved part above the first joint part, a first sealing member provided from an upper surface of the base plate up to a height higher than the first joint part and lower than the curved part, the first sealing member covering the first joint part and a second sealing member provided on the first sealing member, covering the curved part, and having an elastic modulus lower than an elastic modulus of the first sealing member.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: June 14, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Daisuke Murata
  • Patent number: 11363723
    Abstract: A printed circuit board for an electric component contains an electrically insulating substrate which has a surface and at least one electrically conductive conductor track formed within the substrate. The surface of the substrate has a sealing region which is arranged and/or configured such that the sealing region is flat and/or the substrate has a homogenous substrate thickness in the sealing region. An overmolding which adjoins the sealing region is arranged on the surface of the substrate.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: June 14, 2022
    Assignee: Vitesco Technologies Germany GmbH
    Inventor: Johannes Bock
  • Patent number: 11348855
    Abstract: A semiconductor component includes: a semiconductor device; an insulating molded portion configured to encapsulate the semiconductor device; a terminal connected to the semiconductor device, the terminal being configured to project out from the insulating molded portion; and a cooler mounted with the insulating molded portion such that the semiconductor device is cooled; wherein a recessed portion is formed in a surface of the cooler on which the insulating molded portion is mounted so as to extend from a position facing the terminal to a position at inner side of an end portion of the insulating molded portion.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: May 31, 2022
    Assignee: CALSONIC KANSEI CORPORATION
    Inventors: Yutaka Satou, Yasuyuki Ooi
  • Patent number: 11342249
    Abstract: The semiconductor device of the present embodiment includes a lead frame having a projection portion, the projection portion having an upper face and a side face, a semiconductor chip provided above the projection portion, and a bonding material provided between the projection portion and the semiconductor chip, the bonding material being in contact with the upper face and the side face, the bonding material bonding the lead frame and the semiconductor chip.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: May 24, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Masanari Seki, Daisuke Koike, Masahiko Hori
  • Patent number: 11340667
    Abstract: An electronic device includes a substrate including an input terminal arranged a plurality of terminals, a wiring substrate having a flexibility connected to the input terminal part. The wiring substrate includes a base film, a cover film covering the base film, a plurality of wirings between the base film and the cover film, a connection part, and a first region bent in a first the one side and a second region adjacent to the first region. The second region of the connection part includes a first connection terminal group connected to the plurality of wirings, a second connection terminal group, and a dummy terminal group between the first connection terminal group. The first region is provided with an opening through the base film and the cover film, the second region overlaps the input terminal part, and the dummy terminal group and the opening are adjacent to each other.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: May 24, 2022
    Assignee: Japan Display Inc.
    Inventors: Keisuke Asada, Hideaki Abe, Kota Uogishi, Kazuyuki Yamada
  • Patent number: 11335659
    Abstract: Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes forming a first underbump metallization layer on a semiconductor chip is provided. The first underbump metallization layer has a hub, a first portion extending laterally from the hub, and a spoke connecting the hub to the first portion. A polymer layer is applied to the first underbump metallization layer. The polymer layer includes a first opening in alignment with the hub and a second opening in alignment with the spoke. A portion of the spoke is removed via the second opening to sever the connection between the hub and the first portion.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: May 17, 2022
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Roden R. Topacio, Suming Hu, Yip Seng Low
  • Patent number: 11335840
    Abstract: An optical semiconductor device package includes a circuit board in which a first metal, a second metal, and a third metal are sequentially stacked in an optical semiconductor element mounting region. The first metal has a first standard electrode potential. The second metal is disposed on a portion of an upper surface of the first metal and has a second standard electrode potential that is greater than the first standard electrode potential. The third metal is disposed on the upper surface of the first metal and an upper surface of the second metal and has a third standard electrode potential that is greater than the first standard electrode potential and less than the second standard electrode potential.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: May 17, 2022
    Assignee: PANASONIC INTEILECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takahiro Fukunaga, Akinobu Kittaka
  • Patent number: 11329031
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a conductive feature penetrating through the package layer. The chip package further includes an interfacial layer the interfacial layer continuously surrounds the conductive feature. The interfacial layer is between the conductive feature and the package layer, and the interfacial layer is made of a metal oxide material.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Pin Hung, Cheng-Lin Huang, Hsien-Wen Liu, Shin-Puu Jeng
  • Patent number: 11328973
    Abstract: A device comprises: a high temperature semiconductor device comprising a first surface, wherein the high temperature semiconductor device comprises an active area and a termination area disposed adjacent to the active area; an inorganic dielectric insulating layer disposed on the first surface, wherein the inorganic dielectric insulating layer fills a volume extending over an entirety of the termination area and comprises a thickness greater than or equal to 25 ?m and less than or equal to 500 ?m; and an electrical connector connecting the active area of the high temperature semiconductor device to an additional component of the device.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: May 10, 2022
    Assignee: General Electric Company
    Inventors: David Richard Esler, Emad A. Andarawis
  • Patent number: 11319208
    Abstract: A chip package includes a first die, a second die, a molding material, and a redistribution layer. The first die includes a first conductive pad. The second die is disposed on the first die and includes a second conductive pad. The molding material covers the first die and the second die. The molding material includes a top portion, a bottom portion, and an inclined portion adjoins the top portion and the bottom portion. The top portion is located on the second die, and the bottom portion is located on the first die. The redistribution layer is disposed along the top portion, the inclined portion, and the bottom portion. The redistribution layer is electrically connected to the first conductive pad and the second conductive pad.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: May 3, 2022
    Assignee: XINTEC INC.
    Inventors: Tsang-Yu Liu, Chaung-Lin Lai, Shu-Ming Chang
  • Patent number: 11315849
    Abstract: A semiconductor package includes a substrate including an upper surface and a side surface, an adhesive layer disposed on an edge of the upper surface of the substrate, and a stiffener including a horizontal portion disposed on the adhesive layer and extending in an horizontal direction to an outside of the substrate in a plan view and a vertical portion connected to the horizontal portion and extending vertically downwards from the horizontal portion. The vertical portion is spaced apart from the side surface of the substrate with a vertical gap extending in a vertical direction therebetween, and the outer width of the stiffener is 40 mm or more.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: April 26, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Suchang Lee, Dongok Kwak
  • Patent number: 11309192
    Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: April 19, 2022
    Assignee: Intel Corporation
    Inventors: Kristof Kuwawi Darmawikarta, Robert May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov
  • Patent number: 11309281
    Abstract: A semiconductor device assembly includes a substrate having a plurality of external connections, a first stack of semiconductor dies disposed directly over a first location on the substrate and electrically coupled to a first subset of the plurality of external connections, and a second stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. A portion of the semiconductor dies of the second stack overlaps a portion of the semiconductor dies of the first stack. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first stack and the second stack.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: April 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Enyong Tai, Hem P. Takiar, Li Wang, Hong Wan Ng
  • Patent number: 11302600
    Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a lid and outer flanges. The lid overlies the semiconductor package. The outer flanges are disposed at edges of the lid, are connected with the lid, extend from the lid towards the circuit substrate, and face side surfaces of the semiconductor package. The lid has a first region that is located over the semiconductor package and is thicker than a second region that is located outside a footprint of the semiconductor package.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: April 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Ping-Kang Huang, Sao-Ling Chiu, Tsung-Shu Lin, Tsung-Yu Chen, Chien-Yuan Huang, Chen-Hsiang Lao
  • Patent number: 11296025
    Abstract: A sensor package includes a carrier, a sensor, an interconnection structure, a conductor and a housing. The sensor is disposed on the carrier. The interconnection structure is disposed on the carrier and surrounds the sensor. The interconnection structure has a first surface facing away from the carrier. The conductor is disposed on the first carrier. The conductor having a first portion covered by the interconnection structure and a second portion exposed from the first surface of the interconnection structure. The housing is disposed on the carrier and surrounds the interconnection structure.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: April 5, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsun-Wei Chan, Shih-Chieh Tang
  • Patent number: 11296053
    Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: April 5, 2022
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventors: Cyprian Emeka Uzoh, Rajesh Katkar, Thomas Workman, Guilian Gao, Gaius Gillman Fountain, Jr., Laura Wills Mirkarimi, Belgacem Haba, Gabriel Z. Guevara, Joy Watanabe
  • Patent number: 11296197
    Abstract: An apparatus including a circuit structure including a device stratum including a plurality of transistor devices each including a first side defined by a gate electrode and an opposite second side; and a gated supply grid disposed on the second side of the structure, wherein a drain of the at least one of the plurality of transistor devices is coupled to the gated supply grid. A method including providing a supply from a package substrate to power gate transistors in a device layer of a circuit structure, the transistors coupled to circuitry operable to receive a gated supply from the power gate transistors; and distributing the gated supply from the power gate transistors to the circuitry using a grid on an underside of the device layer.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 5, 2022
    Assignee: Intel Corporation
    Inventor: Donald W. Nelson
  • Patent number: 11291107
    Abstract: An object is to suppress the temperature rise of a semiconductor element due to the heat generation of a metal wire. A semiconductor device includes a printed circuit board including a first circuit pattern and a second circuit pattern, and a semiconductor element arranged on an upper surface of the first circuit pattern, in which, in the semiconductor element, a drain electrode is arranged on an upper surface thereof and a gate electrode and a source electrode are arranged on a lower surface thereof, the gate electrode and the source electrode are bonded to the upper surface of the first circuit pattern via a first bonding material, and the drain electrode is bonded to an upper surface of the second circuit pattern via a metal member connected to the upper surface of the semiconductor element.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: March 29, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Takuya Kitabayashi
  • Patent number: 11289437
    Abstract: A semiconductor device includes a power MOS chip having a source electrode on a surface and a control chip mounted on a portion of the power MOS chip, wherein, viewing from a first outer edge of the power MOS chip extending in a first direction to the control chip, a first column bonding pad and a second column bonding pad are formed in a region of the source electrode where the control chip is not mounted, and wherein a distance between a second outer edge of the power MOS chip extending in a second direction and the first column bonding pad is longer than a distance between the second outer edge and the second column bonding pad.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: March 29, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tomoaki Ota, Makoto Tanaka
  • Patent number: 11282760
    Abstract: This disclosure provides devices and methods for 3-D device packaging with backside interconnections. One or more device elements can be hermetically sealed from an ambient environment, such as by vacuum lamination and bonding. One or more via connections provide electrical interconnection from a device element to a back side of a device substrate, and provide electrical interconnection from the device substrate to external circuitry on the back side of the device. The external circuitry can include a printed circuit board or flex circuit. In some implementations, an electrically conductive pad is provided on the back side, which is electrically connected to at least one of the via connections. In some implementations, the one or more via connections are electrically connected to one or more electrical components or interconnections, such as a TFT or a routing line.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: March 22, 2022
    Assignee: Obsidian Sensors, Inc.
    Inventors: Yaoling Pan, Tallis Young Chang, John Hyunchul Hong
  • Patent number: 11282757
    Abstract: A semiconductor device includes a semiconductor substrate and a metal structure in electrical contact with the semiconductor substrate. The metal structure has copper as a main component. An encapsulation layer includes a matrix material and a releasable copper corrosion inhibitor dispersed in the matrix material. The matrix material of the encapsulation layer at least partially covers the metal structure. A protective layer is at least partially on and in contact with a surface of the metal structure, and disposed between the metal structure and the encapsulation layer.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: March 22, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Sabine Reither, Guenter Fafilek, Silvia Larisegger
  • Patent number: 11274972
    Abstract: A semiconductor device includes a first semiconductor element, a first signal terminal group, and a second signal terminal group disposed at an interval from the first signal terminal group. The first semiconductor element includes a control signal electrode to which a control signal for the first semiconductor element is input, and a temperature signal electrode that outputs a signal corresponding to temperature of the first semiconductor element. The temperature signal electrode is connected with a temperature signal terminal included in the first signal terminal group, and the control signal electrode is connected with a first control signal terminal included in the second signal terminal group.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: March 15, 2022
    Assignee: Denso Corporation
    Inventors: Takanori Kawashima, Hitoshi Ozaki
  • Patent number: 11270972
    Abstract: Embodiments for a packaged semiconductor device and methods of making are provided herein, which includes a packaged semiconductor device including: a semiconductor die; a carrier; a plurality of electrical connections formed between the semiconductor die and the carrier; an electrical isolation layer that covers an outer surface of each of the plurality of electrical connections; and a conductive underfill structure between the semiconductor die and the carrier, and surrounding each of the plurality of electrical connections, wherein the electrical isolation layer electrically isolates each electrical connection from the conductive underfill structure.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: March 8, 2022
    Assignee: NXP B.V.
    Inventors: Nishant Lakhera, Akhilesh Kumar Singh, Chee Seng Foong
  • Patent number: 11270969
    Abstract: A semiconductor package according to an embodiment of the present invention Includes: a lead frame comprising a pad and a lead spaced apart from the pad by a regular interval; a semiconductor chip adhered on the pad; and a clip structure electrically connecting the semiconductor chip and the lead, wherein an one end of the clip structure connected to the semiconductor chip inclines with respect to upper surfaces of chip pads of the semiconductor chip and is adhered to the upper surfaces of the chip pads of the semiconductor chip. A semiconductor package according to another embodiment of the present invention includes: a semiconductor chip comprising one or more chip pads; one or more leads electrically connected to the chip pads; and a sealing member covering the semiconductor chip, wherein an one end of the lead inclines with respect to one surface of the chip pad and is adhered to the chip pad and an other end of the lead is exposed to the outside of the sealing member.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: March 8, 2022
    Assignee: JMJ Korea Co., Ltd.
    Inventors: Yun Hwa Choi, Jeonghun Cho, Young Hun Kim, Taeheon Lee
  • Patent number: 11264315
    Abstract: An electronic package with passive components located between a first substrate and a second substrate. The electronic package can include a first substrate including a device interface for communication with an electronic device. An interposer can be electrically coupled to the first substrate. A second substrate can be offset from the first substrate at a distance. The second substrate can be electrically coupled to the first substrate through the interposer. A passive component can be attached to one of the first substrate or the second substrate. The passive component can be located between the first substrate and the second substrate. A height of the passive component can be is less than the distance between the first substrate and the second substrate. The second substrate can include a die interface configured for communication with a die. The die interface can be communicatively coupled to the passive component.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: March 1, 2022
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Min Suet Lim, Jiun Hann Sir, Hoay Tien Teoh, Jimmy Huat Since Huang
  • Patent number: 11251136
    Abstract: A flip-chip die package includes a substrate, a die, a plurality of conductive bumps, and a first metal structure, where an upper surface of the die is electrically coupled, using the conductive bumps, to a surface that is of the substrate and that faces the die, and the first metal structure includes a plurality of first metal rods disposed between the substrate and the die, where each first metal rod is electrically coupled to the substrate and the die, and the first metal rods are arranged around a first active functional circuit, and the first active functional circuit includes an electromagnetic radiation capability or an electromagnetic receiving capability in the die.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: February 15, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Wei Wu, Ding Li, Hongcheng Yin, Xiongcai Kuang
  • Patent number: 11244922
    Abstract: Provided is a semiconductor device stabilizing bond properties between an electrode terminal provided on a case and an internal wiring connected to a semiconductor element. A semiconductor device includes a base part, a semiconductor element, an electrode terminal, an insulating block, and an internal wiring. The semiconductor element is mounted on the base part. The electrode terminal is held by a case surrounding an outer periphery of the semiconductor element. An end portion of the electrode terminal protrudes toward an inner side of the case. The insulating block is provided on the base part between the semiconductor element and the case. In the internal wiring, one end portion is bonded to the end portion of the electrode terminal on the insulating block, and part of a region extending from the one end portion to the other end portion is bonded to the semiconductor element.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: February 8, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takumi Shigemoto, Shohei Ogawa
  • Patent number: 11244874
    Abstract: A device (2) is formed on a main surface of a substrate (1). The main surface of the substrate (1) is bonded to the undersurface of the counter substrate (14) via the bonding member (11,12,13) in a hollow state. A circuit (17) and a bump structure (26) are formed on the top surface of the counter substrate (14). The bump structure (26) is positioned in a region corresponding to at least the bonding member (11,12,13), and has a higher height than that of the circuit (17).
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: February 8, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Koichiro Nishizawa
  • Patent number: 11227851
    Abstract: A control device and a circuit board are provided. The control device can cooperate with the circuit board, and includes a ball grid array. The ball grid array includes a plurality of power balls and a plurality of ground balls, which are jointly arranged in a ball region. The power balls and the ground balls are respectively divided into a plurality of power ball groups and a plurality of ground ball groups. One of the ground ball groups includes two ground balls and is adjacent to a power ball group. A ball pitch between the two ground balls is greater than that between one of the power balls and one of the ground balls adjacent to each other. The circuit board includes a contact pad array corresponding to the ball grid array of the control device so that the control device can be disposed on the circuit board.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: January 18, 2022
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chao-Min Lai, Ping-Chia Wang, Han-Chieh Hsieh, Tang-Hung Chang
  • Patent number: 11227808
    Abstract: A power module which inhibits disjoin between a sealing resin and an adhesive. The power module includes: an insulative substrate having a semiconductor element mounted on the top surface; a base plate joined to the rear surface of the insulative substrate; a case member with the base plate, that surrounds the insulative substrate, the case member having a bottom surface whose inner periphery portion side being in contact with a top surface of the base plate, the bottom surface being provided with an angled surface whose distance to the top surface of the base plate increases toward an outer periphery side of the base plate; an adhesive member filled between the base plate and the angled surface to adhere the base plate and the case member; and a filling member filled in a region bounded by the base plate and the case member.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: January 18, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Haruko Hitomi
  • Patent number: 11211355
    Abstract: A first alignment resin (4) is formed in an annular shape on an electrode (3) of an insulating substrate (1). First plate solder (5) having a thickness thinner than that of the first alignment resin (4) is arranged on the electrode (3) on an inner side of the annular shape of the first alignment resin (4). A semiconductor chip (6) is arranged on the first plate solder (5). The first plate solder (5) is made to melt to bond a lower surface of the semiconductor chip (6) to the electrode (3).
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: December 28, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Isao Oshima
  • Patent number: 11211263
    Abstract: Certain aspects of the present disclosure provide apparatus and techniques for partially molding packages for integrated circuits. A packaged assembly for integrated circuits includes: a substrate having at least one mold barrier between a first region on a first surface of the substrate and a second region on the first surface; a die attached to the substrate; one or more components attached to the substrate in the first region; and a first encapsulant over the one or more components in the first region, wherein the at least one mold barrier is configured to block a portion of the first encapsulant from moving from the first region of the substrate to the second region of the substrate during an application of the first encapsulant.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: December 28, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Srikanth Kulkarni, Rajneesh Kumar, Sayok Chattopadhyay
  • Patent number: 11212911
    Abstract: The present disclosure relates to an apparatus for a non-contactive sensor having an ESD protection structure, and an apparatus for a non-contactive sensor having an ESD protection structure according to one embodiment of the present disclosure includes: a sensing member that acquires sense information emitted from a detection target object; a circuit board that is separately positioned below the sensing member and includes a sensor IC and one or more grounds; and an ESD protection element that is positioned on the circuit board and encloses a part of the sensor IC protruding on the circuit board.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: December 28, 2021
    Assignee: MANDO CORPORATION
    Inventors: Nam Gyun Kim, Jong Hak Jin, Doo Jin Lee
  • Patent number: 11205622
    Abstract: To overcome the problem of devices in a multi-chip package (MCP) interfering with one another, such as through electromagnetic interference (EMI) and/or radio-frequency interference (RFI), the chip package can include an electrically conductive stiffener that at least partially electrically shields the devices from one another. At least some of the devices can be positioned in respective recesses in the stiffener. In some examples, when the devices are positioned in the recesses, at least one device does not extend beyond a plane defined by a first side of the stiffener. Such shielding can help reduce interference between the devices. Because device-to-device electrical interference can be reduced, devices on the package can be positioned closer to one another, thereby reducing a size of the package. The devices can electrically connect to a substrate via electrical connections that extend through the stiffener.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: December 21, 2021
    Assignee: Intel Corporation
    Inventors: Jenny Shio Yin Ong, Seok Ling Lim, Bok Eng Cheah, Jackson Chung Peng Kong
  • Patent number: 11203524
    Abstract: In described examples, a cavity is formed between a substrate and a cap. One or more access holes are formed through the cap for removing portions of a sacrificial layer from within the cavity. A cover is supported by the cap, where the cover is for occulting the one or more access holes along a perspective. An encapsulant seals the cavity, where the encapsulant encapsulates the cover and the one or more access holes.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: December 21, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Jose Antonio Martinez
  • Patent number: 11202367
    Abstract: An embodiment of the present invention relates to a flexible printed circuit board (FPCB), which is applied to various electronic display devices, and may provide the FPCB, including a base, a first metal layer and a second metal layer on both surfaces of the base, a first plating layer on the first metal layer, a second plating layer on the second metal layer, and a first insulating pattern and a second insulating pattern respectively disposed on some region of the first plating layer and the second plating layer, wherein the first plating layer and the second plating layer may have different thicknesses.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: December 14, 2021
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Jun Young Lim, Woong Sik Kim, Hyung Kyu Yoon
  • Patent number: 11189990
    Abstract: A semiconductor laser component including a semiconductor chip arranged to emit laser radiation, a cladding that is electrically insulating and covers the semiconductor chip in places, and a bonding layer that electrically conductively connects the semiconductor chip to a first connection point, wherein the semiconductor chip includes a cover surface, a bottom surface, a first front surface, a second front surface, a first side surface and a second side surface, the first front surface is arranged to decouple the laser beam, the cladding covers the semiconductor chip at least in places on the cover surface, the second front surface, the first side surface and the second side surface, and the bonding layer on the cladding extends from the cover surface to the first connection point.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: November 30, 2021
    Assignee: OSRAM OLED GmbH
    Inventors: Andreas Wojcik, Hubert Halbritter, Thomas Schwarz
  • Patent number: 11189576
    Abstract: A semiconductor device package comprises a semiconductor device, a first encapsulant surrounding the semiconductor device, a second encapsulant covering the semiconductor device and the first encapsulant, and a redistribution layer extending through the second encapsulant and electrically connected to the semiconductor device.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: November 30, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Peng Yang, Yuan-Feng Chiang, Po-Wei Lu
  • Patent number: 11182079
    Abstract: Methods, systems and devices for configuring access to a memory device are disclosed. The configuration of the memory device may be carried out by creating a plurality of access profiles that are adapted to optimize access to the memory device in accordance with a type of access. For example, when an application with specific memory access needs is initiated, the memory access profile that is designed for that particular access need may be utilized to configure access to the memory device. The configuration may apply to a portion of the memory device, a partition of the memory device, a single access location on the memory device, or any combination thereof.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: November 23, 2021
    Assignee: Memory Technologies LLC
    Inventors: Jani Hyvonen, Kimmo J. Mylly, Jussi Hakkinen, Yevgen Gyl
  • Patent number: 11177234
    Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a self-assembled monolayers (SAM) layer. The package substrate includes a SAM layer on portions of a conductive pad, where the SAM layer includes light-reflective moieties. The package substrate also includes a via on a surface portion of the conductive pad, and a dielectric on and around the via, the SAM layer, and the conductive pad, where the SAM layer surrounds and contacts a surface of the via. The SAM layer may be an interfacial organic layer. The light-reflective moieties may include a hemicyanine, a cyclic-hemicyanine, an oligothiophene, and/or a conjugated aromatic compound. The SAM layer may include a molecular structure having a first end group of a first monolayer, an intermediate group, a fifth end group of a second monolayer, and one or more of a first and second light-reflective moieties.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Suddhasattwa Nad, Rahul Manepalli, Marcel Wall
  • Patent number: 11177459
    Abstract: Disclosed are a light-emitting element encapsulation structure, a method for fabricating the same, and a display panel, and the light-emitting element encapsulation structure includes: a first substrate; a second substrate arranged opposite to the first substrate; a light-emitting element located on the side of the second substrate facing the first substrate; an encapsulation layer made of a water-absorbent material, and filled in edge areas of the first substrate and the second substrate, wherein a hermetic space is defined by the encapsulation layer, the first substrate, and the second substrate, and the light-emitting element is located in the hermetic space; and a filler; the hermetic space is full of the filler except for an area occupied by the light-emitting element.
    Type: Grant
    Filed: November 22, 2018
    Date of Patent: November 16, 2021
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd, BOE Technology Group Co., Ltd.
    Inventors: Shihlun Chen, Litao Qu
  • Patent number: 11158569
    Abstract: In an embodiment, a semiconductor package includes at least one die pad, a plurality of outer contacts, a first semiconductor device and a second semiconductor device. The second semiconductor device includes a first transistor device having a source electrode, a gate electrode, a drain electrode, a front surface, and a rear surface. A front metallization is positioned on the front surface and a rear metallization on the rear surface of the second semiconductor device. The front metallization includes a first power contact pad coupled to the source electrode and mounted on the at least one die pad. The rear metallization includes a second power contact pad electrically coupled to the drain electrode, and an auxiliary lateral redistribution structure electrically insulated from the second power contact pad and the drain electrode. The first semiconductor device is electrically coupled to the auxiliary lateral redistribution structure.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: October 26, 2021
    Assignees: Infineon Technologies Austria AG, Infineon Technologies Americas Corp.
    Inventors: Gerhard Noebauer, Ashita Mirchandani
  • Patent number: 11158578
    Abstract: Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: October 26, 2021
    Assignee: Intel Corporation
    Inventors: Mihir K Roy, Mathew J Manusharow
  • Patent number: 11158689
    Abstract: An electroluminescent display panel, a manufacturing method thereof and a display device are provided. The electroluminescent display panel includes a display area and a non-display area; the non-display area is provided with a crack dam; the crack dam includes at least two stacked metal pads and an insulating layer; the at least two metal pads includes a first metal pad and a second metal pad; the first metal pad and the second metal pad are on a same side of the base substrate; the insulating layer is between the first metal pad and the second metal pad and completely covers the second metal pad, wherein a plane of the insulating layer covering and being away from the second metal pad, is a first surface; and the first metal pad covers at least the boundary of the first surface close to the display area.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: October 26, 2021
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Pan Zhao, Zhiliang Jiang, Zhenli Zhou, Ge Wang
  • Patent number: 11154111
    Abstract: An article with a color change portion and a method of changing color. The article includes at least one color change portion capable of changing colors. The color change portion includes composite material including a photonic lattice. The color change portion can change colors according to one or more performance parameters. The article can be connected to a computer and the color change portion can be controlled using the computer.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: October 26, 2021
    Assignee: NIKE, Inc.
    Inventors: Sharna M. Donovan, Sean D. Hartford, Michelle L. Mishler, Vikram Malhotra, James Molyneux, Andrew A. Owings, Aaron B. Weast, Bradley W. Wilkins
  • Patent number: 11156346
    Abstract: LED lighting systems and vehicle headlamp systems are described. An LED lighting system includes a silicon backplane having a top surface, a bottom surface, and side surfaces and a substrate surrounding the side surfaces of the silicon backplane, the substrate having a top surface, a bottom surface and side surfaces. First redistribution layers are provided on the top surface of the silicon backplane and the top surface of the substrate. Second redistribution layers are provided on the bottom surface of the silicon backplane and the bottom surface of the substrate. At least one via extends through the substrate between the first redistribution layers and the second redistribution layers and is filled with a metal material.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: October 26, 2021
    Assignee: Lumileds LLC
    Inventors: Tze Yang Hin, Anantharaman Vaidyanathan, Srini Banna, Ronald Johannes Bonne
  • Patent number: 11145621
    Abstract: A semiconductor package device comprises a substrate, a first electronic component, a first encapsulant, a second electronic component, and a first conductive trace. The substrate has a first surface. The first electronic component is on the first surface of the substrate. The first encapsulant is on the first surface of the substrate and covers the first electronic component. The second electronic component is on the first encapsulant. The first conductive trace is within the first encapsulant. The first conductive trace is electrically connected to the second electronic component.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: October 12, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jr-Wei Lin, Chia-Cheng Liu, Chien-Feng Chan
  • Patent number: 11147160
    Abstract: Disclosed herein are a circuit board and a method of fabricating the same. The circuit board includes: a base substrate having a device mount area defined thereon; a first wiring pattern formed on a first surface of the base substrate; a dummy pattern formed on the base substrate, wherein at least a part of the device mount area is filled with the dummy pattern; a first protective layer covering the first wiring pattern and the dummy pattern; and a lead pattern formed on the first protective layer, wherein the lead pattern is extended to the device mount area.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: October 12, 2021
    Assignee: STEMCO CO., LTD.
    Inventors: Sang Chul Lee, Hyo Jin Park
  • Patent number: 11133568
    Abstract: A semiconductor package structure having an antenna module includes: a substrate, having a first surface, a second surface, and at least one via hole made by a laser running through the substrate; a rewiring layer, disposed on the first surface of the substrate; metal bumps, disposed on the rewiring layer and electrically connected to the rewiring layer; a semiconductor chip, disposed on and electrically connected to the rewiring layer; a conductive column, filling the via hole, and an antenna module, disposed on the second surface of the substrate and electrically connected to the metal bumps through the conductive column and the rewiring layer.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: September 28, 2021
    Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
    Inventors: Yenheng Chen, Chengtar Wu, Chengchung Lin