Beam Leads (i.e., Leads That Extend Beyond The Ends Or Sides Of A Chip Component) Patents (Class 257/735)
  • Patent number: 11328833
    Abstract: Aspects relate to patterned nanostructures having a feature size not including film thickness of below 5 microns. The patterned nanostructures are made up of nanoparticles having an average particle size of less than 100 nm. A nanoparticle composition, which, in some cases, includes a binder, is applied to a substrate. A patterned mold used in concert with electromagnetic radiation function to manipulate the nanoparticle composition in forming the patterned nanostructure. In some embodiments, the patterned mold nanoimprints a pattern onto the nanoparticle composition and the composition is cured through UV or thermal energy, Three-dimensional patterned nanostructures may be formed. A number of patterned nanostructure layers may be prepared and joined together. In some cases, a patterned nanostructure may be formed as a layer that is releasable from the substrate upon which it is initially formed.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: May 10, 2022
    Assignee: University of Massachusetts
    Inventors: James Watkins, Michael R. Beaulieu, Nicholas R. Hendricks
  • Patent number: 11309274
    Abstract: An electronic module has a sealing part 90; a rear surface-exposed conductor 10, 20, 30 having a rear surface-exposed part 12, 22, 32 whose rear surface is exposed; a rear surface-unexposed conductor 40, 50 whose rear surface is not exposed; an electronic element 15, 25, which is provided in the sealing part 90 and provided on a front surface of the rear surface-exposed conductor 40, 50; a first connector 60 for electrically connecting the electronic element 15, 25 with the rear surface-exposed conductor 10, 20, 30; and a second connector 70 for electrically connecting the electronic element 15, 25 with the rear surface-unexposed conductor 40, 50. A thickness T1 of the first connector 60 is thicker than a thickness T2 of the second connector 70.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: April 19, 2022
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventor: Yoshihiro Kamiyama
  • Patent number: 11264351
    Abstract: A method of manufacturing a chip module comprises a step of disposing a first electronic element 13 on a first jig 500, a step of disposing a first connector 60 on the first electronic element 13 via a conductive adhesive 5, a step of disposing a second electronic element 23 on the first connector 60 via a conductive adhesive 5, a step of disposing a second connector 70 on a second jig 550, a step of reversing the second jig in a state where the second connector 70 is fixed to the second jig 550 and disposing the second connector 70 on the second electronic element 23 via a conductive adhesive 5, and a step of curing the conductive adhesives 5.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: March 1, 2022
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Kosuke Ikeda, Osamu Matsuzaki
  • Patent number: 11189591
    Abstract: An electronic module has a first electronic unit having a first substrate 11, a first conductor layer 12 provided on one side of the first substrate 11, and a first electronic element 13 provided on one side of the first conductor layer 12, a first connection body 60 provided on one side of the first electronic element 13, and a second electronic unit having a second electronic element 23 provided on one side of the first connection body 60. The first connection body 60 has a first head part 61 and a plurality of support parts 65 extending from the first head part 61. The electronic module is characterized by that the support part 65 abuts on the first substrate 11 or the first conductor layer 12.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: November 30, 2021
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Kosuke Ikeda, Osamu Matsuzaki
  • Patent number: 11183231
    Abstract: An apparatus for enhancing prefetch access in a memory module may include a memory chip. The memory chip includes a memory cell array, a plurality of bit lines and a plurality of word lines, a plurality of BLSAs, and a plurality of main data lines. The memory cell array may be arranged to store data, and the plurality of bit lines and the plurality of word lines may be arranged to perform access control of the memory cell array. The plurality of BLSAs may sense a plurality of bit-line signals restored from the plurality of memory cells and convert the plurality of bit-line signals into a plurality of amplified signals, respectively. The main data lines may directly output the amplified signals, through selection of CSLs of the BLSAs on the memory chip, to a secondary semiconductor chip, for performing further processing of the memory module, thereby enhancing the prefetch access.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: November 23, 2021
    Assignee: Piecemakers Technology, Inc.
    Inventors: Gyh-Bin Wang, Ming-Hung Wang, Tah-Kang Joseph Ting
  • Patent number: 11145575
    Abstract: An embodiment related to a method for forming a device is disclosed. The method includes providing a package substrate having a first die attach pad (DAP) and a first bond pad, forming a first conductive die-substrate bonding layer on the first DAP, and attaching a first major surface of a first die to the first DAP. The first die includes a first die contact pad on a second major surface of the first die. A first conductive clip-die bonding layer with spacers is formed on the first die contact pad of the first die. A first conductive clip-substrate bonding layer is formed on the first bond pad of the package substrate. The method also includes attaching a first clip bond to the first die and the first bond pad. The first clip bond includes a first horizontal planar portion attached to the first die over the first die contact pad and a second vertical portion attached to the first bond pad.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: October 12, 2021
    Assignee: UTAC Headquarters Pte. Ltd.
    Inventors: Tanawan Chaowasakoo, Hua Hong Tan, Alexander Lucero Laylo, Thanawat Jaengkrajarng
  • Patent number: 11127704
    Abstract: A semiconductor device includes a substrate and at least one bump structure disposed over the substrate. The at least one bump structure includes a pillar formed of a metal having a lower solderability than copper or a copper alloy to a solder alloy disposed over the substrate. A solder alloy is formed directly over and in contact with an upper surface of the metal having the lower solderability than copper or a copper alloy. The pillar has a height of greater than 10 ?m.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: September 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Haw Tsao, Chen-Shien Chen, Cheng-Hung Tsai, Kuo-Chin Chang, Li-Huan Chu
  • Patent number: 10980160
    Abstract: An image pickup module includes a printed wiring board, an electronic component, solder, and a thermosetting resin. The printed wiring board has a first surface provided with first lands. The electronic component includes an image pickup element and has a second surface provided with second lands. The thermosetting resin is in contact with the solder and bonds the printed wiring board to the electronic component. The solder bonds the first lands to the second lands and has a hollow portion. The area of the hollow portion is 5% to 50% of the total area of the solder as observed from the electronic component side in a transmission mode using an X-ray.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: April 13, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventors: Mitsutoshi Hasegawa, Kunihiko Minegishi, Takashi Sakaki, Yoshitomo Fujisawa, Shingo Ishiguri
  • Patent number: 10964637
    Abstract: A package includes a first lead and a second lead. The first lead includes a first part and a second part connected to the first part. The second lead includes a third part and a fourth part connected to the third part. A molded body having a front surface and rear surface opposite to the front surface. The first part has a first terminal exposed from the rear surface. The first terminal is provided within an outer peripheral edge of the rear surface. The third part has a second terminal exposed from the rear surface. The second terminal is provided within the outer peripheral edge. The first lead or the second lead has a heat releasing terminal exposed from the rear surface. The heat releasing terminal is disposed between the first terminal and the second terminal to be spaced apart from the first terminal and the second terminal.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: March 30, 2021
    Assignee: NICHIA CORPORATION
    Inventor: Yuki Shiota
  • Patent number: 10622494
    Abstract: An optoelectronic component includes a housing body comprising a mounting face and a leadframe embedded into the housing body. The leadframe comprises a first and a second leadframe section, wherein the leadframe sections each comprise a contact region and a terminal region. While the contact regions are exposed at the mounting face, the terminal regions project laterally from the housing body. The housing body is completely enclosed by a molding material, wherein the terminal regions are not enclosed by the molding material.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: April 14, 2020
    Assignee: OSRAM OLED GmbH
    Inventors: Daniel Richter, Daniel Wiener
  • Patent number: 10557722
    Abstract: The invention concerns a method for determining a position ? of a position indicator of a position measuring system, in which the sensor signals a1 to ar of a number of r sensors are recorded as a signal vector {right arrow over (a)}=(a1, . . . , ar), a measurement vector {right arrow over (q)} is formed according to {right arrow over (q)}=g({right arrow over (a)}), a 2-component vector {right arrow over (p)} is calculated according to {right arrow over (p)}=M·{right arrow over (q)}, wherein M is a 2×n matrix, and the position ? is determined by means of a predetermined function ƒ({right arrow over (p)}) to ?=ƒ({right arrow over (p)}), wherein the function ƒ({right arrow over (p)})=ƒ(p1,p2) is based on the equations p1=cos(?) and p2=sin(?).
    Type: Grant
    Filed: September 3, 2017
    Date of Patent: February 11, 2020
    Assignees: NM Numerical Modelling GmbH, maglab AG
    Inventor: Markus Roos
  • Patent number: 10528103
    Abstract: A microelectronic assembly may include a first microelectronic device, a second microelectronic device, a first signal link, a second signal link, and a first power connection. The first microelectronic device may include a first interface powered at a first voltage. The second microelectronic device may include a second interface powered at a second voltage. The first signal link may supply a first signal at the first voltage from the first interface to the second interface. The second signal link may supply a second signal at the second voltage from the second interface to the first interface. The first power connection may supply a first reference signal at the first voltage from the first interface to the second interface.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: January 7, 2020
    Assignee: Intel Corporation
    Inventors: Chenchu Punnarao Bandi, Amit Kumar Srivastava
  • Patent number: 10424534
    Abstract: A semiconductor device includes a lead frame including a die paddle and a lead, a semiconductor chip, and a clip. The semiconductor chip has a first side and a second side opposite to the first side. The first side is attached to the die paddle and the second side includes a first bond pad and a second bond pad. The clip electrically couples the first bond pad to the lead. The clip contacts the first bond pad at a first edge portion of the first bond pad adjacent to the second bond pad and defines a first cavity between a central portion of the first bond pad and the clip. Solder is within the first cavity to electrically couple the clip to the first bond pad. The semiconductor device includes a first opening to the first cavity to route flux away from the second bond pad during reflow soldering.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: September 24, 2019
    Assignee: Infineon Technologies AG
    Inventors: Xavier Arokiasamy, Chun Ching Liew
  • Patent number: 10359475
    Abstract: The present invention relates to a common mode noise simulator, and more particularly, to a common mode noise simulator which removes a high-frequency component by controlling impedance of an inductor, a capacitor, and a resistor and evaluates insulation performance of a battery by measuring leakage current of the battery depending on amplitude-modulated common mode noise.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: July 23, 2019
    Assignee: LG CHEM, LTD.
    Inventor: Chanmin Park
  • Patent number: 10312211
    Abstract: A method of manufacturing a semiconductor device which includes a first member and a second member joined to the first member includes: a) producing (Cu,Ni)6Sn5 on a Ni film formed on the first member by melting a first Sn—Cu solder containing 0.9 wt % or higher of Cu on the Ni film of the first member; b) producing (Cu,Ni)6Sn5 on a Ni film formed on the second member by melting a second Sn—Cu solder containing 0.9 wt % or higher of Cu on the Ni film of the second member; and c) joining the first member and the second member to each other by melting the first Sn—Cu solder having undergone step a) and the second Sn—Cu solder having undergone step b) so that the first Sn—Cu solder and the second Sn—Cu solder become integrated.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: June 4, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takuya Kadoguchi, Naoya Take
  • Patent number: 10063282
    Abstract: A chip-to-chip signal transmission system including a first unit set and a second unit set arranged in a first direction is provided. The first unit set and the second unit are configured to perform the signal transmission between a first chip and a second chip. There is a shift between the first unit set and the second unit set in a second direction such that the first unit set and the second unit set are shifted in the second direction and an overlapping region is formed. By adjusting the size of the overlapping region, the signal noise and the signal attenuation due to the misalignment between the first chip and the second chip or the electromagnetic interference of the adjacent signals are reduced and the signal transmission quality is thus improved. Furthermore, a method for arranging chips is also provided.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: August 28, 2018
    Assignee: I-SHOU UNIVERSITY
    Inventors: Yu-Jung Huang, Mei-Hui Guo
  • Patent number: 10026677
    Abstract: A semiconductor device that includes a first die pad, an adhesive, and a second die pad fixed to the top surface of the first die pad via the adhesive. The second die pad includes a body portion and a protrusion portion provided on a side surface of the body portion. A semiconductor chip is fixed to a top surface of the second die pad, and a lead is electrically connected to the semiconductor chip. The semiconductor device further includes a package material that covers the first die pad, the second die pad, the semiconductor chip, and the lead. The first die pad is substantially as thick as the lead.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: July 17, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Naohisa Okumura, Yasuhisa Shintoku, Tetsuya Kurosawa, Hiroaki Kishi
  • Patent number: 9997465
    Abstract: Semiconductor package structures are provided. A semiconductor package structure includes a chip, a molding material surrounding the chip, a through-via extending from a first surface to a second surface of the molding material, a first re-distribution layer (RDL) wire disposed on the second surface of the molding material and coupled to the through-via, and a second RDL wire disposed on the second surface of the molding material and parallel to the first RDL wire. The second surface is opposite to the first surface. A portion of the second RDL wire across the through-via has a first segment with a first width and a second segment with a second width different from the first width.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: June 12, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACUTURING CO., LTD.
    Inventors: Jie Chen, Hsien-Wei Chen
  • Patent number: 9847409
    Abstract: A semiconductor device provides an element arrangement region on a semiconductor substrate including: a first semiconductor region on the semiconductor substrate; a second semiconductor region on the first semiconductor region; multiple trench gates penetrating the first semiconductor region and reaching the second semiconductor region; a third semiconductor region contacting the trench gate; a fourth semiconductor region on a rear surface; a first electrode connected to the first and second semiconductor regions; and a second electrode connected to the fourth semiconductor region. Each trench gate includes a main trench gate for generating a channel and a dummy trench gate for improving a withstand voltage of a component. The device further includes: a dummy gate wiring for applying a predetermined voltage to the dummy trench gate; and a dummy pad connected to the dummy gate wiring. The dummy pad and the first electrode are connected by a conductive member.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: December 19, 2017
    Assignee: DENSO CORPORATION
    Inventors: Tomofusa Shiga, Hiromitsu Tanabe
  • Patent number: 9847448
    Abstract: Methods of forming III-V LED structures on silicon fin templates are described. Those methods and structures may include forming an n-doped III-V layer on a silicon (111) plane of a silicon fin, forming a quantum well layer on the n-doped III-V layer, forming a p-doped III-V layer on the quantum well layer, and then forming an ohmic contact layer on the p-doped III-V layer.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: December 19, 2017
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Robert S. Chau, Marko Radosavljevic, Benjamin Chu-Kung, Sanaz Gardner
  • Patent number: 9755102
    Abstract: The precursor comprises at least one layer of doped crystalline silicon and a layer of doped amorphous semiconductor material. The method comprises the steps of placing the cell precursor sandwiched between a grounded conducting plate and a plate made of insulating material coated with a conducting layer, then applying a state change electrical voltage (U1) between the conducting layer and ground, the said state change electrical voltage (U1) being designed to bring the Fermi level at the interface between crystalline silicon and amorphous semiconductor material closer to the middle of the band gap of the said amorphous semiconductor material, while at the same time heating the cell precursor to a defect equilibration temperature (TE), and finally cooling down the cell precursor (10) prior to interrupting the application of the state change electrical voltage (U1).
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: September 5, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMOIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Renaud Varache
  • Patent number: 9666536
    Abstract: The present invention provides a package structure and fabrication method thereof. The method includes providing a first carrier having a metal layer; forming a dielectric layer on the metal layer; forming a plurality of conductive pillars embedded into the dielectric layer and protruding from a surface of the dielectric layer, and disposing an electronic component on the surface of the dielectric layer; forming an encapsulating layer on the dielectric layer to encompass the plurality of conductive pillars, the dielectric layer and the electronic component; removing a portion of the encapsulating layer and the first carrier such that two ends of each of the plurality of conductive pillars are exposed from the encapsulating layer and the dielectric layer. Therefore, the present invention effectively reduces manufacturing costs and the need for an opening process while manufacturing the conductive pillars can be eliminated.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: May 30, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yi-Wei Liu, Yan-Heng Chen, Mao-Hua Yeh, Hung-Wen Liu, Yi-Che Lai
  • Patent number: 9659848
    Abstract: A component can include a generally planar element, a reinforcing dielectric layer overlying the generally planar element, an encapsulation overlying the reinforcing dielectric layer, and a plurality of wire bonds. Each wire bond can have a tip at a major surface of the encapsulation. The wire bonds can have first portions extending within the reinforcing dielectric layer. The first portions of at least some of the wire bonds can have bends that change an extension direction of the respective wire bond. The reinforcing dielectric layer can have protruding regions surrounding respective ones of the wire bonds, the protruding regions extending to greater peak heights from the first surface of the generally planar element than portions of the reinforcing dielectric layer between adjacent ones of the protruding regions. The peak heights of the protruding regions can coincide with points of contact between the reinforcing dielectric layer and individual wire bonds.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: May 23, 2017
    Assignee: Invensas Corporation
    Inventors: Grant Villavicencio, Sangil Lee, Roseann Alatorre, Javier A. Delacruz, Scott McGrath
  • Patent number: 9640326
    Abstract: A solid electrolytic capacitor includes a capacitor element, a negative terminal, a positive terminal, and a resin package covering the capacitor element. The negative terminal and the positive terminal are joined respectively to a negative electrode section and a positive electrode section of the capacitor element. The negative terminal has a mount portion, a protruding portion, and a collecting portion. The mount portion has the negative electrode section disposed thereon, and is joined to an underside of the negative electrode via a conductive bonding portion. The protruding portion protrudes from a side edge of the mount portion in a same plane as the mount portion, and has a width narrowed stepwise in a protruding direction. The collecting portion is provided adjacent to a side edge of a part where the protruding portion is narrowed stepwise, and accommodates a part of the conductive bonding portion.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: May 2, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Katsuhisa Ishizaki, Kouta Muneyasu
  • Patent number: 9633934
    Abstract: A semiconductor device and method for providing an enhanced removal of heat from a semiconductor die within an integrated fan out package on package configuration is presented. In an embodiment a metal layer is formed on a backside of the semiconductor die, and the semiconductor die along and through vias are encapsulated. Portions of the metal layer are exposed and a thermal die is connected to remove heat from the semiconductor die.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: April 25, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jing-Cheng Lin, Po-Hao Tsai, Li-Hui Cheng, Porter Chen
  • Patent number: 9576924
    Abstract: A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: February 21, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Akihiko Yoshioka, Shinya Suzuki
  • Patent number: 9437567
    Abstract: A semiconductor device includes a contact region over a substrate. The semiconductor device further includes a metal pad over the contact region. Additionally, the semiconductor device includes a post passivation interconnect (PPI) line over the metal pad, where the PPI line is in contact with the metal pad. Furthermore, the semiconductor device includes an under-bump-metallurgy (UBM) layer over the PPI line. Moreover, the semiconductor device includes a plurality of solder balls over the UBM layer, the plurality of solder balls being arranged at some, but not all, intersections of a number of columns and rows of a ball pattern.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: September 6, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Yuan Yu, Hsien-Wei Chen, Ying-Ju Chen, Shih-Wei Liang
  • Patent number: 9269414
    Abstract: A semiconductor integrated circuit includes a plurality of semiconductor chips. Each of the plurality of semiconductor chips includes a chip selection unit suitable for generating an internal chip selection signal in response to one or more selective chip selection signals and transferring the selective chip selection signals to an adjacent semiconductor chip of the plurality of semiconductor chips, a selective setting unit suitable for generating a selective internal signal, selectively activated in each semiconductor chip, in response to the internal chip selection signal and an external setting signal, and a common setting unit suitable for generating a common internal signal, activated in common in the plurality of semiconductor chips, in response to the setting signal and an external common chip selection signal.
    Type: Grant
    Filed: December 15, 2013
    Date of Patent: February 23, 2016
    Assignee: SK Hynix Inc.
    Inventors: Jae-Bum Ko, Sang-Jin Byeon
  • Patent number: 9209124
    Abstract: An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A side recess is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface toward the second surface and across the entire length of the first side. A conducting layer is located on the first surface and electrically connected to the conducting pad, wherein the conducting layer extends to the side recess.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: December 8, 2015
    Assignee: XINTEC INC.
    Inventors: Yu-Lung Huang, Chao-Yen Lin, Wei-Luen Suen, Chien-Hui Chen
  • Patent number: 9147649
    Abstract: A multi-chip module and method is disclosed. One embodiment provides an electronic module having a first metal structure and a second metal structure. A first semiconductor chip is electrically connected with its back side to the first metal structure. A second semiconductor chip is arranged with its back side lying over the front side of the first semiconductor chip. The second metal structure includes multiple external contact elements attached over the front side of the second semiconductor chip. At least two of the multiple external contact elements are electrically connected to the front side of the second semiconductor chip.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: September 29, 2015
    Assignee: Infineon Technologies AG
    Inventors: Stefan Landau, Joachim Mahler, Thomas Wowra
  • Patent number: 9134100
    Abstract: A semiconductor bridge die may have an “H-design” or “trapezoidal” configuration in which a center bridge segment is flanked by one or more angled walls on each side of the bridge segment. Each wall is plated with a conductive material, thereby providing a continuous conductive path across the top surface of the die. A bottom surface of the die may be connected to a top surface of a header by epoxy in various configurations. The plated angled walls facilitate the solderable connection of the walls to a plated top surface of each of several pins on a top surface of the header, thereby providing a continuous electrical connection between the pins and the die. Also, a method is provided for manufacturing a semiconductor bridge die in accordance with the various embodiments of the die.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: September 15, 2015
    Assignee: ENSIGN-BICKFORD AEROSPACE & DEFENSE COMPANY
    Inventors: Bernardo Martinez-Tovar, Craig J. Boucher
  • Patent number: 9082438
    Abstract: One aspect of the present invention is a three-dimensional structure that has a concave-convex form including a gutter for wiring having at least partially a width of 20 ?m or less, wherein at least a part of a wiring conductor is embedded in the gutter for wiring, and a wiring that extends in such a manner as to creep along the concave-convex form is provided.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: July 14, 2015
    Assignee: PANASONIC CORPORATION
    Inventors: Shingo Yoshioka, Hiroaki Fujiwara, Hiromitsu Takashita, Tsuyoshi Takeda
  • Patent number: 9070393
    Abstract: One aspect of the present invention is a three-dimensional structure in which a wiring is formed on a surface, the three-dimensional structure having an insulating resin layer that contains a filler formed from at least one element selected from typical non-metal elements and typical metal elements, wherein a recessed gutter for wiring is formed on a surface of the insulating resin layer, and at least a part of a wiring conductor is embedded in the recessed gutter for wiring.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: June 30, 2015
    Assignee: PANASONIC CORPORATION
    Inventors: Shingo Yoshioka, Hiroaki Fujiwara, Hiromitsu Takashita, Tsuyoshi Takeda
  • Patent number: 9070053
    Abstract: A metal transaction card is provided having a metal core layer with metal cladding layers connected thereto on opposing sides thereof. The metal core layer may have a density and/or thickness that is significantly greater than the density and/or thickness of the metal cladding layers. The density of the metal core layer may be at least 2.5 times greater than the density of the metal cladding layers. The density of the metal core layer may be at least 7.5. The outward facing lateral surface of one or both of the metal cladding layers may be anodized, or anodized and colorized. The anodized lateral surface(s) may be coated to increase the performance of a one or more hot-stamped elements attached to the coated surface(s).
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: June 30, 2015
    Assignee: CPI Card Group—Colorado, Inc.
    Inventor: Barry Mosteller
  • Patent number: 9065030
    Abstract: According to the present invention, there is provided a diode package in which a diode chip is sealed by a molding compound and a lead wire connected to the diode chip is led outside the molding compound, wherein the lead wire is divided into an upper lead wire and a lower lead wire, both lead wires each being formed in a long, flat plate and having a first stage and a second stage, both stages being opposite from each other, the upper side of the diode chip is attached to the lower side of the first stage of the upper lead wire, the lower side of the diode chip is attached to the upper side of the first stage of the lower lead wire, and the second stage of the upper lead wire and the second stage of the lower lead wire are led out in the lateral direction of the molding compound.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: June 23, 2015
    Assignee: GNE TECH CO., LTD.
    Inventor: Jae Ku Kim
  • Patent number: 9059334
    Abstract: First chip main surfaces of first semiconductor chips are bonded to a heat spreader, and second chip main surfaces of the first semiconductor chips are bonded to a first electrode. First chip main surfaces of second semiconductor chips are bonded to a heat spreader, and second chip main surfaces of the second semiconductor chips are bonded to a first electrode. A plurality of electrodes are provided by a lead frame. An insulating member is provided on a side opposite to the chips when viewed from the heat spreader. An insulating substrate is provided on a side opposite to the chips when viewed from the first electrodes.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: June 16, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Osamu Usui, Naoki Yoshimatsu, Masao Kikuchi
  • Patent number: 9048226
    Abstract: A chip assembly includes a PCB and a chip positioned on the PCB. The PCB includes a number of first bonding pads. Each bonding pad includes two first soldering balls formed thereon. The chip includes a number of second bonding pads each corresponding to a first bonding pad. Each second bonding pad includes a second soldering ball. The two first soldering balls of a first bonding pad are electrically connected to the second soldering ball of a corresponding second bonding pad via two bonding wires.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: June 2, 2015
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Kai-Wen Wu
  • Patent number: 9041188
    Abstract: An axially-mountable device includes a semiconductor chip comprising lower and upper electrical contacts. A lower die pad is electrically and mechanically connected to the lower electrical contact of the chip. An upper die pad is electrically and mechanically connected to the upper electrical contact of the chip. A first axially extending electrical lead is electrically and mechanically connected to the upper die pad and extends in a first axial direction. A second axially extending electrical lead is electrically and mechanically connected to the lower die pad and extends in a second axial direction that is opposite to the first axial direction. Packaging material encapsulates the semiconductor chip, the upper and lower die pads and a portion of the first and second axially extending leads. The first and second leads extend from the packaging material and are adapted to allow the device to be axially-mounted with another electrical component.
    Type: Grant
    Filed: November 10, 2012
    Date of Patent: May 26, 2015
    Assignee: VISHAY GENERAL SEMICONDUCTOR LLC
    Inventors: Wan-Lan Chiang, Chih-Ping Peng, Hui-Ying Ding
  • Publication number: 20150130048
    Abstract: A semiconductor package includes a mold body having a first main face, a second main face opposite to the first main face and side faces connecting the first and second main faces, a first semiconductor module including a plurality of first semiconductor chips and a first encapsulation layer disposed above the first semiconductor chips, and a second semiconductor module disposed above the first semiconductor module. The second semiconductor module includes a plurality of second semiconductor channels and a second encapsulation layer disposed above the second semiconductor channels. The semiconductor package further includes a plurality of external connectors extending through one or more of the side faces of the mold body.
    Type: Application
    Filed: November 12, 2013
    Publication date: May 14, 2015
    Inventors: Olaf Hohlfeld, Juergen Hoegerl, Gottfried Beer, Magdalena Hoier
  • Patent number: 9030008
    Abstract: A process for increasing the adhesion of a polymeric material to a metal surface, the process comprising contacting the metal surface with an adhesion promoting composition comprising: 1) an oxidizer; 2) an inorganic acid; 3) a corrosion inhibitor; and 4) an organic phosphonate; and thereafter b) bonding the polymeric material to the metal surface. The organic phosphonate aids in stabilizing the oxidizer and organic components present in the bath and prevents decomposition of the components, thereby increasing the working life of the bath, especially when used with copper alloys having a high iron content.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: May 12, 2015
    Inventor: Nilesh Kapadia
  • Patent number: 9006886
    Abstract: A light emitting device package is disclosed. The light emitting device package includes a body, first and second lead frames disposed on the body, and a light emitting device connected to the first and second lead frames, wherein at least one of the first and second lead frames includes first and second regions having different thicknesses.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: April 14, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventors: Gyu Hyeong Bak, Myoung Kyo Kim, Tae Uk Ha, Kyung Min Je
  • Patent number: 9006857
    Abstract: An IR sensor includes a suspended micro-platform having a support layer and a device layer disposed thereon. IR absorbers are disposed in or on the device layer. IR radiation received by the IR absorbers heats an on-platform junction of each of a plurality of series-connected thermoelectric devices operating in a Seebeck mode, the devices producing a voltage indicative of the received IR. Other thermoelectric devices are used to cool the platform, and a pressure sensing arrangement is used to detect loss of vacuum or pressure leaks.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: April 14, 2015
    Inventor: William N. Carr
  • Patent number: 9000583
    Abstract: A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing towards oppositely-facing first and second surfaces of the first substrate and each having contacts electrically connected with the first substrate. The contact-bearing faces of the first and second microelectronic elements at least partially overlie one another. Leads electrically connect the subassembly with a second substrate, at least portions of the leads being aligned with an aperture in the second substrate. The leads can include wire bonds extending through an aperture in the first substrate and joined to contacts of the first microelectronic element aligned with the first substrate aperture. In one example, the subassembly can be electrically connected with the second substrate using electrically conductive spacer elements.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: April 7, 2015
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Wael Zohni, Richard Dewitt Crisp
  • Patent number: 8994158
    Abstract: Semiconductor packages having lead frames include a lead frame, which supports a semiconductor chip and is electrically connected to the semiconductor chip by bonding wires, and a molding layer encapsulating the semiconductor chip. The lead frame includes first lead frames extending in a first direction and second lead frames extending in a second direction. The first lead frames may run across the semiconductor chip and support the semiconductor chip and the second lead frames may run across the bottom surface of the semiconductor chip.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: March 31, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Do-Hyun Kim, Won-young Kim
  • Patent number: 8975762
    Abstract: A semiconductor device includes a substantially rectangular semiconductor chip having an obverse surface, a first long side, a second long side opposite the first long side, a first short side and a second short side, and a plurality of bump electrodes. A wiring substrate has a main surface, a first side disposed outside of the semiconductor chip and extending substantially parallel with the first long side, a second side disposed outside of the semiconductor chip and extending substantially parallel with the second long side, and a plurality of wiring groups, each including a plurality of wirings. A semiconductor chip is mounted on the wiring substrate such that the obverse surface of the semiconductor chip is faced to the main surface of the wiring substrate and the first long side is located between the first side of the wiring substrate and the second long side, in a plan view.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: March 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Hidenori Egawa
  • Patent number: 8970032
    Abstract: The chip module includes a semiconductor chip having a first contact element on a first main face and a second contact element on a second main face. The semiconductor chip is arranged on a corner in such a way that the first main face of the semiconductor chip faces the carrier. One or more electrical connectors are connected to the carrier and include end faces located in a plane above a plane of the second main face of the semiconductor chip.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: March 3, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Martin Standing
  • Patent number: 8952528
    Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor chip having opposite first and second surfaces; an RDL structure formed on the first surface of the semiconductor chip and having opposite third and fourth surfaces and a plurality of first conductive through holes penetrating the third and fourth surfaces thereof, wherein the RDL structure is formed on the semiconductor chip through the fourth surface thereof and electrically connected to the semiconductor chip through a plurality of first conductive elements, and the third surface of the RDL structure has a redistribution layer formed thereon; a plurality of conductive bumps formed on the redistribution layer; and an encapsulant formed on the first surface of the semiconductor chip for encapsulating the RDL structure, wherein the conductive bumps are embedded in and exposed from the encapsulant. The invention effectively prevents warpage of the semiconductor package and improves the electrical connection significantly.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: February 10, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien-Feng Chan, Chun-Tang Lin, Yi Che Lai
  • Patent number: 8946763
    Abstract: A semiconductor light-emitting device includes a lead frame, a semiconductor light-emitting element mounted on the top surface of the bonding region, and a case covering part of the lead frame. The bottom surface of the bonding region is exposed to the outside of the case. The lead frame includes a thin extension extending from the bonding region and having a top surface which is flush with the top surface of the bonding region. The thin extension has a bottom surface which is offset from the bottom surface of the bonding region toward the top surface of the bonding region.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: February 3, 2015
    Assignee: Rohm Co., Ltd.
    Inventor: Masahiko Kobayakawa
  • Patent number: 8907475
    Abstract: Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: December 9, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hanae Shimokawa, Tasao Soga, Hiroaki Okudaira, Toshiharu Ishida, Tetsuya Nakatsuka, Yoshiharu Inaba, Asao Nishimura
  • Patent number: 8901754
    Abstract: A semiconductor device comprises a semiconductor chip having a plurality of electrode pads; an insulation layer having one or more apertures which expose at least a part of the plurality of electrode pads respectively on the semiconductor chip; and a plurality of wires which are electrically connected to the exposed plurality of electrode pads.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: December 2, 2014
    Assignee: J-Devices Corporation
    Inventor: Osamu Yamagata