Combined With Electrical Contact Or Lead Patents (Class 257/734)
  • Patent number: 10707081
    Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: July 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Chun Huang, Chiu-Hsiang Chen, Ya-Wen Yeh, Yu-Tien Shen, Po-Chin Chang, Chien Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Li-Te Lin, Pinyen Lin, Ru-Gun Liu, Chin-Hsiang Lin
  • Patent number: 10699974
    Abstract: A display device including a film substrate including first and second surfaces, the first surface being opposite to the second surface; a semiconductor chip disposed on the first surface and including an input terminal and a test terminal, which are arranged in a first direction; a first wire extending from the input terminal on the first surface along a second direction, which intersects the first direction; and a second wire including a first extended portion, which extends along the first surface, a second extended portion, which extends along the second surface, and a first via, which penetrates the film substrate and connects the first extended portion and the second extended portion, wherein the first extended portion extends from the test terminal in the second direction and is connected to the first via, and the second extended portion extends from the first via to an edge of the second surface.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: June 30, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: So Young Lim, Ye Chung Chung
  • Patent number: 10693047
    Abstract: A luminous module includes a light source and an optical part for shaping the light rays emitted by the light source. The light source is a semiconductor source that includes a plurality of electroluminescent units of submillimeter dimensions, and at least one positioning outgrowth configured to participate in the positioning of the light source on an optical part. The light source is positioned with respect to the optical part by interaction of the at least one positioning outgrowth with a corresponding receiving orifice formed in the optical part.
    Type: Grant
    Filed: July 4, 2017
    Date of Patent: June 23, 2020
    Assignee: VALEO VISION
    Inventors: Pierre Albou, Christine Roucoules
  • Patent number: 10676359
    Abstract: A method of making carbon nanotubes with equal or other ratio of semiconductive to conductive elements in integrated form includes: depositing a catalyst layer on a substrate and heating same in a reaction furnace to a predetermined temperature. A carbon source gas and a protective gas are introduced to grow a plurality of carbon nanotube segments, some carbon nanotube segments being conductive metallic. A positive electric field is applied to the plurality of carbon nanotube segments, wherein the catalyst layer is positively charged and the positive electric field is reversed to the negative, to grow a second carbon nanotube segment structure from the metallic carbon nanotube segments. The direction of the negative electric field is along a second direction and the second carbon nanotube segment structure then comprises a plurality of semiconducting carbon nanotube segments.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: June 9, 2020
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Jiang-Tao Wang, Peng Liu, Kai-Li Jiang, Shou-Shan Fan
  • Patent number: 10675719
    Abstract: Provided herein is a solder material that includes a spherical core that provides space between a joint object and another object to be joined to the joint object and a solder coated layer that has a melting point at which a core layer of the core is not melted. The solder coated layer includes Sn as a main ingredient and 0 to 2 mass % of Ag, and coats the core. The solder coated layer has an average grain diameter of crystal grains of 3 ?m or less, and the solder material has a spherical diameter of 1 to 230 ?m and a sphericity of 0.95 or more.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: June 9, 2020
    Assignee: Senju Metal Industry Co., Ltd.
    Inventors: Hiroyoshi Kawasaki, Shigeki Kondo, Atsushi Ikeda, Takahiro Roppongi, Takashi Hagiwara, Daisuke Soma, Kaichi Tsuruta, Isamu Sato, Yuji Kawamata
  • Patent number: 10664641
    Abstract: A method for forming an integrated device includes following operations. A first circuit is provided. The first circuit has a first connecting path, a plurality of second connecting paths, and a third connecting path. The plurality of second connecting paths are electrically connected to a first connecting portion of the first connecting path. The third connecting path is electrically coupled to a second connecting portion of the first connecting path. An electromigration (EM) data of the first connecting path is analyzed to determine if a third connecting portion between the first connecting portion and the second connecting portion induces EM phenomenon. The first circuit is modified for generating a second circuit when the third connecting portion induces EM phenomenon. The integrated device according to the second circuit is generated.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: May 26, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hiranmay Biswas, Kuo-Nan Yang, Chung-Hsing Wang, Meng-Xiang Lee
  • Patent number: 10665559
    Abstract: A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Kuei Hsu, Ming-Chih Yew, Po-Hao Tsai, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 10658239
    Abstract: This disclosure provides wafer dicing methods, and relates to the field of semiconductor technologies. Implementations of the dicing method may include: performing laser stealth dicing processing on a wafer from a back surface of the wafer; performing grinding and thinning processing on the back surface of the wafer after performing the laser stealth dicing processing; sticking a dicing tape on the back surface of the wafer after performing the grinding and thinning processing; and performing separation processing on the wafer after sticking the dicing tape. In some implementations, stealth dicing (SD) is performed before grinding, so that a laser is directly imposed on a back surface of a wafer, thereby alleviating a laser attenuation problem and lowering requirements on light transmittance of a dicing tape.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: May 19, 2020
    Assignees: Semiconductor Manufacturing International (Beijing) Corp., Semiconductor Manufacturing International (Shanghai) Corp.
    Inventors: Lihui Lu, Chunchao Fei, Po Yuan Chiang, Yaping Wang
  • Patent number: 10651338
    Abstract: A method for fabricating an optoelectronic semiconductor component is disclosed. A semiconductor chip is produced by singularizing a wafer. The semiconductor chip comprises a substrate and a semiconductor layer sequence with an active layer applied to a main side of the substrate. The semiconductor layer sequence has an active region for emission or absorption of radiation and a sacrificial region arranged next to the active region. The sacrificial region in the finished semiconductor component is not intended to emit or absorb radiation. A trench, introduced into the semiconductor layer sequence, penetrates the active layer and separates the active region from the sacrificial region. The semiconductor chip with the semiconductor layer sequence is applied on a carrier. The substrate is detached from the active region of the semiconductor layer sequence. In the sacrificial region, the semiconductor layer sequence remains mechanically connected to the substrate.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: May 12, 2020
    Assignee: OSRAM OLED GmbH
    Inventor: Dominik Scholz
  • Patent number: 10607942
    Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first pad, and a second pad. A first opening and a second opening are formed in a first main surface of the first semiconductor layer. The second semiconductor layer is stacked on the first semiconductor layer. The first pad for wire bonding is disposed in the first opening. The second pad on which an alignment mark is formed is disposed in the second opening. A third opening and a fourth opening penetrate the second semiconductor layer. The first opening overlaps the third opening. The second opening overlaps the fourth opening.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: March 31, 2020
    Assignee: OLYMPUS CORPORATION
    Inventor: Naohiro Takazawa
  • Patent number: 10608110
    Abstract: Metal-oxide-semiconductor (MOS) transistors with reduced subthreshold conduction, and methods of fabricating the same. Transistor gate structures are fabricated in these transistors of a shape and dimension as to overlap onto the active region from the interface between isolation dielectric structures and the transistor active areas. Minimum channel length conduction is therefore not available at the isolation-to-active interface, but rather the channel length along that interface is substantially lengthened, reducing off-state conduction.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: March 31, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Amitava Chatterjee
  • Patent number: 10600738
    Abstract: A gate electrode is formed in a trench formed in a semiconductor substrate. A gate interlayer insulating film is formed to cover the gate electrode and the like. A gate interconnection and an emitter electrode are formed in contact with the gate interlayer insulating film. A glass coating film and a polyimide film are formed to cover the gate interconnection and the emitter electrode. A solder layer is formed to cover the polyimide film. The gate interconnection and the emitter electrode are each formed of a tungsten film, for example.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: March 24, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Manami Noda, Kota Kimura
  • Patent number: 10586776
    Abstract: A semiconductor device includes a substrate; a laminate which is formed on one main surface side of the substrate, and includes an aluminum alloy wiring and an insulating film surrounding the aluminum alloy wiring; and a silicon nitride film covering the laminate, in which the silicon nitride film and the insulating film have an opening portion, through which the silicon nitride film and the insulating film, formed at a position overlapped with a bonding portion of the aluminum alloy wiring, and a deposition made of a residue caused by reverse sputtering, which contains silicon and nitrogen, adheres to a portion exposed from the opening portion of a surface of the aluminum alloy wiring, to form a film.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: March 10, 2020
    Assignee: ABLIC INC.
    Inventors: Yoichi Mimuro, Shinjiro Kato, Tetsuo Shioura
  • Patent number: 10566273
    Abstract: A chip-on-film semiconductor device includes a translucent insulator film, a first wire group including a plurality of wires on a first surface of the insulator film, a second wire group including a plurality of opaque wires on a second surface of the insulator film opposite to the first surface, and a semiconductor chip mounted on the first surface. The wires of the first wire group and semiconductor connection terminals of the semiconductor chip are joined together at junction portions. The second surface includes an unwired region, in which none of the wires of the second wire group are disposed, at a portion corresponding to any of the junction portions.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: February 18, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Nobuaki Asayama
  • Patent number: 10566292
    Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first pad, and a second pad. A first opening and a second opening are formed in a first main surface of the first semiconductor layer. The second semiconductor layer is stacked on the first semiconductor layer. The first pad for wire bonding is disposed in the first opening. The second pad on which an alignment mark is formed is disposed in the second opening. A third opening and a fourth opening penetrate the second semiconductor layer. The first opening overlaps the third opening. The second opening overlaps the fourth opening.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: February 18, 2020
    Assignee: OLYMPUS CORPORATION
    Inventor: Naohiro Takazawa
  • Patent number: 10559548
    Abstract: An object of the present invention is to provide an anisotropic conductive bonding member capable of achieving excellent conduction reliability and insulation reliability, a semiconductor device using the same, a semiconductor package, and a semiconductor device production method. An anisotropic conductive bonding member of the present invention includes an insulating base which is made of an inorganic material, a plurality of conductive paths which are made of a conductive member, penetrate the insulating base in a thickness direction thereof, and are provided in a mutually insulated state, and a pressure sensitive adhesive layer which is provided on a surface of the insulating base, in which each of the conductive paths has a protrusion protruding from the surface of the insulating base, the protrusion of each of the conductive paths is buried in the pressure sensitive adhesive layer, and the pressure sensitive adhesive layer contains a polymer material and an antioxidant material.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: February 11, 2020
    Assignee: FUJIFILM Corporation
    Inventor: Kosuke Yamashita
  • Patent number: 10553553
    Abstract: A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji I. Nakamura
  • Patent number: 10545590
    Abstract: A touch panel includes a substrate, at least a connecting pad and at least a strengthening sheet. The substrate has a display area and a periphery area around the display area. The connecting pad is disposed in the periphery area. The strengthening sheet is disposed in the periphery area and at an edge of the connecting pad.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: January 28, 2020
    Assignee: TPK Touch Solutions (Xiamen) Inc.
    Inventors: Yuncong Su, Zhuanyuan Zhang, Yan Lin, Li Huang
  • Patent number: 10535728
    Abstract: Provided is a highly conductive crystalline multilayer structure including a corundum-structured crystalline oxide thin film whose resistance has not increased even after annealing (heating). The crystalline multilayer structure includes a base substrate and the corundum-structured crystalline oxide thin film disposed directly on the base substrate or with another layer therebetween. The crystalline oxide thin film is 1 ?m or more in a thickness and 80 m?cm or less in an electrical resistivity. A semiconductor device includes the crystalline multilayer structure.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: January 14, 2020
    Assignee: FLOSFIA INC.
    Inventors: Toshimi Hitora, Masaya Oda
  • Patent number: 10510706
    Abstract: A package structure including at least one semiconductor die, an insulating encapsulant, an insulating layer, conductive pillars, a dummy pillar, a first seed layer and a redistribution layer is provided. The semiconductor die have a first surface and a second surface opposite to the first surface. The insulating encapsulant is encapsulating the semiconductor die. The insulating layer is disposed on the first surface of the semiconductor die and on the insulating encapsulant. The conductive pillars are located on the semiconductor die. The dummy pillar is located on the insulating encapsulant. The first seed layer is embedded in the insulating layer, wherein the first seed layer is located in between the conductive pillars and the semiconductor die, and located in between the dummy pillar and the insulating encapsulant. The redistribution layer is disposed over the insulating layer and is electrically connected to the semiconductor die through the conductive pillars.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Po-Han Wang
  • Patent number: 10510595
    Abstract: A method of forming a semiconductor device includes attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil; forming a conductive pillar on a first side of the metal foil distal the carrier; attaching a semiconductor die to the first side of the metal foil; forming a molding material around the semiconductor die and the conductive pillar; and forming a redistribution structure over the molding material.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Wu, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, Long Hua Lee
  • Patent number: 10497679
    Abstract: A wafer level package that includes a first wafer; a second wafer facing the first wafer; a plurality of chips between the first wafer and the second wafer and arranged in an array; a plurality of sealing frames at predetermined intervals and surrounding each of the plurality of chips to seal the chips; and a coupling portion which couples opposed corners of respective sealing frames.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: December 3, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Masakazu Fukumitsu, Shuhei Yamada
  • Patent number: 10483160
    Abstract: A helmet layer is deposited on a plurality of conductive features on a first dielectric layer on a substrate. A second dielectric layer is deposited on a first portion of the helmet layer. An etch stop layer is deposited on a second portion the helmet layer.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: Jeffery D. Bielefeld, Manish Chandhok, Asad Iqbal, John D. Brooks
  • Patent number: 10483223
    Abstract: A slit is formed along a coupling portion at which a second interconnect is connected to a relatively large area interconnect or pad. Since tensile stress of a resist that is caused due to baking, UV curing, or other treatments in photolithography can be dispersed, contraction and deformation of the resist at an end of the second interconnect can be alleviated, and dimensions and shape of a interconnect, which is formed by etching, can be stabilized.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: November 19, 2019
    Assignee: ABLIC INC.
    Inventor: Hiroyuki Utsunomiya
  • Patent number: 10475741
    Abstract: The present embodiments provides a chip, including a carrier, a redistribution structure, and multiple packaging function modules, where the multiple packaging function modules each have at least a part wrapped by a colloid, and are fastened to the redistribution structure side by side; the redistribution structure is fastened to the carrier, and the redistribution structure includes one or more redistribution metal layers; the redistribution metal layer communicatively connects the multiple packaging function modules and the carrier. The redistribution structure further includes one or more interconnect metal layers, and the interconnect metal layer is communicatively connected to at least two packaging function modules so as to provide a signal path between the at least two packaging function modules. In the chip, two packaging function modules are placed on the carrier side by side, and a signal path is established between the two packaging function modules by using the redistribution structure.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: November 12, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: HuiLi Fu, Xiaodong Zhang, Jyh Rong Lin, Zhiqiang Ma
  • Patent number: 10477682
    Abstract: A printed wiring board includes a build-up layer including an insulating layer and a first conductor layer including a component mounting pad, a covering layer formed on the build-up layer such that the covering layer is covering the insulating layer and has opening exposing the pad, a reinforcement layer formed on the covering layer and having cavity exposing the pad and the covering layer, a conductor layer formed on the reinforcement layer such that the conductor layer is on the opposite side of the covering layer on the build-up layer, and a via conductor formed in the reinforcement layer such that the via conductor electrically connects the first conductor layer and conductor layer on the reinforcement layer. The first conductor layer is embedded in the insulating layer forming a surface of the build-up layer such that the first conductor layer has surface exposed on the surface of the build-up layer.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: November 12, 2019
    Assignee: IBIDEN CO., LTD.
    Inventors: Teruyuki Ishihara, Shunsuke Sakai
  • Patent number: 10468367
    Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: November 5, 2019
    Assignee: Intel Corporation
    Inventors: Chuan Hu, Shawna M. Liff, Gregory S. Clemons
  • Patent number: 10446512
    Abstract: A conductive ball includes a copper ball, a nickel layer formed with being patterned on an outer surface of the copper ball, and a tin-based solder covering each outer surface of the copper ball and the nickel layer.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: October 15, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Kei Murayama
  • Patent number: 10446411
    Abstract: A semiconductor package includes: (1) a substrate; (2) a first isolation layer disposed on the substrate, the first isolation layer including an opening; (3) a pad disposed on the substrate and exposed from the opening; (4) an interconnection layer disposed on the pad; and (5) a conductive post including a bottom surface, the bottom surface having a first part disposed on the interconnection layer and a plurality of second parts disposed on the first isolation layer.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: October 15, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, Yu-Ying Lee, Yu-Tzu Peng
  • Patent number: 10446510
    Abstract: A process of forming a semiconductor apparatus is disclosed. The process includes steps of: depositing a first metal layer containing Ni in a back surface of a substrate, plating the back surface of the substrate so as to expose the first metal layer in a portion of the scribe line, depositing a third metal layer on the whole back surface of the substrate, and selectively removing the third metal layer in the portion of the scribe line so as to leave the first metal layer in the scribe line.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: October 15, 2019
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Masaomi Emori
  • Patent number: 10431519
    Abstract: A semiconductor device assembly having a semiconductor device attached to a substrate with a foil layer on a surface of the substrate. A layer of adhesive connects the substrate to a first surface of the semiconductor device. The semiconductor device assembly enables processing on the second surface of the semiconductor device. An energy pulse may be applied to the foil layer causing an exothermic reaction to the foil layer that releases the substrate from the semiconductor device. The semiconductor device assembly may include a release layer positioned between the foil layer and the layer of adhesive that connects the substrate to the semiconductor device. The heat generated by the exothermic reaction breaks down the release layer to release the substrate from the semiconductor device. The energy pulse may be an electric charge, a heat pulse, or may be applied from a laser.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: James M. Derderian, Andrew M. Bayless, Xiao Li
  • Patent number: 10373914
    Abstract: The present disclosure provides methods for fabricating multi-layered electronic architectures in silicon and/or germanium. In particular the disclosure provides an advanced marker design and a methodology for aligning devices on multiple layers of a multi-layered electronic architecture. The disclosure also provides a process for growing a semiconductor material with high quality surfaces.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: August 6, 2019
    Assignee: NewSouth Innovations Pty Limited
    Inventors: Joris Gerhard Keizer, Matthias Koch, Michelle Yvonne Simmons
  • Patent number: 10373929
    Abstract: A method of manufacturing a semiconductor device includes forming an insulation layer on a support body, selectively forming openings through the insulation layer, forming a conductor pattern in the openings, and above selected portions of, the insulation layer, mounting a first semiconductor element on the insulation layer and electrically connecting the first semiconductor element to the conductor pattern, forming a resin over the first semiconductor element and the insulation layer, removing the support body after the resin is formed to expose a surface of a portion of the conductor pattern, etching the exposed surface of the portion of the conductor pattern to form a recess over the portion of the conductor pattern, and forming a pad containing a metal different than the metal of the conductor pattern in the recess in contact with the conductor pattern.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: August 6, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yoichiro Kurita
  • Patent number: 10355094
    Abstract: An electrical device including at least one contact surface and an interlevel dielectric layer present atop the electrical device, wherein the interlevel dielectric layer includes at least one trench to the at least one contact surface of the electrical device. A conformal titanium liner is present on the sidewalls of the trench and is in direct contact with the at least one contact surface. The conformal titanium liner may be composed of 100 wt. % titanium, and may have a thickness ranging from 10 ? to 100 ?.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: July 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Chih-Chao Yang
  • Patent number: 10346087
    Abstract: An apparatus for outputting an internal state of a memory apparatus and a memory system using the apparatus are provided. The apparatus includes a state signal generating circuit that generates a first signal indicating an internal operation state of the memory apparatus, and a state signal output control circuit that receives the first signal and outputs a second signal to an output pad based on a chip enable signal or an initially set function command, or both. The first signal indicates one state from among two states and the second signal indicates one state from among three states.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: July 9, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seong-hoon Woo, Hak-sun Kim, Kwang-jin Lee, Su-chang Jeon
  • Patent number: 10332856
    Abstract: A package structure including at least one semiconductor die, an insulating encapsulant, an insulating layer, conductive pillars, a dummy pillar, a first seed layer and a redistribution layer is provided. The semiconductor die have a first surface and a second surface opposite to the first surface. The insulating encapsulant is encapsulating the semiconductor die. The insulating layer is disposed on the first surface of the semiconductor die and on the insulating encapsulant. The conductive pillars are located on the semiconductor die. The dummy pillar is located on the insulating encapsulant. The first seed layer is embedded in the insulating layer, wherein the first seed layer is located in between the conductive pillars and the semiconductor die, and located in between the dummy pillar and the insulating encapsulant. The redistribution layer is disposed over the insulating layer and is electrically connected to the semiconductor die through the conductive pillars.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: June 25, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Po-Han Wang
  • Patent number: 10312603
    Abstract: A fixing method for fixing a terminal to a conductive pattern with a brazing filler metal disposed therebetween includes: a first step of disposing the brazing filler metal on the conductive pattern; a second step of bringing the terminal into contact with the brazing filler metal; and a third step of forming a penetrating hole in the terminal by irradiating a laser beam onto the terminal. In the third step, the laser beam is irradiated onto the terminal in such a manner that the penetrating hole is filled with the brazing filler metal melted by the irradiation of the laser beam.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: June 4, 2019
    Assignee: Japan Aviation Electronics Industry, Ltd.
    Inventors: Takushi Yoshida, Hiroshi Akimoto, Yosuke Seki
  • Patent number: 10297466
    Abstract: Provided are a semiconductor device including an interposer having a relatively thin thickness without a through silicon via and a method of manufacturing the same. The method of manufacturing a semiconductor device includes forming an interposer including a redistribution layer and a dielectric layer on a dummy substrate, connecting a semiconductor die to the redistribution layer facing an upper portion of the interposer, encapsulating the semiconductor die by using an encapsulation, removing the dummy substrate from the interposer, and connecting a bump to the redistribution layer facing a lower portion of the interposer.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: May 21, 2019
    Assignee: Amkor Technology, Inc.
    Inventors: Won Chul Do, Doo Hyun Park, Jong Sik Paek, Ji Hun Lee, Seong Min Seo
  • Patent number: 10278629
    Abstract: In one embodiment, an implantable biosensor includes a sense antenna comprising a silicon carbide substrate and a radiating electrode formed on the substrate.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: May 7, 2019
    Assignees: University of South Florida, Mississippi State University
    Inventors: Shamima Afroz, Sylvia Wilson Thomas, Stephen E. Saddow, Gokhan Mumcu, Erdem Topsakal
  • Patent number: 10283453
    Abstract: Embodiments of the present disclosure are directed toward interconnect routing configurations and associated techniques. In one embodiment, an apparatus includes a substrate, a first routing layer disposed on the substrate and having a first plurality of traces, and a second routing layer disposed directly adjacent to the first routing layer and having a second plurality of traces, wherein a first trace of the first plurality of traces has a width that is greater than a width of a second trace of the second plurality of traces. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: May 7, 2019
    Assignee: Intel Corporation
    Inventors: Zhiguo Qian, Kemal Aygun, Dae-Woo Kim
  • Patent number: 10276493
    Abstract: A semiconductor structure includes a conductive feature on a substrate. A plurality of first dielectric layers are disposed on the conductive feature, and stress directions of at least two of the first dielectric layers are different from one another. A first hole penetrates through the plurality of the first dielectric layers to expose the conductive feature. A first conductive plug conformally covers the first hole and is electrically connected to the conductive feature. A first insulating plug on the first conductive plug fills the first hole.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: April 30, 2019
    Assignee: VANGUARD ENTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Wei-Lun Hsia, Chun-Hsien Lin, Hsiao-Ying Yang
  • Patent number: 10278292
    Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: April 30, 2019
    Assignee: Intel Corporation
    Inventors: Md Altaf Hossain, Scott A. Gilbert
  • Patent number: 10266390
    Abstract: A device includes a substrate, a routing conductive line over the substrate, a dielectric layer over the routing conductive line, and an etch stop layer over the dielectric layer. A Micro-Electro-Mechanical System (MEMS) device has a portion over the etch stop layer. A contact plug penetrates through the etch stop layer and the dielectric layer. The contact plug connects the portion of the MEMS device to the routing conductive line. An escort ring is disposed over the etch stop layer and under the MEMS device, wherein the escort ring encircles the contact plug.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Ying Tsai, Hsin-Ting Huang, Lung Yuan Pan, Jung-Huei Peng, Hung-Hua Lin, Yao-Te Huang
  • Patent number: 10256174
    Abstract: A film type semiconductor package includes a film substrate; a metal pattern extending a first length in a first direction on the film substrate, having a first width in a second direction perpendicular to the first direction the first length being larger than the first width, and includes a plurality of through holes spaced apart from each other in the first direction; a semiconductor chip including a plurality of pads; and a plurality of bumps spaced apart from each other in the first direction, bonded with the metal pattern, and overlapping the plurality of through holes and connected to the pads of the semiconductor chip.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: April 9, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Na-rae Shin, Jun-ho Song, Ji-yong Park, Kyoung-suk Yang, Hee-jung Hwang, Young-hun Jung
  • Patent number: 10249724
    Abstract: An electrical device including at least one contact surface and an interlevel dielectric layer present atop the electrical device, wherein the interlevel dielectric layer includes at least one trench to the at least one contact surface of the electrical device. A conformal titanium liner is present on the sidewalls of the trench and is in direct contact with the at least one contact surface. The conformal titanium liner may be composed of 100 wt. % titanium, and may have a thickness ranging from 10? to 100?.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Chih-Chao Yang
  • Patent number: 10242927
    Abstract: A semiconductor package includes a substrate, a first electronic component, a film and a package body. The first electronic component is disposed on the substrate and has an upper surface. The film is disposed on the upper surface of the first electronic component. The package body encapsulates the first electronic component and the film.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: March 26, 2019
    Assignee: MediaTek Inc.
    Inventors: Wen-Sung Hsu, Shih-Chin Lin, Ming-Jen Hsiung
  • Patent number: 10243881
    Abstract: Embodiments described herein generally relate to the use of three-dimensional solid state memory structures, both volatile and non-volatile, utilizing a Network-on-Chip routing protocol which provide for the access of memory storage via a router. As such, data may be sent to and/or from memory storage as data packets on the chip. The Network-on-Chip routing protocol may be utilized to interconnect unlimited numbers of three-dimensional memory cell matrices, spread on a die, or multiple dies, thus allowing for reduced latencies among matrices, selective power control, unlimited memory density growth without major latency penalties, and reduced parasitic capacitance and resistance. Other benefits include a reduction in total density as compared to two-dimensional solid state memory structures utilizing a Network-on-Chip routing protocol, improved signal integrity, larger die areas, improved bandwidths and higher frequencies of operation.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: March 26, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Zvonimir Z. Bandic, Luis Cargnini, Kurt Allan Rubin, Dejan Vucinic
  • Patent number: 10243106
    Abstract: A light emitting device includes a substrate, a light emitting element, a plurality of bumps and a cover member. The bumps are disposed between the substrate and the light emitting element to mount the light emitting element on the substrate. The bumps include a plurality of first bumps bonded to a first electrode of the light emitting element, and a plurality of second bumps bonded to a second electrode of the light emitting element. The first bumps are spaced apart from exposed portions of a first semiconductor layer of the light emitting element. The first bumps include a plurality of large bumps and a plurality of small bumps each having a smaller surface area than each of the large bumps in a plan view. The cover member covers the light emitting element, the bumps, and the substrate.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: March 26, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Kenji Ozeki, Akira Goto
  • Patent number: 10217644
    Abstract: In various aspects of the disclosure, a semiconductor device including at least one semiconductor die; a dielectric layer adjoining the semiconductor die; geometric structures formed in the dielectric layer; and a conductive layer deposited over the dielectric layer, wherein the conductive layer is at least partially located over the geometric structures.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: February 26, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Grille, Ursula Hedenig, Joern Plagmann, Helmut Schoenherr, Ralph Muth
  • Patent number: 10204978
    Abstract: Provided is a highly conductive crystalline multilayer structure including a corundum-structured crystalline oxide thin film whose resistance has not increased even after annealing (heating). The crystalline multilayer structure includes a base substrate and the corundum-structured crystalline oxide thin film disposed directly on the base substrate or with another layer therebetween. The crystalline oxide thin film is 1 ?m or more in a thickness and 80 m?cm or less in an electrical resistivity. A semiconductor device includes the crystalline multilayer structure.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: February 12, 2019
    Assignee: FLOSFIA INC.
    Inventors: Toshimi Hitora, Masaya Oda