Combined With Electrical Contact Or Lead Patents (Class 257/734)
  • Patent number: 10346087
    Abstract: An apparatus for outputting an internal state of a memory apparatus and a memory system using the apparatus are provided. The apparatus includes a state signal generating circuit that generates a first signal indicating an internal operation state of the memory apparatus, and a state signal output control circuit that receives the first signal and outputs a second signal to an output pad based on a chip enable signal or an initially set function command, or both. The first signal indicates one state from among two states and the second signal indicates one state from among three states.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: July 9, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seong-hoon Woo, Hak-sun Kim, Kwang-jin Lee, Su-chang Jeon
  • Patent number: 10332856
    Abstract: A package structure including at least one semiconductor die, an insulating encapsulant, an insulating layer, conductive pillars, a dummy pillar, a first seed layer and a redistribution layer is provided. The semiconductor die have a first surface and a second surface opposite to the first surface. The insulating encapsulant is encapsulating the semiconductor die. The insulating layer is disposed on the first surface of the semiconductor die and on the insulating encapsulant. The conductive pillars are located on the semiconductor die. The dummy pillar is located on the insulating encapsulant. The first seed layer is embedded in the insulating layer, wherein the first seed layer is located in between the conductive pillars and the semiconductor die, and located in between the dummy pillar and the insulating encapsulant. The redistribution layer is disposed over the insulating layer and is electrically connected to the semiconductor die through the conductive pillars.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: June 25, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Po-Han Wang
  • Patent number: 10312603
    Abstract: A fixing method for fixing a terminal to a conductive pattern with a brazing filler metal disposed therebetween includes: a first step of disposing the brazing filler metal on the conductive pattern; a second step of bringing the terminal into contact with the brazing filler metal; and a third step of forming a penetrating hole in the terminal by irradiating a laser beam onto the terminal. In the third step, the laser beam is irradiated onto the terminal in such a manner that the penetrating hole is filled with the brazing filler metal melted by the irradiation of the laser beam.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: June 4, 2019
    Assignee: Japan Aviation Electronics Industry, Ltd.
    Inventors: Takushi Yoshida, Hiroshi Akimoto, Yosuke Seki
  • Patent number: 10297466
    Abstract: Provided are a semiconductor device including an interposer having a relatively thin thickness without a through silicon via and a method of manufacturing the same. The method of manufacturing a semiconductor device includes forming an interposer including a redistribution layer and a dielectric layer on a dummy substrate, connecting a semiconductor die to the redistribution layer facing an upper portion of the interposer, encapsulating the semiconductor die by using an encapsulation, removing the dummy substrate from the interposer, and connecting a bump to the redistribution layer facing a lower portion of the interposer.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: May 21, 2019
    Assignee: Amkor Technology, Inc.
    Inventors: Won Chul Do, Doo Hyun Park, Jong Sik Paek, Ji Hun Lee, Seong Min Seo
  • Patent number: 10278629
    Abstract: In one embodiment, an implantable biosensor includes a sense antenna comprising a silicon carbide substrate and a radiating electrode formed on the substrate.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: May 7, 2019
    Assignees: University of South Florida, Mississippi State University
    Inventors: Shamima Afroz, Sylvia Wilson Thomas, Stephen E. Saddow, Gokhan Mumcu, Erdem Topsakal
  • Patent number: 10283453
    Abstract: Embodiments of the present disclosure are directed toward interconnect routing configurations and associated techniques. In one embodiment, an apparatus includes a substrate, a first routing layer disposed on the substrate and having a first plurality of traces, and a second routing layer disposed directly adjacent to the first routing layer and having a second plurality of traces, wherein a first trace of the first plurality of traces has a width that is greater than a width of a second trace of the second plurality of traces. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: May 7, 2019
    Assignee: Intel Corporation
    Inventors: Zhiguo Qian, Kemal Aygun, Dae-Woo Kim
  • Patent number: 10276493
    Abstract: A semiconductor structure includes a conductive feature on a substrate. A plurality of first dielectric layers are disposed on the conductive feature, and stress directions of at least two of the first dielectric layers are different from one another. A first hole penetrates through the plurality of the first dielectric layers to expose the conductive feature. A first conductive plug conformally covers the first hole and is electrically connected to the conductive feature. A first insulating plug on the first conductive plug fills the first hole.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: April 30, 2019
    Assignee: VANGUARD ENTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Wei-Lun Hsia, Chun-Hsien Lin, Hsiao-Ying Yang
  • Patent number: 10278292
    Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: April 30, 2019
    Assignee: Intel Corporation
    Inventors: Md Altaf Hossain, Scott A. Gilbert
  • Patent number: 10266390
    Abstract: A device includes a substrate, a routing conductive line over the substrate, a dielectric layer over the routing conductive line, and an etch stop layer over the dielectric layer. A Micro-Electro-Mechanical System (MEMS) device has a portion over the etch stop layer. A contact plug penetrates through the etch stop layer and the dielectric layer. The contact plug connects the portion of the MEMS device to the routing conductive line. An escort ring is disposed over the etch stop layer and under the MEMS device, wherein the escort ring encircles the contact plug.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Ying Tsai, Hsin-Ting Huang, Lung Yuan Pan, Jung-Huei Peng, Hung-Hua Lin, Yao-Te Huang
  • Patent number: 10256174
    Abstract: A film type semiconductor package includes a film substrate; a metal pattern extending a first length in a first direction on the film substrate, having a first width in a second direction perpendicular to the first direction the first length being larger than the first width, and includes a plurality of through holes spaced apart from each other in the first direction; a semiconductor chip including a plurality of pads; and a plurality of bumps spaced apart from each other in the first direction, bonded with the metal pattern, and overlapping the plurality of through holes and connected to the pads of the semiconductor chip.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: April 9, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Na-rae Shin, Jun-ho Song, Ji-yong Park, Kyoung-suk Yang, Hee-jung Hwang, Young-hun Jung
  • Patent number: 10249724
    Abstract: An electrical device including at least one contact surface and an interlevel dielectric layer present atop the electrical device, wherein the interlevel dielectric layer includes at least one trench to the at least one contact surface of the electrical device. A conformal titanium liner is present on the sidewalls of the trench and is in direct contact with the at least one contact surface. The conformal titanium liner may be composed of 100 wt. % titanium, and may have a thickness ranging from 10? to 100?.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Chih-Chao Yang
  • Patent number: 10243106
    Abstract: A light emitting device includes a substrate, a light emitting element, a plurality of bumps and a cover member. The bumps are disposed between the substrate and the light emitting element to mount the light emitting element on the substrate. The bumps include a plurality of first bumps bonded to a first electrode of the light emitting element, and a plurality of second bumps bonded to a second electrode of the light emitting element. The first bumps are spaced apart from exposed portions of a first semiconductor layer of the light emitting element. The first bumps include a plurality of large bumps and a plurality of small bumps each having a smaller surface area than each of the large bumps in a plan view. The cover member covers the light emitting element, the bumps, and the substrate.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: March 26, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Kenji Ozeki, Akira Goto
  • Patent number: 10242927
    Abstract: A semiconductor package includes a substrate, a first electronic component, a film and a package body. The first electronic component is disposed on the substrate and has an upper surface. The film is disposed on the upper surface of the first electronic component. The package body encapsulates the first electronic component and the film.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: March 26, 2019
    Assignee: MediaTek Inc.
    Inventors: Wen-Sung Hsu, Shih-Chin Lin, Ming-Jen Hsiung
  • Patent number: 10243881
    Abstract: Embodiments described herein generally relate to the use of three-dimensional solid state memory structures, both volatile and non-volatile, utilizing a Network-on-Chip routing protocol which provide for the access of memory storage via a router. As such, data may be sent to and/or from memory storage as data packets on the chip. The Network-on-Chip routing protocol may be utilized to interconnect unlimited numbers of three-dimensional memory cell matrices, spread on a die, or multiple dies, thus allowing for reduced latencies among matrices, selective power control, unlimited memory density growth without major latency penalties, and reduced parasitic capacitance and resistance. Other benefits include a reduction in total density as compared to two-dimensional solid state memory structures utilizing a Network-on-Chip routing protocol, improved signal integrity, larger die areas, improved bandwidths and higher frequencies of operation.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: March 26, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Zvonimir Z. Bandic, Luis Cargnini, Kurt Allan Rubin, Dejan Vucinic
  • Patent number: 10217644
    Abstract: In various aspects of the disclosure, a semiconductor device including at least one semiconductor die; a dielectric layer adjoining the semiconductor die; geometric structures formed in the dielectric layer; and a conductive layer deposited over the dielectric layer, wherein the conductive layer is at least partially located over the geometric structures.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: February 26, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Grille, Ursula Hedenig, Joern Plagmann, Helmut Schoenherr, Ralph Muth
  • Patent number: 10204978
    Abstract: Provided is a highly conductive crystalline multilayer structure including a corundum-structured crystalline oxide thin film whose resistance has not increased even after annealing (heating). The crystalline multilayer structure includes a base substrate and the corundum-structured crystalline oxide thin film disposed directly on the base substrate or with another layer therebetween. The crystalline oxide thin film is 1 ?m or more in a thickness and 80 m?cm or less in an electrical resistivity. A semiconductor device includes the crystalline multilayer structure.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: February 12, 2019
    Assignee: FLOSFIA INC.
    Inventors: Toshimi Hitora, Masaya Oda
  • Patent number: 10192798
    Abstract: An electronic system is provided, including an integrated circuit die having at least 2 bond pads, and a redistribution layer having at least one solder pad including 2 portions separated from each other and configured to provide an electrical connection between each of the 2 portions by a solder ball disposed on the solder pad, and to electrically isolate the 2 portions in an absence of the solder ball on the solder pad, and at least 2 redistribution wires, each connecting a different one of the portions to a different one of the bond pads, a second bond pad being connected via a second redistribution wire to a second portion being dedicated to die testing; and a grounded printed circuit board track, wherein the solder ball is disposed between the solder pad and the track, and neither of the redistribution wires traverses a separation space between the 2 portions.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: January 29, 2019
    Assignee: EM Microelectronic-Marin SA
    Inventors: Christoph Kuratli, Yves Dupraz
  • Patent number: 10181438
    Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer is embedded in the dielectric layer and is exposed from the first surface. The first protection layer covers a portion of the first circuit layer and defines a plurality of holes that expose a remaining portion of the first circuit layer. The conductive posts are formed in the holes.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: January 15, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chun-Che Lee, Ming-Chiang Lee, Yuan-Chang Su, Tien-Szu Chen, Chih-Cheng Lee, You-Lung Yen
  • Patent number: 10177083
    Abstract: Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: January 8, 2019
    Assignee: Intel Corporation
    Inventors: Dae-Woo Kim, Sujit Sharan
  • Patent number: 10177011
    Abstract: A chip packaging method includes forming a first redistribution layer and a first dielectric layer on a first temporary carrier to generate a plurality of first conductive interfaces close to the first temporary carrier, each pair of neighboring first conductive interfaces having a first pitch; forming a second dielectric layer on a first portion of the first redistribution layer and the first dielectric layer so as to cover the first portion of the first redistribution layer and expose a second portion; and forming a second redistribution layer and a third dielectric layer over the second dielectric layer to generate a plurality of second conductive interfaces. A circuitry being formed by at least the first redistribution layer and the second redistribution layer and each pair of neighboring second conductive interfaces has a second pitch larger than the first pitch.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: January 8, 2019
    Assignee: POWERTECH TECHNOLOGY INC.
    Inventors: Hung-Hsin Hsu, Nan-Chun Lin, Shang-Yu Chang Chien
  • Patent number: 10164106
    Abstract: A semiconductor device includes a substrate provided with an electronic device, an interlayer dielectric (ILD) layer formed over the electronic device, a wiring pattern formed on the ILD layer and a contact formed in the ILD layer and physically and electrically connecting the wiring pattern to a conductive region of the electronic device. An insulating liner layer is provided on sidewalls of the contact between the contact and the ILD layer. A height of the insulating liner layer measured from a top of the conductive region of the electronic device is less than 90% of a height of the contact measured between the top of the conductive region and a level of an interface between the ILD layer and the wiring pattern.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Lien Huang, Meng-Chun Chang
  • Patent number: 10157889
    Abstract: A method comprises depositing a first dielectric layer over a first chip comprising a plurality of first active circuits and a first connection pad, patterning the first dielectric layer to form a first opening, filling the first opening to form a connector in contact with the first connection pad, depositing a second dielectric layer over the first dielectric layer, patterning the second dielectric layer to form a second opening over the connector, filling the second opening to form a first bonding pad in contact with the connector, stacking a second chip on the first chip, wherein the second chip comprises a plurality of second active circuits and a second bonding pad and bonding the first chip and a second chip together to form a stacked semiconductor device through applying a hybrid bonding process to the first bonding pad and the second bonding pad.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ying Chen, Meng-Hsun Wan, Dun-Nian Yaung
  • Patent number: 10153222
    Abstract: An embodiment is a method including: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a second die to first side of the first component using second electrical connectors, attaching a dummy die to the first side of the first component in a scribe line region of the first component, adhering a cover structure to a second side of the second die, and singulating the first component and the dummy die to form a package structure.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: December 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hsien-Pin Hu, Jing-Cheng Lin, Szu-Wei Lu, Shang-Yun Hou, Wen-Hsin Wei, Ying-Ching Shih, Chi-Hsi Wu
  • Patent number: 10134653
    Abstract: The semiconductor device has the CSP structure, and may include a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps may be arranged in two rows along the periphery of the semiconductor device. The electrode pads may be arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring may be extended from an electrode pad, and may be connected to any one of the outermost solder bumps or any one of the inner solder bumps.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: November 20, 2018
    Assignee: ROHM CO., LTD.
    Inventor: Kunihiro Komiya
  • Patent number: 10134984
    Abstract: Providing an electrode for a two-terminal memory device is described herein. By way of example, the electrode can comprise a contact surface that comprises at least one surface discontinuity. For instance, the electrode can have a gap, break, or other discontinuous portion of a surface that makes electrical contact with another component of the two-terminal memory device. In one example, the contact surface can comprise an annulus or an approximation of an annulus, having a discontinuity within a center of the annulus, for instance. In some embodiments, a disclosed electrode can be formed from a conductive layer deposited over a non-continuous surface formed by a via or trench in an insulator, or over a pillar device formed from or on the insulator.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: November 20, 2018
    Assignee: CROSSBAR, INC.
    Inventors: Sung Hyun Jo, Joanna Bettinger, Xianliang Liu, Zeying Ren, Xu Zhao, Fnu Atiquzzaman
  • Patent number: 10134757
    Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: November 20, 2018
    Assignee: ASM IP Holding B.V.
    Inventors: Seung Ju Chun, Yong Min Yoo, Jong Wan Choi, Young Jae Kim, Sun Ja Kim, Wan Gyu Lim, Yoon Ki Min, Hae Jin Lee, Tae Hee Yoo
  • Patent number: 10134698
    Abstract: The present disclosure provides bond pad structures, boning ring structure; and MEMS device packaging methods. An exemplary bonding pad structure includes a plurality of first metal blocks made of a first metal material; and a plurality of second metal blocks made of a second metal material. The plurality of first metal blocks are used to prevent the squeezing out and extending of the plurality of second metal blocks. On at least one equal dividing plane of the bonding pad structure, the first metal material is shown at least one time; and the second metal material is shown at least one time.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: November 20, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Fucheng Chen, Linbo Shi, Yao Liu
  • Patent number: 10115691
    Abstract: A module, comprising an electronic component having a first electrode, a mounting board having a second electrode, a solder-bump configured to connect the first electrode and the second electrode, and a thermoplastic resin member configured to contact both the first electrode and the second electrode and cover the solder-bump, so as to form a space between the electronic component and the mounting board.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: October 30, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Ichiro Kataoka, Takahiro Hachisu, Tadashi Kosaka
  • Patent number: 10109566
    Abstract: A semiconductor package includes a substrate and a flip-chip on the substrate The flip-chip includes first bump pads and second bump pads on an active surface of the flip-chip. Vias are disposed on the second bump pads. The first bump pads have a pad size that is smaller than that of the second bump pads. An underfill layer is disposed between the flip-chip and the substrate to surround the vias. The underfill layer is in direct contact with a surface of each of the first bump pads.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: October 23, 2018
    Assignee: MEDIATEK INC.
    Inventors: Jia-Wei Fang, Tzu-Hung Lin
  • Patent number: 10109707
    Abstract: Provided is a highly conductive crystalline multilayer structure including a corundum-structured crystalline oxide thin film whose resistance has not increased even after annealing (heating). The crystalline multilayer structure includes a base substrate and the corundum-structured crystalline oxide thin film disposed directly on the base substrate or with another layer therebetween. The crystalline oxide thin film is 1 ?m or more in a thickness and 80 m?cm or less in an electrical resistivity. A semiconductor device includes the crystalline multilayer structure.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: October 23, 2018
    Assignee: FLOSFIA INC.
    Inventors: Toshimi Hitora, Masaya Oda
  • Patent number: 10096551
    Abstract: An electronic component of integrated circuitry comprises a substrate comprising at least two terminals. Material of one of the terminals has an upper surface. A conductive via extends elevationally into the material of the one terminal. The conductive via extends laterally into the material of the one terminal under the upper surface of the one terminal. Material of the one terminal is above at least some of the laterally extending conductive via. Other embodiments, including method embodiments, are disclosed.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: October 9, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Deepak Chandra Pandey, Haitao Liu
  • Patent number: 10090238
    Abstract: A wiring substrate includes insulating layers including a first insulating layer and an outermost insulating layer such that the first insulating layer is positioned at one end of the insulating layers in a lamination direction and that the outermost insulating layer is positioned at the opposite end of the insulating layers in the lamination direction and includes a reinforcing material; conductive layers laminated on the insulating layers such that the conductive layers include an outermost conductive layer formed on the outermost insulating layer and including pads, and a semiconductor element accommodated in an accommodating portion of the first insulating layer. The insulating layers are formed such that the insulating layers do not contain a reinforcing material other than the outermost insulating layer.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: October 2, 2018
    Assignee: IBIDEN CO., LTD.
    Inventors: Hajime Sakamoto, Keisuke Shimizu
  • Patent number: 10074624
    Abstract: Integrated circuit dies are provide with a passivation layer having a plurality of differently sized openings exposing bond pads for bonding. The sizes of the bond pads vary in a manner that at least partially compensates for stresses during bonding, such as flip chip thermocompression bonding, due to asymmetric distribution of bond pads.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: September 11, 2018
    Assignee: Analog Devices, Inc.
    Inventor: Vikram Venkatadri
  • Patent number: 10074632
    Abstract: A solid-state drive (SSD) includes a main printed circuit board (PCB), and a first semiconductor package and a second semiconductor package respectively mounted on a top surface and a bottom surface of the main PCB. Each of the first and second semiconductor packages has a surface on which connection pads corresponding to a package ball map are disposed. The package ball map includes cells arranged in a plurality of rows and a plurality of columns, and one signal corresponds to each of the cells of the package ball map. The package ball map includes first signals corresponding to at least some of cells included in a selected reference column from among the plurality of columns, and at least one pair of second signals respectively corresponding to cells that are symmetrical to each other with respect to the reference column. The pair of second signals are swappable signals, and the first signals are not swappable signals.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: September 11, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Sub Song, Sang-Ho Park, Ki-Hong Jeong
  • Patent number: 10065418
    Abstract: A liquid election head includes a recording element substrate, an electrical wiring substrate configured to supply an electrical signal to the recording element substrate, a plurality of wires electrically connecting a plurality of electrode terminals on the recording element substrate with a plurality of connection terminals on the electrical wiring substrate, and a sealant sealing an electrical connection portion. The plurality of wires form a wire array. At least one of the plurality of wires positioned at one end of the wire array in a wire array direction is shorter than the other wires in the wire array.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: September 4, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tomohiro Takahashi
  • Patent number: 10056352
    Abstract: An apparatus includes at least a first IC die and a second IC die. Bottom surfaces of the first and second IC dice include a first plurality of connection pads and top surfaces of the first and second IC dice include a second plurality of connection pads. The apparatus also includes a layer of non-conductive material covering the top surfaces of the first and second IC dice, a plurality of through-vias, first conductive interconnect between at least a portion of the first plurality of connection pads and at least one through via, and second conductive interconnect on a top surface of the layer of non-conductive material that provides electrical continuity between at least a portion of the second plurality of connection pads and at least one through-via of the plurality of through-vias.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: August 21, 2018
    Assignee: Intel IP Corporation
    Inventor: Thorsten Meyer
  • Patent number: 10040807
    Abstract: A flame retardant filler having brominated silica particles, for example, imparts flame retardancy to manufactured articles such as printed circuit boards (PCBs), connectors, and other articles of manufacture that employ thermosetting plastics or thermoplastics. In this example, brominated silica particles serve both as a filler for rheology control (viscosity, flow, etc.) and a flame retardant. In an exemplary application, a PCB laminate stack-up includes conductive planes separated from each other by a dielectric material that includes a flame retardant filler comprised of brominated silica particles. In an exemplary method of synthesizing the brominated silica particles, a monomer having a brominated aromatic functional group is reacted with functionalized silica particles (e.g., isocyanate, vinyl, amine, or epoxy functionalized silica particles).
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporation
    Inventors: Dylan J. Boday, Joseph Kuczynski, Robert E. Meyer, III
  • Patent number: 10037943
    Abstract: A method for fabricating a metal gate transistor includes forming a dummy gate structure surrounded by a first dielectric layer on a semiconductor substrate and a source/drain region in the semiconductor substrate on each side of the dummy gate structure. The top surface of the dummy gate structure is leveled with the top surface of the first dielectric layer. The method then includes forming an etch stop sidewall in the first dielectric layer on each side of the dummy gate structure, forming a first trench by removing the dummy gate structure, and forming a metal gate structure to partially fill the first trench. The top portion of the first trench becomes a second trench. Further, the method also includes forming an etch stop layer by filling the second trench, and then forming a contact plug in the first dielectric layer to electrically connect to each source/drain region.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: July 31, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Jie Zhao
  • Patent number: 10037942
    Abstract: An electrical device including at least one contact surface and an interlevel dielectric layer present atop the electrical device, wherein the interlevel dielectric layer includes at least one trench to the at least one contact surface of the electrical device. A conformal titanium liner is present on the sidewalls of the trench and is in direct contact with the at least one contact surface. The conformal titanium liner may be composed of 100 wt. % titanium, and may have a thickness ranging from 10 ? to 100 ?.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: July 31, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Chih-Chao Yang
  • Patent number: 10037937
    Abstract: A method of fabricating semiconductor packages includes providing an interposer layer having a first surface and a second surface opposite to the first surface, in which the interposer layer includes through interposer vias embedded inside, and the through interposer vias extended from the first surface toward the second surface, in which through interposer vias are patterned to form repetitive polygonal-packing units, and part of the through interposer vias can be grouped within at least two distinct said polygonal-packing units; subsequently, forming at least one redistribution layer on the first surface to form terminals on a surface of the redistribution layer away from the interposer layer, in which the terminals are selectively connected to the through interposer vias respectively; and then disposing at least one semiconductor chip on the redistribution layer, wherein the semiconductor chip includes active surfaces electrically connected to the terminals respectively.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: July 31, 2018
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Po-Chun Lin
  • Patent number: 10032721
    Abstract: An electrical device including at least one contact surface and an interlevel dielectric layer present atop the electrical device, wherein the interlevel dielectric layer includes at least one trench to the at least one contact surface of the electrical device. A conformal titanium liner is present on the sidewalls of the trench and is in direct contact with the at least one contact surface. The conformal titanium liner may be composed of 100 wt. % titanium, and may have a thickness ranging from 10 ? to 100 ?.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: July 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Chih-Chao Yang
  • Patent number: 10026707
    Abstract: A copper pillar bump semiconductor packaging method patterns an organic insulation layer formed under the copper pillar bumps to areas surrounding and in the vicinity of the copper pillar bumps only. The organic insulation layer, typically a thin film polymer layer, acts as a barrier layer for the copper pillar bumps to protect the semiconductor wafer during the copper pillar flip chip bonding process. The copper pillar bump semiconductor packaging method limits the areas where the organic insulation layer is applied to reduce the stress introduced to the semiconductor wafer by the organic insulation layer. In another embodiment, a copper pillar bump semiconductor packaging method patterns an organic insulation layer formed under the copper pillar bumps to areas surrounding the copper pillar bumps and along the path of a redistribution layer without using a large and continuous organic insulation layer.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: July 17, 2018
    Assignee: Microchip Technology Incorportated
    Inventor: George Chu
  • Patent number: 10020434
    Abstract: A surface-mountable optoelectronic component has a radiation passage face, an optoelectronic semiconductor chip and a chip carrier. A cavity is formed in the chip carrier and the semiconductor chip is arranged in the cavity. A molding surrounds the chip carrier at least in places. The chip carrier extends completely through the molding in a vertical direction perpendicular to the radiation passage face.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: July 10, 2018
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Michael Zitzlsperger, Harald Jaeger
  • Patent number: 10020357
    Abstract: An integrated sense resistor within an integrated circuit (IC) may be surroundingly positioned near and coupled to a connection such as a pin or ball. The integrated sense resistor may be shaped such that more surface area of the integrated sense resistor is coupled to be positioned closer or in actual contact with the pin or ball than conventional straight layered integrated sense resistor solutions. The integrated sense resistor may be a non-straight shape that entirely surrounds or wraps around a connection to the pin or ball, such as a circular or oval shape, a box or rectangular shape, a triangular shape, or a polygonal shape. The integrated sense resistor may be a non-straight shape that partially surrounds a connection to the pin or ball, such as an open-circular or semi-circular shape, an open-sided box or rectangular shape, an open-sided triangular shape, an angular shape, or an open curved shape.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: July 10, 2018
    Assignee: Cirrus Logic, Inc.
    Inventors: Scott Allan Woodford, John Christopher Tucker, Marc L. Tarabbia
  • Patent number: 10020248
    Abstract: Provided is a tape for electronic devices with lead crack and a method of manufacturing the tape. According to the present invention, by forming a cutting portion on a narrow circuit pattern to be connected from an inner lead to an outer lead and further forming the cutting portion within a resin application portion, the problem of occurrence of cracks along a width of a narrow wiring can be avoided. The tape may include a first lead and a second lead formed on a dielectric substrate and a cutting portion formed on one of the first lead and the second lead wherein the cutting portion is formed within a resin application portion.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: July 10, 2018
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Dae Sung Yoo, Han Mo Koo, Ki Tae Park, Jun Young Lim, Tae Ki Hong
  • Patent number: 9993189
    Abstract: Personal diagnostic devices including diagnostic patches (bio-patches) and interactive medical bracelets (bio-bracelets) are provided with a skin/patch interface, at least one analysis layer, a signal processing layer, and a user output interface. Embodiments of the interactive diagnostic devices may include micro-fluidic circuits with reaction chambers, analysis chambers, mixing cambers, and various pre-disposed chemistries or reagents for performing a wide verity of tests by transdermal transport of blood or perspiration. Sample collection chambers for the fluidic circuit may include minimally invasive tubules that penetrate the skin surface to acquire blood samples from capillaries near the epidermis. Alternate implementations of the personal diagnostic device may be equipped with logic processing, input/output devices, acoustic microphones, cryogenic circuits, embedded processors, electrical control circuitry, and battery current sources or photovoltaic sources of electrical power.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: June 12, 2018
    Assignee: Life Patch International
    Inventors: Brigitte Chau Phan, Andrew Atilla Pal, Ramoncito M. Valencia, Donald Bollella
  • Patent number: 9991373
    Abstract: In an embodiment, a semiconductor device includes a substrate, a Group III nitride based transistor arranged on a front surface of the substrate, and a conductive through substrate via. The conductive through substrate via includes a via extending from the front surface to a rear surface of the substrate, and conductive material extending from the front surface to the rear surface of the substrate. The via tapers from the front surface to the rear surface of the substrate.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: June 5, 2018
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Helmut Brech
  • Patent number: 9978711
    Abstract: A semiconductor chip includes a semiconductor body having a lower side with a lower chip metallization applied thereto. A first contact metallization layer is produced on the lower chip metallization. A second contact metallization layer is produced on a metal surface of a substrate. The semiconductor chip and the substrate are pressed onto one another for a pressing time so that the first and second contact metallization layers bear directly and extensively on one another. During the pressing time, the first contact metallization layer is kept continuously at temperatures which are lower than the melting temperature of the first contact metallization layer. The second contact metallization layer is kept continuously at temperatures which are lower than the melting temperature of the second contact metallization layer during the pressing time. After the pressing together, the first and second contact metallization layers have a total thickness less than 1000 nm.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: May 22, 2018
    Assignee: Infineon Technologies AG
    Inventors: Gopalakrishnan Trichy Rengarajan, Christian Stahlhut
  • Patent number: 9972556
    Abstract: A system of producing metal cored solder structures on a substrate includes: a decal having a plurality of apertures, the apertures being tapered from a top surface to a bottom surface of the decal; a carrier configured for positioning beneath the bottom of the decal, the carrier having cavities in a top surface and the cavities located in alignment with the apertures of the decal; the decal being configured for positioning on the carrier having the decal bottom surface in contact with the carrier top surface to form feature cavities defined by the decal apertures and the carrier cavities, the feature cavities being shaped to receive a plurality of metal elements therein, the feature cavities configured for receiving molten solder being cooled in the cavities, the decal being separable from the carrier to partially expose metal core solder contacts; and receiving elements of a substrate being configured to receive the metal core solder contacts thereon, and the metal core solder contacts being exposed and pos
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: May 15, 2018
    Assignee: International Business Machines Corporation
    Inventors: Peter A. Gruber, Jae-Woong Nah
  • Patent number: 9966335
    Abstract: A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: May 8, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: NamJu Cho, HeeJo Chi, HanGil Shin