Combined With Electrical Contact Or Lead Patents (Class 257/734)
  • Patent number: 11335660
    Abstract: A semiconductor module includes a first semiconductor element and a second semiconductor element each having an upper-surface electrode and a lower-surface electrode, and being connected in parallel to configure an upper arm, a first conductive layer having a U-shape in planar view, having two end portions, and having an upper surface on which the first semiconductor element and the second semiconductor element are disposed in a mirror image arrangement, a positive electrode terminal having a body part and at least two positive electrode ends branched from the body part, and a negative electrode terminal having a negative electrode end disposed between the positive electrode ends. The positive electrode ends are respectively connected to one of the two end portions of the first conductive layer.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: May 17, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Yuma Murata, Naoyuki Kanai, Akito Nakagome, Yoshinari Ikeda
  • Patent number: 11315891
    Abstract: An embodiment is a device including an integrated circuit die having an active side and a back side, the back side being opposite the active side, a molding compound encapsulating the integrated circuit die, and a first redistribution structure overlying the integrated circuit die and the molding compound, the first redistribution structure including a first metallization pattern and a first dielectric layer, the first metallization pattern being electrically coupled to the active side of the integrated circuit die, at least a portion of the first metallization pattern forming an inductor.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: April 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hao Tsai, Chia-Chia Lin, Kai-Chiang Wu, Chuei-Tang Wang, Chen-Hua Yu
  • Patent number: 11309266
    Abstract: The present disclosure discloses a semiconductor device structure with an air gap for reducing capacitive coupling and a method for forming the semiconductor device structure. The semiconductor device structure includes a first conductive pad over a first semiconductor substrate, and a first conductive structure over the first conductive pad. The semiconductor device structure also includes a second conductive structure over the first conductive structure, and a second conductive pad over the second conductive structure. The second conductive pad is electrically connected to the first conductive pad through the first and the second conductive structures. The semiconductor device structure further includes a second semiconductor substrate over the second conductive pad, a first passivation layer between the first and the second semiconductor substrates and covering the first conductive structure, and a second passivation layer between the first passivation layer and the second semiconductor substrate.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: April 19, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 11302516
    Abstract: The present invention provides apparatus for an imaging system comprising a multitude of chemical emitting elements upon a substrate. In some embodiments the substrate may be approximately round with a radius of approximately one inch. Various methods relating to using and producing an imaging system of chemical emitters are disclosed.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: April 12, 2022
    Inventor: Frederick A. Flitsch
  • Patent number: 11296030
    Abstract: An embedded component package structure including a dielectric structure, a semiconductor chip, a first polymer layer, and a patterned conductive layer is provided. The semiconductor chip is embedded in the dielectric structure. The first polymer layer covers the semiconductor chip and has a first thickness, and the first thickness is greater than a second thickness of the dielectric structure above the first polymer layer. The patterned conductive layer covers an upper surface of the dielectric structure and extends over the first polymer layer, and the patterned conductive layer is electrically connected to the semiconductor chip.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: April 5, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-Ju Liao, Chien-Fan Chen, Chien-Hao Wang
  • Patent number: 11296002
    Abstract: A semiconductor device package includes a substrate, a first electronic component and a first encapsulant. The substrate has a first surface and a second surface opposite to the first surface. The first electronic component is disposed on the first surface of the substrate. The first encapsulant is disposed on the first surface of the substrate and covers the first electronic component. The first encapsulant has a first surface facing away the first surface of the substrate and includes a recess at an edge of the first surface of the first encapsulant.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: April 5, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 11282803
    Abstract: A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.
    Type: Grant
    Filed: November 29, 2020
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Kuei Hsu, Ming-Chih Yew, Po-Hao Tsai, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11267992
    Abstract: The present invention provides a film-shaped firing material 1 including sinterable metal particles 10, and a binder component 20, in which a content of the sinterable metal particles 10 is in a range of 15% to 98% by mass, a content of the binder component 20 is in a range of 2% to 50% by mass, a tensile elasticity of the film-shaped firing material at 60° C. is in a range of 4.0 to 10.0 MPa, and a breaking elongation thereof at 60° C. is 500% or greater; and a film-shaped firing material with a support sheet including the film-shaped firing material 1 which contains sinterable metal particles and a binder component, and a support sheet 2 which is provided on at least one side of the film-shaped firing material, in which an adhesive force (a2) of the film-shaped firing material to the support sheet is smaller than an adhesive force (a1) of the film-shaped firing material to a semiconductor wafer, the adhesive force (a1) is 0.1 N/25 mm or greater, and the adhesive force (a2) is in a range of 0.1 N/25 mm to 0.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: March 8, 2022
    Assignee: LINTEC Corporation
    Inventors: Isao Ichikawa, Hidekazu Nakayama, Akinori Sato
  • Patent number: 11271003
    Abstract: A semiconductor device includes a lower structure and a stack structure that extends into a connection region on the lower structure, where the stack structure includes gate pads and mold pads. The mold pads include intermediate mold pads that include first intermediate mold pads and a second intermediate mold pad between a pair of the first intermediate mold pads, each of the first intermediate mold pads has a first length in a first direction, the second intermediate mold pad has a second length in the first direction, greater than the first length, one of the intermediate mold pads includes a mold pad portion and an insulating protrusion portion on the mold pad portion, one of the first intermediate mold pads includes the mold pad portion and the insulating protrusion portion, and a central region of the second intermediate mold pad does not include the insulating protrusion portion.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: March 8, 2022
    Inventors: Geunwon Lim, Seokcheon Baek
  • Patent number: 11264990
    Abstract: An application specific integrated circuit (ASIC) and a method for its design and fabrication is disclosed. In one embodiment, the camouflaged application specific integrated circuit (ASIC), comprises a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions, wherein the functional logic cells comprise a camouflage cell including: a source region of a first conductivity type, a drain region of the first conductivity type, and a camouflage region of a second conductivity type disposed between the source region and the drain region. The camouflage region renders the camouflage cell always off in a first camouflage cell configuration and always on in a second camouflage cell configuration having a planar layout substantially indistinguishable from the first configuration.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: March 1, 2022
    Assignee: RAMBUS INC.
    Inventors: Ronald P. Cocchi, Lap Wai Chow, James P. Baukus, Bryan J. Wang
  • Patent number: 11257765
    Abstract: Chip package structure and chip package method are provided. The chip package structure includes an encapsulating layer, a redistribution layer, a soldering pad group, and bare chips. Connecting posts is formed on a side of the bare chips. The encapsulating layer covers the bare chips and the connecting posts, while exposes a side of the connecting posts away from the bare chips. The redistribution layer on the connecting posts includes a first redistribution wire, a second redistribution wire, and a third redistribution wire. The first redistribution wire and the second redistribution wire are electrically connected to at least one connecting post respectively, and the third redistribution layer is electrically connected to remaining connecting posts. The soldering pad group on the redistribution layer includes an input soldering pad electrically connected to the first redistribution wire and an output soldering pad electrically connected to the second redistribution wire.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: February 22, 2022
    Assignee: Shanghai AVIC OPTO Electronics Co., Ltd.
    Inventors: Kerui Xi, Feng Qin, Jine Liu, Xiaohe Li, Tingting Cui, Yuan Ding
  • Patent number: 11257751
    Abstract: A device includes: a substrate; a first wiring layer above the substrate; a second wiring layer above the first wiring layer; a first insulating film on the first and second wiring layers; a second insulating film in the first insulating film, provided at a position overlapping with a part of the first wiring layer and a part of the second wiring layer in a first direction perpendicular to a surface of the substrate, and including a first portion higher than an upper surface of an end portion of the second wiring layer and a second portion lower than the upper surface of the end portion of the second wiring layer; and a plug via the second insulating film in the first insulating film, provided on the upper surface of the end portion of the second wiring layer, and electrically connected to the second wiring layer.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: February 22, 2022
    Assignee: Toshiba Memory Corporation
    Inventor: Yoshinori Ito
  • Patent number: 11251043
    Abstract: A method for forming a semiconductor structure including forming a plurality of mandrel lines on a first dielectric layer and forming one or more groups of discontinuous mandrel line pairs with a first mask. The method further includes disposing a second dielectric layer, and forming dielectric spacers on sidewalls of the mandrel lines and the discontinuous mandrel line pairs. The method further includes removing the mandrel lines and the discontinuous mandrel line pairs to form spacer masks, forming one or more groups of blocked regions using a second mask, and forming openings extended through the first dielectric layer with a conjunction of the spacer masks and the second mask. The method also includes removing the spacer masks and the second mask, disposing an objective material in the openings, and forming objective lines with top surfaces coplanar with the top surfaces of the first dielectric layer.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: February 15, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Lu Ming Fan, Zi Qun Hua, Bi Feng Li, Qingchen Cao, Yaobin Feng, Zhiliang Xia, Zongliang Huo
  • Patent number: 11244885
    Abstract: Disclosed is a semiconductor package system comprising a substrate, a first semiconductor package on the substrate, and a heat radiation structure on the first semiconductor package. The heat radiation structure includes a first part on a top surface of the first semiconductor package and a second part connected to the first part. The second part has a bottom surface at a level lower than a level of the top surface of the first semiconductor package. A vent hole is provided between an edge region of the substrate and the first part of the heat radiation structure.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: February 8, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Heungkyu Kwon
  • Patent number: 11239189
    Abstract: An electronic component includes a substrate having a first main surface on one side and a second main surface on the other side, a chip having a first chip main surface on one side and a second chip main surface on the other side, and a plurality of electrodes formed on the first chip main surface and/or the second chip main surface, the chip being arranged on the first main surface of the substrate, a sealing insulation layer that seals the chip on the first main surface of the substrate such that the second main surface of the substrate is exposed, the sealing insulation layer having a sealing main surface that opposes the first main surface of the substrate, and a plurality of external terminals formed to penetrate through the sealing insulation layer so as to be exposed from the sealing main surface of the sealing insulation layer, the external terminals being respectively electrically connected to the plurality of electrodes of the chip.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: February 1, 2022
    Assignee: ROHM CO., LTD.
    Inventor: Masatoshi Aketa
  • Patent number: 11211202
    Abstract: A method of manufacturing a multilayer ceramic electronic component includes preparing a ceramic green sheet, forming an internal electrode pattern by applying a paste for an internal electrode including a conductive powder to the ceramic green sheet, forming a ceramic laminate structure by layering the ceramic green sheet on which the internal electrode pattern is formed, forming a body including a dielectric layer and an internal electrode by sintering the ceramic laminate structure, and forming an external electrode by forming an electrode layer on the body, and forming a conductive resin layer on the electrode layer, and the conductive powder includes a conductive metal and tin (Sn), and a content of tin (Sn) is 1.5 wt % or higher, based on a weight of the conductive metal.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 28, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seok Kyoon Woo, Kyoung Jin Cha, Jeong Ryeol Kim, Ji Hong Jo
  • Patent number: 11195770
    Abstract: A method of manufacturing a semiconductor device includes providing, in a housing, an insulating substrate having a metal pattern, a semiconductor chip, a sinter material applied on the semiconductor chip, and a terminal, providing multiple granular sealing resins supported by a grid provided in the housing, heating an inside of the housing until a temperature thereof reaches a first temperature higher than a room temperature and thereby discharging a vaporized solvent of the sinter material out of the housing via a gap of the grid and a gap of the sealing resins, and heating the inside of the housing until the temperature thereof reaches a second temperature higher than the first temperature and thereby causing the melted sealing resins to pass the gap of the grid and form a resin layer covering the semiconductor chip.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: December 7, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenta Nakahara, Akitoshi Shirao
  • Patent number: 11171084
    Abstract: Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having a conductive thin metal layer on a top via that promotes the selective growth of the next level interconnect lines (the line above). In a non-limiting embodiment of the invention, a first conductive line is formed in a dielectric layer. A via is formed on the first conductive line and a seed layer is formed on the via and the dielectric layer. A surface of the seed layer is exposed and a second conductive line is deposited onto the exposed surface of the seed layer. In a non-limiting embodiment of the invention, the second conductive line is selectively grown from the seed layer.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: November 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent Anderson, Lawrence A. Clevenger, Christopher J. Penny, Nicholas Anthony Lanzillo, Kisik Choi, Robert Robison
  • Patent number: 11171079
    Abstract: A semiconductor device includes a substrate including wiring at a surface thereof, a semiconductor element on a surface of the substrate, a first solder resist on the wiring, a bonding wire connecting the wiring and the semiconductor element, and a second solder resist. The first solder resist has an opening region at which a part of the wiring is non-covered by the first solder resist, and the bonding wire connects the wiring and the semiconductor element in the opening region. The second solder resist at least partially covers the non-covered part of the wiring in the opening region.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: November 9, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinji Saito, Yoshitaka Ono
  • Patent number: 11171068
    Abstract: A method of manufacturing a semiconductor device includes providing, in a housing, an insulating substrate having a metal pattern, a semiconductor chip, a sinter material applied on the semiconductor chip, and a terminal, providing multiple granular sealing resins supported by a grid provided in the housing, heating an inside of the housing until a temperature thereof reaches a first temperature higher than a room temperature and thereby discharging a vaporized solvent of the sinter material out of the housing via a gap of the grid and a gap of the sealing resins, and heating the inside of the housing until the temperature thereof reaches a second temperature higher than the first temperature and thereby causing the melted sealing resins to pass the gap of the grid and form a resin layer covering the semiconductor chip.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: November 9, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenta Nakahara, Akitoshi Shirao
  • Patent number: 11158538
    Abstract: An interconnect structure, and a method for forming the same includes forming recess within a dielectric layer and conformally depositing a barrier layer within the recess. A cobalt-infused ruthenium liner is formed above the barrier layer, the cobalt containing ruthenium liner formed by stacking a second liner above a first liner, the first liner positioned above the barrier layer. The first liner includes ruthenium while the second liner includes cobalt. Cobalt atoms migrate from the second liner to the first liner forming the cobalt-infused ruthenium liner. A conductive material is deposited above the cobalt-infused ruthenium liner to fill the recess followed by a capping layer made of cobalt.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: October 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Joseph F. Maniscalco, Koichi Motoyama, Oscar van der Straten, Scott A. DeVries, Alexander Reznicek
  • Patent number: 11152320
    Abstract: The disclosure provides a semiconductor package structure, including a substrate having a front side and a back side, a first insulating layer disposed on the front side of the substrate, and a die disposed on the first insulating layer; wherein the die includes a first die pad and a second die pad, the first die pad coupled to a first portion of a metal layer, the second die pad coupled to a second portion of the metal layer, and the first portion of the metal layer and the second portion of the metal layer spaced apart by a second insulating layer. An associated semiconductor packaging method and another semiconductor package structure are also disclosed.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: October 19, 2021
    Assignee: INPAQ TECHNOLOGY CO., LTD.
    Inventors: Yu-Ming Peng, Wei-Lun Hsu, Chu-Chun Hsu, Hong-Sheng Ke, Yu Chia Chang
  • Patent number: 11152286
    Abstract: A power semiconductor module device includes: a plurality of semiconductor elements that are arranged at intervals and flush with each other on a plane; an insulating support that fixes the semiconductor elements; a first thick-film plating layer that is formed as a first-surface-side electrode that electrically connects the semiconductor elements to each other on at least one surface of a front surface side and a rear surface side. The first thick-film plating layer supports the semiconductor elements from at least one of an upper direction and a lower direction.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: October 19, 2021
    Assignee: WASEDA UNIVERSITY
    Inventor: Kohei Tatsumi
  • Patent number: 11139244
    Abstract: Disclosed is a semiconductor device comprising a substrate, a first dielectric layer on the substrate, a first lower conductive line in the first dielectric layer, an etch stop layer on the first dielectric layer, a via-structure that penetrates the etch stop layer and connects to the first lower conductive line, a second dielectric layer on the etch stop layer, and an upper conductive line that penetrates the second dielectric layer and connects to the via-structure. The first dielectric layer includes a dielectric pattern at a level higher than a top surface of the first lower conductive line. The upper conductive line is in contact with a top surface of the etch stop layer. The etch stop layer has at an upper portion a rounded surface in contact with the via-structure.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: October 5, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jangho Lee, Jongmin Baek, Wookyung You, Kyu-Hee Han, Suhyun Bark
  • Patent number: 11133271
    Abstract: In a semiconductor device, a first outer edge of a conductive pattern is located between the outermost edge of a first dimple and the innermost edge of a second dimple in a cross-sectional view of the device. When thermal stress due to temperature changes in the semiconductor device is applied to the ceramic circuit board, the first and second dimples suppress deformation of the ceramic circuit board that is caused due to the temperature changes. As a result, cracks in the ceramic circuit board and separation of the metal plate and the conductive pattern are prevented.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: September 28, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshinori Uezato
  • Patent number: 11127667
    Abstract: A display device comprises a pad terminal area and a first circuit board attached to the pad terminal area. The pad terminal area comprises a first pad terminal area having a first pad terminal row of first pad terminals and a second pad terminal area having a second pad terminal row of second pad terminals. The first circuit board comprises a first film having a first lead terminal row of first lead terminals and a second film having a second lead terminal row of second lead terminals. The first lead terminals are connected to the first pad terminals, the second lead terminals are connected to the second pad terminals, an end of the second film protrudes outward from an end of the first film, and the second pad terminal area overlaps an area between the end of the first film and the end of the second film.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: September 21, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung Jun Lee, Myung Ho Lee
  • Patent number: 11121098
    Abstract: Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Yu Cheng, Chih-Ping Chao, Kuan-Chi Tsai, Shih-Shiung Chen, Wei-Kung Tsai
  • Patent number: 11121116
    Abstract: A power semiconductor element and a support member are stacked with an intermediate structure being interposed between the power semiconductor element and the support member. The intermediate structure includes a first metal paste layer and at least one first penetrating member. The first metal paste layer contains a plurality of first metal particles. The at least one first penetrating member penetrates the first metal paste layer. At least one first vibrator attached to the at least one first penetrating member penetrating the first metal paste layer is vibrated. The first metal paste layer is heated so that the plurality of first metal particles are sintered or fused.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: September 14, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Keisuke Kawamoto
  • Patent number: 11121100
    Abstract: Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Yu Cheng, Chih-Ping Chao, Kuan-Chi Tsai, Shih-Shiung Chen, Wei-Kung Tsai
  • Patent number: 11101349
    Abstract: A lateral power semiconductor device with a metal interconnect layout for low on-resistance. The metal interconnect layout includes first, second, and third metal layers, each of which include source bars and drain bars. Source bars in the first, second, and third metal layers are electrically connected. Drain bars in the first, second, and third metal layers are electrically connected. In one embodiment, the first and second metal layers are parallel, and the third metal layer is perpendicular to the first and second metal layers. In another embodiment, the first and third metal layer are parallel, and the second metal layer is perpendicular to the first and third metal layers. A nonconductive layer ensures solder bumps electrically connect to only source bars or only drain bars. As a result, a plurality of available pathways exists and enables current to take any of the plurality of available pathways.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: August 24, 2021
    Assignee: Efficient Power Conversion Corporation
    Inventors: Wen-Chia Liao, Jianjun Cao, Fang Chang Liu, Muskan Sharma
  • Patent number: 11094708
    Abstract: A vertical-type memory device includes a plurality of gate electrode layers spaced apart from one another and stacked on a substrate, and extending by different lengths in a first direction and forming a staircase structure, a first interlayer insulating layer covering the staircase structure of the plurality of gate electrode layers, and a plurality of gate contact plugs penetrating the interlayer insulating layer and respectively in contact with the gate electrode layers. The plurality of gate electrode layers include lower gate electrode layers disposed adjacently to the substrate, and upper gate electrode layers disposed on the lower gate electrode layers, so that the lower gate electrodes are between the substrate and the upper gate electrode layers. The plurality of gate contact plugs include lower gate contact plugs connected to the lower gate electrode layers, and upper gate contact plugs connected to the upper gate electrode layers.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: August 17, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joo Won Park, Kyeong Jin Park
  • Patent number: 11075153
    Abstract: An electronic component-incorporating substrate includes a metal mount portion and a first insulation layer. The mount portion includes a first accommodation portion recessed from the upper surface. The first insulation layer includes a second accommodation portion configured by an opening that exposes the first accommodation portion and partially exposes the upper surface of the mount portion located around the first accommodation portion. The electronic component-incorporating substrate further includes an electronic component mounted on the first accommodation portion and including a connection pad, a second insulation layer covering the first insulation layer, the electronic component, and the connection pad, a wiring layer formed on an upper surface of the second insulation layer and including a via wiring extending through the second insulation layer in a thickness-wise direction and a wiring pattern connected to the connection pad of the electronic component by the via wiring.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: July 27, 2021
    Inventor: Yoshihisa Kanbe
  • Patent number: 11069650
    Abstract: The apparatus which assists in deriving bonding conditions includes a bonding unit which bonds a semiconductor chip and a substrate by applying heat and pressure with NCF interposed therebetween, a library in which a variety of physical property information including viscosity characteristic information is collected with respect to each of a plurality of types of NCFs, an initial evaluation condition determination unit which acquires the physical property information corresponding to the NCF used for bonding with reference to the library and determines an initial value of an evaluation condition of bonding evaluation performed by bonding the semiconductor chip and the substrate, and a bonding evaluation unit which drives the bonding unit in accordance with set evaluation condition, bonds the semiconductor chip and the substrate and performs the bonding evaluation at least once to measure the viscosity of the NCF at the time of the bonding.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: July 20, 2021
    Assignee: SHINKAWA LTD.
    Inventor: Tomonori Nakamura
  • Patent number: 11069620
    Abstract: A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect. The bridge die is embedded in the multilayer substrate structure. The substrate interconnect extends from a level above the bridge die to a level below the bridge die. The multilayer substrate structure further comprises an electrically insulating layer comprising a first electrically insulating material. The multilayer substrate structure further comprises an electrically insulating filler structure located laterally between the bridge die and the electrically insulating layer, wherein the electrically insulating filler structure comprises a second electrically insulating material different from the first electrically insulating material.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: July 20, 2021
    Assignee: Intel Corporation
    Inventors: Robert Alan May, Kristof Darmawikarta, Sri Ranga Sai Sai Boyapati
  • Patent number: 11069591
    Abstract: A semiconductor device includes a semiconductor chip having a passivation film, a stress relieving layer provided on the passivation film, and a groove formed in a periphery of a surface of the semiconductor chip, the groove being provided inside of an edge of the semiconductor chip, wherein the stress relieving layer is partly disposed in the groove.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: July 20, 2021
    Assignee: ROHM CO., LTD.
    Inventors: Osamu Miyata, Masaki Kasai, Shingo Higuchi
  • Patent number: 11058006
    Abstract: A component-embedded substrate includes: a buildup layer including an insulating resin layer and a conductor layer; a cavity that is formed in the buildup layer; an electronic component that is mounted on a bottom face of the cavity through an adhesive layer; a pedestal that is disposed on the bottom face of the cavity so as to be opposed to four corners of the electronic component; and a filling resin layer that is filled into the cavity to cover the electronic component and the pedestal.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: July 6, 2021
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Hirokazu Yoshino
  • Patent number: 11031308
    Abstract: A first workpiece includes first active pads, a first test pad, and a second test pad on a primary surface of the first workpiece, the first test pad electrically connected to the second test pad. A second workpiece includes second active pads, a third test pad, and a fourth test pad on a primary surface of the second workpiece. The first and second workpieces are bonded along an interface between the primary surface of the first workpiece and the primary surface of the second workpiece to bond the first active pads with the second active pads, bond the first test pad with the third test pad, and bond the second test pad with the fourth test pad. Connectivity detection circuits test electrical connectivity between the third test pad and the fourth test pad.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: June 8, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Seungpil Lee, Kwang-Ho Kim
  • Patent number: 11031330
    Abstract: An electroconductive substrate, including: a base material; a foundation layer disposed on the base material; a trench formation layer disposed on the foundation layer, and an electroconductive pattern layer including metal plating. A trench including a bottom surface to which the foundation layer is exposed, is formed. The trench is filled with the electroconductive pattern layer. The foundation layer includes a mixed region which is formed from a surface of the foundation layer on the electroconductive pattern layer side towards the inside thereof, and contains metal particles which contain a metal configuring the electroconductive pattern layer, and enter the foundation layer.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: June 8, 2021
    Assignee: TDK CORPORATION
    Inventors: Takashi Daitoku, Susumu Taniguchi, Akiko Seki, Atsushi Sato, Yuhei Horikawa, Makoto Orikasa, Hisayuki Abe
  • Patent number: 11018069
    Abstract: A semiconductor device and method of reducing the risk of underbump metallization poisoning from the application of underfill material is provided. In an embodiment a spacer is located between a first underbump metallization and a second underbump metallization. When an underfill material is dispensed between the first underbump metallization and the second underbump metallization, the spacer prevents the underfill material from creeping towards the second underbump metallization. In another embodiment a passivation layer is used to inhibit the flow of underfill material as the underfill material is being dispensed.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ju Chen, An-Jhih Su, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 11018237
    Abstract: An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: May 25, 2021
    Assignee: Acorn Semi, LLC
    Inventors: Daniel E. Grupp, Daniel J. Connelly
  • Patent number: 11011714
    Abstract: A flexible OLED display panel and a manufacturing method for a flexible OLED display panel are provided. A through hole defined in a flexible substrate is filled with a transparent layer such that the flexible OLED display panel looks as an integral structure visually and more conforms to visual effect of full screens.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: May 18, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Weixin Ma
  • Patent number: 11004903
    Abstract: The present disclosure discloses an electronic device having a hexagonal structure and an addressing method therefor. The electronic device according to one embodiment of the present disclosure includes a first conductor arranged in a first direction, a second conductor disposed on the first conductor and arranged in a second direction, a third conductor disposed on the second conductor and arranged in a third direction, a selection element disposed at a portion between the first and second conductors where the first, second, and third conductors intersect, and a memory element disposed at a portion between the second and third conductors where the first, second, and third conductors intersect.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: May 11, 2021
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Jong Souk Yeo, Deok Jin Jeon
  • Patent number: 10999926
    Abstract: Methods, devices, and systems for producing a flexible electronic device that reduces stress and forces on electronic components are provided. In particular, one or more transition layers with intermediate flexibility, or flexural modulus, are positioned between rigid components and flexible outer layers. This gradually reduces the flexural modulus of the flexible electronics device rather than have an interface between a rigid material and a flexible material. Various materials and methods of forming the layers are described. In addition, an encapsulate layer can be cured to varying flexural moduli to gradually reduce the flexural moduli from the rigid component to the flexible outer layers or bulk structure of the flexible electronic device.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: May 4, 2021
    Assignee: Flex Ltd.
    Inventors: Weifeng Liu, William L. Uy, Dongkai Shangguan
  • Patent number: 10985116
    Abstract: A semiconductor package and a method of forming the same are disclosed. A method of forming a semiconductor package includes the following operations. A polymer layer is formed over a die. A metal feature is formed in the polymer layer. An argon-containing plasma treatment is performed to the polymer layer and the metal feature.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Wen Chen, Hung-Jui Kuo, Ming-Che Ho
  • Patent number: 10976880
    Abstract: A touch device is provided, including a first substrate, a touch sensing structure, a plurality of first electrodes, a first register mark and a circuit board. The touch sensing structure is disposed on the first substrate. The first electrodes are disposed on the first substrate and arranged along a first direction, wherein a portion of the first electrodes are electrically connected to the touch sensing structure. The first register mark is disposed on the first substrate. The circuit board is partially overlapping the first substrate in a vertical projection direction and electrically connected to the portion of the first electrodes.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: April 13, 2021
    Assignee: INNOLUX CORPORATION
    Inventors: Chia-Hsiung Chang, Yang-Chen Chen, Kuo-Chang Su, Hsia-Ching Chu
  • Patent number: 10978339
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a trench in the dielectric layer; forming a first liner in the trench, wherein the first liner comprises Co—Ru alloy; forming a metal layer on the first liner; and planarizing the metal layer and the first liner to form a metal interconnection.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: April 13, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Bin-Siang Tsai
  • Patent number: 10959320
    Abstract: A circuit board according to the present disclosure includes a substrate that includes a through hole, and a penetrating conductor positioned inside of the through hole. The substrate is made of a ceramic. The penetrating conductor contains silver and copper that are main components; at least one selected from a group A of titanium, zirconium, hafnium, and niobium; at least one selected from a group B of molybdenum, tantalum, tungsten, rhenium, and osmium; and a first alloy made of one of (i) silver and indium and (ii) silver and tin.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: March 23, 2021
    Assignee: Kyocera Corporation
    Inventor: Yuichi Abe
  • Patent number: 10957650
    Abstract: A module including a first semiconductor device, a second semiconductor device, a bridge support structure and a base substrate. The semiconductor devices each having first bonding pads having a first solder joined with the base substrate and the semiconductor devices each having second and third bonding pads joined to second and third bonding pads on the bridge support structure by a second solder and a third solder, respectively, on the second and third bonding pads; the semiconductor devices positioned adjacent to each other such that the bridge support structure joins to both of the semiconductor devices by the second and third solders wherein the third bonding pads are larger than the second bonding pads and the third bonding pads are at a larger pitch than the second bonding pads.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles L. Arvin, Karen P. McLaughlin, Brian W. Quinlan, Thomas Weiss
  • Patent number: 10943887
    Abstract: An electronic package can include a substrate, a first die and a second die. The first die can include a first thickness and the second die can include a second thickness. The first and second dies can be coupled to the substrate. A mold can be disposed on the substrate and cover the first die and the second die. The mold can include a planar upper surface. A first via, having a first length, can be extended between the first die and the planar upper surface. A second via, having a second length, can be extended between the second die and the planar upper surface. In some examples, a third die can be communicatively coupled to the first die using the first via and the second die using the second via.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventor: Yen Hsiang Chew
  • Patent number: 10937959
    Abstract: A multiple-atom silicon quantum dot is provided that includes multiple dangling bonds on an otherwise H-terminated silicon surface, each dangling bonds having one of three ionization states of +1, 0 or ?1 and corresponding respectively to 0, 1, or 2 electrons in a dangling bond state. The dangling bonds together in close proximity and having the dangling bond states energetically in the silicon band gap with selective control of the ionization state of one of the dangling bonds. A new class of electronics elements is provided through the inclusion of at least one input and at least one output to the multiple dangling bonds. Selective modification or creation of a dangling bond is also detailed.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: March 2, 2021
    Assignee: QUANTUM SILICON INC.
    Inventors: Robert A. Wolkow, Roshan Achal, Taleana Huff, Hatem Labidi, Lucian Livadaru, Paul Piva, Mohammad Rashidi