Combined With Electrical Contact Or Lead Patents (Class 257/734)
  • Patent number: 11031308
    Abstract: A first workpiece includes first active pads, a first test pad, and a second test pad on a primary surface of the first workpiece, the first test pad electrically connected to the second test pad. A second workpiece includes second active pads, a third test pad, and a fourth test pad on a primary surface of the second workpiece. The first and second workpieces are bonded along an interface between the primary surface of the first workpiece and the primary surface of the second workpiece to bond the first active pads with the second active pads, bond the first test pad with the third test pad, and bond the second test pad with the fourth test pad. Connectivity detection circuits test electrical connectivity between the third test pad and the fourth test pad.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: June 8, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Seungpil Lee, Kwang-Ho Kim
  • Patent number: 11031330
    Abstract: An electroconductive substrate, including: a base material; a foundation layer disposed on the base material; a trench formation layer disposed on the foundation layer, and an electroconductive pattern layer including metal plating. A trench including a bottom surface to which the foundation layer is exposed, is formed. The trench is filled with the electroconductive pattern layer. The foundation layer includes a mixed region which is formed from a surface of the foundation layer on the electroconductive pattern layer side towards the inside thereof, and contains metal particles which contain a metal configuring the electroconductive pattern layer, and enter the foundation layer.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: June 8, 2021
    Assignee: TDK CORPORATION
    Inventors: Takashi Daitoku, Susumu Taniguchi, Akiko Seki, Atsushi Sato, Yuhei Horikawa, Makoto Orikasa, Hisayuki Abe
  • Patent number: 11018237
    Abstract: An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: May 25, 2021
    Assignee: Acorn Semi, LLC
    Inventors: Daniel E. Grupp, Daniel J. Connelly
  • Patent number: 11018069
    Abstract: A semiconductor device and method of reducing the risk of underbump metallization poisoning from the application of underfill material is provided. In an embodiment a spacer is located between a first underbump metallization and a second underbump metallization. When an underfill material is dispensed between the first underbump metallization and the second underbump metallization, the spacer prevents the underfill material from creeping towards the second underbump metallization. In another embodiment a passivation layer is used to inhibit the flow of underfill material as the underfill material is being dispensed.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ju Chen, An-Jhih Su, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 11011714
    Abstract: A flexible OLED display panel and a manufacturing method for a flexible OLED display panel are provided. A through hole defined in a flexible substrate is filled with a transparent layer such that the flexible OLED display panel looks as an integral structure visually and more conforms to visual effect of full screens.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: May 18, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Weixin Ma
  • Patent number: 11004903
    Abstract: The present disclosure discloses an electronic device having a hexagonal structure and an addressing method therefor. The electronic device according to one embodiment of the present disclosure includes a first conductor arranged in a first direction, a second conductor disposed on the first conductor and arranged in a second direction, a third conductor disposed on the second conductor and arranged in a third direction, a selection element disposed at a portion between the first and second conductors where the first, second, and third conductors intersect, and a memory element disposed at a portion between the second and third conductors where the first, second, and third conductors intersect.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: May 11, 2021
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Jong Souk Yeo, Deok Jin Jeon
  • Patent number: 10999926
    Abstract: Methods, devices, and systems for producing a flexible electronic device that reduces stress and forces on electronic components are provided. In particular, one or more transition layers with intermediate flexibility, or flexural modulus, are positioned between rigid components and flexible outer layers. This gradually reduces the flexural modulus of the flexible electronics device rather than have an interface between a rigid material and a flexible material. Various materials and methods of forming the layers are described. In addition, an encapsulate layer can be cured to varying flexural moduli to gradually reduce the flexural moduli from the rigid component to the flexible outer layers or bulk structure of the flexible electronic device.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: May 4, 2021
    Assignee: Flex Ltd.
    Inventors: Weifeng Liu, William L. Uy, Dongkai Shangguan
  • Patent number: 10985116
    Abstract: A semiconductor package and a method of forming the same are disclosed. A method of forming a semiconductor package includes the following operations. A polymer layer is formed over a die. A metal feature is formed in the polymer layer. An argon-containing plasma treatment is performed to the polymer layer and the metal feature.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Wen Chen, Hung-Jui Kuo, Ming-Che Ho
  • Patent number: 10978339
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a trench in the dielectric layer; forming a first liner in the trench, wherein the first liner comprises Co—Ru alloy; forming a metal layer on the first liner; and planarizing the metal layer and the first liner to form a metal interconnection.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: April 13, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Bin-Siang Tsai
  • Patent number: 10976880
    Abstract: A touch device is provided, including a first substrate, a touch sensing structure, a plurality of first electrodes, a first register mark and a circuit board. The touch sensing structure is disposed on the first substrate. The first electrodes are disposed on the first substrate and arranged along a first direction, wherein a portion of the first electrodes are electrically connected to the touch sensing structure. The first register mark is disposed on the first substrate. The circuit board is partially overlapping the first substrate in a vertical projection direction and electrically connected to the portion of the first electrodes.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: April 13, 2021
    Assignee: INNOLUX CORPORATION
    Inventors: Chia-Hsiung Chang, Yang-Chen Chen, Kuo-Chang Su, Hsia-Ching Chu
  • Patent number: 10959320
    Abstract: A circuit board according to the present disclosure includes a substrate that includes a through hole, and a penetrating conductor positioned inside of the through hole. The substrate is made of a ceramic. The penetrating conductor contains silver and copper that are main components; at least one selected from a group A of titanium, zirconium, hafnium, and niobium; at least one selected from a group B of molybdenum, tantalum, tungsten, rhenium, and osmium; and a first alloy made of one of (i) silver and indium and (ii) silver and tin.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: March 23, 2021
    Assignee: Kyocera Corporation
    Inventor: Yuichi Abe
  • Patent number: 10957650
    Abstract: A module including a first semiconductor device, a second semiconductor device, a bridge support structure and a base substrate. The semiconductor devices each having first bonding pads having a first solder joined with the base substrate and the semiconductor devices each having second and third bonding pads joined to second and third bonding pads on the bridge support structure by a second solder and a third solder, respectively, on the second and third bonding pads; the semiconductor devices positioned adjacent to each other such that the bridge support structure joins to both of the semiconductor devices by the second and third solders wherein the third bonding pads are larger than the second bonding pads and the third bonding pads are at a larger pitch than the second bonding pads.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles L. Arvin, Karen P. McLaughlin, Brian W. Quinlan, Thomas Weiss
  • Patent number: 10943887
    Abstract: An electronic package can include a substrate, a first die and a second die. The first die can include a first thickness and the second die can include a second thickness. The first and second dies can be coupled to the substrate. A mold can be disposed on the substrate and cover the first die and the second die. The mold can include a planar upper surface. A first via, having a first length, can be extended between the first die and the planar upper surface. A second via, having a second length, can be extended between the second die and the planar upper surface. In some examples, a third die can be communicatively coupled to the first die using the first via and the second die using the second via.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventor: Yen Hsiang Chew
  • Patent number: 10937658
    Abstract: An LED wafer is formed from a sapphire substrate having a front side. A plurality of crossing division lines are formed on the front side of the sapphire substrate to thereby define a plurality of separate regions where a plurality of LEDs are respectively formed. An LED wafer processing method includes preparing a V-blade having an annular cutting edge whose outer circumferential portion has a V-shaped cross section, rotatably mounting the V-blade in a cutting unit, holding the LED wafer on a holding table with the back side of the LED wafer exposed upward, and then relatively moving the cutting unit and the holding table to form a chamfered portion on the back side of the LED wafer along an area corresponding to each division line formed on the front side of the LED wafer.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: March 2, 2021
    Assignee: DISCO CORPORATION
    Inventor: Makiko Ohmae
  • Patent number: 10937959
    Abstract: A multiple-atom silicon quantum dot is provided that includes multiple dangling bonds on an otherwise H-terminated silicon surface, each dangling bonds having one of three ionization states of +1, 0 or ?1 and corresponding respectively to 0, 1, or 2 electrons in a dangling bond state. The dangling bonds together in close proximity and having the dangling bond states energetically in the silicon band gap with selective control of the ionization state of one of the dangling bonds. A new class of electronics elements is provided through the inclusion of at least one input and at least one output to the multiple dangling bonds. Selective modification or creation of a dangling bond is also detailed.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: March 2, 2021
    Assignee: QUANTUM SILICON INC.
    Inventors: Robert A. Wolkow, Roshan Achal, Taleana Huff, Hatem Labidi, Lucian Livadaru, Paul Piva, Mohammad Rashidi
  • Patent number: 10932386
    Abstract: An electronic module on a flexible planar circuit substrate with a conductor configuration on a first substrate surface and a plurality of electronic components on the opposite, second substrate surface, wherein the components have component contacts, which are electrically connected selectively by way of vias in the circuit substrate and the conductor configuration, wherein the circuit substrate is a thermoplastic polymer and the component contacts are melted or thermally pressed into the second substrate surface in the region of the vias.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: February 23, 2021
    Assignee: DYCONEX AG
    Inventors: Marc Hauer, Eckardt Bihler, Jochen Held
  • Patent number: 10927249
    Abstract: Provided herein are mixed resin systems and the use thereof for wafer-level underfill (WAUF) for three-dimensional TSV packages. In one aspect, there are provided compositions comprising (1) an epoxy resin, (2) a maleimide, nadimide or itaconamide, (3) a toughening agent and (4) a filler. In certain aspects, the invention relates to underfill films prepared from invention compositions. In certain aspects, the invention relates to articles comprising the underfill films described herein.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: February 23, 2021
    Assignee: HENKEL IP & HOLDING GMBH
    Inventors: Jie Bai, Ly Do
  • Patent number: 10923414
    Abstract: A semiconductor device includes: an insulated circuit board including metal layers having recesses, and an insulating board having an upper surface on which the metal layers are arranged; external terminals having bottom ends with a width narrower than the width of openings of the recesses, these bottom ends being inserted into the recesses; a printed circuit board that directly supports the external terminals; and first bonding material that is arranged inside the recesses and respectively conductively connects the bottom ends of the external terminals to the metal layers.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: February 16, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hideyo Nakamura, Tatsuo Nishizawa
  • Patent number: 10923511
    Abstract: An array substrate and a display device having thereof, the array substrate having a display region and a bending region surrounding the display region, wherein the array substrate includes a first substrate layer, a first buffer layer, a second substrate layer, at least one opening, and at least one metal trace extending over the display region and the bending region, wherein at least a part of the at least one metal trace covers a surface inside the at least one opening; an organic layer disposed in the at least one opening and encasing the at least one metal trace located inside the at least one opening.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: February 16, 2021
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Junyan Hu
  • Patent number: 10923448
    Abstract: A bond pad with micro-protrusions for direct metallic bonding. In one embodiment, a semiconductor device comprises a semiconductor substrate, a through-silicon via (TSV) extending through the semiconductor substrate, and a copper pad electrically connected to the TSV and having a coupling side. The semiconductor device further includes a copper element that projects away from the coupling side of the copper pad. In another embodiment, a bonded semiconductor assembly comprises a first semiconductor substrate with a first TSV and a first copper pad electrically coupled to the first TSV, wherein the first copper pad has a first coupling side. The bonded semiconductor assembly further comprises a second semiconductor substrate, opposite to the first semiconductor substrate, the second semiconductor substrate comprising a second copper pad having a second coupling side. A plurality of copper connecting elements extend between the first and second coupling sides of the first and second copper pads.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: February 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Aibin Yu, Wei Zhou, Zhaohui Ma
  • Patent number: 10903181
    Abstract: A wafer level fan out semiconductor device and a manufacturing method thereof are provided. A first sealing part is formed on lateral surfaces of a semiconductor die. A plurality of redistribution layers are formed on surfaces of the semiconductor die and the first sealing part, and solder balls are attached to the redistribution layers. The solder balls are arrayed on the semiconductor die and the first sealing part. In addition, a second sealing part is formed on the semiconductor die, the first sealing part and lower portions of the solder balls. The solder balls are exposed to the outside through the second sealing part. Since the first sealing part and the second sealing part are formed of materials having thermal expansion coefficients which are the same as or similar to each other, warpage occurring to the wafer level fan out semiconductor device can be suppressed.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: January 26, 2021
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Boo Yang Jung, Jong Sik Paek, Choon Heung Lee, In Bae Park, Sang Won Kim, Sung Kyu Kim, Sang Gyu Lee
  • Patent number: 10901277
    Abstract: A display device includes a substrate stack including two substrates, a line between the two substrates, and a substrate side line connection part at an end of the line. The display device also includes an electronic component having an electronic component side line connection part. The electronic component side line connection part faces a vertical end surface of the substrate stack. The display device further includes a junction part that electrically joins the vertical end surface and the electronic component. The junction part includes a solder junction part between the substrate side line connection part and the electronic component side line connection part, a resin adhesion part at a region outside the solder junction part that adheres the vertical end surface and the electronic component, and a low-melting junction part between the vertical end surface and the electronic component and formed of a material having a melting point lower than the solder particle.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: January 26, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventor: Kaoru Furuta
  • Patent number: 10884030
    Abstract: In an object of the present invention, an object is to provide a technique for achieving higher accuracy in current detection of a radio frequency current, in a current detection device. The current detection device of the present invention includes two or more conductors through which a current shunted from a same conductor flows; conductors through which the shunted current flows have portions opposed to each other; currents flow in opposite directions in opposing portions of the conductors; and a magnetic field detecting element is provided between the opposing portions of the conductors.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: January 5, 2021
    Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Takashi Hirao, Akihiro Namba
  • Patent number: 10867898
    Abstract: An electroconductive substrate, including: a base material; a foundation layer disposed on the base material; a trench formation layer disposed on the foundation layer, and an electroconductive pattern layer including metal plating. A trench including a bottom surface to which the foundation layer is exposed, is formed. The trench is filled with the electroconductive pattern layer. The foundation layer includes a mixed region which is formed from a surface of the foundation layer on the electroconductive pattern layer side towards the inside thereof, and contains metal particles which contain a metal configuring the electroconductive pattern layer, and enter the foundation layer.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: December 15, 2020
    Assignee: TDK CORPORATION
    Inventors: Takashi Daitoku, Susumu Taniguchi, Akiko Seki, Atsushi Sato, Yuhei Horikawa, Makoto Orikasa, Hisayuki Abe
  • Patent number: 10861765
    Abstract: A semiconductor device assembly having a semiconductor device attached to a substrate with a foil layer on a surface of the substrate. A layer of adhesive connects the substrate to a first surface of the semiconductor device. The semiconductor device assembly enables processing on the second surface of the semiconductor device. An energy pulse may be applied to the foil layer causing an exothermic reaction to the foil layer that releases the substrate from the semiconductor device. The semiconductor device assembly may include a release layer positioned between the foil layer and the layer of adhesive that connects the substrate to the semiconductor device. The heat generated by the exothermic reaction breaks down the release layer to release the substrate from the semiconductor device. The energy pulse may be an electric charge, a heat pulse, or may be applied from a laser.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: December 8, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: James M. Derderian, Andrew M. Bayless, Xiao Li
  • Patent number: 10854563
    Abstract: A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Kuei Hsu, Ming-Chih Yew, Po-Hao Tsai, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 10856417
    Abstract: The present disclosure provides a power supply module used in a smart terminal and a power supply module assembly structure, the power supply module includes a substrate having first and second surfaces opposite to each other; a power passive element, an active element and a plurality of first conductive parts disposed at the substrate; the power passive element being independently disposed on the first surface of the substrate as a whole; wherein a maximum height of the power passive element disposed on the first surface of the substrate is greater than a sum of a maximum height of an element disposed on the second surface of the substrate and an half of the thickness of the substrate.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: December 1, 2020
    Assignee: Delta Electronics (Shanghai) CO., LTD
    Inventors: Pengkai Ji, Jianhong Zeng, Yu Zhang, Shouyu Hong, Jinping Zhou, Bau-Ru Lu
  • Patent number: 10845713
    Abstract: A method of reconstructing a characteristic of a structure formed on a substrate by a lithographic process, and an associated metrology apparatus. The method includes combining measured values of a first parameter associated with the lithographic process to obtain an estimated value of the first parameter; and reconstructing at least a second parameter associated with the characteristic of the structure using the estimated value of the first parameter and a measurement of the structure. The combining may involve modeling a variation of the first parameter to obtain a parameter model or fingerprint of the first parameter.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: November 24, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Thomas Theeuwes, Hugo Augustinus Joseph Cramer
  • Patent number: 10818631
    Abstract: A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a first substrate; a first adhesive layer disposed on the surface of the first substrate; a first buffer layer disposed on the surface of the first adhesive layer; and a first bonding layer disposed on the surface of the first buffer layer, wherein the densities of the first adhesive layer and the first buffer layer are greater than that of the first bonding layer. The first adhesive layer of the semiconductor structure has higher adhesion with the first substrate and the first buffer layer, and the first buffer layer and the first bonding layer exhibit higher adhesion, which are beneficial to improve the performance of the semiconductor structure.
    Type: Grant
    Filed: April 7, 2019
    Date of Patent: October 27, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xinsheng Wang, Li Zhang, Gaosheng Zhang, Xianjin Wan, Ziqun Hua, Jiawen Wang, Taotao Ding, Hongbin Zhu, Weihua Cheng, Shining Yang
  • Patent number: 10777525
    Abstract: A flip chip package includes a substrate, a chip body bonding on the substrate and bumps connected between the chip body and the substrate. The substrate includes input wires and output wires. The chip body includes a first package unit including a first seal ring and first pads and a second package unit including a second seal ring and second pads. The chip body extends continuously between the first seal ring and the second seal ring. Each of the input wires has one end overlapping the chip body and the other end positioned at a first bonding region of the substrate. Each of the output wires has one end overlapping the chip body and the other end positioned at a second bonding region of the substrate. The first bonding region and the second bonding region are located at opposite sides of the chip body.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: September 15, 2020
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Pai-Sheng Cheng, Wen-Chieh Tu
  • Patent number: 10765370
    Abstract: Systems and methods for controlled sympathectomy procedures for neuromodulation are disclosed. A system for controlled micro ablation procedures is disclosed. A guidewire including one or more sensors or electrodes for accessing and recording physiologic information from one or more anatomical sites within the parenchyma of an organ as part of a physiologic monitoring session, a diagnostic test, or a neuromodulation procedure is disclosed. A guidewire including one or more sensors and/or a means for energy delivery, for performing a neuromodulation procedure within a small vessel within a body is disclosed.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: September 8, 2020
    Assignee: Autonomix Medical, INC.
    Inventors: Landy Toth, Robert Schwartz
  • Patent number: 10770392
    Abstract: A method of fabricating a semiconductor device structure comprising depositing a layer of material on a dielectric stack and patterning the layer of material to form a hard mask, depositing a metal layer covering the hard mask to form a metal hard mask, forming vias in the dielectric stack using the metal hard mask, removing the metal hard mask, and forming trenches in the dielectric stack using the hard mask, wherein the hard mask and the metal hard mask are used to define a line end structure separating the trenches.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: September 8, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Nicholas V. Licausi, Shao Beng Law
  • Patent number: 10755976
    Abstract: A method of forming source/drain contacts with reduced capacitance and resistance, including, forming a source/drain and a channel region on an active region of a substrate, forming a dielectric fill on the source/drain, forming a trench in the dielectric fill, forming a source/drain contact in the trench, forming an inner contact mask section on a portion of an exposed top surface of the source/drain contact, removing a portion of the source/drain contact to form a channel between a sidewall of the dielectric fill and a remaining portion of the source/drain contact, where a surface area of the remaining portion of the source/drain contact is greater than the surface area of the exposed top surface of the source/drain contact, and forming a source/drain electrode fill on the remaining portion of the source/drain contact.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: August 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Chi-Chun Liu, Peng Xu
  • Patent number: 10756061
    Abstract: A multi-layer chip and a fabrication method thereof are disclosed. The method includes: bonding a first chip having a first metal layer to a second chip having a second metal layer; forming a first metal contact in the second chip, the first metal contact connecting to the second metal layer; depositing oxide on the second chip to form a first oxide layer; bonding the first oxide layer and a second oxide layer of a third chip; and forming a second metal contact penetrating through the first oxide layer and the second oxide layer for connecting the first metal contact with a third metal layer in the third chip via the second metal contact.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: August 25, 2020
    Assignee: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing Cao, Sheng Hu
  • Patent number: 10734439
    Abstract: A method of manufacturing an optoelectronic device, including the successive steps of: a) transferring, onto a surface of a control integrated circuit including a plurality of metal connection pads, an active diode stack including at least first and second doped semiconductor layers of opposite conductivity types, so that the second layer of the stack is electrically connected to the metal pads of the control circuit; and b) forming in the active stack trenches delimiting a plurality of diodes connected to different metal pads of the control circuit.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: August 4, 2020
    Assignees: Commissariat à l'Énergie Atomique et aux Énergies Alternatives, Thales
    Inventors: François Templier, Lamine Benaissa, Marc Rabarot
  • Patent number: 10727201
    Abstract: A method includes bonding a first device die and a second device die to a substrate, and filling a gap between the first device die and the second device die with a gap-filling material. A top portion of the gap-filling material covers the first device die and the second device die. Vias are formed to penetrate through the top portion of the gap-filling material. The vias are electrically coupled to the first device die and the second device die. The method further includes forming redistribution lines over the gap-filling material using damascene processes, and forming electrical connectors over and electrically coupling to the redistribution lines.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chen-Hua Yu
  • Patent number: 10729006
    Abstract: [Objective] To provide a wiring substrate for electronic component inspection apparatus which includes a first laminate of resin layers with a plurality of pads for probe provided on its front surface and a second laminate of ceramic layers disposed on the back side of the first laminate and which, despite joining by brazing of a plurality of studs to the back surface of the second laminate, is free from deformation of resin of the first laminate caused by softening or the like and from accidental formation of a short circuit between brazing material layers used for the brazing and external connection terminals formed on the back surface of the second laminate.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: July 28, 2020
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventors: Takakuni Nasu, Yousuke Kondo, Kouta Kimata, Guangzhu Jin
  • Patent number: 10707081
    Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: July 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Chun Huang, Chiu-Hsiang Chen, Ya-Wen Yeh, Yu-Tien Shen, Po-Chin Chang, Chien Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Li-Te Lin, Pinyen Lin, Ru-Gun Liu, Chin-Hsiang Lin
  • Patent number: 10699974
    Abstract: A display device including a film substrate including first and second surfaces, the first surface being opposite to the second surface; a semiconductor chip disposed on the first surface and including an input terminal and a test terminal, which are arranged in a first direction; a first wire extending from the input terminal on the first surface along a second direction, which intersects the first direction; and a second wire including a first extended portion, which extends along the first surface, a second extended portion, which extends along the second surface, and a first via, which penetrates the film substrate and connects the first extended portion and the second extended portion, wherein the first extended portion extends from the test terminal in the second direction and is connected to the first via, and the second extended portion extends from the first via to an edge of the second surface.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: June 30, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: So Young Lim, Ye Chung Chung
  • Patent number: 10693047
    Abstract: A luminous module includes a light source and an optical part for shaping the light rays emitted by the light source. The light source is a semiconductor source that includes a plurality of electroluminescent units of submillimeter dimensions, and at least one positioning outgrowth configured to participate in the positioning of the light source on an optical part. The light source is positioned with respect to the optical part by interaction of the at least one positioning outgrowth with a corresponding receiving orifice formed in the optical part.
    Type: Grant
    Filed: July 4, 2017
    Date of Patent: June 23, 2020
    Assignee: VALEO VISION
    Inventors: Pierre Albou, Christine Roucoules
  • Patent number: 10676359
    Abstract: A method of making carbon nanotubes with equal or other ratio of semiconductive to conductive elements in integrated form includes: depositing a catalyst layer on a substrate and heating same in a reaction furnace to a predetermined temperature. A carbon source gas and a protective gas are introduced to grow a plurality of carbon nanotube segments, some carbon nanotube segments being conductive metallic. A positive electric field is applied to the plurality of carbon nanotube segments, wherein the catalyst layer is positively charged and the positive electric field is reversed to the negative, to grow a second carbon nanotube segment structure from the metallic carbon nanotube segments. The direction of the negative electric field is along a second direction and the second carbon nanotube segment structure then comprises a plurality of semiconducting carbon nanotube segments.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: June 9, 2020
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Jiang-Tao Wang, Peng Liu, Kai-Li Jiang, Shou-Shan Fan
  • Patent number: 10675719
    Abstract: Provided herein is a solder material that includes a spherical core that provides space between a joint object and another object to be joined to the joint object and a solder coated layer that has a melting point at which a core layer of the core is not melted. The solder coated layer includes Sn as a main ingredient and 0 to 2 mass % of Ag, and coats the core. The solder coated layer has an average grain diameter of crystal grains of 3 ?m or less, and the solder material has a spherical diameter of 1 to 230 ?m and a sphericity of 0.95 or more.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: June 9, 2020
    Assignee: Senju Metal Industry Co., Ltd.
    Inventors: Hiroyoshi Kawasaki, Shigeki Kondo, Atsushi Ikeda, Takahiro Roppongi, Takashi Hagiwara, Daisuke Soma, Kaichi Tsuruta, Isamu Sato, Yuji Kawamata
  • Patent number: 10664641
    Abstract: A method for forming an integrated device includes following operations. A first circuit is provided. The first circuit has a first connecting path, a plurality of second connecting paths, and a third connecting path. The plurality of second connecting paths are electrically connected to a first connecting portion of the first connecting path. The third connecting path is electrically coupled to a second connecting portion of the first connecting path. An electromigration (EM) data of the first connecting path is analyzed to determine if a third connecting portion between the first connecting portion and the second connecting portion induces EM phenomenon. The first circuit is modified for generating a second circuit when the third connecting portion induces EM phenomenon. The integrated device according to the second circuit is generated.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: May 26, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hiranmay Biswas, Kuo-Nan Yang, Chung-Hsing Wang, Meng-Xiang Lee
  • Patent number: 10665559
    Abstract: A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Kuei Hsu, Ming-Chih Yew, Po-Hao Tsai, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 10658239
    Abstract: This disclosure provides wafer dicing methods, and relates to the field of semiconductor technologies. Implementations of the dicing method may include: performing laser stealth dicing processing on a wafer from a back surface of the wafer; performing grinding and thinning processing on the back surface of the wafer after performing the laser stealth dicing processing; sticking a dicing tape on the back surface of the wafer after performing the grinding and thinning processing; and performing separation processing on the wafer after sticking the dicing tape. In some implementations, stealth dicing (SD) is performed before grinding, so that a laser is directly imposed on a back surface of a wafer, thereby alleviating a laser attenuation problem and lowering requirements on light transmittance of a dicing tape.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: May 19, 2020
    Assignees: Semiconductor Manufacturing International (Beijing) Corp., Semiconductor Manufacturing International (Shanghai) Corp.
    Inventors: Lihui Lu, Chunchao Fei, Po Yuan Chiang, Yaping Wang
  • Patent number: 10651338
    Abstract: A method for fabricating an optoelectronic semiconductor component is disclosed. A semiconductor chip is produced by singularizing a wafer. The semiconductor chip comprises a substrate and a semiconductor layer sequence with an active layer applied to a main side of the substrate. The semiconductor layer sequence has an active region for emission or absorption of radiation and a sacrificial region arranged next to the active region. The sacrificial region in the finished semiconductor component is not intended to emit or absorb radiation. A trench, introduced into the semiconductor layer sequence, penetrates the active layer and separates the active region from the sacrificial region. The semiconductor chip with the semiconductor layer sequence is applied on a carrier. The substrate is detached from the active region of the semiconductor layer sequence. In the sacrificial region, the semiconductor layer sequence remains mechanically connected to the substrate.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: May 12, 2020
    Assignee: OSRAM OLED GmbH
    Inventor: Dominik Scholz
  • Patent number: 10608110
    Abstract: Metal-oxide-semiconductor (MOS) transistors with reduced subthreshold conduction, and methods of fabricating the same. Transistor gate structures are fabricated in these transistors of a shape and dimension as to overlap onto the active region from the interface between isolation dielectric structures and the transistor active areas. Minimum channel length conduction is therefore not available at the isolation-to-active interface, but rather the channel length along that interface is substantially lengthened, reducing off-state conduction.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: March 31, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Amitava Chatterjee
  • Patent number: 10607942
    Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first pad, and a second pad. A first opening and a second opening are formed in a first main surface of the first semiconductor layer. The second semiconductor layer is stacked on the first semiconductor layer. The first pad for wire bonding is disposed in the first opening. The second pad on which an alignment mark is formed is disposed in the second opening. A third opening and a fourth opening penetrate the second semiconductor layer. The first opening overlaps the third opening. The second opening overlaps the fourth opening.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: March 31, 2020
    Assignee: OLYMPUS CORPORATION
    Inventor: Naohiro Takazawa
  • Patent number: 10600738
    Abstract: A gate electrode is formed in a trench formed in a semiconductor substrate. A gate interlayer insulating film is formed to cover the gate electrode and the like. A gate interconnection and an emitter electrode are formed in contact with the gate interlayer insulating film. A glass coating film and a polyimide film are formed to cover the gate interconnection and the emitter electrode. A solder layer is formed to cover the polyimide film. The gate interconnection and the emitter electrode are each formed of a tungsten film, for example.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: March 24, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Manami Noda, Kota Kimura
  • Patent number: 10586776
    Abstract: A semiconductor device includes a substrate; a laminate which is formed on one main surface side of the substrate, and includes an aluminum alloy wiring and an insulating film surrounding the aluminum alloy wiring; and a silicon nitride film covering the laminate, in which the silicon nitride film and the insulating film have an opening portion, through which the silicon nitride film and the insulating film, formed at a position overlapped with a bonding portion of the aluminum alloy wiring, and a deposition made of a residue caused by reverse sputtering, which contains silicon and nitrogen, adheres to a portion exposed from the opening portion of a surface of the aluminum alloy wiring, to form a film.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: March 10, 2020
    Assignee: ABLIC INC.
    Inventors: Yoichi Mimuro, Shinjiro Kato, Tetsuo Shioura