With Means To Prevent Contact From Penetrating Shallow Pn Junction (e.g., Prevention Of Aluminum "spiking") Patents (Class 257/740)
  • Patent number: 10269713
    Abstract: Contact structures and methods of forming contacts structures are contemplated by this disclosure. A structure includes a dielectric layer over a substrate, an adhesion layer, a silicide, a barrier layer, and a conductive material. The dielectric layer has an opening to a surface of the substrate. The adhesion layer is along sidewalls of the opening. The silicide is on the surface of the substrate. The barrier layer is on the adhesion layer and the silicide, and the barrier layer directly adjoins the silicide. The conductive material is on the barrier layer in the opening.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Mei-Hui Fu, Sheng-Hsuan Lin
  • Patent number: 9773716
    Abstract: A semiconductor device is disclosed in some embodiments. The device includes a substrate, and a layer disposed over the substrate. The layer includes an opening extending through the layer. A plurality of bar or pillar structures or a tapered region are arranged in a peripheral portion of the opening and laterally surround a central portion of the opening. A metal body extends through the central portion of the opening.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: September 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Chieh Liao, Han-Wei Yang, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien
  • Patent number: 9373536
    Abstract: A stress reduction apparatus comprises a metal structure formed over a substrate, an inter metal dielectric layer formed over the substrate, wherein a lower portion of the metal structure is embedded in the inter metal dielectric layer and an inverted cup shaped stress reduction layer formed over the metal structure, wherein an upper portion of the metal structure is embedded in the inverted cup shaped stress reduction layer.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: June 21, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ti Lu, Wen-Tsao Chen, Ming-Ray Mao, Kuan-Chi Tsai
  • Patent number: 8368219
    Abstract: A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: February 5, 2013
    Assignees: Advanced Micro Devices, Inc., Spansion LLC
    Inventors: Arvind Halliyal, Zoran Krivokapic, Matthew S. Buynoski, Nicholas H. Tripsas, Minh Van Ngo, Mark T. Ramsbey, Jeffrey A. Shields, Jusuke Ogura
  • Patent number: 8174118
    Abstract: A method for manufacturing a detection device includes the steps of providing bonding bumps on at least one of a light-receiving element array and a read-out circuit multiplexer, fixing a bump height adjusting member for adjusting the heights of the bumps to the light-receiving element array and/or the read-out circuit multiplexer on which the bumps are provided, and pressing a flat plate on the tops of the bumps and deforming the bumps until the flat plate comes in contact with the end of the bump height adjusting member.
    Type: Grant
    Filed: January 4, 2010
    Date of Patent: May 8, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Youichi Nagai, Hiroshi Inada
  • Patent number: 8174121
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate in which a first interlayer insulation layer having a first via hole and a first trench is formed. The semiconductor device also includes a first via plug and a first metal line respectively formed by filling the first via hole and the first trench with a first metal, a predetermined scratch being formed on the first metal line; and a second via plug a second metal line respectively formed by filling a second via hole and a second trench with a second metal, the second metal lines being separated.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: May 8, 2012
    Assignee: Dongbu Electronics Co. Ltd.
    Inventor: Min Dae Hong
  • Patent number: 8049334
    Abstract: A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: November 1, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Arvind Halliyal, Zoran Krivokapic, Matthew S. Buynoski, Nicholas H. Tripsas, Minh Van Ngo, Mark T. Ramsbey, Jeffrey A. Shields, Jusuke Ogura
  • Patent number: 7893455
    Abstract: An inclined surface having an inclination angle ? is formed in an edge portion which forms an opening portion of an inter-layer insulating film, thereby reducing a stress by the inclined surface.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: February 22, 2011
    Assignee: Oki Data Corporation
    Inventors: Mitsuhiko Ogihara, Hiroyuki Fujiwara, Masataka Muto, Tomoki Igari, Hiroshi Kurokawa
  • Publication number: 20110031622
    Abstract: A method for fabricating a semiconductor device according to an embodiment includes: forming a nickel (Ni) film containing phosphorus (P) elements on a substrate having at least one of a diffusion layer formed by using silicon (Si) and a gate electrode formed by using Si exposed on a surface thereof; and forming a nickel silicide (NiSi) film containing P elements on the substrate from the Ni film containing the P elements and Si in at least one of the diffusion layer and the gate electrode.
    Type: Application
    Filed: August 9, 2010
    Publication date: February 10, 2011
    Inventors: Makoto HONDA, Junichi Wada
  • Publication number: 20080179741
    Abstract: By forming an aluminum nitride layer by a self-limiting process sequence, the interface characteristics of a copper-based metallization layer may be significantly enhanced while nevertheless maintaining the overall permittivity of the layer stack at a lower level.
    Type: Application
    Filed: November 30, 2007
    Publication date: July 31, 2008
    Inventors: Christof Streck, Volker Kahlert
  • Patent number: 7276796
    Abstract: An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the surface oxidation problem of plating a conductive material onto a noble metal seed layer are provided. In accordance with the present invention, a hydrogen plasma treatment is used to treat a noble metal seed layer such that the treated noble metal seed layer is highly resistant to surface oxidation. The inventive oxidation-resistant noble metal seed layer has a low C content and/or a low nitrogen content.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: October 2, 2007
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Nancy R. Klymko, Christopher C. Parks, Keith Kwong Hon Wong
  • Patent number: 7235844
    Abstract: A high-reliability power composite integrated semiconductor device uses thick copper electrodes as current collecting electrodes of a power device portion to resist wire resistance needed for reducing ON-resistance. Furthermore, wire bonding connection of the copper electrodes is secured, and also the time-lapse degradation under high temperature which causes diffusion of copper and corrosion of copper is suppressed. Still furthermore, direct bonding connection can be established to current collecting electrodes in the power device portion, and also established to a bonding pad formed on the control circuit portion in the control circuit portion. A pad area at the device peripheral portion which has been hitherto needed is reduced, so that the area of the device is saved, and the manufacturing cost is reduced.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: June 26, 2007
    Assignee: Denso Corporation
    Inventor: Hiroyasu Itou
  • Patent number: 6936906
    Abstract: The present invention generally relates to filling of a feature by depositing a barrier layer, depositing a seed layer over the barrier layer, and depositing a conductive layer over the seed layer. In one embodiment, the seed layer comprises a copper alloy seed layer deposited over the barrier layer. For example, the copper alloy seed layer may comprise copper and a metal, such as aluminum, magnesium, titanium, zirconium, tin, and combinations thereof. In another embodiment, the seed layer comprises a copper allloy seed layer deposited over the barrier layer and a second seed layer deposited over the copper alloy seed layer. The copper alloy seed layer may comprise copper and a metal, such as aluminum, magnesium, titanium, zirconium, tin, and combinations thereof The second seed layer may comprise a metal, such as undoped copper. In still another embodiment, the seed layer comprises a first seed layer and a second seed layer.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: August 30, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Hua Chung, Ling Chen, Jick Yu, Mei Chang
  • Patent number: 6888245
    Abstract: A semiconductor device includes a conductive layer formed on a silicon semiconductor substrate, cobalt silicide films formed in a surface layer of the conductive layer, an interlayer insulating film which covers the silicon semiconductor substrate thereabove, and a barrier metal film and a tungsten film which fill in a contact hole formed in the interlayer insulating film and is electrically connected to the cobalt silicide film. The positions of lower surfaces of the cobalt silicide films at the bottom of the contact hole are set lower than the position of a lower surface of the cobalt silicide film provided outside the contact hole. A cobalt silicide film having a necessary thickness can be ensured at the bottom of the contact hole. Further, a contact resistance can be reduced and a junction leak can be suppressed.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: May 3, 2005
    Assignee: Renesas Technology Corp.
    Inventor: Kazuhiro Tsukamoto
  • Patent number: 6866943
    Abstract: A bond pad structure formed over a predetermined area of an IC substrate comprising quickly and easily removable redundancy and passivation layers upon lithography and plasma etching in a plasma containing Cl2, the bond structure comprises: a liner or lower metal layer formed on a predetermined area of the IC substrate; an aluminum-based metal layer formed on the liner layer as the last metal layer for bond purposes; a tungsten based redundancy layer formed on top of the aluminum-based last metal layer; and a passivation layer formed over the IC substrate and on the tungsten based redundancy layer.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: March 15, 2005
    Assignee: Infineon Technologies AG
    Inventors: Gerald Friese, Werner K. Robl, Hans-Joachim Barth, Axel Brintzinger
  • Patent number: 6787908
    Abstract: Metal bond pads are formed over active circuitry in a semiconductor chip in a reliable and cost effective manner. According to an example embodiment of the present invention, a metal bond pad is formed over circuitry in the semiconductor chip. A metal layer is formed over the circuitry and the metal bond pad, and a diffusion barrier layer is formed between the metal layer and the metal bond pad. In this manner, additional metal can be formed on the pad site using only one additional mask step, and thicker metal at the pad site improves the reliability of the chip by providing for a metal cushion at the pad useful in subsequent wire bonding processes.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: September 7, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Steven L Skala, Subhas Bothra, Emmanuel Demuizon
  • Patent number: 6649995
    Abstract: A Schottky diode that achieves a predetermined reverse-direction breakdown voltage even if a state of a surface in a vicinity of a Schottky junction interface changes due to a welding of a bonding wire. The semiconductor device having the Schottky junction includes a semiconductor substrate of a first conductivity type. A well region of a second conductivity type is formed in a top surface of the semiconductor substrate. A Schottky electrode is formed on the top surface of the semiconductor substrate. A connecting conductive member is electrically connected to the Schottky electrode. The connecting conductive member is selectively connected to the Schottky electrode above the well region such that a connection surface between the connecting conductive member and the Schottky electrode is not extended above a Schottky junction between the Schottky electrode and the semiconductor substrate of the first conductivity type.
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: November 18, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shigeo Tooi, Katsumi Satoh
  • Patent number: 6624517
    Abstract: This invention constitutes a contact structure incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe2)4, as the precursor. The contact structure is fabricated by etching a contact opening through an dielectric layer down to a diffusion region to which electrical contact is to be made. Titanium metal is deposited over the surface of the wafer so that the exposed surface of the diffusion region is completely covered by a layer of the metal. At least a portion of the titanium metal layer is eventually converted to titanium silicide, thus providing an excellent conductive interface at the surface of the diffusion region. A titanium nitride barrier layer is then deposited using the LPCVD process, coating the walls and floor of the contact opening.
    Type: Grant
    Filed: February 16, 2000
    Date of Patent: September 23, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Trung T. Doan, Tyler A. Lowrey
  • Patent number: 6528817
    Abstract: A semiconductor device having at least three independently accessible memories, with at least one of the memories having a different memory capacity than the others. Separate selection signals are provided to the memories so that they can be independently activated. This allows the memories to be separately tested. When testing the semiconductor device, the memories are tested serially, except for the memory with the largest capacity, since this memory also has the longest test time. The memory with the longest test time is tested in parallel with the serially tested memories. This reduces the current that must be supplied by a test device to the semiconductor device during testing.
    Type: Grant
    Filed: July 26, 2000
    Date of Patent: March 4, 2003
    Assignee: Fujitsu Limited
    Inventors: Makoto Koga, Kunihiko Gotoh, Kenichi Matsumaru, Mitsuya Kawata
  • Publication number: 20030030142
    Abstract: There are included a semiconductor substrate provided with a desirable element region, an electrode pad formed to come in contact with a surface of the semiconductor substrate or a wiring layer provided on the surface of the semiconductor substrate, a bump formed on a surface of the electrode pad through an intermediate layer, and a resin insulating film formed in at least a peripheral portion of the bump to cover an interface of the bump and the intermediate layer which is exposed to a side surface of the bump.
    Type: Application
    Filed: July 24, 2002
    Publication date: February 13, 2003
    Applicant: Rohm Co., Ltd.
    Inventor: Goro Nakatani
  • Patent number: 6448652
    Abstract: A first interlayer insulating film and an etching stopper film are sequentially formed on a semiconductor substrate with a surface area on which first wiring is formed. The etching stopper film is patterned so as to correspond to a pattern of via hole formed on the first interlayer insulating film and a pattern of forming a second wiring. A second interlayer insulating film is formed on the etching stopper film. For forming the second wiring, a wiring trench is formed by etching the second interlayer insulating film. Continuously, the via hole Is formed by etching the first interlayer insulating film while having the etching stopper film as a photomask. Conductive materials are laid in the via hole and the wiring trench so that the second wiring connected to the first wiring is formed.
    Type: Grant
    Filed: July 26, 2000
    Date of Patent: September 10, 2002
    Assignee: NEC Corporation
    Inventor: Norio Okada
  • Patent number: 6437372
    Abstract: A diffusion preventing barrier spike is disclosed. The spike prevents diffusion of dopants into another layer without forming a pn junction in the layer. The spikes are illustratively Al or an aluminum containing material such as AlAs and have a thickness on the order of 1 nm. The spikes of the present invention may be used to stop dopant diffusion out of a doped layer in a variety of III-V semiconductor structures, such a InP-based PIN devices.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: August 20, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Michael Geva, Jayatirtha N Holavanahalli, Abdallah Ougazzaden, Lawrence Edwin Smith
  • Patent number: 6417564
    Abstract: The invention relates to a semiconductor element which comprises a metal layer with gold and germanium. A thin covering layer of germanium oxide lies on the metal layer, protecting the subjacent metal layer from undesirable oxidation of the germanium. The invention also relates to a method of manufacturing such a semiconductor element.
    Type: Grant
    Filed: January 25, 2001
    Date of Patent: July 9, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Michael Rother
  • Patent number: 6400026
    Abstract: In a semiconductor device, an active region is formed on a semiconductor substrate. An electrode layer is directly formed on the active region and serves as a bonding pad. The electrode layer is mainly formed by an Al alloy layer containing Cu.
    Type: Grant
    Filed: June 26, 2000
    Date of Patent: June 4, 2002
    Assignee: NEC Corporation
    Inventors: Takayoshi Andou, Hitoshi Ninomiya, Kinya Ohtani
  • Patent number: 6362526
    Abstract: A semiconductor barrier layer and manufacturing method therefor for copper interconnects which is a tantalum-titanium, tantalum-titanium nitride, tantalum-titanium sandwich. The tantalum in the tantalum-titanium alloy bonds strongly with the semiconductor dielectric, the tantalum-titanium nitride acts as the barrier to prevent diffusion of copper, and the titanium bonds strongly with the copper.
    Type: Grant
    Filed: October 8, 1998
    Date of Patent: March 26, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shekhar Pramanick, John A. Iacoponi
  • Publication number: 20010026018
    Abstract: Metal bond pads are formed over active circuitry in a semiconductor chip in a reliable and cost effective manner. According to an example embodiment of the present invention, a metal bond pad is formed over circuitry in the semiconductor chip. A metal layer is formed over the circuitry and the metal bond pad, and a diffusion barrier layer is formed between the metal layer and the metal bond pad. In this manner, additional metal can be formed on the pad site using only one additional mask step, and thicker metal at the pad site improves the reliability of the chip by providing for a metal cushion at the pad useful in subsequent wire bonding processes.
    Type: Application
    Filed: June 5, 2001
    Publication date: October 4, 2001
    Applicant: Philips Semiconductors, Inc.
    Inventors: Stephen L. Skala, Subhas Bothra, Emmanuel Demuizon
  • Patent number: 6297535
    Abstract: A transistor fabrication process is provided which derives a benefit from having barrier atoms incorporated in a lateral area under a gate oxide of the transistor in close proximity to the drain. To form the transistor, a gate oxide layer is first grown across a silicon-based substrate. A polysilicon layer is then deposited across the gate oxide layer. Portions of the polysilicon layer and the oxide layer are removed to form a gate conductor and gate oxide, thereby exposing source-side and drain-side junctions within the substrate. An LDD implant is performed to lightly dope the source-side and drain-side junctions. An etch stop material may be formed upon opposed sidewall surfaces of the gate conductor, the upper surface of the gate conductor, and the source-side and drain-side junctions. Spacers may then be formed laterally adjacent the etch stop material located upon sidewall surfaces of the gate conductor.
    Type: Grant
    Filed: February 22, 2000
    Date of Patent: October 2, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark I. Gardner, H. Jim Fulford, Jr.
  • Patent number: 6222267
    Abstract: A semiconductor device has: a silicon substrate; a plurality of impurity doped regions formed in a surface layer of the silicon substrate; contact layers each in contact with a surface of associated one of the plurality of impurity doped regions, the contact layer being made of an alloy selected from a group consisting of TiMo, TiV, TiW, TiMoNb, TiMoTa, TiMoV, TiMoW, TiNbV, TiNbW, TiMoNbTa, TiMoNbV, TiMoNbW, TiMoTaW, TiMoVW, TiNbTaW, TiNbVW, TiMoNbTaW, TiMoNbVW, and the like; barrier layers each disposed on associated one of the contact layers and made of refractory metal nitride or refractory metal oxynitride; and a metal wiring layer disposed on each of the barrier layers. The semiconductor device capable of lowering contact resistances between the metal wiring layers and n-type and p-type impurity doped regions of the silicon substrate, as well as its manufacture method are provided.
    Type: Grant
    Filed: June 12, 1998
    Date of Patent: April 24, 2001
    Assignee: Yamaha Corporation
    Inventor: Masayoshi Omura
  • Patent number: 6197628
    Abstract: A method for use in the fabrication of integrated circuits includes providing a substrate assembly having a surface. A diffusion barrier layer is formed over at least a portion of the surface. The diffusion barrier layer is formed of RuSix, where x is in the range of about 0.01 to about 10. The barrier layer may be formed by depositing RuSix, by chemical vapor deposition or the barrier layer may be formed by forming a layer of ruthenium relative to a silicon containing region and performing an anneal to form RuSix from the layer of ruthenium and the silicon containing region. Capacitor electrodes, interconnects or other structures may be formed with such a diffusion barrier layer.
    Type: Grant
    Filed: August 27, 1998
    Date of Patent: March 6, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Brian A. Vaartstra, Eugene P. Marsh
  • Patent number: 6165917
    Abstract: A method for passivating copper, aluminum, or other refractory metal films using ammonia-free silicon nitride and structures produced by the method. A thin film transistor for use in a liquid crystal display and a method of constructing the same, wherein the transistor has a gate, a source and a drain, and a gate insulator between the gate and an active silicon layer. The improvement is a layer of the ammonia-free silicon nitride deposited between the copper, aluminum, or other refractory metal gate and the gate insulator. Further, the gate is copper, aluminum, or another refractory metal and is deposited directly on the substrate. The layer of ammonia-free silicon nitride is also deposited on portions of the substrate adjacent the gate and the gate line extending therefrom. The layer is made in a plasma-enhanced chemical vapor deposition process wherein the gas mixture comprises one part silane to 135 parts nitrogen to 100 parts helium and 100 parts hydrogen.
    Type: Grant
    Filed: June 18, 1997
    Date of Patent: December 26, 2000
    Assignee: International Business Machines Corporation
    Inventors: John Batey, Peter M. Fryer, Jun Hyung Souk
  • Patent number: 6130481
    Abstract: A semiconductor integrated circuit structure includes a semiconductor substrate; an electronic element disposed in the substrate; a first electrically insulating layer disposed on the substrate and the electronic element; a first electrically conducting interconnection layer electrically connected to the electronic element and disposed at least partly on the first electrically insulating layer; a second electrically insulating layer disposed on the first electrically conducting interconnection layer; a second electrically conducting interconnection layer disposed on the second electrically insulating layer; and a through-hole penetrating the second electrically insulating layer to the first electrically conducting interconnection layer, part of the second interconnection layer being disposed within the through-hole and contacting the first electrically conducting interconnection layer wherein the first electrically conducting interconnection layer includes a current barrier including at least one opening in t
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: October 10, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shigeru Harada, Kenji Kishibe, Akira Ihisa, Hiroshi Mochizuki, Eisuke Tanaka
  • Patent number: 6111298
    Abstract: A process is provided for forming a transistor gate conductor having an etch stop arranged at a depth below its upper surface such that the lateral width of the gate conductor above the etch stop may be exclusively narrowed to provide for reduction of transistor channel length. A masking layer, i.e., photoresist, patterned above the gate conductor is isotropically etched so as to minimize its lateral width prior to etching the gate conductor. Portions of the gate conductor not protected by the photoresist may be etched from above the etch stop to define a new pair of opposed sidewall surfaces for the upper portion of the gate conductor. The lateral width of the upper portion of the gate conductor thus may be reduced to a smaller dimension than that of conventional gate conductors. The gate conductor is subjected to an anisotropic etch in which portions of the gate conductor not protected by the narrowed photoresist are etched down to the etch stop.
    Type: Grant
    Filed: September 1, 1998
    Date of Patent: August 29, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark I. Gardner, Daniel Kadosh, Michael P. Duane
  • Patent number: 6093966
    Abstract: A method of forming a semiconductor device by first providing a substrate in a processing chamber. The substrate has an insulating layer and an opening in the insulating layer. A copper barrier layer is formed on the insulating layer and in the opening by providing a plurality of refractory metal atoms and a plurality of silicon atoms in the processing chamber. The atoms are ionized by applying a first bias to the atoms to form a plasma. The substrate is then biased by a first stage bias followed by a second stage bias to accelerate the plasma to the substrate to form the copper barrier layer, where the first stage bias is less than the second stage bias. The copper-containing metal is then deposited on the copper barrier layer over the insulating layer and in the opening. The present invention further includes a semiconductor device formed by the above method.
    Type: Grant
    Filed: March 20, 1998
    Date of Patent: July 25, 2000
    Assignee: Motorola, Inc.
    Inventors: Ramnath Venkatraman, John Mendonca, Gregory N. Hamilton, Jeffrey T. Wetzel, Tze W. Poon, Sam S. Garcia
  • Patent number: 6081034
    Abstract: This invention constitutes a contact structure incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe.sub.2).sub.4, as the precursor. The contact structure is fabricated by etching a contact opening through an dielectric layer down to a diffusion region to which electrical contact is to be made. Titanium metal is deposited over the surface of the wafer so that the exposed surface of the diffusion region is completely covered by a layer of the metal. At least a portion of the titanium metal layer is eventually converted to titanium silicide, thus providing an excellent conductive interface at the surface of the diffusion region. A titanium nitride barrier layer is then deposited using the LPCVD process, coating the walls and floor of the contact opening.
    Type: Grant
    Filed: January 23, 1998
    Date of Patent: June 27, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Trung T. Doan, Tyler A. Lowrey
  • Patent number: 6040604
    Abstract: A semiconductor component (10) includes a substrate (11), doped regions (15, 20) in the substrate (11), interconnect layers (23, 26, 29) coupled to one of the doped layers, and dielectric layers (21, 24, 27) between the interconnect layers (23, 26, 29) wherein a portion (48) of the top interconnect layer (29) overlies portions (47, 42, 43) of the underlying interconnect layers (23, 26) and wherein a portion (47) of the middle interconnect layer (26) does not overlie the portions (42, 43) of the bottom interconnect layer (23) and also does not overlie portions (32, 33) of one of the doped regions (20).
    Type: Grant
    Filed: July 21, 1997
    Date of Patent: March 21, 2000
    Assignee: Motorola, Inc.
    Inventors: Olivier J. Lauvray, David Rodriguez
  • Patent number: 5952721
    Abstract: A phosphorous doped amorphous silicon storage node electrode is treated with heat so as to be converted into a phosphorous doped polysilicon storage electrode, and the heat causes the phosphorous to be diffused into a shallow n-type source region of an n-channel enhancement type switching transistor; to protect the shallow n-type source region from the phosphorous, a phosphorous/oxygen doped amorphous silicon layer is formed between the shallow n-type source region and the phosphorous-doped amorphous silicon storage node electrode, and the oxygen decelerates the phosphorous diffused therethrough, thereby decreasing the amount of phosphorous diffused into the n-type shallow source region.
    Type: Grant
    Filed: March 6, 1997
    Date of Patent: September 14, 1999
    Assignee: NEC Corporation
    Inventor: Shuji Fujiwara
  • Patent number: 5939787
    Abstract: A semiconductor device and manufacturing method thereof having a diffusion barrier layer formed on a semiconductor wafer, whose surface region is provided with a silylation layer, wherein the silylation layer is formed on the diffusion barrier layer which is formed on the semiconductor wafer, by a plasma process using silicon hydride or by a reactive sputtering method using SiH.sub.4. When the metal layer is formed on the silylation layer, the wettability between the diffusion barrier layer and the metal is enhanced and large grains are formed, thereby increasing the step coverage for the contact hole of the metal layer or for the via hole. Additionally, when heat treatment is performed after the metal layer is formed on the silylation layer, the reflow characteristic of the metal layer becomes good, to thereby facilitate the filling of the contact hole or the via hole easy.
    Type: Grant
    Filed: September 15, 1997
    Date of Patent: August 17, 1999
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-in Lee
  • Patent number: 5852328
    Abstract: After forming a first wire on a first interlayer insulation film, a second interlayer insulation film is formed and planarized, to thereby form a via hole. At this stage, the via hole is formed off the first wire. Next, after making an exposed edge and an exposed side wall of the first wire slanted surfaces, a second wire is formed with or without a conductive film buried within the via hole. Since the side wall of the first wire is a slanted surface in this manner, it is possible to completely bury a wire material of the second wire or the conductive film within the via hole, and therefore, it is possible to ensure electric conduction all over the slanted surfaces of the first wire. As a result, even if the via hole which connects the first wire in a lower layer and the second wire in an upper layer is formed of f the first wire, an increase in a wire resistance in the via hole is prevented.
    Type: Grant
    Filed: February 5, 1997
    Date of Patent: December 22, 1998
    Assignee: Matsushita Electronics Corporation
    Inventors: Hiroshi Nishimura, Shinichi Ogawa
  • Patent number: 5831283
    Abstract: A layer for passivating copper, aluminum, or other refractory metal films using ammonia-free silicon nitride and structures produced by the method. A thin film transistor for use in a liquid crystal display, wherein the transistor has a gate, a source and a drain, and a gate insulator between the gate and an active silicon layer. The improvement is a layer of the ammonia-free silicon nitride deposited between the copper, aluminum, or other refractory metal gate and the gate insulator. Further, the gate is copper, aluminum, or another refractory metal and is deposited directly on the substrate. The layer of ammonia-free silicon nitride is also deposited on portions of the substrate adjacent the gate and the gate line extending therefrom. The structure provides stable and low-resistance electrical contact between copper, aluminum, or another refractory metal gate lines and a metallization layer of aluminum and/or molybdenum, includes using a conductive material, such as an indium tin oxide bridge.
    Type: Grant
    Filed: April 22, 1996
    Date of Patent: November 3, 1998
    Assignee: International Business Machines Corporation
    Inventors: John Batey, Peter M. Fryer, Jun Hyung Souk
  • Patent number: 5760476
    Abstract: In a first approach, an interconnect structure (10) reduces peak localized interconnect current density by distributing current flow around the perimeter (22) of an interlevel connector (14) in a semiconductor device. A first interconnect level (12) is connected to a second interconnect level by the interlevel connector (14), and the perimeter (22) of the interlevel connector (14) is located at the juncture between the first interconnect level (12) and the interlevel connector (14). The first interconnect level (12) has two or more fingers (16,18,20) protruding therefrom that connect to the perimeter (22) of the interlevel connector (14). At least one opening (36, 38) is disposed between two of the fingers (16,18,20) for dividing current flow.
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: June 2, 1998
    Assignee: Motorola, Inc.
    Inventors: Charles J. Varker, Michael L. Dreyer, Thomas E. Zirkle
  • Patent number: 5614767
    Abstract: An alignment accuracy check pattern includes a contact hole formed in an insulating film on a major surface of a semiconductor substrate in a region different from an element region, and a photoresist for patterning which is formed in at least part of the contact hole. A wiring layer is formed under the insulating film, and another insulating film is formed under the wiring layer.
    Type: Grant
    Filed: May 16, 1996
    Date of Patent: March 25, 1997
    Assignee: NEC Corporation
    Inventor: Shinji Ohara
  • Patent number: 5570119
    Abstract: A device for use with a liquid jet recording head, and such a head, include a substrate having a semiconductor functional element, an electrothermal transducer electrically connected to the semiconductor functional element for generating thermal energy to be utilized to discharge liquid from the liquid jet recording head, and an insulating layer disposed on the semiconductor functional element and having a contact hole. An electrode is disposed within the contact hole and another insulating layer is disposed on the electrode and has a through hole. The transducer is disposed on the other insulating layer and has a resistor layer and a pair of electrodes, and that resistor layer includes a portion disposed between the electrode within the contact hole and one of the pair of electrodes within the through hole.
    Type: Grant
    Filed: November 23, 1994
    Date of Patent: October 29, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Asao Saito, Ryoichi Koizumi, Tsutomu Kato
  • Patent number: 5565708
    Abstract: A semiconductor device comprising conductors electrically connected through a contact hole interlayer insulation layer with a trilayer barrier layer comprising a titanium silicide layer, titanium silicide layer formed on the titanium silicide by collimation sputtering, and a thermally nitrided titanium formed on the titanium nitride layer. The use of a trilayer barrier layer enables through the capacity of the collimation sputtering apparatus to be increased, prevents particles from occurring, and formation of a low resistance electrical connection between conductors, in addition to preventing diffusion from the titanium nitride layer and the second titanium layer to the thermally nitrided titanium layer, and between conductors.
    Type: Grant
    Filed: May 15, 1995
    Date of Patent: October 15, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akihiko Ohsaki, Sumio Yamaguchi, Atsushi Ishii, Kazuyoshi Maekawa, Masahiko Fujisawa
  • Patent number: 5552341
    Abstract: A semiconductor device and manufacturing method thereof having a diffusion barrier layer formed on a semiconductor wafer. The diffusion barrier layer has a surface region provided with a silylation layer which is formed on the diffusion barrier layer by a plasma process using silicon hydride or by a reactive sputtering method using SiH.sub.4. When a metal layer is formed on the silylation layer, the wettability between the diffusion barrier layer and the metal is enhanced and large grains are formed, thereby increasing the step coverage for the contact hole of the metal layer or for the via hole. Additionally, when heat treatment is performed after the metal layer is formed on the silylation layer, the reflow characteristic of the metal layer becomes good, to thereby facilitate the filling of the contact hole or the via hole. When the wiring layer is thus formed, metal wiring having good reliability can be obtained and a subsequent scintering process is rendered unnecessary.
    Type: Grant
    Filed: December 10, 1993
    Date of Patent: September 3, 1996
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-in Lee
  • Patent number: 5414301
    Abstract: A semiconductor integrated circuit device is provided with an electrical interconnect system which is stable at high temperatures. The interconnect system employs refractory metal compounds which are electrically conductive, which form stable couples with silicon and compounds thereof, and which remain stable at temperatures exceeding approximately 500.degree. C.
    Type: Grant
    Filed: February 16, 1994
    Date of Patent: May 9, 1995
    Assignee: National Semiconductor Corporation
    Inventor: Michael E. Thomas
  • Patent number: 5406121
    Abstract: Disclosed herein is a semiconductor device having a substrate, an insulating layer covering the substrate, a plurality of wiring layer formed on the insulating layer, each wiring layer having a top surface and a side surface, and a sidewall insulating film formed on and along the side surface of each of the wiring layers. The sidewall insulating film suppresses a hillock projecting from the side surface of each wiring layer.
    Type: Grant
    Filed: July 30, 1993
    Date of Patent: April 11, 1995
    Assignee: NEC Corporation
    Inventor: Shuji Toyoda
  • Patent number: 5395457
    Abstract: A photovoltaic device having a tab soldered onto it for modularization, includes a first conductivity type crystalline semiconductor layer, a collector electrode electrically connected to the tab by soldering, a short-preventing layer formed under a soldered portion of the collector electrode, and a second, opposite conductivity type amorphous semiconductor layer formed above the crystalline semiconductor layer. The short-preventing layer is an insulating layer of SiO.sub.2 or the like, or an opposite conductivity type doped layer formed in the first conductivity type crystalline semiconductor layer.
    Type: Grant
    Filed: November 12, 1993
    Date of Patent: March 7, 1995
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Keiichi Sano, Satoshi Ishida
  • Patent number: 5380371
    Abstract: A thin film solar cell having a semiconductor layer deposited on a substrate is composed of a passivation layer made of a polymer resin coated on the upper portion of the semiconductor layer, and an upper electrode made of a conductive paste laminated on the passivation layer. Also, a collector electrode may be laminated on the upper electrode by electroplating. A method for fabricating a solar cell by depositing a semiconductor layer on the substrate includes coating a passivation layer made of a polymer resin on the upper portion of the semiconductor layer, and laminating an upper electrode made of a conductive paste containing a component capable of dissolving the polymer resin on the passivation layer. Also, the method may include laminating a collector electrode on the upper electrode by electroplating.
    Type: Grant
    Filed: August 28, 1992
    Date of Patent: January 10, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tsutomu Murakami
  • Patent number: 5378652
    Abstract: A semiconductor device with an electrode wiring structure comprises at least one diffused region provided in a semiconductor substrate, a silicon oxide layer covering the substrate surface, a silicon nitride layer provided on the silicon oxide layer, a through-hole reaching the diffused region through the silicon oxide layer from an upper surface of the silicon nitride layer, a silicon semiconductor layer filled in the through-hole and serving as an electrode wiring layer, and an interconnection layer electrically connected to the diffused region through the silicon semiconductor layer. According to the structure, since the silicon oxide layer is covered with the silicon nitride layer, unwanted contaminations such as phosphorus, boron, etc., previously contained in the silicon oxide layer are not added to the silicon semiconductor layer during its growth process. Therefore, the electrode wiring layer of silicon semiconductor having controlled conductivity can be provided.
    Type: Grant
    Filed: April 3, 1991
    Date of Patent: January 3, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shuichi Samata, Yuuichi Mikata, Toshiro Usami
  • Patent number: RE41670
    Abstract: A 4-T SRAM cell in which two layers of permanent SOG (with an intermediate oxide layer) are used to provide planarization between the first and topmost poly layers.
    Type: Grant
    Filed: January 20, 2000
    Date of Patent: September 14, 2010
    Assignee: STMicroelectronics, Inc.
    Inventors: Loi Nguyen, Ravishankar Sundaresan