Abstract: An object is to provide a semiconductor device in which the area of inspection wiring for detecting chipping, cracks, or the like is narrowed. The semiconductor device includes a semiconductor substrate including an effective region including a semiconductor element and an ineffective region provided on a circumference of the effective region on a front surface thereof, and a rear surface electrode on a rear surface thereof; and inspection wiring provided in the ineffective region on the front surface of the semiconductor substrate so as to surround an outer periphery of the effective region. The inspection wiring is electrically connected to the rear surface electrode in such a manner that one end of the inspection wiring is in contact with the semiconductor layer which is provided in the ineffective region on the front surface of the semiconductor substrate and electrically connected to the rear surface electrode.

Abstract: A semiconductor structure includes: a base including a substrate and a dielectric layer, herein the substrate having a front surface and a back surface that are oppositely arranged, and the dielectric layer is located on the front surface; a connecting hole penetrating the substrate and extending to the dielectric layer; a connecting structure, located in the connecting hole; and an insulating structure, located between the connecting structure and the inner wall of the connecting hole. The insulating structure, the inner wall of the connecting hole, and the connecting structure define an air gap.

Abstract: Disclosed is a semiconductor device comprising a substrate, a first lower pattern group on the substrate and including a first key pattern and first lower test patterns horizontally spaced apart from the first key pattern, and a first upper pattern group on the first lower pattern group and including first pads horizontally spaced apart from each other and first upper test patterns between adjacent ones of the first pads. The first key pattern is configured to be used for a photography process associated with fabrication of the semiconductor device. The first pads are electrically connected to the first upper test patterns. One of the first pads vertically overlaps with the first key pattern.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes providing a substrate having a first fin, and the first fin has a channel region and a source/drain region. The method includes forming a stack structure over the first fin, and the stack structure includes a first semiconductor layer and a second semiconductor layer vertically stacked over the fin. The method also includes removing a portion of the second semiconductor layer in the channel region, and a portion of the first semiconductor layer is remaining in the channel region. The method further includes forming a cladding layer over the remaining first semiconductor material layer in the channel region to form a nanostructure, wherein the nanostructure has a dumbbell shape. The method includes forming a gate structure surrounding the nanostructure.

Abstract: Semiconductor packages are provided. One of the semiconductor packages includes an integrated circuit, a die, an encapsulant and an inductor. The die is bonded to the integrated circuit. The encapsulant encapsulates the die over the integrated circuit. The inductor includes a plurality of first conductive patterns and a plurality of second conductive patterns. The first conductive patterns penetrate through the encapsulant. The second conductive patterns are disposed over opposite surfaces of the encapsulant. The first conductive patterns and the second conductive patterns are electrically connected to one another to form a spiral structure having two ends.

Abstract: The present disclosure relates to a redistribution layer (RDL) structure, a manufacturing method thereof, and a semiconductor structure having the same. The RDL structure includes an RDL, disposed on a substrate, and including a bond pad portion and a wire portion connected to the bond pad portion, where a thickness of the bond pad portion is greater than a thickness of the wire portion.

Abstract: A system includes a processor configured to determine a power parameter associated with a cell in an integrated circuit (IC) layout diagram. In response to the determined power parameter exceeding a design criterion, the processor is configured to perform a modification of the IC layout diagram, the modification including at least one of altering a placement of the cell in the IC layout diagram or modifying a power delivery path to the cell. The power parameter includes at least one of a power density of a tile containing the cell, a voltage drop of the tile containing the cell, or a voltage drop of the cell.

Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a carrier substrate, a through substrate via (TSV), a first conductive pattern, and an encapsulated die. The TSV penetrates through the carrier substrate and includes a first portion and a second portion connected to the first portion, the first portion includes a first slanted sidewall with a first slope, the second portion includes a second slanted sidewall with a second slope, and the first slope is substantially milder than the second slope. The first conductive pattern is disposed on the carrier substrate and connected to the first portion of the TSV. The encapsulated die is disposed on the carrier substrate and electrically coupled to the TSV through the first conductive pattern.

Abstract: Semiconductor devices having improved under-bump metallization layouts and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes an IC die; an interconnect structure coupled to the IC die and including a metallization pattern including a via portion extending through a dielectric layer; a second dielectric layer over the dielectric layer opposite the IC die; and a second metallization pattern coupled to the metallization pattern and including a line portion in the dielectric layer and a second via portion extending through the second dielectric layer; and a UBM over the second metallization pattern and the second dielectric layer, the UBM being coupled to the second metallization pattern, a centerline of the via portion and a second centerline of the second via portion being misaligned with a third centerline of the UBM, the centerline and the second centerline being on opposite sides of the third centerline.

Abstract: A semiconductor package includes a semiconductor chip having first and second contact pads that are alternately arranged in a first direction; an insulating film having first openings respectively defining first pad regions of first contact pads, and second openings respectively defining second pad regions of the second contact pads; first and second conductive capping layers on the first and second pad regions, respectively; and an insulating layer on the insulating film, and having first and second contact holes respectively connected to the first and second conductive capping layers. Each of the first and second pad regions includes a bonding region having a first width and a probing region having a second width, greater than the first width, and each of the second pad regions is arranged in a direction that is opposite to each of the plurality of first pad regions.

Abstract: Packages and packaging techniques are described in which a patterned carrier substrate can be used to create a reconstituted fanout substrate with a topography that can accommodate components of different thicknesses. In an embodiment, a wiring layer is formed directly on a multiple level topography of a molding compound layer including embedded components.

Abstract: A semiconductor device includes a semiconductor chip and a package. The semiconductor chip includes a signal processing circuit, a plurality of pads, and a first resistor which arc formed on a semiconductor substrate. On the semiconductor chip, there is no shot-circuiting between a first pad and a second pad of the plurality of pads. A signal input terminal of the signal processing circuit is connected to the second pad. The first resistor is provided between a reference potential supply terminal for supplying a power supply potential and the first pad. A specific terminal of the plurality of terminals of the package is connected to the first pad by a first bonding wire, and is connected to the second pad by a second bonding wire.

Abstract: A semiconductor package includes a first die including a signal region and a peripheral region bordering the signal region and having first vias in the peripheral region, a second die stacked on the first die and having second vias at positions corresponding to the first vias in the peripheral region, and first connection terminals between the first die and the second die that are configured to connect the second vias to the first vias, respectively. The peripheral region includes first regions and second regions configured to transmit different signals, which are alternately arranged in a first direction. The first vias are arranged in at least two rows along a second direction intersecting the first direction in each of the first and second regions.

Abstract: Provided are a solid-state image-capturing device, a semiconductor apparatus, an electronic apparatus, and a manufacturing method that enable improvement in reliability of through electrodes and increase in density of through electrodes. A common opening portion is formed including a through electrode formation region that is a region in which the plurality of through electrodes electrically connected respectively to a plurality of electrode pads provided on a joint surface side from a device formation surface of a semiconductor substrate is formed. A plurality of through portions is formed so as to penetrate to the plurality of respective electrode pads in the common opening portion, and wiring is formed along the common opening portion and the through portions from the electrode pads to the device formation surface corresponding to the respective through electrodes. The present technology can be applied to a layer-type solid-state image-capturing device, for example.

Abstract: A semiconductor device with improved reliability is provided. The semiconductor device is characterized by its embodiments in that sloped portions are formed on connection parts between a pad and a lead-out wiring portion, respectively. This feature suppresses crack formation in a coating area where a part of the pad is covered with a surface protective film.

Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

Abstract: A transistor structure with an air gap includes a substrate. A transistor is disposed on the substrate. An etching stop layer covers and contacts the transistor and the substrate. A first dielectric layer covers and contacts the etching stop layer. A second dielectric layer covers the first dielectric layer. A trench is disposed on the gate structure and within the first dielectric layer and the second dielectric layer. A width of the trench within the second dielectric layer is smaller than a width of the trench within the first dielectric layer. A filling layer is disposed within the trench and covers the top surface of the second dielectric layer. An air gap is formed within the filling layer.

Abstract: A system for performing operations including accessing an integrated circuit design that includes a clock tree interconnecting a clock source to a plurality of clock sinks. The operations include receiving a request to adjust a current timing offset of the clock tree to a target timing offset. The clock tree is modified by moving a terminal of the group from a first location in the clock tree to a second location in the clock tree to generate an updated clock tree. During modification, the first and second locations are analyzed to determine a load reduction and increase at the respective terminals. One or more neighboring clock tree instances are adjusted to compensate for the load reduction and increase. The operations include providing an indication that the clock tree has been updated and complies with the target timing offset.

Abstract: A semiconductor chip including a semiconductor substrate having a first surface and a second surface and having an active layer in a region adjacent to the first surface, a first through electrode penetrating at least a portion of the semiconductor substrate and connected to the active layer, a second through electrode located at a greater radial location from the center of the semiconductor substrate than the first through electrode, penetrating at least a portion of the semiconductor substrate, and connected to the active layer. The semiconductor chip also including a first chip connection pad having a first height and a first width, located on the second surface of the semiconductor substrate, and connected to the first through electrode, and a second chip connection pad having a second height greater than the first height and a second width greater than the first width, located on the second surface of the semiconductor substrate, and connected to the second through electrode.

Abstract: A semiconductor package structure includes a first substrate, a second substrate, a first redistribution layer, and a first reconnection layer. The first substrate may have a first surface. The second substrate can be spaced apart from the first substrate with a gap and may have a second surface. The first redistribution layer can be disposed between the first redistribution layer and the gap. The first substrate can be electrically connected to the second substrate via the first reconnection layer.

Abstract: A substrate, a semiconductor package, and a method of manufacturing the same are provided. The substrate includes an interposer element. The interposer element has a first surface and a second surface opposite to the first surface. At least two rows of pads are disposed adjacent to the first surface of the interposer element. The interposer element includes at least one slot disposed between the two rows of pads and extending from the first surface to the second surface, wherein a projection area extending from an edge of the slot to an edge of the first surface of the interpose element is nonoverlapping at least one pad.

Abstract: A display device including: a substrate; a pixel circuit; a light emitting element including a first electrode, a light emitting; layer, and a second electrode: signal lines; a first voltage supply line overlapping the signal lines, configured to supply a first voltage to the pixel circuit, and, including first lower and upper conductive layers; a second voltage supply overlapping the signal lines, configured to supply a second voltage to the second electrode, and including a second lower conductive layer on a same layer as the first lower conductive layer and a second upper conductive layer on the second lower conductive layer on a same layer as the first upper conductive layer, an encapsulation layer on the second electrode, and the first and second voltage supply lines; and sensing signal lines on the encapsulation layer, the first lower conductive layer and the second upper conductive layer overlapping each other.

Abstract: An integrated circuit (IC) structure includes a power rail oriented in a power rail direction and first metal segments above the power rail, oriented in a first metal level direction perpendicular to the power rail direction. First vias positioned between the power rail and the first metal segments are positioned at locations where first metal segments overlap the power rail. A second metal segment is positioned above the first metal segments, overlaps the power rail, and is oriented in the power rail direction. Second vias are positioned above the first vias between the first metal segments and the second metal segments, and a power strap is positioned above the second metal segment. The power strap is electrically connected to the power rail, each first metal segment of the plurality of first metal segments has a minimum width, and the power strap has a width greater than a minimum width.

Abstract: An embedded cross-point memory array is described. In an example, an integrated circuit structure includes a first die including a cross-point memory array comprising separate memory blocks, the memory blocks including orthogonally arranged conductive lines, and memory elements at cross-sections of the conductive lines. A first plurality of sockets is on the first die adjacent to the memory blocks, the first plurality of sockets comprising a first plurality of pads that connect to at least a portion to the conductive lines of the corresponding memory block. A second die includes logic circuitry and a second plurality of sockets comprising a second plurality of pads at least partially aligned with positions of the first plurality of pads on the first die. A top of the first die and a top of the second die face one another, wherein the first plurality of pads are bonded with the second plurality pads to directly connect the cross-point memory array to the logic circuitry.

Abstract: Signal isolation for module with ball grid array. In some embodiments, a packaged module can include a packaging substrate having an underside, and an arrangement of conductive features implemented on the underside of the packaging substrate to allow the packaged module to be capable of being mounted on a circuit board. The arrangement of conductive features can include a signal feature implemented at a first region and configured for passing of a signal, and one or more shielding features placed at a selected location relative to the signal feature to provide an enhanced isolation between the signal feature and a second region of the underside of the packaging substrate.

Abstract: A semiconductor device includes a first lead portion and a second lead portion spaced from each other in a first direction. A semiconductor chip is mounted to the first lead portion. A first connector has a first portion contacting a second electrode on the chip and a second portion connected to the second lead portion. A second connector has third portion that contacts the second electrode, but at a position further away than the first portion, and a fourth portion connected to the second portion. At least a part of the second connector overlaps a part of the first connector between the first lead portion and the second lead portion.

Abstract: A display device includes a substrate including a display area, a peripheral area outside the display area, and a pad area within the peripheral area; a testing circuit unit disposed within the pad area; a cover layer covering the testing circuit unit; an output pad disposed within the pad area and arranged between the testing circuit unit and the display area; an input pad disposed within the pad area, disposed at an opposite side with respect to the plurality of output pads; and a protective layer covering the output pad and the input pad, and, on a plane, an end of the protective layer is apart from the cover layer.

Abstract: One of embodiments is a method of manufacturing driven element chips by dividing a semiconductor wafer into the driven element chips. The method includes preparing a semiconductor wafer which includes chip substrate portions arrayed in an array direction, and a clearance between the chip substrate portions adjacent to each other in the array direction. Each chip substrate portion includes: a conductive layer provided inside the chip substrate portion and including interconnect portions; and a dummy conductor provided in a part of the conductive layer where the interconnect portions are not provided.

Abstract: A semiconductor device includes: a stack structure including horizontal conductive patterns and interlayer insulating layers, which are alternately stacked; gate patterns overlapping with both ends of the stack structure under the stack structure, the gate patterns being spaced apart from each other; and a channel pattern including vertical parts penetrating the stack structure, and a connection part disposed under the stack structure, the connection part connecting the vertical parts.

Abstract: A method of manufacturing an implantable stimulation device includes providing a circuit board of the implantable stimulation device, the circuit board being equipped with circuit components and an antenna, adhering one or more electrodes to the circuit board, and applying an insulation material to the circuit board such that the insulation material forms a housing that surrounds the circuit board, the circuit components, and the antenna, while leaving the one or more electrodes exposed for stimulating a tissue.

Abstract: An integrated circuit includes a semiconductor substrate, first through third power rails, and first through fourth clock gate lines. The first power rail through third power rails are formed above the semiconductor substrate, and extend in a first direction and arranged sequentially in a second direction perpendicular to the first direction. The first through fourth clock gate lines are formed above the semiconductor substrate, and extend in the second direction to pass through a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail. The first clock gate line and the second clock gate line are arranged to be adjacent to each other in the first direction, and the third clock gate line and the fourth clock gate line are arranged to be adjacent to each other in the first direction.

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a substrate, a redistribution layer (RDL) structure, a first die, an encapsulant and a plurality of conductive terminals. The RDL structure is disposed on and electrically connected to the substrate. A width of the RDL structure is less than a width of the substrate. The first die is disposed on the substrate and the RDL structure. The first connectors of the first die are electrically connected to the RDL structure. The second connectors of the first die are electrically connected to the substrate. A first pitch of two adjacent first connectors is less than a second pitch of two adjacent second connectors. The encapsulant is on the substrate to encapsulate the RDL structure and the first die. The conductive terminals are electrically connected to the first die through the substrate and the RDL structure.

Abstract: Reliability of a semiconductor device having a plated layer formed on an electrode pad is improved. The method of manufacturing the semiconductor device includes a step for forming the plated layer on the electrode pad by moving the semiconductor wafer at a second speed, in a nickel-plating solution, after moving the semiconductor wafer at a first speed higher than the second speed. After moving the semiconductor wafer at the first speed, the semiconductor wafer is moved at the second speed without bringing the semiconductor wafer out from the nickel-plating solution.

Abstract: A packaged semiconductor device includes a substrate having input/output (I/O) pads, a semiconductor die attached to the substrate and electrically connected to the substrate with bond wires. A bond-wire reinforcement structure is formed over the bond wires before the assembly is covered with a molding compound. The bond-wire reinforcement structure prevents wire sweep during molding and protects the wires from shorting with other wires. In one embodiment, the bond-wire reinforcement structure is formed with a fiberglass and liquid epoxy mixture.

Abstract: A chip on film package includes a driving integrated circuit chip; a base substrate including: a driving integrated circuit region, and a first region at which stress is converged by the base substrate bent along a side surface of the display panel; and an electrical ground pattern structure on the base substrate in the first region thereof at which the stress is converged. The electrical ground pattern structure is connected to a first side of the driving integrated circuit chip, and the ground pattern structure includes extended from the first side of the driving integrated circuit chip: in a first portion of the first region, ground patterns each inclined in a first direction, and in a second portion of the first region, ground patterns each inclined in a second direction different from the first direction.

Abstract: Apparatus and methods are provided for bond bads layout and structure of semiconductor dies. According to various aspects of the subject innovation, the provided techniques may provide a semiconductor die that may comprise an outer bond pad elongated in a first direction parallel to an edge of the semiconductor die and an inner bond pad elongated in a second direction perpendicular to the edge of the semiconductor die. The outer bond pad may have a probing area and two wire bond areas aligned in the first direction and the inner bond pad may have one probing area and one wire bond area aligned in the second direction. The outer bond pad may be positioned closer to the edge of the semiconductor die than the inner bond pad.

Abstract: Methods of singulation and bonding, as well as structures formed thereby, are disclosed. A method includes singulating a first chip and after the singulating the first chip, bonding the first chip to a second chip. The first chip includes a first semiconductor substrate and a first interconnect structure on a front side of the first semiconductor substrate. The singulating the first chip includes etching through a back side of the first semiconductor substrate through the first interconnect structure.

Abstract: Semiconductor structures are provided in which a first chip on a substrate has at least one first protruding section, the first protruding section including first interconnect locations, a second chip on the substrate having at least one second protruding section, the second protruding section including second interconnect locations and the first chip and the second chip are arranged such that the first protruding section is interdigitated with the second protruding section.

Abstract: A semiconductor device includes a first bit line disposed over a semiconductor substrate. The semiconductor device also includes a capacitor contact and a dielectric structure disposed over the semiconductor substrate and adjacent to the first bit line. The capacitor contact, the dielectric structure and the first bit line are separated from one another by an air gap structure.

Abstract: Apparatuses for providing a clock signal for a semiconductor device are described. An example apparatus includes a chip including a first clock tree and a second clock tree. The first clock tree includes a first wiring segment extending in a first direction and a second wiring segment extending in a second direction perpendicular to the first direction and coupled the first wiring segment. The second clock tree includes a third wiring segment extending in the second direction, a fourth wiring segment extending in the first direction and coupled to the third wiring segment, and a fifth wiring segment extending in the second direction and coupled to the fourth wiring segment.

Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.

Abstract: CMOS Ultrasonic Transducers and processes for making such devices are described. The processes may include forming cavities on a first wafer and bonding the first wafer to a second wafer. The second wafer may be processed to form a membrane for the cavities. Electrical access to the cavities may be provided.

Abstract: The present disclosure is directed to a leadframe package having a side solder ball contact and methods of manufacturing the same. A plurality of solder balls are coupled to recesses in a leadframe before encapsulation and singulation. After singulation, a portion of each solder ball is exposed on sidewalls of the package. This ensures that the sidewalls of the leads are solder wettable, which allows for the formation of stronger joints when the package is coupled to a substrate. This increased adhesion reduces resistance at the joints and also mitigates the effects of expansion of the components in the package such that delamination is less likely to occur. As a result, packages with a side solder ball contact have increased life cycle expectancies.

Abstract: A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer.

Abstract: A semiconductor device includes a plurality of first signal lines and a plurality of second signal lines which are alternately arranged adjacent to each other, wherein the first signal lines and the second signal lines comprise a plurality of main signal lines and at least one spare signal line, a first signal transmitter suitable for transmitting signals through the main signal lines of the first signal lines, and shifting a signal transmission path to adjacent signal lines among the main signal lines and the spare signal line of the first signal lines, based on repair information, and a second signal transmitter suitable for transmitting signals through the main signal lines of the second signal lines, and shifting a signal transmission path to adjacent signal lines among the main signal lines and the spare signal line of the second signal lines, based on the repair information.

Abstract: According to one embodiment, there is provided a memory device which includes a plurality of elements that include three-dimensionally arranged memory cells, a transistor that is electrically connected to at least one of the plurality of elements, an inspection pad that is connected in series to at least one of the plurality of elements through the transistor, and a wiring that is electrically connected to the inspection pad and a gate of the transistor and capable of supplying a common potential to both the inspection pad and the transistor for turning the transistor to an OFF state.

Abstract: A method for forming a 3D memory device is disclosed. The method includes: forming an first insulating layer on a substrate in a peripheral region, the first insulating layer having a slope near a boundary between the peripheral region and a core region of the substrate; forming an alternating conductive/dielectric stack on the substrate and the slope of the first insulating layer, a lateral portion of the alternating conductive/dielectric stack extending along a top surface of the substrate in the core region, and an inclined portion of the alternating conductive/dielectric stack extending along the slope of the first insulating layer; and forming a plurality of contacts to electrically contact a plurality of conductive layers in the inclined portion of the alternating conductive/dielectric stack.

Abstract: Some embodiments relate to a bond pad structure of an integrated circuit (IC). The bond structure includes a bond pad and an intervening metal layer positioned below the bond pad. The intervening metal layer has a first face and a second face. A first via layer is in contact with the first face of intervening metal layer. The first via layer has a first via pattern. The bond structure also includes a second via layer in contact with the second face of the intervening metal layer. The second via layer has a second via pattern that is different than first via pattern. The second via pattern includes a first group of elongated vias extending in parallel with one another in a first direction and a second group of vias in between the first group of elongated vias. The second group of vias extend in a second direction orthogonal to the first direction.

Abstract: A die edge crack and delamination detection device includes a semiconductor device including an IC active area surrounded by at least one mechanical protection barrier (MPB); one or more metallization layers stacked on the IC active area; a plurality of passive electronic devices placed within the metallization layers at respective predetermined distances from the MPB; and a detection circuit having circuitry. The circuitry is configured to determine a specific metallization layer in which a crack or a delamination is encroaching from an edge of the semiconductor device, determine a lateral distance of a lead end of the crack or the delamination from the MPB, and determine a rate of approach of the crack or the delamination encroaching towards the MPB, via a nominal change in an electrical measurement of at least one of the passive electronic devices.

Abstract: The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure, a dielectric structure and a metal bump. The conductive structure has a first conductive surface and a second conductive surface. The dielectric structure has a first dielectric surface and a second dielectric surface. The first conductive surface does not protrude from the first dielectric surface. The second conductive surface is recessed from the second dielectric surface. The metal bump is disposed in a dielectric opening of the dielectric structure, and is physically and electrically connected to the second conductive surface. The metal bump has a concave surface.