Configuration Or Pattern Of Bonds Patents (Class 257/786)
  • Patent number: 11322471
    Abstract: A semiconductor package structure includes a first substrate, a second substrate, a first redistribution layer, and a first reconnection layer. The first substrate may have a first surface. The second substrate can be spaced apart from the first substrate with a gap and may have a second surface. The first redistribution layer can be disposed between the first redistribution layer and the gap. The first substrate can be electrically connected to the second substrate via the first reconnection layer.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: May 3, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Patent number: 11296034
    Abstract: A substrate, a semiconductor package, and a method of manufacturing the same are provided. The substrate includes an interposer element. The interposer element has a first surface and a second surface opposite to the first surface. At least two rows of pads are disposed adjacent to the first surface of the interposer element. The interposer element includes at least one slot disposed between the two rows of pads and extending from the first surface to the second surface, wherein a projection area extending from an edge of the slot to an edge of the first surface of the interpose element is nonoverlapping at least one pad.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: April 5, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei-Hao Chang, Yi Chen
  • Patent number: 11276745
    Abstract: A display device including: a substrate; a pixel circuit; a light emitting element including a first electrode, a light emitting; layer, and a second electrode: signal lines; a first voltage supply line overlapping the signal lines, configured to supply a first voltage to the pixel circuit, and, including first lower and upper conductive layers; a second voltage supply overlapping the signal lines, configured to supply a second voltage to the second electrode, and including a second lower conductive layer on a same layer as the first lower conductive layer and a second upper conductive layer on the second lower conductive layer on a same layer as the first upper conductive layer, an encapsulation layer on the second electrode, and the first and second voltage supply lines; and sensing signal lines on the encapsulation layer, the first lower conductive layer and the second upper conductive layer overlapping each other.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: March 15, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ki Ho Bang, Won Suk Choi
  • Patent number: 11251124
    Abstract: An integrated circuit (IC) structure includes a power rail oriented in a power rail direction and first metal segments above the power rail, oriented in a first metal level direction perpendicular to the power rail direction. First vias positioned between the power rail and the first metal segments are positioned at locations where first metal segments overlap the power rail. A second metal segment is positioned above the first metal segments, overlaps the power rail, and is oriented in the power rail direction. Second vias are positioned above the first vias between the first metal segments and the second metal segments, and a power strap is positioned above the second metal segment. The power strap is electrically connected to the power rail, each first metal segment of the plurality of first metal segments has a minimum width, and the power strap has a width greater than a minimum width.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: February 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hiranmay Biswas, Chi-Yeh Yu, Chung-Hsing Wang, Kuo-Nan Yang, Stefan Rusu, Chin-Shen Lin
  • Patent number: 11233014
    Abstract: Signal isolation for module with ball grid array. In some embodiments, a packaged module can include a packaging substrate having an underside, and an arrangement of conductive features implemented on the underside of the packaging substrate to allow the packaged module to be capable of being mounted on a circuit board. The arrangement of conductive features can include a signal feature implemented at a first region and configured for passing of a signal, and one or more shielding features placed at a selected location relative to the signal feature to provide an enhanced isolation between the signal feature and a second region of the underside of the packaging substrate.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: January 25, 2022
    Assignee: Skyworks Solutions, Inc.
    Inventors: Howard E. Chen, David Viveiros, Jr., Russ Alan Reisner, Robert Francis Darveaux
  • Patent number: 11233040
    Abstract: An embedded cross-point memory array is described. In an example, an integrated circuit structure includes a first die including a cross-point memory array comprising separate memory blocks, the memory blocks including orthogonally arranged conductive lines, and memory elements at cross-sections of the conductive lines. A first plurality of sockets is on the first die adjacent to the memory blocks, the first plurality of sockets comprising a first plurality of pads that connect to at least a portion to the conductive lines of the corresponding memory block. A second die includes logic circuitry and a second plurality of sockets comprising a second plurality of pads at least partially aligned with positions of the first plurality of pads on the first die. A top of the first die and a top of the second die face one another, wherein the first plurality of pads are bonded with the second plurality pads to directly connect the cross-point memory array to the logic circuitry.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Elijah V. Karpov, Prashant Majhi, Brian S. Doyle, Ravi Pillarisetty, Yih Wang
  • Patent number: 11195814
    Abstract: A semiconductor device includes a first lead portion and a second lead portion spaced from each other in a first direction. A semiconductor chip is mounted to the first lead portion. A first connector has a first portion contacting a second electrode on the chip and a second portion connected to the second lead portion. A second connector has third portion that contacts the second electrode, but at a position further away than the first portion, and a fourth portion connected to the second portion. At least a part of the second connector overlaps a part of the first connector between the first lead portion and the second lead portion.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: December 7, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Yoshiharu Takada
  • Patent number: 11182037
    Abstract: A display device includes a substrate including a display area, a peripheral area outside the display area, and a pad area within the peripheral area; a testing circuit unit disposed within the pad area; a cover layer covering the testing circuit unit; an output pad disposed within the pad area and arranged between the testing circuit unit and the display area; an input pad disposed within the pad area, disposed at an opposite side with respect to the plurality of output pads; and a protective layer covering the output pad and the input pad, and, on a plane, an end of the protective layer is apart from the cover layer.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: November 23, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Eunbyul Kim, Myonghoon Roh, Boyoul Shim, Changwoo Won, Seungjin Lim
  • Patent number: 11152532
    Abstract: One of embodiments is a method of manufacturing driven element chips by dividing a semiconductor wafer into the driven element chips. The method includes preparing a semiconductor wafer which includes chip substrate portions arrayed in an array direction, and a clearance between the chip substrate portions adjacent to each other in the array direction. Each chip substrate portion includes: a conductive layer provided inside the chip substrate portion and including interconnect portions; and a dummy conductor provided in a part of the conductive layer where the interconnect portions are not provided.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: October 19, 2021
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Akira Nagumo, Shinya Jumonji, Minoru Fujita
  • Patent number: 11133328
    Abstract: A semiconductor device includes: a stack structure including horizontal conductive patterns and interlayer insulating layers, which are alternately stacked; gate patterns overlapping with both ends of the stack structure under the stack structure, the gate patterns being spaced apart from each other; and a channel pattern including vertical parts penetrating the stack structure, and a connection part disposed under the stack structure, the connection part connecting the vertical parts.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: September 28, 2021
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Patent number: 11109490
    Abstract: A method of manufacturing an implantable stimulation device includes providing a circuit board of the implantable stimulation device, the circuit board being equipped with circuit components and an antenna, adhering one or more electrodes to the circuit board, and applying an insulation material to the circuit board such that the insulation material forms a housing that surrounds the circuit board, the circuit components, and the antenna, while leaving the one or more electrodes exposed for stimulating a tissue.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: August 31, 2021
    Assignee: Micron Medical LLC
    Inventors: Benjamin Speck, Graham Patrick Greene
  • Patent number: 11094654
    Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a substrate, a redistribution layer (RDL) structure, a first die, an encapsulant and a plurality of conductive terminals. The RDL structure is disposed on and electrically connected to the substrate. A width of the RDL structure is less than a width of the substrate. The first die is disposed on the substrate and the RDL structure. The first connectors of the first die are electrically connected to the RDL structure. The second connectors of the first die are electrically connected to the substrate. A first pitch of two adjacent first connectors is less than a second pitch of two adjacent second connectors. The encapsulant is on the substrate to encapsulate the RDL structure and the first die. The conductive terminals are electrically connected to the first die through the substrate and the RDL structure.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: August 17, 2021
    Assignee: Powertech Technology Inc.
    Inventors: Nan-Chun Lin, Hung-Hsin Hsu, Shang-Yu Chang Chien
  • Patent number: 11094686
    Abstract: An integrated circuit includes a semiconductor substrate, first through third power rails, and first through fourth clock gate lines. The first power rail through third power rails are formed above the semiconductor substrate, and extend in a first direction and arranged sequentially in a second direction perpendicular to the first direction. The first through fourth clock gate lines are formed above the semiconductor substrate, and extend in the second direction to pass through a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail. The first clock gate line and the second clock gate line are arranged to be adjacent to each other in the first direction, and the third clock gate line and the fourth clock gate line are arranged to be adjacent to each other in the first direction.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: August 17, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Min-Su Kim
  • Patent number: 11081454
    Abstract: Reliability of a semiconductor device having a plated layer formed on an electrode pad is improved. The method of manufacturing the semiconductor device includes a step for forming the plated layer on the electrode pad by moving the semiconductor wafer at a second speed, in a nickel-plating solution, after moving the semiconductor wafer at a first speed higher than the second speed. After moving the semiconductor wafer at the first speed, the semiconductor wafer is moved at the second speed without bringing the semiconductor wafer out from the nickel-plating solution.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: August 3, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takashi Tonegawa
  • Patent number: 11056457
    Abstract: A packaged semiconductor device includes a substrate having input/output (I/O) pads, a semiconductor die attached to the substrate and electrically connected to the substrate with bond wires. A bond-wire reinforcement structure is formed over the bond wires before the assembly is covered with a molding compound. The bond-wire reinforcement structure prevents wire sweep during molding and protects the wires from shorting with other wires. In one embodiment, the bond-wire reinforcement structure is formed with a fiberglass and liquid epoxy mixture.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 6, 2021
    Assignee: NXP USA, INC.
    Inventors: Boon Yew Low, Lan Chu Tan, Wai Yew Lo, Poh Leng Eu, Chin Teck Siong
  • Patent number: 11043438
    Abstract: A chip on film package includes a driving integrated circuit chip; a base substrate including: a driving integrated circuit region, and a first region at which stress is converged by the base substrate bent along a side surface of the display panel; and an electrical ground pattern structure on the base substrate in the first region thereof at which the stress is converged. The electrical ground pattern structure is connected to a first side of the driving integrated circuit chip, and the ground pattern structure includes extended from the first side of the driving integrated circuit chip: in a first portion of the first region, ground patterns each inclined in a first direction, and in a second portion of the first region, ground patterns each inclined in a second direction different from the first direction.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: June 22, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sehui Jang, Jihyun Kim, Chongguk Lee
  • Patent number: 11043435
    Abstract: Apparatus and methods are provided for bond bads layout and structure of semiconductor dies. According to various aspects of the subject innovation, the provided techniques may provide a semiconductor die that may comprise an outer bond pad elongated in a first direction parallel to an edge of the semiconductor die and an inner bond pad elongated in a second direction perpendicular to the edge of the semiconductor die. The outer bond pad may have a probing area and two wire bond areas aligned in the first direction and the inner bond pad may have one probing area and one wire bond area aligned in the second direction. The outer bond pad may be positioned closer to the edge of the semiconductor die than the inner bond pad.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: June 22, 2021
    Assignee: Innogrit Technologies Co., Ltd.
    Inventors: Lin Chen, Gang Zhao, Wei Jiang, Shiann-Ming Liou
  • Patent number: 11037904
    Abstract: Methods of singulation and bonding, as well as structures formed thereby, are disclosed. A method includes singulating a first chip and after the singulating the first chip, bonding the first chip to a second chip. The first chip includes a first semiconductor substrate and a first interconnect structure on a front side of the first semiconductor substrate. The singulating the first chip includes etching through a back side of the first semiconductor substrate through the first interconnect structure.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 11031343
    Abstract: Semiconductor structures are provided in which a first chip on a substrate has at least one first protruding section, the first protruding section including first interconnect locations, a second chip on the substrate having at least one second protruding section, the second protruding section including second interconnect locations and the first chip and the second chip are arranged such that the first protruding section is interdigitated with the second protruding section.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: June 8, 2021
    Assignee: International Business Machines Corporation
    Inventors: Charles Leon Arvin, Richard Francis Indyk, Bhupender Singh, Jon Alfred Casey
  • Patent number: 10937790
    Abstract: A semiconductor device includes a first bit line disposed over a semiconductor substrate. The semiconductor device also includes a capacitor contact and a dielectric structure disposed over the semiconductor substrate and adjacent to the first bit line. The capacitor contact, the dielectric structure and the first bit line are separated from one another by an air gap structure.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: March 2, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Kuo-Hui Su
  • Patent number: 10885959
    Abstract: Apparatuses for providing a clock signal for a semiconductor device are described. An example apparatus includes a chip including a first clock tree and a second clock tree. The first clock tree includes a first wiring segment extending in a first direction and a second wiring segment extending in a second direction perpendicular to the first direction and coupled the first wiring segment. The second clock tree includes a third wiring segment extending in the second direction, a fourth wiring segment extending in the first direction and coupled to the third wiring segment, and a fifth wiring segment extending in the second direction and coupled to the fourth wiring segment.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Ryosuke Yatsushiro, Seiji Narui
  • Patent number: 10872870
    Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: December 22, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yi-Cheih Chen, Sung-Huan Sun, Cheng-An Chang, Chien-Hung Wu, Fu-Tang Huang
  • Patent number: 10843227
    Abstract: CMOS Ultrasonic Transducers and processes for making such devices are described. The processes may include forming cavities on a first wafer and bonding the first wafer to a second wafer. The second wafer may be processed to form a membrane for the cavities. Electrical access to the cavities may be provided.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: November 24, 2020
    Assignee: Butterfly Network, Inc.
    Inventors: Jonathan M. Rothberg, Keith G. Fife, Tyler S. Ralston, Gregory L. Charvat, Nevada J. Sanchez
  • Patent number: 10840168
    Abstract: The present disclosure is directed to a leadframe package having a side solder ball contact and methods of manufacturing the same. A plurality of solder balls are coupled to recesses in a leadframe before encapsulation and singulation. After singulation, a portion of each solder ball is exposed on sidewalls of the package. This ensures that the sidewalls of the leads are solder wettable, which allows for the formation of stronger joints when the package is coupled to a substrate. This increased adhesion reduces resistance at the joints and also mitigates the effects of expansion of the components in the package such that delamination is less likely to occur. As a result, packages with a side solder ball contact have increased life cycle expectancies.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: November 17, 2020
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Jefferson Talledo, Tito Mangaoang
  • Patent number: 10833144
    Abstract: A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: November 10, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Hua Chen, Teck-Chong Lee
  • Patent number: 10763181
    Abstract: A semiconductor device includes a plurality of first signal lines and a plurality of second signal lines which are alternately arranged adjacent to each other, wherein the first signal lines and the second signal lines comprise a plurality of main signal lines and at least one spare signal line, a first signal transmitter suitable for transmitting signals through the main signal lines of the first signal lines, and shifting a signal transmission path to adjacent signal lines among the main signal lines and the spare signal line of the first signal lines, based on repair information, and a second signal transmitter suitable for transmitting signals through the main signal lines of the second signal lines, and shifting a signal transmission path to adjacent signal lines among the main signal lines and the spare signal line of the second signal lines, based on the repair information.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: September 1, 2020
    Assignee: SK hynix Inc.
    Inventors: Hee-Jin Byun, Ho-Uk Song, Sun-Young Hwang
  • Patent number: 10748915
    Abstract: According to one embodiment, there is provided a memory device which includes a plurality of elements that include three-dimensionally arranged memory cells, a transistor that is electrically connected to at least one of the plurality of elements, an inspection pad that is connected in series to at least one of the plurality of elements through the transistor, and a wiring that is electrically connected to the inspection pad and a gate of the transistor and capable of supplying a common potential to both the inspection pad and the transistor for turning the transistor to an OFF state.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: August 18, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuhiro Nojima, Megumi Shibata, Tomonori Kajino, Taro Shiokawa
  • Patent number: 10734339
    Abstract: Some embodiments relate to a bond pad structure of an integrated circuit (IC). The bond structure includes a bond pad and an intervening metal layer positioned below the bond pad. The intervening metal layer has a first face and a second face. A first via layer is in contact with the first face of intervening metal layer. The first via layer has a first via pattern. The bond structure also includes a second via layer in contact with the second face of the intervening metal layer. The second via layer has a second via pattern that is different than first via pattern. The second via pattern includes a first group of elongated vias extending in parallel with one another in a first direction and a second group of vias in between the first group of elongated vias. The second group of vias extend in a second direction orthogonal to the first direction.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Chan Chen, Yueh-Chuan Lee
  • Patent number: 10734397
    Abstract: A method for forming a 3D memory device is disclosed. The method includes: forming an first insulating layer on a substrate in a peripheral region, the first insulating layer having a slope near a boundary between the peripheral region and a core region of the substrate; forming an alternating conductive/dielectric stack on the substrate and the slope of the first insulating layer, a lateral portion of the alternating conductive/dielectric stack extending along a top surface of the substrate in the core region, and an inclined portion of the alternating conductive/dielectric stack extending along the slope of the first insulating layer; and forming a plurality of contacts to electrically contact a plurality of conductive layers in the inclined portion of the alternating conductive/dielectric stack.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: August 4, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Cheng Zhou, Bin Yuan, QingBo Liu, Song Man Xu, Siying Liu, Rui Gong, Zhiguo Zhao, Zhaoyun Tang, Zhiliang Xia, Zongliang Huo
  • Patent number: 10629504
    Abstract: A die edge crack and delamination detection device includes a semiconductor device including an IC active area surrounded by at least one mechanical protection barrier (MPB); one or more metallization layers stacked on the IC active area; a plurality of passive electronic devices placed within the metallization layers at respective predetermined distances from the MPB; and a detection circuit having circuitry. The circuitry is configured to determine a specific metallization layer in which a crack or a delamination is encroaching from an edge of the semiconductor device, determine a lateral distance of a lead end of the crack or the delamination from the MPB, and determine a rate of approach of the crack or the delamination encroaching towards the MPB, via a nominal change in an electrical measurement of at least one of the passive electronic devices.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: April 21, 2020
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Ennis T. Ogawa, Yusang Lin, Liming Tsau
  • Patent number: 10515884
    Abstract: The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure, a dielectric structure and a metal bump. The conductive structure has a first conductive surface and a second conductive surface. The dielectric structure has a first dielectric surface and a second dielectric surface. The first conductive surface does not protrude from the first dielectric surface. The second conductive surface is recessed from the second dielectric surface. The metal bump is disposed in a dielectric opening of the dielectric structure, and is physically and electrically connected to the second conductive surface. The metal bump has a concave surface.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: December 24, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, Yu-Ying Lee, Li-Chuan Tsai, Chih-Cheng Lee
  • Patent number: 10501310
    Abstract: A MEMS resonator is equipped with a substrate, a moving structure suspended above the substrate in a horizontal plane formed by first and second axes, having first and second arms, parallel to one another and extending along the second axis, coupled at their respective ends by first and second transverse joining elements, forming an internal window. A first electrode structure is positioned outside the window and capacitively coupled to the moving structure. A second electrode structure is positioned inside the window. One of the first and second electrode structures causes an oscillatory movement of the flexing arms in opposite directions along the first horizontal axis at a resonance frequency, and the other electrode structure has a function of detecting the oscillation. A suspension structure has a suspension arm in the window. An attachment arrangement is coupled to the suspension element centrally in the window, near the second electrode structure.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: December 10, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Gabriele Gattere, Alessandro Tocchio, Carlo Valzasina
  • Patent number: 10497587
    Abstract: A method for manipulating ions contained in an encapsulation material for a semiconductor device is provided. The method includes processing the encapsulation material and applying an electric field to the encapsulation material before the encapsulation material is finally cured. The ions contained in the encapsulation material have a mobility that decreases as the encapsulation material cures. By applying the electric field to the encapsulation material before the encapsulation material is finally cured, the amount of ions contained in the encapsulation material is reduced and/or the ions contained are concentrated in one or more regions of the encapsulation material. Corresponding apparatuses and semiconductor packages manufactured by the method are also described.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: December 3, 2019
    Assignee: Infineon Technologies AG
    Inventors: Rabie Djemour, Michael Bauer, Stefan Miethaner
  • Patent number: 10433422
    Abstract: Provided is a differential wiring method for a high-speed printed circuit board, including the following steps: setting a pre-set impedance required value Z2 of a non-ball grid array (BGA) region, determining the width w2 of the second differential wire and the distance d2 between the two second differential wires according to the pre-set impedance required value Z2; calculating the width w1 of the first differential wire and the distance d1 between the two first differential wires, according to the distance s1 between two adjacent rows of bonding pads in a BGA region bonding pad array and the minimum processable distance s2 between the bonding pad and the first differential wire, where w1 and d1 should satisfy 2w1+d1?s1?2s2, while further calculating w1 and d1 according to a differential characteristic impedance formula; arranging the two first differential wires disposed oppositely to each other in the BGA region according to the determined d1, and arranging the two second differential wires disposed opposi
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: October 1, 2019
    Assignees: Guangzhou Fastprint Circuit Tech Co., Ltd., Shenzhen Fastprint Circuit Tech Co., Ltd., Yixing Silicon Valley Electronics Technology Co.
    Inventors: Hong Fan, Hongfei Wang, Bei Chen
  • Patent number: 10312195
    Abstract: A fan-out semiconductor package includes: a semiconductor chip; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on the semiconductor chip and including a first redistribution layer electrically connected to the connection pads and a second redistribution layer electrically connected to the connection pads and disposed on the first redistribution layer. The first redistribution layer includes a first pattern having a plurality of degassing holes, the second redistribution layer includes a second pattern having a first line portion having a first line width and a second line portion connected to the first line portion and having a second line width greater than the first line width, and the second line portion overlaps at least one of the plurality of degassing holes when being projected in a direction perpendicular to the active surface.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: June 4, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ji Hyun Lee, Jin Gu Kim, Chang Bae Lee, Jin Su Kim
  • Patent number: 10297569
    Abstract: A first semiconductor structure including a first bonding oxide layer having a first metallic bonding structure embedded therein and a second semiconductor structure including a second bonding oxide layer having a second metallic bonding structure embedded therein are provided. A nitride surface treatment process is performed to provide a nitrided surface layer to each structure. Each nitrided surface layer includes nitridized oxide regions located in an upper portion of the bonding oxide layer and nitridized metallic regions located in an upper portion of the metallic bonding structures. The nitrogen within the nitridized metallic regions is then removed to restore the upper portion of the metallic bonding structures to its original composition. Bonding is performed to form a dielectric bonding interface between the nitridized oxide regions present in the first and second structures, and a metallic bonding interface between the first and second metallic bonding structures.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Chih-Chao Yang
  • Patent number: 10290530
    Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
  • Patent number: 10269734
    Abstract: A semiconductor element that has an element first main surface, an element second main surface that is the reverse surface from the element first main surface, and an element side surface. The semiconductor element is configured from a semiconductor substrate part and an insulating layer part and is provided with: a signal transmission/reception terminal that is provided to the element first main surface and that contacts and can transmit/receive signals to/from an external-substrate signal transmission/reception terminal that is provided to an external substrate that is external to the semiconductor element; and a signal transmission/reception coil that is provided to the element side surface and that, via the element side surface, can transmit/receive signals in a non-contact manner to/from an external-semiconductor-element signal transmission/reception part that is provided to an external semiconductor element that is external to the semiconductor element.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: April 23, 2019
    Assignee: ULTRAMEMORY INC.
    Inventors: Motoaki Saito, Takao Adachi
  • Patent number: 10269684
    Abstract: The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in proximity to the first substrate and a second surface away from the first substrate; a first interconnect penetrating the first surface of the first dielectric layer; and a protection layer extending along a portion of a sidewall of the first interconnect. A thickness of the protection layer is in a range of from about 0.02 ?m to about 0.2 ?m.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tsung-Han Tsai, Volume Chien, Yung-Lung Hsu, Chung-Bin Tseng, Keng-Ying Liao, Po-Zen Chen
  • Patent number: 10217717
    Abstract: An integrated circuit includes peripheral conductive pads interconnected by a peripheral conductive track within an integrated circuit chip. The integrated circuit chip further includes internal conductive pads interconnected by an internal conductive track within the integrated circuit chip. A conductive bonding wire external to the integrated circuit chip connects the one peripheral conductive pad to one internal conductive pad. A package encapsulates the integrated circuit chip and the conductive bonding wire.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: February 26, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Nicolas Froidevaux, Yann Bacher
  • Patent number: 10192840
    Abstract: In some forms, an electronic assembly includes a substrate; and a ball pad mounted on the substrate, wherein the ball pad includes a plurality of lobes projecting distally from a center of the ball pad. In some forms, he electronic assembly includes a substrate; and a ball pad mounted on the substrate, wherein the ball pad includes a lobe projecting distally from a center of the ball pad. In some forms, the electronic assembly includes a substrate; and a ball pad mounted on the substrate, wherein the ball pad includes at least one lobe projecting distally from a center of the ball pad; and an electronic package that includes at least one conductor that electrically connects the ball pad on the substrate to the electronic package.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: January 29, 2019
    Assignee: Intel Corporation
    Inventors: Yuhong Cai, Mao Guo
  • Patent number: 10157254
    Abstract: In some embodiments, the present disclosure relates to a clock tree structure disposed on a semiconductor substrate. The clock tree structure includes a first clock line having a first line width and being arranged at a first height as measured from an upper surface of the semiconductor substrate. The clock tree structure also includes a second clock line having a second line width, which differs from the first line width. The second clock line is arranged at a second height as measured from the upper surface of the semiconductor substrate and the second height is equal to the first height. The first line width can be directly proportional to a first current level for the first clock line and the second line width can be directly proportional to a second current level for the second clock line.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Nan Yang, Chung-Hsing Wang, Yi-Kan Cheng, Kumar Lalgudi
  • Patent number: 10068913
    Abstract: A three-dimensional semiconductor device includes a semiconductor substrate including a cell array region and a peripheral circuit region, an electrode structure including electrodes vertically stacked on the cell array region, a MOS capacitor on the peripheral circuit region, an interlayer dielectric layer covering the electrode structure and the MOS capacitor, first and second power lines spaced apart from each other in a first direction and extending in a second direction on the interlayer dielectric layer, first lower plugs connected to the first power line and a first terminal of the MOS capacitor, and second lower plugs connected to the second power line to a second terminal of the MOS capacitor. The second power line is on one of the first lower plugs that is adjacent to some of the second lower plugs in one of the first and second directions.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: September 4, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaeick Son, Sunghoon Kim
  • Patent number: 10068834
    Abstract: Embodiments of a semiconductor device including a floating bond pad are disclosed. In one preferred embodiment, the semiconductor device is a power semiconductor device. In one embodiment, the semiconductor device includes a substrate that includes an active area and a control contact area, a first bond pad on the active area, a floating control bond pad on the control contact area and laterally extending over a portion of the first bond pad, and a dielectric between the portion of the first bond pad and the floating control bond pad. The floating control bond pad enables the active area to extend below the floating control bond pad, which in turn decreases a size of the power semiconductor device for a particular rated current or, conversely, increases a size of the active area and thus a rated current for a particular semiconductor die size.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: September 4, 2018
    Assignee: Cree, Inc.
    Inventors: Sarah Kay Haney, Brett Hull, Daniel Namishia
  • Patent number: 10062638
    Abstract: A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals. A side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: August 28, 2018
    Assignee: J-DEVICES CORPORATION
    Inventor: Masafumi Suzuhara
  • Patent number: 10056316
    Abstract: The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in proximity to the first substrate and a second surface away from the first substrate; a first interconnect penetrating the first surface of the first dielectric layer; and a protection layer extending along a portion of a sidewall of the first interconnect. A thickness of the protection layer is in a range of from about 0.02 ?m to about 0.2 ?m.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: August 21, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tsung-Han Tsai, Volume Chien, Yung-Lung Hsu, Chung-Bin Tseng, Keng-Ying Liao, Po-Zen Chen
  • Patent number: 10050048
    Abstract: A semiconductor memory device includes a substrate having a memory region and a peripheral region that are adjacent to each other, and a plurality of insulating layers and a plurality of wiring layers that are alternately formed on the memory region and the peripheral region of the substrate. On the memory region, the insulating layers and the wiring layers are alternately formed along a thickness direction of the memory device. On the peripheral region, first portions of the insulating layers and first portions of the wiring layers are alternately formed along the thickness direction and second portions of the insulating layers and second portions of the wiring layers are alternately formed along a lateral direction. A width of the second portion of each of the wiring layers in the lateral direction is greater than a thickness of the first portion of the wiring layer.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: August 14, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Takuya Inatsuka
  • Patent number: 10037397
    Abstract: An integrated circuit design tool includes a cell library. An entry in the cell library comprises a specification of the cell including a first transistor and a second transistor. The first transistor can include a first set of nanowires or 2D material strips arranged in parallel to form a channel structure, and a gate conductor disposed across the first set of nanowires or 2D material strips. The second transistor can include a second set of nanowires or 2D material strips arranged in parallel to form a channel structure, and a gate conductor disposed across the first set of nanowires or 2D material strips. The number of nanowires or 2D material strips in the first set can be different from the number of nanowires or 2D material strips in the second set, so that the drive power of the individual transistors can be set with finer granularity.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: July 31, 2018
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Jamil Kawa
  • Patent number: 10002222
    Abstract: A method for modifying metal portions of a layout data file associated with a self-aligned multiple patterning (SAMP) process. The method comprises receiving the layout data file that includes one or more active metal portions and layout information associated with an integrated circuit. The method also comprises converting the layout data file to further include mask information having at least a first set of trim features associated with one or more redundant metal portions and one or more active metal portions of the layout data file. The method also comprises determining the one or more redundant metal portions to be perforated. The method further comprises modifying the mask information to further include a second set of trim features for perforating the one or more redundant metal portions. The first set of trim features and the second set of trim features are associated with a trim mask of the SAMP process.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: June 19, 2018
    Assignee: ARM Limited
    Inventors: Brian Tracy Cline, Gregory Munson Yeric
  • Patent number: 9978704
    Abstract: A semiconductor device includes a contact region over a substrate. The semiconductor device further includes a metal pad over the contact region. Additionally, the semiconductor device includes a post passivation interconnect (PPI) line over the metal pad, where the PPI line is in contact with the metal pad. Furthermore, the semiconductor device includes an under-bump-metallurgy (UBM) layer over the PPI line. Moreover, the semiconductor device includes a plurality of solder balls over the UBM layer, the plurality of solder balls being arranged at some, but not all, intersections of a number of columns and rows of a ball pattern.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Yuan Yu, Hsien-Wei Chen, Ying-Ju Chen, Shih-Wei Liang