Configuration Or Pattern Of Bonds Patents (Class 257/786)
  • Patent number: 10312195
    Abstract: A fan-out semiconductor package includes: a semiconductor chip; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on the semiconductor chip and including a first redistribution layer electrically connected to the connection pads and a second redistribution layer electrically connected to the connection pads and disposed on the first redistribution layer. The first redistribution layer includes a first pattern having a plurality of degassing holes, the second redistribution layer includes a second pattern having a first line portion having a first line width and a second line portion connected to the first line portion and having a second line width greater than the first line width, and the second line portion overlaps at least one of the plurality of degassing holes when being projected in a direction perpendicular to the active surface.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: June 4, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ji Hyun Lee, Jin Gu Kim, Chang Bae Lee, Jin Su Kim
  • Patent number: 10297569
    Abstract: A first semiconductor structure including a first bonding oxide layer having a first metallic bonding structure embedded therein and a second semiconductor structure including a second bonding oxide layer having a second metallic bonding structure embedded therein are provided. A nitride surface treatment process is performed to provide a nitrided surface layer to each structure. Each nitrided surface layer includes nitridized oxide regions located in an upper portion of the bonding oxide layer and nitridized metallic regions located in an upper portion of the metallic bonding structures. The nitrogen within the nitridized metallic regions is then removed to restore the upper portion of the metallic bonding structures to its original composition. Bonding is performed to form a dielectric bonding interface between the nitridized oxide regions present in the first and second structures, and a metallic bonding interface between the first and second metallic bonding structures.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Chih-Chao Yang
  • Patent number: 10290530
    Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
  • Patent number: 10269684
    Abstract: The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in proximity to the first substrate and a second surface away from the first substrate; a first interconnect penetrating the first surface of the first dielectric layer; and a protection layer extending along a portion of a sidewall of the first interconnect. A thickness of the protection layer is in a range of from about 0.02 ?m to about 0.2 ?m.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tsung-Han Tsai, Volume Chien, Yung-Lung Hsu, Chung-Bin Tseng, Keng-Ying Liao, Po-Zen Chen
  • Patent number: 10269734
    Abstract: A semiconductor element that has an element first main surface, an element second main surface that is the reverse surface from the element first main surface, and an element side surface. The semiconductor element is configured from a semiconductor substrate part and an insulating layer part and is provided with: a signal transmission/reception terminal that is provided to the element first main surface and that contacts and can transmit/receive signals to/from an external-substrate signal transmission/reception terminal that is provided to an external substrate that is external to the semiconductor element; and a signal transmission/reception coil that is provided to the element side surface and that, via the element side surface, can transmit/receive signals in a non-contact manner to/from an external-semiconductor-element signal transmission/reception part that is provided to an external semiconductor element that is external to the semiconductor element.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: April 23, 2019
    Assignee: ULTRAMEMORY INC.
    Inventors: Motoaki Saito, Takao Adachi
  • Patent number: 10217717
    Abstract: An integrated circuit includes peripheral conductive pads interconnected by a peripheral conductive track within an integrated circuit chip. The integrated circuit chip further includes internal conductive pads interconnected by an internal conductive track within the integrated circuit chip. A conductive bonding wire external to the integrated circuit chip connects the one peripheral conductive pad to one internal conductive pad. A package encapsulates the integrated circuit chip and the conductive bonding wire.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: February 26, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Nicolas Froidevaux, Yann Bacher
  • Patent number: 10192840
    Abstract: In some forms, an electronic assembly includes a substrate; and a ball pad mounted on the substrate, wherein the ball pad includes a plurality of lobes projecting distally from a center of the ball pad. In some forms, he electronic assembly includes a substrate; and a ball pad mounted on the substrate, wherein the ball pad includes a lobe projecting distally from a center of the ball pad. In some forms, the electronic assembly includes a substrate; and a ball pad mounted on the substrate, wherein the ball pad includes at least one lobe projecting distally from a center of the ball pad; and an electronic package that includes at least one conductor that electrically connects the ball pad on the substrate to the electronic package.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: January 29, 2019
    Assignee: Intel Corporation
    Inventors: Yuhong Cai, Mao Guo
  • Patent number: 10157254
    Abstract: In some embodiments, the present disclosure relates to a clock tree structure disposed on a semiconductor substrate. The clock tree structure includes a first clock line having a first line width and being arranged at a first height as measured from an upper surface of the semiconductor substrate. The clock tree structure also includes a second clock line having a second line width, which differs from the first line width. The second clock line is arranged at a second height as measured from the upper surface of the semiconductor substrate and the second height is equal to the first height. The first line width can be directly proportional to a first current level for the first clock line and the second line width can be directly proportional to a second current level for the second clock line.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Nan Yang, Chung-Hsing Wang, Yi-Kan Cheng, Kumar Lalgudi
  • Patent number: 10068913
    Abstract: A three-dimensional semiconductor device includes a semiconductor substrate including a cell array region and a peripheral circuit region, an electrode structure including electrodes vertically stacked on the cell array region, a MOS capacitor on the peripheral circuit region, an interlayer dielectric layer covering the electrode structure and the MOS capacitor, first and second power lines spaced apart from each other in a first direction and extending in a second direction on the interlayer dielectric layer, first lower plugs connected to the first power line and a first terminal of the MOS capacitor, and second lower plugs connected to the second power line to a second terminal of the MOS capacitor. The second power line is on one of the first lower plugs that is adjacent to some of the second lower plugs in one of the first and second directions.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: September 4, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaeick Son, Sunghoon Kim
  • Patent number: 10068834
    Abstract: Embodiments of a semiconductor device including a floating bond pad are disclosed. In one preferred embodiment, the semiconductor device is a power semiconductor device. In one embodiment, the semiconductor device includes a substrate that includes an active area and a control contact area, a first bond pad on the active area, a floating control bond pad on the control contact area and laterally extending over a portion of the first bond pad, and a dielectric between the portion of the first bond pad and the floating control bond pad. The floating control bond pad enables the active area to extend below the floating control bond pad, which in turn decreases a size of the power semiconductor device for a particular rated current or, conversely, increases a size of the active area and thus a rated current for a particular semiconductor die size.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: September 4, 2018
    Assignee: Cree, Inc.
    Inventors: Sarah Kay Haney, Brett Hull, Daniel Namishia
  • Patent number: 10062638
    Abstract: A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals. A side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: August 28, 2018
    Assignee: J-DEVICES CORPORATION
    Inventor: Masafumi Suzuhara
  • Patent number: 10056316
    Abstract: The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in proximity to the first substrate and a second surface away from the first substrate; a first interconnect penetrating the first surface of the first dielectric layer; and a protection layer extending along a portion of a sidewall of the first interconnect. A thickness of the protection layer is in a range of from about 0.02 ?m to about 0.2 ?m.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: August 21, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tsung-Han Tsai, Volume Chien, Yung-Lung Hsu, Chung-Bin Tseng, Keng-Ying Liao, Po-Zen Chen
  • Patent number: 10050048
    Abstract: A semiconductor memory device includes a substrate having a memory region and a peripheral region that are adjacent to each other, and a plurality of insulating layers and a plurality of wiring layers that are alternately formed on the memory region and the peripheral region of the substrate. On the memory region, the insulating layers and the wiring layers are alternately formed along a thickness direction of the memory device. On the peripheral region, first portions of the insulating layers and first portions of the wiring layers are alternately formed along the thickness direction and second portions of the insulating layers and second portions of the wiring layers are alternately formed along a lateral direction. A width of the second portion of each of the wiring layers in the lateral direction is greater than a thickness of the first portion of the wiring layer.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: August 14, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Takuya Inatsuka
  • Patent number: 10037397
    Abstract: An integrated circuit design tool includes a cell library. An entry in the cell library comprises a specification of the cell including a first transistor and a second transistor. The first transistor can include a first set of nanowires or 2D material strips arranged in parallel to form a channel structure, and a gate conductor disposed across the first set of nanowires or 2D material strips. The second transistor can include a second set of nanowires or 2D material strips arranged in parallel to form a channel structure, and a gate conductor disposed across the first set of nanowires or 2D material strips. The number of nanowires or 2D material strips in the first set can be different from the number of nanowires or 2D material strips in the second set, so that the drive power of the individual transistors can be set with finer granularity.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: July 31, 2018
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Jamil Kawa
  • Patent number: 10002222
    Abstract: A method for modifying metal portions of a layout data file associated with a self-aligned multiple patterning (SAMP) process. The method comprises receiving the layout data file that includes one or more active metal portions and layout information associated with an integrated circuit. The method also comprises converting the layout data file to further include mask information having at least a first set of trim features associated with one or more redundant metal portions and one or more active metal portions of the layout data file. The method also comprises determining the one or more redundant metal portions to be perforated. The method further comprises modifying the mask information to further include a second set of trim features for perforating the one or more redundant metal portions. The first set of trim features and the second set of trim features are associated with a trim mask of the SAMP process.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: June 19, 2018
    Assignee: ARM Limited
    Inventors: Brian Tracy Cline, Gregory Munson Yeric
  • Patent number: 9978704
    Abstract: A semiconductor device includes a contact region over a substrate. The semiconductor device further includes a metal pad over the contact region. Additionally, the semiconductor device includes a post passivation interconnect (PPI) line over the metal pad, where the PPI line is in contact with the metal pad. Furthermore, the semiconductor device includes an under-bump-metallurgy (UBM) layer over the PPI line. Moreover, the semiconductor device includes a plurality of solder balls over the UBM layer, the plurality of solder balls being arranged at some, but not all, intersections of a number of columns and rows of a ball pattern.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Yuan Yu, Hsien-Wei Chen, Ying-Ju Chen, Shih-Wei Liang
  • Patent number: 9979080
    Abstract: An apparatus includes a radio-frequency (RF) path that includes an antenna tuner. The apparatus also includes calibration circuitry coupled to the antenna tuner. The calibration circuitry is configured to selectively isolate an antenna from a component of the RF path.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: May 22, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Adrianus van Bezooijen, Kevin Robert Boyle, Maurice Adrianus de Jongh, Robbin Damen, Erwin Spits, David Loweth Winslow
  • Patent number: 9947636
    Abstract: A method for making a semiconductor device may include bonding a top lead frame component, having recesses, with a bottom lead frame component to form a lead frame, the top and bottom lead frame components each including metal. The method may include mounting an IC on the lead frame, encapsulating the IC and the lead frame, and removing portions of the bottom lead frame component to define contacts for the IC.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: April 17, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Jefferson Talledo
  • Patent number: 9941241
    Abstract: A first semiconductor structure including a first bonding oxide layer having a first metallic bonding structure embedded therein and a second semiconductor structure including a second bonding oxide layer having a second metallic bonding structure embedded therein are provided. A nitride surface treatment process is performed to provide a nitrided surface layer to each structure. Each nitrided surface layer includes nitridized oxide regions located in an upper portion of the bonding oxide layer and nitridized metallic regions located in an upper portion of the metallic bonding structures. The nitrogen within the nitridized metallic regions is then removed to restore the upper portion of the metallic bonding structures to its original composition. Bonding is performed to form a dielectric bonding interface between the nitridized oxide regions present in the first and second structures, and a metallic bonding interface between the first and second metallic bonding structures.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: April 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Chih-Chao Yang
  • Patent number: 9936582
    Abstract: Embodiments of integrated circuit (IC) assemblies and related techniques are disclosed herein. For example, in some embodiments, an IC assembly may include a first printed circuit board (PCB) having a first face and an opposing second face; a die electrically coupled to the first face of the first PCB; a second PCB having a first face and an opposing second face, wherein the second face of the second PCB is coupled to the first face of the first PCB via one or more solder joints; and a molding compound. The molding compound may be in contact with the first face of the first PCB and the second face of the second PCB. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: April 3, 2018
    Assignee: INTEL CORPORATION
    Inventors: Junfeng Zhao, Saeed S. Shojaie, Cheng Yang
  • Patent number: 9910165
    Abstract: A detector system for a CT scanner is provided. The detector system may include a plurality of detector modules. Each of the detector modules may include a supporting frame, two or more detectors and an interface board. A supporting frame may be connected to a casing of the detector system. Detectors may be mounted onto a supporting frame and may convert an X-ray beam within a CT scanner into an electrical signal. An interface board may be disposed in an outer side of a supporting frame away from the focus of an X-ray tube, and may be electrically connected to a plurality of detectors through a connector, so as to provide a control signal and a power supply to the detectors, and to transmit a digital signal outputted by the detectors to a backplane of the detector system through an output line.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: March 6, 2018
    Assignee: Shenyang Neusoft Medical Systems Co., Ltd.
    Inventor: Jun Yu
  • Patent number: 9851379
    Abstract: A test probe structure having a planar surface and contact locations matched to test hardware is provided. The fabrication of the test probe structure addresses problems related to the possible deformation of base substrates during manufacture. Positional accuracy of contact locations and planarity of base substrates is achieved using dielectric layers, laser ablation, injection molded solder or redistribution layer wiring, and planarization techniques.
    Type: Grant
    Filed: March 25, 2017
    Date of Patent: December 26, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bing Dang, John U. Knickerbocker, Jae-Woong Nah, Robert E. Trzcinski, Cornelia Kang-I Tsang
  • Patent number: 9825194
    Abstract: A substrate pad for soldering at least one self-aligning component thereon, wherein at least one edge of a body of the substrate pad is shaped to conform to a corresponding edge of a component pad, and the at least one edge of the body of the substrate pad further include a plurality of pad fingers leading away from the substrate pad. Related apparatus and methods are also described.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: November 21, 2017
    Assignee: Essence Solar Solutions Ltd.
    Inventors: Slava Hasin, Ron Helfan
  • Patent number: 9818694
    Abstract: An integrated circuit (IC) comprises a first conductor in one layer of the IC, a second conductor in another layer of the IC, and a first metal plug connecting the first and second conductors. The IC further comprises an atomic source conductor (ASC) in the one layer of the IC and joined to the first conductor, and a second metal plug connecting the ASC to a voltage source of the IC. The first conductor and the ASC are configured to be biased to different voltages so as to establish an electron path from the second metal plug to the first metal plug such that the ASC acts as an active atomic source for the first conductor.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: November 14, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Hsien Lin, Anthony Oates
  • Patent number: 9818621
    Abstract: Embodiments described herein relate to methods for etching a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment to implant ions into a spacer material, performing an etching process on an implanted region of the spacer material, and repeating the inert plasma treatment and the etching process to form a predominantly flat top spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as pressure, may be controlled to influence a desired spacer profile.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: November 14, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Aurelien Tavernier, Qingjun Zhou, Tom Choi, Yungchen Lin, Ying Zhang, Olivier Joubert
  • Patent number: 9814141
    Abstract: The present invention provides a connection structure of conductors in which, when connecting a pair of conductors facing each other using an anisotropic conductive film containing conductive particles dispersed therein, a short circuit between the adjacent conductors due to a movement of conductive particles is be prevented, and a display apparatus having the connection structure of conductors. When executing thermo-compression bonding processing while interposing the anisotropic conductive film, even if conductive particles dispersed in the anisotropic conductive film are concentrated and continued in a gap between adjacent first terminals, in the vicinity of an edge of an interlayer insulation film, since a distance between the first terminals adjacent to each other is increased due to notches formed therein, the first terminals adjacent to each other are not short-circuited.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: November 7, 2017
    Assignee: Sakai Display Products Corporation
    Inventor: Hidetoshi Nakagawa
  • Patent number: 9799604
    Abstract: A semiconductor device includes a semiconductor substrate and a plurality of metal layers above the semiconductor substrate. A first of the metal layers includes a plurality of first power rails which extend in a first direction and provide a first voltage, a plurality of second power rails which extend in the first direction and provide a second voltage, and a first conductor which is integral with one end of each of the first power rails and extends in a second direction. The first direction is perpendicular to the second direction. The first voltage is one of a ground voltage and a power source voltage and the second voltage is the other voltage.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: October 24, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sung Su Byun
  • Patent number: 9786520
    Abstract: Some embodiments of the present disclosure provide a method of manufacturing a device. The method includes providing a carrier, the carrier including a top surface, covering a portion of the top surface with a plurality of active dies, disposing a protrudent band over a periphery of the carrier, wherein the protrudent band includes a rim shaped along the contour of the carrier, and forming a molding compound over the carrier to cover the plurality of active dies. A method for determining a width of the protrudent band of a device described herein is also provided.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: October 10, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Chih Liu, Chang-Chia Huang, Shih-Yen Lin, Chin-Liang Chen, Kuan-Lin Ho, Wei-Ting Lin
  • Patent number: 9761513
    Abstract: A method of fabricating a three dimensional integrated circuit comprises forming a redistribution layer on a first side of a packaging component, forming a holding chamber in the redistribution layer, attaching an integrated circuit die on the first side of the packaging component, wherein an interconnect bump of the integrated circuit die is inserted into the holding chamber, applying a reflow process to the integrated circuit die and the packaging component and forming an encapsulation layer on the packaging component.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: September 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chung Yee, Chun Hui Yu
  • Patent number: 9728516
    Abstract: An electric apparatus may include a plurality of electric patterns arranged on a substrate. Each of the electric patterns may include a pad for connection with a solder ball, an electrical trace laterally extending from a portion of the pad to allow an electrical signal to be transmitted from or to the pad, a first dummy trace laterally extending from other portion of the pad, and a first connection line connecting the first dummy trace to the electrical trace. The first dummy trace may be provided at a position deviated from a straight line connecting the pad to the electrical trace.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: August 8, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hongbin Shi, Kang Joon Lee
  • Patent number: 9721911
    Abstract: A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface. The conductive pad is located on the first surface. The second surface has a first through hole to expose the conductive pad. The laser stopper is located on the conductive pad in the first through hole. The isolation layer is located on the second surface and in the first through hole. The isolation layer has a third surface opposite to the second surface, and has a second through hole to expose the laser stopper. The redistribution layer is located on the third surface, a sidewall of the second through hole, and the laser stopper in the second through hole. The conductive structure is located on the redistribution.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: August 1, 2017
    Assignee: XINTEC INC.
    Inventors: Ho-Yin Yiu, Ying-Nan Wen, Chien-Hung Liu, Shih-Yi Lee
  • Patent number: 9674955
    Abstract: Provided are a tape carrier package and a method of manufacturing the same, the method, including: forming through holes by performing a drill process using a laser to an insulating film of a flexible copper clad laminate (FCCL) film consisting of the insulating film and a copper layer; forming a circuit pattern layer by performing an etching process to the copper layer of the FCCL film; and selectively forming a plating layer on the circuit pattern layer. The method of manufacturing the tape carrier package according to the present invention is advantageous because a punching process, and processes for laminating and drying the copper layer which are necessary for the conventional method of manufacturing the tape carrier package can be omitted, a production cost of the tape carrier package is reduced, and the time required for the drying process is saved.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: June 6, 2017
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Hong Il Kim
  • Patent number: 9640429
    Abstract: A method of fabricating a semiconductor device includes: forming a metal layer containing Al; forming an insulating film on the metal layer; forming an opening pattern to the insulating film, the metal layer being exposed in the opening pattern; and forming a wiring layer in the opening pattern, a first portion being disposed between an edge of the wiring layer and an edge of the opening pattern, a width of the first portion being 1 ?m or less, and the metal layer being exposed in the first portion.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: May 2, 2017
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Masahiro Nishi
  • Patent number: 9607994
    Abstract: Provided are semiconductor devices and methods of fabricating the same. In methods of forming the same, an etch stop pattern and a separate spacer can be formed on a sidewall of a bit line contact, wherein the etch stop pattern and the separate spacer each comprise material having an etch selectivity relative to an oxide. A storage node contact plug hole can be formed so that the etch stop pattern and the separate spacer form a portion of a sidewall of the storage node contact plug hole spaced apart from the bit line contact. The storage node contact plug hole can be cleaned to remove a natural oxide formed in the storage node contact plug hole. Related devices are also disclosed.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: March 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keunnam Kim, Sunyoung Park, Kyehee Yeom, Hyeon-Woo Jang, Jin-Won Jeong, Changhyun Cho, HyeongSun Hong
  • Patent number: 9607945
    Abstract: A semiconductor device including a multiplicity of large current power elements with each power element divided into a multiplicity of divisional elements and arranged such that the power elements belonging to different power elements are arranged in a repetitive sequential order. The IC chip of the semiconductor device is formed to have output wires extending from the respective divisional elements connected to corresponding output pads without crossing other output wires. Arranged on the IC chip are output bumps in association with the respective output pads. A rewiring layer is provided having output coupling wires for connecting together the bumps that belong to the same power element and connecting them further to an external output electrode.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: March 28, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Kunihiro Komiya
  • Patent number: 9601446
    Abstract: A method of forming a bond pad structure is provided. The method includes forming a first conductive layer over a substrate and depositing a first dielectric layer over the first conductive layer. The first dielectric layer is patterned to form a contiguous planar path substantially parallel to a top surface of the substrate. Patterning the first dielectric layer includes defining a dielectric region of the first dielectric layer surrounded by a portion of the contiguous planar path, and forming a first via hole in the dielectric region. The contiguous planar path and the via hole are filled with a conductive material. The conductive material in the contiguous planar path forms a second conductive layer, and the contiguous planar path extends from a first lateral side wall of the second conductive layer to a second lateral sidewall of the second conductive layer. A bond pad is formed over the second conductive layer, and the bond pad is electrically connected to the second conductive layer.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Hsien-Wei Chen, Hao-Yi Tsai, Yu-Wen Liu
  • Patent number: 9595489
    Abstract: A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers, a plurality of first power supply voltage bond fingers, and a plurality of second power supply voltage bond fingers. The signal pads are connected respectively to the signal bond fingers by first wires. The first power supply voltage bond fingers and the second power supply voltage bond fingers are connected respectively to the auxiliary pads by second wires. The first wires are disposed between those of the second wires which are connected to the first power supply voltage bond fingers and those of the second wires which are connected to the second power supply voltage bond fingers.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: March 14, 2017
    Assignee: Longitude Semiconductor S.a.r.l.
    Inventors: Mitsuaki Katagiri, Ken Iwakura, Yutaka Uematsu
  • Patent number: 9560740
    Abstract: A circuit module, including: a substrate having electronic components mounted thereon and further having a conductive pattern that defines respective shielded areas where the electronic components are mounted; a sealing layer covering the substrate and the electronic components, the sealing layer having grooves formed therein along the conductive pattern; and a conductive shield, including: a first shielding section covering a top surface of the sealing layer; a second shielding section covering side faces of the sealing layer; and a third shielding section filling the grooves in the sealing layer, wherein the grooves are shaped such that the third shielding section has at least one end thereof connected to the second shielding section, the third shielding section thereby acting as shielding walls partitioning the respective shielded areas, and that said at least one end of the third shielding section has a width wider than other portions of the third shielding section.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: January 31, 2017
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Kenzo Kitazaki, Eiji Mugiya, Masaya Shimamura
  • Patent number: 9551573
    Abstract: A device includes sensor substantially coplanar with one another in a sensor plane, each sensor generating a sense value that varies according to a physical distance between the sensor and an object. The device also includes control circuits configured to generate a first position value, a second position value, and a third value using the sense values in a first mode to detect a hover or glove operation by the object. The first position value and the second position values identify a two-dimensional position of the object in the sensor plane and the third value varies in response to movement of the object in a Z-direction substantially perpendicular to the sensor plane. The control circuits are also configured to generate a fourth position value and a fifth position value in a second mode to detect a touch operation by the object. The control circuits include a programmable integrated circuit including an analog portion and a digital portion.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: January 24, 2017
    Assignee: Creator Technology B.V
    Inventors: Richard Harding, John B. Foreman
  • Patent number: 9514984
    Abstract: A method for manufacturing a semiconductor device includes forming an insulating layer on a semiconductor layer; forming a metal layer on the insulating layer; and forming a first interconnect by selectively etching the metal layer. The first interconnect is electrically connected to the semiconductor layer and has a loop configuration. The method includes forming a first mask layer covering the first interconnect and the insulating layer; and forming a second mask layer on the first mask layer. The second mask layer has a first opening over a portion of the first interconnect. The method further includes exposing the portion of the first interconnect by selectively removing the first mask layer using the second mask layer; and forming a second interconnect by selectively removing the portion of the first interconnect using the first mask layer. The second interconnect has two ends and is electrically connected to the semiconductor layer.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: December 6, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Katsumi Yamamoto
  • Patent number: 9461000
    Abstract: A silicon interposer with redundant thru-silicon vias. The silicon interposer includes a first trace structure on a first side of the interposer and a second trace structure on a second side of the interposer. The silicon interposer also includes at least two redundant thru-silicon vias connecting the first trace structure to the second trace structure.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: October 4, 2016
    Assignee: eSilicon Corporation
    Inventor: Javier DeLaCruz
  • Patent number: 9455270
    Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate having a trench, a stacked structure, an etching stop structure, a plurality of memory structure, and a first filled slit groove formed in the stacked structure. The stacked structure has a horizontal extended region and a vertical extended region extending along a sidewall of the trench. The stacked structure includes a plurality of conductive layer s and a plurality of insulating layers interlacedly stacked in the trench. The etching stop structure is formed in the vertical extended region. The memory structures vertically penetrate through the conductive layers and the insulating layers in the horizontal extended region. The conductive layers and the insulating layers in the vertical extended region are formed on the etching stop structure and located between the etching stop structure and the first filled slit groove.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: September 27, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Erh-Kun Lai
  • Patent number: 9426914
    Abstract: Systems and methods provide for a device including a film having a shape that defines an interior region. The device may also include one or more electronic components disposed within the interior region of the film, and a hardened thermo-set resin within the interior region, wherein the thermo-set resin encompasses the electronic components and substantially fills the interior region of the film. In one example, printed content is coupled to a surface of the film. In addition, the thermo-set resin may include an additive that is configured to absorb and distribute heat generated by the electronic components.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: August 23, 2016
    Assignee: Intel Corporation
    Inventors: Peter Davison, David Pidwerbecki
  • Patent number: 9397271
    Abstract: An optoelectronic semiconductor component includes a connection carrier with at least two connection points and a carrier top that in a main side of the connection carrier, wherein the connection carrier configured with a silicone matrix with a fiber reinforcement, at least one optoelectronic semiconductor chip mounted on the connection carrier and in direct contact therewith, an annular potting body includes a soft silicone on the carrier top and in direct contact with the carrier top, but not in direct contact with the semiconductor chip, and a glass body comprising a glass sheet applied over the semiconductor chip and over sides of the potting body remote from the connection carrier, thereby forming a space between the semiconductor chip and the potting body.
    Type: Grant
    Filed: April 20, 2009
    Date of Patent: July 19, 2016
    Assignees: OSRAM Opto Semiconductors GmbH, Shin-Etsu Chemical Co., Ltd.
    Inventors: Harald Jaeger, Joerg Erich Sorg, Tsutomu Kashiwagi, Toshio Shiobara
  • Patent number: 9391033
    Abstract: The semiconductor device has the CSP structure, and may include a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps may be arranged in two rows along the periphery of the semiconductor device. The electrode pads may be arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring may be extended from an electrode pad, and may be connected to any one of the outermost solder bumps or any one of the inner solder bumps.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: July 12, 2016
    Assignee: ROHM CO., LTD.
    Inventor: Kunihiro Komiya
  • Patent number: 9355947
    Abstract: A printed circuit board (PCB) includes a base substrate including upper and lower surfaces, a plurality of solder ball pads separately formed on the lower surface of the base substrate in a radial direction and forming one or more radial pad groups, a plurality of first traces respectively connected to the plurality of solder ball pads and extending to an inside of the radial pad group, and a plurality of second traces respectively connected to the plurality of first traces and extending to an outside of the radial pad group.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: May 31, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyo-soon Kang, Sun-won Kang, Joon-young Park, Doo-hee Hwang, Tae-young Yoon
  • Patent number: 9337152
    Abstract: Disclosed and claimed herein is a formulation for packaging an electronic device and assemblies made therefrom.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 10, 2016
    Assignee: Nuvotronics, Inc
    Inventors: David William Sherrer, James D MacDonald
  • Patent number: 9331008
    Abstract: The semiconductor device of the present invention includes a semiconductor substrate provided with semiconductor elements, a lower layer wiring pattern which includes first wiring and second wiring, the first wiring and the second wiring disposed separately so as to be flush with each other, and the first wiring and the second wiring being fixed at a mutually different potential, an uppermost interlayer film disposed on the lower layer wiring pattern, a titanium nitride layer disposed on the uppermost interlayer film so as to cover the first wiring and the second wiring, and the titanium nitride having the thickness of 800 ? or more, and a pad metal disposed on the titanium nitride layer.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: May 3, 2016
    Assignee: ROHM CO., LTD.
    Inventor: Motoharu Haga
  • Patent number: 9322848
    Abstract: A semiconductor die with an array of contacts, where at least two contacts in adjacent positions have the same data signal during testing operations with a test probe. The adjacent contacts of the cluster allow the use of a larger test probe tip and/or greater tolerance on test probe tip alignment during testing operations.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: April 26, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Otto A. Torreiter, Dieter Wendel
  • Patent number: 9318454
    Abstract: This drive chip has a configuration that is provided with: a base main body; two terminal groups that are respectively disposed along the base main body sides in the longitudinal direction of the base main body, said sides facing each other; a narrow-pitch section in one terminal group wherein terminals are disposed in a zigzag manner in two or more rows, said narrow-pitch section having a narrow terminal pitch in the longitudinal direction; a rough pitch section in the one terminal group, said rough pitch section having a terminal pitch in the longitudinal direction wider than that of the narrow pitch section; and a dummy bump that is disposed between the two terminal groups, said dummy bump being disposed parallel to the rough pitch section.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: April 19, 2016
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takashi Matsui, Takeshi Horiguchi, Motoji Shiota