Abstract: Better semiconductor encapsulation is achieved with a liquid epoxy resin composition comprising (A) a liquid epoxy resin, (B) a curing agent containing at least 5 wt % of an aromatic amine compound, (C) a microencapsulated catalyst containing a phenolic hydroxy-bearing benzoic acid derivative, and optionally, (D) an inorganic filler.

Abstract: A semiconductor device is made by forming solder bumps on a first side of a semiconductor wafer. A protective layer is formed on a second side of the semiconductor wafer opposite the first side. The protective layer can be adhesive paste, laminated film, spin-coated resin, epoxy based elastomer, organic rubbery material, polystyrene, polyethylene terephthalate, or other polymer material. The semiconductor wafer is singulated into semiconductor die. The semiconductor die is mounted to a carrier. A molding compound is formed around the semiconductor die. The protective layer provides stress relief for the semiconductor die. The protective layer is removed from the semiconductor die. The protective layer can provide a thermal dissipation, in which case it is made with metal or polymer-based material with a filler such as alumina, zinc oxide, silicon dioxide, silver, aluminum, and aluminum nitride.

Abstract: Methods and apparatus to control surface properties via colloidal coatings are described. In one embodiment, colloidal coating may be used on a surface to enhance flow control. Other embodiments are also described.

Abstract: A microelectronic device includes a die having an active surface and a non-active surface. To assemble the microelectronic device, the active surface of the die is placed on a substrate. A first material is dispensed between the active surface of the die and the substrate. A second material is dispensed on at least a portion of the non-active surface of the die. The second material is different than the first material and the first material and the second material are simultaneously cured.

Abstract: An ultra-thin semiconductor chip of an FeRAM, which is miniaturized and highly integrated with characteristic degradation of a ferroelectric capacitor suppressed though a thin package structure is applied to the FeRAM is realized. The semiconductor chip is molded up by using a sealing resin with a filler content set at a value in a range of 90 weight % to 93 weight % to produce a package structure.

Abstract: An epoxy resin molding material for sealing which comprises an epoxy resin, an epoxy resin curing agent, and a pitch, as well as an electronic component comprising an element that is sealed with the molding material. This molding material exhibits favorable coloring properties, and even when used in packages with narrow distances between pads or wires, shorting defects caused by conductive materials can be prevented, as the molding material contains no conductive carbon black.

Abstract: A semiconductor device in which chips are resin-molded, including: frames having front and back surfaces and die pads; power chips mounted on the surfaces of the die pads; an insulation resin sheet having a first and a second surfaces which are opposed against each other, the resin sheet being disposed such that the back surfaces of the die pads contact the first surface of the resin sheet; and a mold resin applied on the first surface of the resin sheet so as to seal up the power chips. The thermal conductivity of the resin sheet is larger than that of the mold resin.

Abstract: An epoxy resin composition for semiconductor encapsulation includes at least one epoxy resin, at least one curing agent, at least one filler, and at least one first curing accelerator, the first curing accelerator having a tetracyanoethylene, a 7,7,8,8-tetracyanoquinodimethane, a compound having the chemical structure of Formula 1, or a mixture thereof, wherein each of R1 through R7, independently, represents a hydrogen atom or a C1-C12 hydrocarbon group, provided that when R1 through R7 are C1-C12 hydrocarbon groups, R1 and R2, R2 and R3, R3 and R4, R4 and R5, R5 and R6, and R6 and R7 can be joined to each other to form a cyclic structure.

Abstract: A board 1 according to the present invention includes a board main body 3; electronic parts 5 electrically connected to and mounted on the board main body 3; and an under-fill material 19 with which a part between the board main body 3 and a surface of the electronic parts 5 electrically connected to the board main body is filled. A hole 21 passing through a layer 19a of the under-fill material that flows outside from a connecting area of the electronic parts 5 and the board main body 3 is provided for electrically connecting other parts to the board main body.

Abstract: A device is disclosed which includes a die comprising an integrated circuit and an interposer that is coupled to the die, the interposer having a smaller footprint than that of the die. A method is disclosed which includes operatively coupling an interposer to a die comprising an integrated circuit, the interposer having a smaller footprint than that of the die, and filling a space between the interposer and the die with an underfill material.

Abstract: A module component in which mounting components and a conductive partition for dividing into a plurality of circuit blocks are mounted on a substrate. The circuit blocks are covered with a sealing member, which is further covered on its surface with a conductive film to electrically shield the circuit blocks individually. This module component can maintain bending strength, with little warpage by a sufficient shielding effect achieved without increasing the number of manufacturing processes.

Abstract: An electrical component is placed on a substrate. At least one film comprising a plastic material is connected to the component and to the substrate in such a way that a surface contour defined by the component and the substrate is represent is represented in a surface contour of the part of the film. Said film is laminated onto the component and the substrate in such a way that the film follows the topology of the arrangement consisting of the component and the substrate. Said film is in contact with the component and the substrate in a positive and non-positive manner, and comprises a composite material containing a filler that is different to the plastic material. The processability and electrical properties of the film are influenced by the filler or the composite material obtained thereby. In this way, other functions can be integrated into the film. Said component is, for example, a power semiconductor component. An electrically insulating and thermoconductive film is used, for example.

Abstract: A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.

Abstract: In some embodiments, a method includes providing a composition which includes a base at least partially filled with filler particles and applying the composition as an underfill composition. At least some of the filler particles are electrically conductive.

Abstract: There is provided an epoxy resin composition for semiconductor encapsulating use comprising: an epoxy resin (A); a phenol resin (B); a curing accelerator (C); and an inorganic filler (D), wherein the inorganic filler (D) contains a spherical fused silica (d1) which contains: metal or semimetal other than silicon; and/or an inorganic compound comprising the metal or semimetal other than silicon.

Abstract: Inorganic-based nanoparticles, such as nanoparticles based on silicon dioxide, are used in order to produce protective layers for semiconductor chips having scratch-resistant properties. The nanoparticles are preferably processed to form a sol, which is applied onto the semiconductor chips to be coated and subsequently converted by sintering into the protective layer.

Abstract: A semiconductor chip 23 is mounted on an island section 22 in a lead frame composed of a lead having the island section 22, a ground-bonding lead section 28 and a lead 21a each continuing in sequence, and other lead terminal sections 21b to 21d, and then a grounding electrode 24a and other electrodes 24b to 24d for the semiconductor chip are respectively wire-bonded to the lead 21a and other lead terminals 21b to 21d by gold wires 25a to 25d before being embedded in a resin to form a package 27. The lead with the semiconductor chip 23 mounted thereon is structured so that the ground-bonding lead section 28 continuing to both the lead 21a and the island section 22 are absent on both the sides of the wire-bonding region 28a with respect to the island section 22 in the longitudinal section along the grounded gold wire 25a.

Abstract: A semiconductor photodetector which can achieve spectral sensitivity characteristics close to relative luminous characteristics at low cost while using a light receiving element of a semiconductor made from such as silicon, has a semiconductor light receiving element having high spectral sensitivity in a wavelength range between approximately 400 nm to 1100 nm and an optical transmitting resin for sealing at least a light receiving surface of the semiconductor light receiving element. The optical transmitting resin is formed by dispersing metal boride micro particles whose particle diameter is not more than approximately 100 nm in a transparent resin and blocks light in wavelengths approximately 700 nm or above.

Abstract: A high frequency IC package mainly includes a substrate, a bumped chip, and a plurality of conductive fillers where the substrate has a plurality of bump holes penetrating from the top surface to the bottom surface. The active surface of the chip is attached to the top surface of the substrate in a manner that the bumps are inserted into the bump holes respectively. The conductive fillers are formed in the bump holes to electrically connect the bumps to the circuit layer of the substrate. The high frequency IC package has a shorter electrical path and a thinner package thickness.

Abstract: Polymerized materials for forming the underfill and encapsulation structures for semiconductor package are disclosed. A filler constituent, such as boron nitride, silicates, elemental metals, or alloys, may be added to a liquid photopolymer resin to tailor the physical properties thereof upon curing. The filler constituents may be employed to alter the coefficient of thermal expansion, thermal conductivity, or electrical conductivity of the polymerized material. A number of different embodiments are disclosed that employ the above materials in selected regions of the underfill and encapsulation structures of the semiconductor package. The polymerized materials may also be used to form support structures and covers for optically interactive semiconductor devices. Methods for forming the above structures using stereolithography are also disclosed.

Abstract: A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into the lead frame. The sidewall material extends into the aperture, thereby forming a strong interfacial bond that provides a low leakage, sidewall-lead-frame interface. The base has a reentrant feature that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby forming a low leakage base-sidewall interface. The top surface of the base has a groove that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby enhancing the low leakage base-sidewall interface.

Abstract: A method of making chip assemblies includes providing an in-process assembly including a semiconductor wafer, a wafer compliant structure overlying a front surface of the wafer and cavities, and terminals carried on the compliant structure adjacent the cavities and electrically connected to the wafer, the cavities being substantially sealed. The method includes subdividing the in-process assembly to form individual chip assemblies, each including one or more chip regions of the wafer, a portion of the compliant structure and the terminals carried on the portion, and opening vents communicating with said cavities after said providing step.

Abstract: In one embodiment the present invention includes a method of manufacturing a chip scale package. Embodiments of the present invention include sawing kerfs between semiconductor device boundaries on opposite sides of the wafer and filling the kerfs with mold compound. The devices may then be sawed into individual packaged devices encapsulated in mold compound. In one embodiment, kerfs on opposite sides of the wafer have different widths to create a step in the wafer boundary with the mold compound, which improves the integrity of the package. In one embodiment, a device and one or more neighboring devices are bonded together using bond wires to form a group of device that are encapsulated in mold compound.

Abstract: A flame retardant featuring: an inorganic porous fine particle, a phosphazene compound represented by the following average compositional formula (1) (X is a single bond, CH2, C(CH3)2, SO2, S, 0, or O(CO)O; n is an integer of from 3 to 1000; d and e are numbers with 2d+e=2n), and a resin layer. The phosphazene compound is supported on the inorganic porous fine particle, and the resin layer coats the inorganic porous fine particle with the phosphazene compound supported thereon. The resin layer thermally decomposes to lose weight by 10% at a temperature of from 300° C. to 500° C., as measured by thermogravimetry in the air at a heating rate of 10° C./min.

Abstract: A semiconductor device includes: a substrate; a semiconductor element mounted on the substrate; a sealing structure for sealing the semiconductor element, the sealing structure being mounted on the substrate; and an adhesive for bonding the sealing structure and the substrate, wherein the sealing structure has a groove for storing the adhesive.

Abstract: A semiconductor apparatus includes a substrate and elements or semiconductor chips provided on the substrate. The elements are sealed by being brought into contact with a sealing compound. The surface of contact on the elements or the sealing compound is plasma treated. The semiconductor chip is adhesively attached to another semiconductor chip via an adhesive compound. The surface of the semiconductor chip in contact with the adhesive compound is plasma treated.

Abstract: A circuit with embedding components (13) is produced by placing the components (13) on a substrate (14) and applying sheets (15) of prepreg. The prepreg sheets (15) have apertures to accommodate the -components, the number of sheets and arrangement of apertures being chosen to accommodate a variety of component X, Y and Z dimensions. A top layer with Cu foil (16(b)) is applied. The assembly is pressed in an operation analogous to conventional multilayer board lamination pressing. This causes all of the prepreg resin to flow to completely embed the components without raids or damage. Electrical connections are made by drilling and plating vias.

Abstract: A high reliability semiconductor device is provided which can prevent electromigration due to the deposition of metal ions originating from wires. The device includes: a flexible wiring board 11 including a base film 1 and multiple wires 9; a semiconductor chip 5 mounted to the flexible wiring board 11; and a sealing resin 6 disposed between the flexible wiring board 11 and the semiconductor chip 5 so as to at least partially in contact with the wires 9. The sealing resin 6 contains a metal ion binder mixed thereto.

Abstract: An embodiment of a semiconductor device includes a supporting member, a semiconductor die mounted on a portion of the supporting member, a buffer region, and a plastic encapsulation. The buffer region covers a portion of the die, and includes a resin and filler particles packed within the resin. The filler particles have a mix of filler sizes and are tightly packed within the resin. The buffer region has a first dielectric constant and a first loss tangent. The plastic encapsulation encloses at least part of the supporting member and the die. The plastic encapsulation includes a plastic material of a second dielectric constant and a second loss tangent, where the second dielectric constant is larger than the first dielectric constant and the second loss tangent is larger than the first loss tangent.

Abstract: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes coupling a plurality of singulated imaging dies to a support member. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes forming a plurality of stand-offs on corresponding imaging dies before and/or after the imaging dies are singulated and electrically connecting the external contacts of the imaging dies to corresponding terminals on the support member. The individual stand-offs include a portion between adjacent external contacts.

Abstract: In an epoxy resin composition comprising (A) an epoxy resin, (B) a curing agent, (C) an inorganic compound, and (D) an inorganic filler, the inorganic compound (C) is an oxide of metal elements at least one of which is a metal element of Group II in the Periodic Table having a second ionization potential of up to 20 eV, typically Zn2SiO4, ZnCrO4, ZnFeO4 or ZnMoO4. When used for semiconductor encapsulation, the epoxy resin composition is highly reliable and cures into a product which is effective for minimizing electrical failure such as defective insulation due to a copper migration phenomenon.

Abstract: A semiconductor light-emitting device having a semiconductor light-emitting chip; a high refractive index lens covering around the semiconductor light-emitting chip; and a resin having fine particles mixed therein that fills a space between the semiconductor light-emitting chip and the lens is provided. In the semiconductor light emitting device, the resin having fine particles mixed therein is composed of an optically transparent resin into which a large number of high refractive fine particles having a mean diameter of 100 nm or less and composed of a dielectric material are mixed uniformly to have a distance 200 nm or less between respective particles.

Abstract: To provide a circuit device freed from constrains of a mounting direction. The circuit device according to the present invention includes: a conductive pattern for forming a die pad, a first bonding pad, and a second bonding pad; and a semiconductor element (TR) attached to the conductive pattern. The circuit device further includes: a sealing resin for covering the semiconductor element (TR) and the conductive pattern with a rear surface of the conductive pattern being exposed; and a coating resin for covering the rear surface of the conductive pattern exposed from the sealing resin. The rear surface of the conductive pattern is exposed from openings of the coating resin, and the openings are arranged with rotational symmetry about a central point of the circuit device.

Abstract: Microelectronic imaging units and methods for manufacturing microelectronic imaging units are disclosed herein. In one embodiment, a method includes placing a plurality of singulated imaging dies on a support member. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes disposing a plurality of discrete stand-offs on the support member. The discrete stand-offs are arranged in arrays relative to corresponding imaging dies. The method further includes electrically connecting the external contacts of the imaging dies to corresponding terminals on the support member, and attaching a plurality of covers to corresponding stand-off arrays so that the covers are positioned over the image sensors.

Abstract: Ball grid array packages for semiconductor die include a thermally conductive container and a substrate that substantially enclose a semiconductor die. The die is positioned with respect to the container by thermally conductive supports formed in the container or attached to the container. The die contacts the supports so that the die and the container form a cavity that is at least partially filled with a thermally conductive material such as a conductive epoxy to promote thermal conduction between the die and the container. The die electrically connects to the substrate with bond wires that extend through an aperture in the substrate and attach to bond pads provided on the substrate. The aperture is typically filled with a protective layer of resin, epoxy, or other material that also encapsulates the bond wires.

Abstract: An encapsulating epoxy resin molding material, comprising (A) an epoxy resin, (B) a curing agent, and (C) an inorganic filler, wherein the inorganic filler (C) has an average particle size of 12 ?m or less and a specific surface area of 3.0 m2/g or more.

Abstract: A chip module having a chip which is mounted by means of chip adhesive on a mount and is electrically connected via bonding wires to contact pads, and an encapsulation compound which surrounds the chip and the bonding wires and is bounded by a subarea of the mount. The encapsulation compound is radiation-hardened and heat-hardened in a combined form and has radiation-impermeable pigments.

Abstract: An underfill composition is formulated to increase the surface tension thereof for use in capillary underfilling of an integrated circuit die that is coupled to a mounting substrate. A method includes mixing a surface tension-increasing additive with a bulk polymer and a hardener and allowing the underfill composition to flow between the integrated circuit die and the mounting substrate. An article is achieved by the method. The article can be assembled into a computing system.

Abstract: In one embodiment, a semiconductor package is formed by adding a layer of particles to desired portions of a packing substrate. The layer of particles forms a matrix of crevices that provides a micro-lock feature for mechanically locking or engaging encapsulating materials.

Abstract: An anti-warp package comprising a packaging substrate, a chip and a stiffening member is provided. The chip is disposed on a top surface of the packaging substrate. The stiffening member is disposed on a bottom surface of the packaging substrate in a location underneath the surrounding area of the chip. Through the disposition of a stiffening member, warping stress on the packaging substrate when the chip is encapsulated by molding compound is counterbalanced.

Abstract: A circuit device which enables easy formation of a connection part that connects wiring layers to each other, and a manufacturing method thereof are provided. In a method for manufacturing a hybrid integrated circuit device of the present invention, a first resin film is formed so as to cover a first wiring layer. Thereafter, a first through-hole is formed, which penetrates the first resin film and exposes the first wiring layer from a bottom thereof. Next, a second resin film is formed so as to fill up the first through-hole. Moreover, a second through-hole is formed in the second resin film buried in the first through-hole, and a connection part is formed.

Abstract: The invention provides electronic articles and methods of making said articles. The electronic articles comprise an electronic component bonded and electrically connected to a substrate using an underfill adhesive comprising the reaction product of a thermosetting resin, curing catalyst, and surface-treated nanoparticles that are substantially spherical, non-agglomerated, amorphous, and solid.

Abstract: Accumulating spaces for conductive particles are formed in gaps of wiring patterns for conductive wirings which are disposed on a surface of a supporting body. When interconnecting a pair of interconnection objects having the respective wiring patterns via an anisotropic conductive film thereon due to a thermocompression bonding, the conductive particles to be flown-out into the gaps by the thermocompression bonding are allowed to escape into the accumulating spaces, so that an over-density of the conductive particles can be prevented to avoid a shortage in the wiring patterns.

Abstract: A circuit device suitable for connecting a plurality of laminated wiring layers to each other through an insulating layer, and a manufacturing method thereof are provided. According to a hybrid integrated circuit device of the present invention and a manufacturing method thereof, a first conductive film is laminated on a first insulating layer, and a first wiring layer is formed by patterning the first conductive film. Next, a second conductive film is laminated on a second insulating layer. Thereafter, by partially removing the second insulating layer and the second conductive film in a desired spot, a connection part for connecting the wiring layers to each other is formed.

Abstract: A disclosed substrate having a built-in semiconductor chip includes the built-in semiconductor chip, a resin member having the built-in semiconductor chip contained therein and external connection terminals. The resin member contains a resin and 60 to 90% by weight of spherical filler.

Abstract: An optoelectronic device, comprising a package body (57) and at least one semiconductor chip (50) arranged on the package body (57). The surface of the package body (57) has a metallized subregion (15) and a non-metallized subregion (20). The package body (57) includes at least two different plastics (53, 54), one of the plastics being non-metallizable (54) and this plastic determining the non-metallized subregion (20). A method for producing such components and a method for the patterned metallization of a plastic-containing body are also provided.

Abstract: A semiconductor device has antenna pads and a testing pad formed on the substrate. An insulating resin layer containing a filler covers the testing pad, and bumps are provided on the antenna pads. Specific data in the semiconductor device are inhibited from being read out or rewritten, by the provision of the insulating resin layer containing a filler.

Abstract: A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into the lead frame. The sidewall material extends into the aperture, thereby forming a strong interfacial bond that provides a low leakage, sidewall-lead-frame interface. The base has a reentrant feature that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby forming a low leakage base-sidewalls interface. The top surface of the base has a groove that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby enhancing the low leakage base-sidewall interface.

Abstract: A semiconductor device that exhibits an enhanced inhibition to a generation of voids in an underfill resin for encapsulation supplied between a semiconductor chip and an electronic component, which are mutually coupled through bump electrodes. The semiconductor device includes a first semiconductor chip and a second semiconductor chip, wherein bumps-formed surface of the first semiconductor chip is opposed to bumps-formed surface of the electronic component. The semiconductor device includes insulating films that function as protective films respectively formed on an uppermost surface of the first semiconductor chip and on an uppermost surface of the electronic component. Openings for supplying an underfill resin between the first semiconductor chip and the second semiconductor chip are provided in the vicinity of the bumps-formed regions of at least one of the insulating films.

Abstract: An underfill includes a base material and a filler material added to the base material wherein the filler material constitutes a selected percentage by weight of the underfill to provide an optimum balance between interfacial die stress and solder bump strain for next generation, Cu, low-K silicon technology.