Encapsulated Patents (Class 257/787)
  • Patent number: 11410942
    Abstract: A package is disclosed. In one example, the package comprises a carrier, an electronic component mounted on the carrier, and an encapsulant encapsulating at least part of the electronic component and only part of the carrier so that another exposed part of the carrier is exposed with regard to the encapsulant. The exposed part of the carrier comprises an electric connection structure and a corrosion protection structure. One of the electric connection structure and the corrosion protection structure is selectively formed on only a sub-portion of the other one of the electric connection structure and the corrosion protection structure outside of the encapsulant.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: August 9, 2022
    Assignee: Infineon Technologies AG
    Inventors: Jochen Dangelmaier, Klaus Elian
  • Patent number: 11335570
    Abstract: A microelectronic device, in a multirow gull-wing chip scale package, has a die connected to intermediate pads by wire bonds. The intermediate pads are free of photolithographically-defined structures. An encapsulation material at least partially surrounds the die and the wire bonds, and contacts the intermediate pads. Inner gull-wing leads and outer gull-wing leads, located outside of the encapsulation material, are attached to the intermediate pads. The gull-wing leads have external attachment surfaces opposite from the intermediate pads. The external attachment surfaces of the outer gull-wing leads are located outside of the external attachment surfaces of the inner gull-wing leads. The microelectronic device is formed by mounting the die on a carrier, forming the intermediate pads without using a photolithographic process, and forming the wire bonds. The encapsulation material is formed, and the carrier is subsequently removed, exposing the intermediate pads.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: May 17, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sreenivasan K Koduri
  • Patent number: 11322456
    Abstract: A foundation layer having a stiffener and methods of forming a stiffener are described. One or more dies are formed over the foundation layer. Each die has a front side surface that is electrically coupled to the foundation layer and a back side surface that is opposite from the front side surface. A stiffening layer (or a stiffener) is formed on the back side surface of at least one of the dies. The stiffening layer may be directly coupled to the back side surface of the one or more dies without an adhesive layer. The stiffening layer may include one or more materials, including at least one of a metal, a metal alloy, and a ceramic. The stiffening layer may be formed to reduce warpage based on the foundation layer and the dies. The one or more materials of the stiffening layer can be formed using a cold spray.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: May 3, 2022
    Assignee: Intel Corporation
    Inventors: Feras Eid, Venkata Suresh R. Guthikonda, Shankar Devasenathipathy, Chandra M. Jha, Je-Young Chang, Kyle Yazzie, Prasanna Raghavan, Pramod Malatkar
  • Patent number: 11310402
    Abstract: An image capturing device including a cover plate, an image capturing module, a frame body, a first adhesive layer, and a second adhesive layer is provided. The frame body and the image capturing module are located on the same side of the cover plate. The frame body is joined to the cover plate through the first adhesive layer. The image capturing module is joined to the frame body through the second adhesive layer. An orthographic projection of the second adhesive layer on the cover plate falls within an orthographic projection of the frame body on the cover plate.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: April 19, 2022
    Assignee: Gingy Technology Inc.
    Inventors: Wen-Chen Lee, Chiung-Han Wang, Jen-Chieh Wu
  • Patent number: 11309232
    Abstract: A semiconductor device includes: a substrate; a semiconductor element that disposed on the upper surface of the substrate; a sealing portion that seals the substrate and the semiconductor element; a first lead frame that has one end in contact with a upper surface of the first conductive layer at an end extending in the side direction of the upper surface of the substrate in the sealing portion, and has the other end exposed from the sealing portion; a first conductive bonding material that bonds between the upper surface of the first conductive layer and the lower surface side of the one end portion of the first lead frame at the end portion of the substrate, and has electrical conductivity.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: April 19, 2022
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Soichiro Umeda, Takenori Ishioka
  • Patent number: 11302682
    Abstract: An optical device package comprises a carrier having a first surface and a second surface recessed with respect to the first surface and a lid disposed on the second surface of the carrier.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: April 12, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tsung-Yueh Tsai, Meng-Jen Wang, Yu-Fang Tsai, Meng-Jung Chuang
  • Patent number: 11289396
    Abstract: A semiconductor package includes a semiconductor die including a sensing component, an encapsulant extending along sidewalls of the semiconductor die, a through insulator via (TIV) and a dummy TIV penetrating through the encapsulant and disposed aside the semiconductor die, a patterned dielectric layer disposed on the encapsulant and exposing the sensing component of the semiconductor die, a conductive pattern disposed on the patterned dielectric layer and extending to be in contact with the TIV and the semiconductor die, and a first dummy conductive pattern disposed on the patterned dielectric layer and connected to the dummy TIV through an alignment opening of the first patterned dielectric layer. The semiconductor die is in a hollow region of the encapsulant, and a top width of the hollow region is greater than a width of the semiconductor die.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Chu, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Tian Hu
  • Patent number: 11282879
    Abstract: An image sensor packaging method, an image sensor packaging structure and a lens module are disclosed by the present invention provides. With the image sensor packaging method, a plurality of image sensor chips are embedded in a molding layer, thus allowing a greatly reduced thickness and improved slimness of the resulting packaging structure. Moreover, in this packaging method, instead of bonding wires, solder pads are externally connected by thin film metal layer formed on non-photosensitive surface area located on the same side as light-sensing surfaces. This allows a reduced impact on the light-sensing surfaces as well as a shorter distance from each solder pad to a corresponding one of the light-sensing surfaces along the direction parallel to the light-sensing surfaces, when compared to the use of bonding wires.
    Type: Grant
    Filed: September 29, 2018
    Date of Patent: March 22, 2022
    Assignee: INNO-PACH TECHNOLOGY PTE LTD
    Inventors: Liping Chang, Deze Yu, Wanning Zhang
  • Patent number: 11262607
    Abstract: A liquid crystal antenna and a manufacturing method thereof are disclosed. The liquid crystal antenna includes: an antenna array including a first substrate and a second substrate arranged opposite to each other and configured to change a phase of an electromagnetic wave signal fed into the liquid crystal antenna to transmit or receive a beam in a preset direction; and an inertial navigation element configured to determine a motion parameter of the liquid crystal antenna in a navigation coordinate system, the inertial navigation element is disposed on a side of the second substrate facing the first substrate; and the antenna array adjusts the preset direction according to the motion parameter acquired by the inertial navigation element.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: March 1, 2022
    Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ying Wang, Xue Cao, Peizhi Cai, Zhifu Li, Hao Liu
  • Patent number: 11251135
    Abstract: An electronic device module includes a substrate, at least one first component and at least one second component disposed on one surface of the substrate, a second sealing portion having the at least one second component embedded therein, and disposed on the substrate, and a first sealing portion disposed outside of the second sealing portion, at least a portion of the first sealing portion being disposed between the at least one first component and the substrate.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: February 15, 2022
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jong In Ryu, Suk Youn Hong, Gi Su Chi, Seung Hyun Hong, Ki Chan Kim
  • Patent number: 11195816
    Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes a plurality of integrated circuits, a first encapsulant, a first redistribution structure, a plurality of conductive pillars, a second redistribution structure, a second encapsulant and a third redistribution structure. The first encapsulant encapsulates the integrated circuits. The first redistribution structure is disposed over the first encapsulant and electrically connected to the integrated circuits. The conductive pillars are disposed over the first redistribution structure. The conductive pillars are disposed between and electrically connected to the first and second redistribution structures. The second encapsulant encapsulates the conductive pillars and is disposed between the first redistribution structure and second redistribution structure.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: December 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee
  • Patent number: 11171090
    Abstract: A method includes forming a device structure, the method including forming a first redistribution structure over and electrically connected to a semiconductor device, forming a molding material surrounding the first redistribution structure and the semiconductor device, forming a second redistribution structure over the molding material and the first redistribution structure, the second redistribution structure electrically connected to the first redistribution structure, attaching an interconnect structure to the second redistribution structure, the interconnect structure including a core substrate, the interconnect structure electrically connected to the second redistribution structure, forming an underfill material on sidewalls of the interconnect structure and between the second redistribution structure and the interconnect structure.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun Yi Wu, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu, Shou-Yi Wang, Chien-Hsun Chen
  • Patent number: 11164756
    Abstract: The present disclosure relates to a semiconductor device package including a substrate, a semiconductor device and an underfill. The substrate has a first surface and a second surface angled with respect to the first surface. The semiconductor device is mounted on the first surface of the substrate and has a first surface facing the first surface of the substrate and a second surface angled with respect to the first surface of the substrate. The underfill is disposed between the first surface of the semiconductor device and the first surface of the substrate. The second surface of the substrate is located in the substrate and external to a vertical projection of the semiconductor device on the first surface of the substrate.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: November 2, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ying-Xu Lu, Tang-Yuan Chen, Jin-Yuan Lai, Tse-Chuan Chou, Meng-Kai Shih, Shin-Luh Tarng
  • Patent number: 11158609
    Abstract: The present invention relates to a three-dimensional integrated package device for a high-voltage silicon carbide power module, comprising a source substrate, first chip submodules, a first driving terminal, a first driving substrate, a ceramic housing, a metal substrate, a water inlet, a water outlet, second chip submodules, a second driving terminal, a second driving substrate and a drain substrate from top to bottom; and each first chip submodule is composed of a driving connection substrate, a power source metal block, a first driving gate metal post, second driving gate metal posts, a silicon carbide bare chip, an insulation structure and the like. A three-dimensional integrated half-bridge structure is adopted to greatly reduce corresponding parasitic parameters.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: October 26, 2021
    Assignee: XI'AN JIAOTONG UNIVERSITY
    Inventors: Laili Wang, Xiaodong Hou, Cheng Zhao, Jianpeng Wang, Dingkun Ma, Chengzi Yang, Xu Yang
  • Patent number: 11150710
    Abstract: One embodiment is directed towards an encapsulated device. The encapsulated device includes a device, and a first encapsulation covering the device. The first encapsulation has one or more exterior surfaces. One or more recesses in one or more of the exterior surfaces is configured to receive a second encapsulation.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: October 19, 2021
    Assignee: Intersil Americas LLC
    Inventors: Randolph Cruz, Loyde M. Carpenter, Jr., Mark A. Kwoka
  • Patent number: 11139225
    Abstract: A device includes a die paddle and a plurality of leads. The leads surround the die paddle. Each of the leads includes an inner lead portion adjacent to and spaced apart from the die paddle, an outer lead portion opposite to the inner lead portion and a bridge portion between the inner lead portion and the outer lead portion. The inner lead portion has an upper bond section connected to the bridge portion and a lower support section below the upper bond section. A sum of a thickness of the upper bond section and a thickness of the lower support section is greater than a thickness of the bridge portion.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: October 5, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Kuang-Hsiung Chen, Chih-Hung Hsu, Mei-Lin Hsieh, Yi-Cheng Hsu, Yuan-Chun Chen, Yu-Shun Hsieh, Ko-Pu Wu
  • Patent number: 11133199
    Abstract: A semiconductor package is provided which addresses problems of mold cap heel cracking. The package may made by using a cavity die and a gate insertion tool. The gate insertion tool, which fits into the cavity die, has an elongated body and includes a nozzle head with an edge which is contoured in relation to a mold cap formed on a substrate. The edge defines a curved border, for the mold cap, from a plane above the substrate to a plane lying on the substrate. The nozzle head includes a slot, for admitting a cull runner tip, centered on an axis of the elongated body.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: September 28, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Manengway Bumal-o Bangaan, Rosil Pascual Siloy, Arvin Abellera Dela Cruz, Reynaldo Malandac Maniacup
  • Patent number: 11121004
    Abstract: A method for producing a power semiconductor module arrangement includes forming a pre-layer by depositing inorganic filler on a first surface within a housing, the inorganic filler being impermeable to corrosive gases. The method further includes filling casting material into the housing to fill spaces present in the inorganic filler of the pre-layer with the casting material, and hardening the casting material to form a first layer.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: September 14, 2021
    Assignee: Infineon Technologies AG
    Inventors: Gopalakrishnan Trichy Rengarajan, Sebastian Michalski
  • Patent number: 11120843
    Abstract: A memory device includes a first semiconductor chip including a memory cell array disposed on a first substrate, and a first bonding metal on a first uppermost metal layer of the first semiconductor chip, and a second semiconductor chip including circuit devices disposed on a second substrate and a second bonding metal on a second uppermost metal layer of the second semiconductor chip, the circuit devices providing a peripheral circuit operating the memory cell array. The first and second semiconductor chips are electrically connected to each other by the first bonding metal and the second bonding metal in a bonding area. A routing wire electrically connected to the peripheral circuit is disposed in one or both of the first and second uppermost metal layers and is disposed in a non-bonding area in which the first and second semiconductor chips are not electrically connected to each other.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: September 14, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jooyong Park, Chanho Kim, Daeseok Byeon
  • Patent number: 11107761
    Abstract: A semiconductor device may include a first conductive plate, a plurality of semiconductor chips disposed on the first conductive plate, and a first external connection terminal connected to the first conductive plate. The plurality of semiconductor chips may include first, second, and third semiconductor chips. The second semiconductor chip may be located between the first semiconductor chip and the third semiconductor chip. A portion of the first conductive plate where the first external connection terminal is connected may be closest to the second semiconductor chip among the first, second, and third semiconductor chips. The first conductive plate may be provided with an aperture located between the portion of the first conductive plate where the first external connection terminal is connected and a portion of the first conductive plate where the second semiconductor chip is connected.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: August 31, 2021
    Assignee: DENSO CORPORATION
    Inventor: Takanori Kawashima
  • Patent number: 11101242
    Abstract: A semiconductor device includes a substrate, a first semiconductor chip on the substrate, a first adhesive material on the first semiconductor chip, a spacer chip on the first adhesive material, a second adhesive material on the spacer chip, a second semiconductor chip on the second adhesive material, and a resin material that covers the first and second semiconductor chips and the spacer chip. The spacer chip has a first region with which the resin material comes in contact is roughened and a second region that is different from the first region.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: August 24, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yuichi Sano
  • Patent number: 11094616
    Abstract: In some examples, a system comprises a die having multiple electrical connectors extending from a surface of the die and a lead coupled to the multiple electrical connectors. The lead comprises a first conductive member; a first non-solder metal plating stacked on the first conductive member; an electroplated layer stacked on the first non-solder metal plating; a second non-solder metal plating stacked on the electroplated layer; and a second conductive member stacked on the second non-solder metal plating, the second conductive member being thinner than the first conductive member. The system also comprises a molding to at least partially encapsulate the die and the lead.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: August 17, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sreenivasan K. Koduri, Nazila Dadvand
  • Patent number: 11087058
    Abstract: Embodiments of systems and methods for an FIB-aware anti-probing physical design flow are described in the present disclosure. Such embodiments incorporate new and improved security-critical steps in a physical design flow, in which the design is constrained to provide coverage on asset nets through an internal shield.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: August 10, 2021
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Domenic J. Forte, Mark M. Tehranipoor, Qihang Shi, Huanyu Wang, Haoting Shen
  • Patent number: 11076485
    Abstract: A component mounting board includes first and second substrates, a connection substrate, an interposer, and an electronic component. The first substrate has first and second surfaces opposing each other, a first side surface between the first and second surfaces, and a first signal pattern. The second substrate is disposed on the first substrate, has third and fourth surfaces opposing each other and a second side surface between the third and fourth surfaces, and includes a second signal pattern. The connection substrate is bent to connect the first and second side surfaces, and the interposer is disposed between the first and third surfaces and electrically connects the first and second signal patterns. The electronic component is mounted on at least one of the first to fourth surfaces.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: July 27, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Tae Seong Kim, Yun Je Ji, Ho Kwon Yoon, Yong Hoon Kim
  • Patent number: 11069606
    Abstract: A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a solid state diffusion bonding is disclosed. A plurality of traces is formed on a substrate, each respective trace comprising at least four different conductive materials having different melting points and plastic deformation properties, which are optimized for both diffusion bonding of chips and soldering of passives components.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: July 20, 2021
    Assignee: Compass Technology Company Limited
    Inventors: Kelvin Po Leung Pun, Chee Wah Cheung
  • Patent number: 11069588
    Abstract: A semiconductor package includes a package substrate, at least one semiconductor chip mounted on the package substrate, and a molding member that surrounds the at least one semiconductor chip. The molding member includes fillers. Each of the fillers includes a core and a coating layer that surrounds the core. The core includes a non-electromagnetic material and the coating layer includes an electromagnetic material. The molding member includes regions respectively have different distributions of the fillers.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: July 20, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-young Oh, Hyun-ki Kim, Sang-soo Kim, Seung-hwan Kim, Yong-kwan Lee
  • Patent number: 11038279
    Abstract: An antenna module includes a connection member including at least one wiring layer and at least one insulating layer; an integrated circuit (IC) package disposed on a first surface of the connection member; and an antenna package including a plurality of antenna members and a plurality of feed vias, and disposed on a second surface of the connection member, wherein the IC package includes: an IC having an active surface electrically connected to at least one wiring layer and an inactive surface opposing the active surface, and generating the RF signal; a heat sink member disposed on the inactive surface of the IC; and an encapsulant encapsulating at least portions of the IC and the heat sink member.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: June 15, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo Il Kim, Jung Hyun Cho, Won Wook So, Young Sik Hur, Yong Ho Baek
  • Patent number: 11031353
    Abstract: A microelectronic device and/or microelectronic device package having a warpage control structure. The warpage control structure may be positioned over an encapsulating material, wherein the encapsulating material is positioned between the warpage control structure and a die positioned over a substrate. The warpage control structure may have a first thickness over a first portion of the encapsulating material and a second thickness over a second portion of the encapsulating material. Methods of forming the microelectronic device are also disclosed herein.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: June 8, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Christopher Glancey, Shams U. Arifeen
  • Patent number: 10982120
    Abstract: Conventionally, when an adherend is nickel or the like, it has been difficult to realize an electroconductive adhesive that lowers connection resistance in various kinds of thermocurable curing resins. However, it is possible to provide an electroconductive adhesive, in the case where the adherend is nickel or the like, which reduces connection resistance in various kinds of thermocurable curing resins while simultaneously maintaining storage stability to have good handleability. The present description provides a thermocurable electroconductive adhesive including the following components (A) to (D): Component (A): a curable resin, Component (B): a thermal curing agent that cures Component (A), Component (C): an organometallic complex, and Component (D): electroconductive particles.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: April 20, 2021
    Assignee: THREEBOND CO., LTD.
    Inventors: Soichi Ota, Hitoshi Mafune, Makoto Kato, Tomoya Kodama
  • Patent number: 10985147
    Abstract: A stiffener on a semiconductor package substrate includes a plurality of parts that are electrically coupled to the semiconductor package substrate on a die side. Both stiffener parts are electrically contacted through a passive device that is soldered between the two stiffener parts and by an electrically conductive adhesive that bonds a given stiffener part to the semiconductor package substrate. The passive device is embedded between two stiffener parts to create a smaller X-Y footprint as well as a lower Z-direction profile.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: April 20, 2021
    Assignee: Intel Corporation
    Inventors: Jenny Shio Yin Ong, Seok Ling Lim, Bok Eng Cheah, Jackson Chung Peng Kong, Chin Lee Kuan
  • Patent number: 10943858
    Abstract: A semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a thin fine-pitch redistribution structure.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: March 9, 2021
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Michael Kelly, David Hiner, Ronald Huemoeller, Roger St. Amand
  • Patent number: 10942110
    Abstract: A system and method for detecting particles in a fluidic medium using a microfluidic sensor is described. The system utilises microfluidic channels though which the fluidic medium is passed. On one section of the microfluidic channel, an array of non-flexible electrodes are coupled with uniform spacing therebetween. On the opposing section of the channel, a flexible electrode is coupled and all electrodes are connected to an electrical analyser which is used to generate an electrical field inside the microfluidic channel with the flexible electrode acting as ground. The flexible electrode is actuated by different means to narrow the width of the microfluidic in the section of interest and to capture the particle between the section, where sectional scans of the particles are obtained and electrical properties of the particle are measured, thereby detecting the particles in the fluidic medium.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: March 9, 2021
    Assignee: UNITED ARAB EMIRATES UNIVERSITY
    Inventor: Mahmoud F. Y. Al Ahmad
  • Patent number: 10930523
    Abstract: It is an object of the present invention to provide a method for manufacturing a resin-sealed power semiconductor device that facilitates the separation of a suspension lead from a mold resin and a lead frame. A method for manufacturing a resin-sealed power semiconductor device according to the present invention includes the following steps: (a) sealing a semiconductor element and a lead frame, to prepare a sealed body in which a terminal lead and a suspension lead that are included in the lead frame project outward from a side of the mold resin; (b) punching a portion of the suspension lead, the portion projecting from the mold resin, with a first punch in a first direction, to separate the suspension lead from the mold resin; and (c) punching the projecting portion of the suspension lead with a second punch in a second direction.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: February 23, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Keitaro Ichikawa, Ken Sakamoto, Kazuo Funahashi
  • Patent number: 10910588
    Abstract: A display device includes a substrate including an upper surface, a lower surface, and side surfaces; a display element layer on the upper surface overlapping the display area; an encapsulation layer on the upper surface, the encapsulation layer including a main part that overlaps the display element layer and a protruding part that protrudes along a first direction from the main part and overlaps the bezel area; an input sensor on the main part; a first circuit board facing the main part, overlapping the bezel area, and on the upper surface; and a second circuit board on the protruding part, wherein each of the first circuit board and the second circuit board is adjacent to a first side surface among the side surfaces, and in the first direction, the protruding part is more adjacent to the first side surface than the main part.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: February 2, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyoung-Joo Kim, Yunsoo Kim, Jun-Hee Lee, Cheollae Roh, Gyoowan Han
  • Patent number: 10903090
    Abstract: A method of forming a package structure includes the following processes. A die is attached to a polymer layer. An encapsulant is formed over the polymer layer to encapsulate sidewalls of the die. A RDL structure is formed on the encapsulant and the die. A conductive terminal is electrically connected to the die through the RDL structure. A light transmitting film is formed on the polymer layer. An alignment process is performed, and the alignment process uses an optical equipment to see through the light transmitting film to capture the alignment information included in the polymer layer. A singulating process is performed to singulate the package structure according to the alignment information.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: January 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Ting Chen, Ching-Hua Hsieh, Hsiu-Jen Lin, Hao-Jan Pei, Wei-Yu Chen, Chia-Lun Chang, Chia-Shen Cheng, Cheng-Shiuan Wong
  • Patent number: 10886694
    Abstract: A hermetic capsule including a semiconductor/metal base with sensitive semiconductor/polymer electrical and optical components formed thereon and a semiconductor/metal lid. The semiconductor/metal lid sealed to the semiconductor/metal base by metallization so as to form a chamber including all of the sensitive semiconductor/polymer electrical and optical components and hermetically sealing the chamber and all sensitive components from the ambient. External access to the sensitive semiconductor/polymer electrical and optical components is provided through a metallization.
    Type: Grant
    Filed: December 15, 2019
    Date of Patent: January 5, 2021
    Assignee: Lightwave Logic Inc.
    Inventor: Michael Lebby
  • Patent number: 10886255
    Abstract: A die stack structure may include a base die having base contact pads insulated by a base protection patterns and a flat side surface, a die stack bonded to the base die and having a plurality of component dies on the base die such that each of the component dies includes component contact pads insulated by a corresponding component protection pattern, and a residual mold unevenly arranged on a side surface of the die stack such that the component dies are attached to each other by the residual mold.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: January 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-Seok Hong, Ji-Hoon Kim, Tae-Hun Kim, Hyuek-Jae Lee, Ji-Hwan Hwang
  • Patent number: 10872848
    Abstract: An embodiment of a semiconductor package includes a leadframe and a mold compound partly encasing the leadframe so that leads protrude from the mold compound and at least two die pads have a surface at a first side of the leadframe which is not covered by the mold compound. A laser module is attached to the surface of the at least two die pads which is not covered by the mold compound. A driver die is attached to the leadframe at a second side of the leadframe opposite the first side so that the laser module and the driver die are disposed in a stacked arrangement, the driver die configured to control the laser module. The driver die is in direct electrical communication with the laser module only through the leadframe and any interconnects which attach the laser module and driver die to the leadframe.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: December 22, 2020
    Assignee: Infineon Technologies AG
    Inventors: Woon Yik Yong, Andreas Kucher, Chia-Yen Lee, Shao Ping Wan
  • Patent number: 10872853
    Abstract: A module with high reliability is provided by inhibiting occurrences of air bubbles caused with rise in flow resistance of resin when a sealing resin layer is formed using a die. A module includes a wiring board, components mounted over an upper face of the wiring board, and a sealing resin layer laminated over the upper face. On the upper face, the sealing resin layer includes a high-level region with a long distance from the upper face of the wiring board, a low-level region with a short distance from the upper face, and a level difference region. In a portion included in the wiring board and corresponding to the low-level region and the level difference region, a thin portion is formed so as to be thinner than the remaining portion and overlaps the low-level region at least partially in a plan view.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: December 22, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Issei Yamamoto
  • Patent number: 10868251
    Abstract: A method for fabricating an organic light emitting diode (OLED) display is provided. The fabricating method includes: forming a switch array layer on a base substrate; forming an organic light emitting display layer on the switch array layer; forming a thin film package layer on the organic light emitting display layer; and forming a superhydrophobic thin film on the thin film package layer using plasma chemical vapor deposition. The superhydrophobic thin film has a thickness smaller than a predetermined thickness.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: December 15, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Jing Wang, San Zhu
  • Patent number: 10847478
    Abstract: A method of forming an electronic device structure includes providing an electronic component having a first major surface, an opposing second major surface, a first edge surface, and an opposing second edge surface. A substrate having a substrate first major surface and an opposing substrate second major surface is provided. The second major surface of the first electronic component is placed proximate to the substrate first major surface and providing a conductive material adjacent the first edge surface of the first electronic component. The conductive material is exposed to an elevated temperature to reflow the conductive material to raise the first electronic component into an upright position such that the second edge surface is spaced further away from the substrate first major surface than the first edge surface. The method is suitable for providing electronic components, such as antenna, sensors, or optical devices in a vertical or on-edge.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: November 24, 2020
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventor: Shaun Bowers
  • Patent number: 10804196
    Abstract: An electronic component device includes an electronic component embedded in a resin structure and including a portion exposed on a first main surface of the resin structure, first wiring lines extending from the first main surface of the resin structure to the electronic component and electrically connected to the electronic component, second wiring lines on a side of a second main surface of the resin structure and electrically connected to respective connection electrodes that are electrically connected to the first wiring lines, and low-elastic modulus layers at a height position between the first wiring lines and the exposed portion of the electronic component in respective regions in which the first wiring lines straddle boundaries between the resin structure and the electronic component, having elastic moduli lower than those of the first wiring lines, and made of a conductive material.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: October 13, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takashi Iwamoto
  • Patent number: 10790208
    Abstract: Implementations of semiconductor packages may include: a semiconductor wafer, a glass lid fixedly coupled to a first side of the semiconductor die by an adhesive, a redistribution layer coupled to a second side of the semiconductor die, and a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer coupled to the semiconductor die. The adhesive may be located in a trench around a perimeter of the semiconductor die and located in a corresponding trench around a perimeter of the glass lid.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: September 29, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Yu-Te Hsieh
  • Patent number: 10763192
    Abstract: A method of attaching a semiconductor die or chip onto a support member such as a leadframe comprises: applying onto the support member at least one stretch of ribbon electrical bonding material and coupling the ribbon material to the support member, arranging at least one semiconductor die onto the ribbon material with the ribbon material between the support member and the semiconductor die, coupling the semiconductor die to the ribbon material.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: September 1, 2020
    Assignee: STMICROELECTRONICS S.r.l.
    Inventor: Dario Vitello
  • Patent number: 10727125
    Abstract: A bonding structure for a flexible screen and a manufacturing method are provided a flexible screen and a chip mounted on a surface of the flexible screen are arranged on the bonding structure for the flexible screen, and a bonding area for bonding the chip is arranged on the flexible screen, and a flexible protective layer is coated in the bonding area, and the flexible protective layer surrounds around the chip. Compared with the prior art, by forming the flexible protective layer with different hardness around the chip, the stress generated around the chip during the peeling-off are greatly dispersed, a stress gradient is formed, the stress concentration at the position closely adjacent to the periphery of the chip is avoided, the risk of the circuits around the chip being pulled broken can be reduced, and the peeling-off yield of the flexible screen can be finally increased.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: July 28, 2020
    Assignee: Kunshan New Flat Panel Display Technology Center Co., Ltd.
    Inventors: Xiuyu Zhang, Baoyou Wang, Pengle Dang, Liwei Ding, Xiaobao Zhang, Hui Zhu
  • Patent number: 10714404
    Abstract: A technique disclosed in the Description relates to a technique for improving the heat dissipation capability of a semiconductor element and the heat dissipation capability of a lead electrode without increasing the size of a product. A semiconductor device of the technique includes the following: a semiconductor element; a lead electrode having a lower surface connected to an upper surface of the semiconductor element at one end of the lead electrode, the lead electrode being an external terminal; a cooling mechanism disposed on a lower surface side of the semiconductor element; and a heat dissipation mechanism provided to be thermally joined between the lower surface of the lead electrode and the cooling mechanism, the lower surface being more adjacent to an other-end side of the lead electrode than the one end, the heat dissipation mechanism including at least one insulating layer.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: July 14, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ryoji Murai, Mitsunori Aiko, Takaaki Shirasawa
  • Patent number: 10692792
    Abstract: An electronic device includes an electronic component, a sealing resin body, and a plurality of conductive members electrically connected to the electronic component in the sealing resin body, including respective portions exposed from the sealing resin body to the outside of the sealing resin body, and having different potentials. The conductive members include a heat sink and a terminal extending from an inside to the outside of the sealing resin body. A surface of the terminal includes, as a part covered with the sealing resin body, a higher adhesion part and a lower adhesion part. The lower adhesion part is provided in an entire portion of a back surface of the terminal, the back surface being opposite to a connection surface of the terminal which is adjacent to a connection part electrically connected to the electronic component. The higher adhesion part is provided in the connection surface.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: June 23, 2020
    Assignee: DENSO CORPORATION
    Inventor: Hirohito Fujita
  • Patent number: 10690628
    Abstract: Individual biological micro-objects can be deterministically selected and moved into holding pens in a micro-fluidic device. A flow of a first liquid medium can be provided to the pens. Physical pens can be structured to impede a direct flow of the first medium into a second medium in the pens while allowing diffusive mixing of the first medium and the second medium. Virtual pens can allow a common flow of medium to multiple ones of the pens.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: June 23, 2020
    Assignee: Berkeley Lights, Inc
    Inventors: Kevin T. Chapman, Igor Y. Khandros, Gaetan L. Mathieu, J. Tanner Nevill, Ming C. Wu
  • Patent number: 10694633
    Abstract: A method of encapsulating a printed circuit board of a motor controller with a potting material includes inserting the printed circuit board into a recess formed in a base portion of an encapsulation assembly such that a bottom surface of the printed circuit board is spaced from a surface of the recess. The method also includes coupling a cover portion of the encapsulation assembly to the base portion to define a cavity therebetween. The method further includes injecting the potting material into the cavity through at least one injection port defined in at least one of the base portion and the cover portion such that the printed circuit board is at least partially coated in the potting material.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: June 23, 2020
    Assignee: REGAL BELOIT AMERICA, INC.
    Inventors: Maung Eddison, Zachary Joseph Stauffer, Mark A. Swiger, Luis D. Morales
  • Patent number: 10665509
    Abstract: A method for manufacturing chip package includes the steps below. A wafer having an upper surface and a lower surface opposite thereto is provided, in which conductive bumps are disposed on the upper surface. The upper surface of the wafer is diced to form trenches. A first insulation layer exposing the conductive bumps is formed on the upper surface and in the trenches. A surface treatment layer is formed on the conductive bumps, and a top surface of the surface treatment layer is higher than that of the first insulation layer. The wafer is thinned from the lower surface toward the upper surface to expose the first insulation layer in the trenches. A second insulation layer is formed below the lower surface. The first and second insulation layers are diced along a center of each trench to form chip packages.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: May 26, 2020
    Assignee: COMCHIP TECHNOLOGY CO., LTD.
    Inventors: Chien-Chih Lai, Hung-Wen Lin