Encapsulated Patents (Class 257/787)
  • Patent number: 10332965
    Abstract: A semiconductor device includes a plurality of fins. Each of the fins has a multi-layer stack comprising a first nanowire and a second nanowire. A first portion of the first nanowire and second nanowire are doped to form source and drain regions. An epitaxial layer wraps around the first portion of first nanowire and second nanowire over the source and drain region. A gate is disposed over a second portion of the first nanowire and second nanowire. The epitaxial layer is interposed in between the first nanowire and the second nanowire over the source and drain region. The epitaxial layer has a zig-zag contour.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: June 25, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Martin Christopher Holland, Mark Van Dal, Georgios Vellianitis, Blandine Duriez, Gerben Doornbos
  • Patent number: 10325877
    Abstract: In a vertically integrated microelectronic package, a first microelectronic device is coupled to an upper surface of a circuit platform in a wire bond-only surface area thereof. Wire bond wires are coupled to and extends away from an upper surface of the first microelectronic device. A second microelectronic device in a face-down orientation is coupled to upper ends of the wire bond wires in a surface mount-only area. The second microelectronic device is located above and at least partially overlaps the first microelectronic device. A protective layer is disposed over the circuit platform and the first microelectronic device. An upper surface of the protective layer has the surface mount-only area. The upper surface of the protective layer has the second microelectronic device disposed thereon in the face-down orientation in the surface mount-only area for coupling to the upper ends of the first wire bond wires.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: June 18, 2019
    Assignee: Invensas Corporation
    Inventors: Javier A. Delacruz, Abiola Awujoola, Ashok S. Prabhu, Christopher W. Lattin, Zhuowen Sun
  • Patent number: 10316135
    Abstract: Four conjugated copolymers with a donor/acceptor architecture including 4,4-dihexadecyl-4H-cyclopenta[1,2-b:5,4-b?]dithiophene as the donor structural unit and benzo[2,1,3]thiodiazole fragments with varying degrees of fluorination have been synthesized and characterized. It has been shown that the HOMO levels were decreased after the fluorine substitution. The field-effect charge carrier mobility was similar for all polymers with less than an order of magnitude difference between different acceptor units.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: June 11, 2019
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Ming Wang, Guillermo C. Bazan
  • Patent number: 10276463
    Abstract: A semiconductor device includes a substrate with a recess subsiding from a selected surface of the substrate to accommodate a semiconductor element. Connected to the semiconductor element, an electroconductive portion extends from the recess onto the selected surface. A post, formed at the selected surface, has a first surface in contact with the electroconductive portion, a second surface, and a side surface between the first and second surfaces. A sealing resin covers the side surface of the post and the semiconductor element, and has a mounting surface facing in the same direction as the selected surface of the substrate. A pad, on the mounting surface of the sealing resin, is in contact with the second surface of the post. In the thickness direction, the second surface of the post is offset from the mounting surface of the sealing resin toward the selected surface of the substrate.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: April 30, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Hideaki Yanagida
  • Patent number: 10264674
    Abstract: A passive element array includes an element body that includes laminated base material layers, passive elements at different positions in the element body when viewed from a lamination direction of the base material layers, input/output terminals at a first main surface of the element body and connected to one end of each of the passive elements, input/output terminals at a second main surface of the element body and connected to the other end of each of the passive elements, a first ground terminal between the first input/output terminal and the input/output terminal at the first main surface, and a second ground terminal between the input/output terminal and the input/output terminal at the second main surface.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: April 16, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Keito Yonemori, Hirokazu Yazaki
  • Patent number: 10264710
    Abstract: In an embodiment, thermal conductive material within a device having electrical component is described. In an embodiment, a device is disclosed comprising: a printed circuit board comprising electrical components; a housing of the device, wherein the housing substantially encloses the printed circuit board; a thermal conductive material coated on the printed circuit board, wherein the thermal conductive material is configured to coat an interface between an electrical component and the printed circuit board, and wherein the thermal conductive material is located between the printed circuit board and a portion of the housing according to both a three dimensional topography of the printed circuit board and a three dimensional shape of the portion of the housing.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: April 16, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Juha Erkki Antero Penttinen
  • Patent number: 10242924
    Abstract: A base-attached encapsulant for semiconductor encapsulation is used for collectively encapsulating a device-mounted surface of the semiconductor device-mounted substrate having semiconductor devices mounted thereon or a device-formed surface of a semiconductor device-formed wafer having semiconductor devices formed thereon. The base-attached encapsulant has a base and an encapsulating resin layer containing an uncured or semi-cured thermosetting resin component formed onto one of the surfaces of the base, and a linear expansion coefficient ?1 of the semiconductor device to be encapsulated by the base-attached encapsulant, a linear expansion coefficient ?2 of a cured product of the encapsulating resin layer, and a linear expansion coefficient ?3 of the base satisfy both of the following formula (1) and (2); ?1<?3<?2??(1) ?2<?1+?2?2?3<2??(2) wherein the unit of the linear expansion coefficient is ppm/K.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: March 26, 2019
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Tomoaki Nakamura, Hideki Akiba, Toshio Shiobara
  • Patent number: 10230028
    Abstract: A semiconductor light emitting device includes a substrate made of resin, a first wiring and a second wiring formed on the substrate, a light emitting element disposed on the substrate and electrically connected to the first wiring and the second wiring, and a transparent sealing resin configured to seal the light emitting element. The substrate contains an acrylic resin, and the sealing resin contains silicon.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: March 12, 2019
    Assignee: Rohm Co., Ltd.
    Inventors: Hirotaka Obuchi, Junichi Itai
  • Patent number: 10224584
    Abstract: An exemplary battery pack heat exchanger includes a wall of an enclosure, and a heat exchanger lid held against the wall to provide a chamber that receives a fluid to exchange thermal energy with a battery array that is outside of the chamber. An exemplary method of managing battery pack thermal energy includes moving a fluid through a chamber within an enclosure wall of a battery pack to adjust thermal energy levels of the battery pack.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: March 5, 2019
    Assignee: Ford Global Technologies, LLC
    Inventors: Dave Moschet, Rajaram Subramanian, Sai K. Perumalla, Saravanan Paramasivam
  • Patent number: 10199299
    Abstract: Mold compound transfer systems and methods for making mold compound transfer systems are disclosed herein. A method configured in accordance with a particular embodiment includes placing a sheet mold compound in a containment area defined by a tray cover, and dispensing a granular mold compound over the sheet mold compound. The sheet mold compound can have a first density and the overall granular mold compound can have a second density less than the first density. The method further comprises transferring the solid sheet carrying the dispensed grains to a molding machine without using a release film.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: February 5, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kean Tat Koh, Lien Wah Choong
  • Patent number: 10163765
    Abstract: A semiconductor device includes a semiconductor chip having a terminal thereon, a lead frame for connection to an external device, a bonding wire connecting the terminal of the semiconductor chip and the lead frame. A mold resin layer encloses the semiconductor chip and the bonding wire, such that a portion of the lead frame extends out of the mold resin layer. A molecular bonding layer has a portion on a surface of the bonding wire and includes a first molecular portion covalently bonded to a material of the bonding wire and a material of the mold resin layer.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: December 25, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihiko Happoya
  • Patent number: 10162111
    Abstract: An hermetically sealed monolithic photonic integrated circuit (PIC) including optical components and multiple optical and electrical inputs/outputs. The integrated circuit including a semiconductor/metal base with sensitive semiconductor/polymer electrical and optical components formed therein. The electrical and optical components having multiple optical and electrical inputs, multiple optical and electrical outputs, and/or multiple optical and electrical inputs and outputs. A semiconductor/metal basic lid is sealed to the semiconductor/metal base by metallization so as to form a chamber including the sensitive semiconductor/polymer electrical and optical components and hermetically sealing the chamber and the sensitive components from the ambient in a basic hermetic capsule with multiple optical pathways coupling multiple optical fibers to the optical components sealed within the chamber.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: December 25, 2018
    Assignee: Lightwave Logic Inc.
    Inventor: Michael Lebby
  • Patent number: 10128131
    Abstract: A sealing sheet with separators on both surfaces is provided with a sealing sheet, a separator (A) stacked on one surface of the sealing sheet and having a thickness of 50 ?m or more, and a separator (B) stacked on the other surface of the sealing sheet.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: November 13, 2018
    Assignee: NITTO DENKO CORPORATION
    Inventors: Goji Shiga, Tsuyoshi Ishizaka, Kosuke Morita, Chie Iino
  • Patent number: 10104767
    Abstract: A printed circuit board includes: a strip substrate sectioned into unit areas; electronic components respectively installed in each of the unit areas; and a separation space disposed between the unit areas.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: October 16, 2018
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hyung-Gi Ha, Jong-Myeon Lee, Jong-Rip Kim
  • Patent number: 10090237
    Abstract: A semiconductor device includes a die pad, a semiconductor chip with a bonding pad being formed, a lead one end of which is located in the vicinity of the semiconductor chip, a coupling wire that connects an electrode and the lead, and a sealing body that seals the semiconductor chip, the coupling wire, a part of the lead, and a part of the die pad. A lower surface of the die pad is exposed from a lower surface of the sealing body, the die pad and the coupling wire are comprised of copper, and a thickness of the semiconductor chip is larger than the sum of a thickness of the die pad and a thickness from an upper surface of the semiconductor chip to an upper surface of the sealing body.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: October 2, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshihiko Shimanuki
  • Patent number: 10084125
    Abstract: An electronic component includes a substrate a functional section provided on the substrate, and a sealing body which is provided on the substrate and seals the functional section. In a temperature region having a lowest temperature that is at least as high as the glass transition temperature of the sealing body, the coefficient of linear expansion of the sealing body is greater than the coefficient of linear expansion of the substrate. In a temperature region having a highest temperature that is lower than the glass transition temperature of the sealing body, the coefficient of linear expansion of the sealing body is less than the coefficient of linear expansion of the substrate. The electronic component exhibits superior reliability even upon prolonged use.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: September 25, 2018
    Assignee: SKYWORKS FILTER SOLUTIONS JAPAN CO., LTD.
    Inventors: Hidenori Uematsu, Tomohiro Fujita, Ichiro Kameyama, Tetsuya Furihata, Fuyuki Abe, Kazunori Nishimura
  • Patent number: 10056349
    Abstract: A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method for manufacturing a semiconductor device that comprises ordering and performing processing steps in a manner that prevents warpage deformation from occurring to a wafer and/or die due to mismatching thermal coefficients.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: August 21, 2018
    Assignee: Amkor Technology, Inc.
    Inventors: Yeong Beom Ko, Jin Han Kim, Dong Jin Kim, Do Hyung Kim, Glenn Rinne
  • Patent number: 10020206
    Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: July 10, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Thomas Scott Morris, David Jandzinski, Stephen Parker, Jon Chadwick, Julio C. Costa
  • Patent number: 9997376
    Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: June 12, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Thomas Scott Morris, David Jandzinski, Stephen Parker, Jon Chadwick, Julio C. Costa
  • Patent number: 9984992
    Abstract: In a vertically integrated microelectronic package, a first microelectronic device is coupled to an upper surface of a circuit platform in a wire bond-only surface area thereof. Wire bond wires are coupled to and extends away from an upper surface of the first microelectronic device. A second microelectronic device in a face-down orientation is coupled to upper ends of the wire bond wires in a surface mount-only area. The second microelectronic device is located above and at least partially overlaps the first microelectronic device. A protective layer is disposed over the circuit platform and the first microelectronic device. An upper surface of the protective layer has the surface mount-only area. The upper surface of the protective layer has the second microelectronic device disposed thereon in the face-down orientation in the surface mount-only area for coupling to the upper ends of the first wire bond wires.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: May 29, 2018
    Assignee: Invensas Corporation
    Inventors: Javier A. DeLaCruz, Abiola Awujoola, Ashok S. Prabhu, Christopher W. Lattin, Zhuowen Sun
  • Patent number: 9972576
    Abstract: The semiconductor chip package comprises a semiconductor chip, and an encapsulation body encapsulating the semiconductor chip, wherein the encapsulation body comprises a semiconductor chip; an encapsulation body encapsulating the semiconductor chip, wherein the encapsulation body comprises two opposing main faces and side faces which connect the two main faces with each other, wherein the side face have a smaller surface area than the main faces, respectively, and wherein a marking is provided on at least one of the side faces.
    Type: Grant
    Filed: November 24, 2016
    Date of Patent: May 15, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Teck Sim Lee, Amirul Afiq Hud, Fabian Schnoy, Felix Grawert, Uwe Kirchner, Bernd Schmoelzer, Franz Stueckler
  • Patent number: 9960054
    Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: May 1, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Thomas Scott Morris, David Jandzinski, Stephen Parker, Jon Chadwick, Julio C. Costa
  • Patent number: 9947552
    Abstract: Structures and formation methods of a chip package are provided. The method includes forming multiple conductive structures over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes disposing a mold over the carrier substrate. The method further includes forming a protection layer between the mold and the carrier substrate to surround the semiconductor die and the conductive structures. In addition, the method includes removing the mold.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: April 17, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shing-Chao Chen, Chih-Wei Lin, Meng-Tse Chen, Hui-Min Huang, Ming-Da Cheng, Kuo-Lung Pan, Wei-Sen Chang, Tin-Hao Kuo, Hao-Yi Tsai
  • Patent number: 9929078
    Abstract: A semiconductor package structure includes a conductive structure, at least two semiconductor elements and an encapsulant. The conductive structure has a first surface and a second surface opposite the first surface. The semiconductor elements are disposed on and electrically connected to the first surface of the conductive structure. The encapsulant covers the semiconductor elements and the first surface of the conductive structure. The encapsulant has a width ‘L’ and defines at least one notch portion. A minimum distance ‘d’ is between a bottom surface of the notch portion and the second surface of the conductive structure. The encapsulant has a Young's modulus ‘E’ and a rupture strength ‘Sr’, and L/(K×d)>E/Sr, wherein ‘K’ is a stress concentration factor with a value of greater than 1.2.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: March 27, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen-Long Lu, Chi-Chang Lee, Wei-Min Hsiao, Yuan-Feng Chiang
  • Patent number: 9929024
    Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: March 27, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Thomas Scott Morris, David Jandzinski, Stephen Parker, Jon Chadwick, Julio C. Costa
  • Patent number: 9917039
    Abstract: A method of forming a packaged semiconductor device includes providing a conductive frame structure. The conductive frame structure includes a first frame having leadfingers configured for directly attaching to a semiconductor device, such as an integrated power semiconductor device that includes both power devices and logic type devices. The leadfingers are further configured to provide high current capacity and a high thermal dissipation capacity for the power device portion of the semiconductor device. In one embodiment, the conductive frame structure further includes a second frame joined to the first frame. The second frame includes a plurality of leads configured to electrically connect to low power device portions of the semiconductor device. A package body is formed to encapsulate the semiconductor device and at least portions of the leadfingers and leads.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: March 13, 2018
    Assignee: Amkor Technology, Inc.
    Inventors: Marc Alan Mangrum, Thinh Van Pham
  • Patent number: 9892937
    Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: February 13, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Thomas Scott Morris, David Jandzinski, Stephen Parker, Jon Chadwick, Julio C. Costa
  • Patent number: 9887104
    Abstract: Some embodiments relate to an electronic package. The electronic package includes a substrate and a die attached to the substrate. The electronic package further includes an underfill positioned between the die and the substrate due to capillary action. A support surrounds the die. The support provides the same beneficial fillet geometry on all die edges. Therefore, the support provides similar stress reduction on all die edges. Other embodiments relate to method of fabricating an electronic package. The method includes attaching a die to a substrate and inserting an underfill between the die and the substrate using capillary action. The method further includes placing a support around the die such that the support surrounds the die.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: February 6, 2018
    Assignee: Intel Corporation
    Inventors: Manish Dubey, Rajendra C. Dias, Patrick Nardi, David Woodhams
  • Patent number: 9859132
    Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: January 2, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Thomas Scott Morris, David Jandzinski, Stephen Parker, Jon Chadwick, Julio C. Costa
  • Patent number: 9859196
    Abstract: An electronic device may include leads, an IC having first and second bond pads, and an encapsulation material adjacent the leads and the IC so the leads extend to a bottom surface of the encapsulation material defining first contact pads. The electronic device may include bond wires between the first bond pads and corresponding ones of the leads, and conductors extending from corresponding ones of the second bond pads to the bottom surface of the encapsulation material defining second contact pads.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: January 2, 2018
    Assignee: STMICROELECTRONICS (SHENZHEN) R&D CO., LTD.
    Inventor: Jing-En Luan
  • Patent number: 9847269
    Abstract: An embodiment a device package includes a semiconductor die, a molding compound extending along sidewalls of the semiconductor die, and a planarizing polymer layer over the molding compound and extending along the sidewalls of the semiconductor die. The molding compound includes first fillers, and the planarizing polymer layer includes second fillers smaller than the first fillers. The device package further includes one or more fan-out redistribution layers (RDLs) electrically connected to the semiconductor die, wherein the one or more fan-out RDLs extend past edges of the semiconductor die onto a top surface of the planarizing polymer layer.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: December 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Jeffrey Chang, Chun-Hsing Su, Tsei-Chung Fu, Yi-Chao Mao
  • Patent number: 9817079
    Abstract: A molded sensor package includes a leadframe having a sensor die attached to the leadframe, a magnet aligned with the sensor die and a single molding compound encasing the sensor die and attaching the magnet to the leadframe. A method of manufacturing the molded sensor package includes loading the magnet and the leadframe into a molding tool so that the magnet is aligned with the sensor die in the molding tool, molding the magnet and the sensor die with the same molding compound while loaded in the molding tool and curing the molding compound so that the magnet is attached to the leadframe by the same molding compound that encases the sensor die.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: November 14, 2017
    Assignee: Infineon Technologies AG
    Inventors: Choo Tian Ooi, Chew Theng Tai, Klaus Elian, Mohd Hirzarul Hafiz Mohd Tahir
  • Patent number: 9812388
    Abstract: A semiconductor device includes a die pad, a semiconductor chip with a bonding pad being formed, a lead one end of which is located in the vicinity of the semiconductor chip, a coupling wire that connects an electrode and the lead, and a sealing body that seals the semiconductor chip, the coupling wire, a part of the lead, and a part of the die pad. A lower surface of the die pad is exposed from a lower surface of the sealing body, the die pad and the coupling wire are comprised of copper, and a thickness of the semiconductor chip is larger than the sum of a thickness of the die pad and a thickness from an upper surface of the semiconductor chip to an upper surface of the sealing body.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: November 7, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshihiko Shimanuki
  • Patent number: 9806133
    Abstract: An organic light emitting diode (OLED) display includes a substrate, a thin film transistor (TFT) on the substrate, an OLED connected to the TFT and configured to emit white light, and a capping layer on the OLED. The capping layer includes a first high refractive index layer, a first low refractive index layer, a second high refractive index layer, and a second low refractive index layer that are sequentially stacked.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: October 31, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Nam Su Kang, Ji-Hye Shim
  • Patent number: 9806066
    Abstract: A semiconductor package includes a substrate comprising a chip area and a peripheral area, at least one semiconductor chip mounted on the chip area, a plurality of stubs respectively on a plurality of pads arranged in the peripheral area, and a molding unit configured to cover at least a partial area of the at least one semiconductor chip and at least a partial area of the plurality of stubs on the substrate while exposing an upper surface of at least one of the plurality of stubs to outside of the molding unit, wherein at least a partial area of the upper surface of at least one of the plurality of stubs is substantially flat.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: October 31, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Maohua Du
  • Patent number: 9793106
    Abstract: It has been discovered that poor TDDB reliability of microelectronic device capacitors with organic polymer material in the capacitor dielectric is due to water molecules infiltrating the organic polymer material when the microelectronic device is exposed to water vapor in the operating ambient. Water molecule infiltration from water vapor in the ambient is effectively reduced by a moisture barrier comprising a layer of aluminum oxide formed by an atomic layer deposition (ALD) process. A microelectronic device includes a capacitor with organic polymer material in the capacitor dielectric and a moisture barrier with a layer of aluminum oxide formed by an ALD process.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: October 17, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Honglin Guo, Tim A. Taylor, Jeff A. West, Ricky A. Jackson, Byron Williams
  • Patent number: 9761510
    Abstract: A chip package including a first device substrate is provided. The first device substrate is attached to a first surface of a second device substrate. A third device substrate is attached to a second surface of the second device substrate opposite to the first surface. An insulating layer covers the first, second and third device substrates and has at least one opening therein. At least one bump is disposed under a bottom of the opening. A redistribution layer is disposed on the insulating layer and electrically connected to the bump through the opening. A method for forming the chip package is also provided.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: September 12, 2017
    Assignee: XINTEC INC.
    Inventor: Chien-Hung Liu
  • Patent number: 9721906
    Abstract: An electronic package that includes a substrate and a die attached to the substrate. A plurality of supports attached to the substrate adjacent to the die. At least one support in the plurality of supports is positioned adjacent to at least one corner of the die such that the at least one corner of the die is positioned adjacent to the at least one support. Other example forms relate to a method of fabricating an electronic package. The method includes securing a die to a substrate and securing a plurality of supports to the substrate such that at least one support is adjacent to at least one corner of the die.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: August 1, 2017
    Assignee: Intel Corporation
    Inventors: Manish Dubey, Rajendra C. Dias, Baris Bicen, Digvijay Raorane, Bharat P. Penmecha
  • Patent number: 9721874
    Abstract: Pre-encapsulated lead frames suitable for use in microelectronic device packages are disclosed. Individual lead frames can include a set of multiple lead fingers arranged side by side with neighboring lead fingers spaced apart from each other by a corresponding gap. An encapsulating compound at least partially encapsulates the set of lead fingers without encapsulating a microelectronic device. The encapsulating compound can generally fill the plurality of gaps between two adjacent lead fingers.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: August 1, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Ai Chie Wang, Choon Kuan Lee, Chin Hui Chong, Wuu Yean Tay
  • Patent number: 9704090
    Abstract: A package structure includes a first member that surrounds a semiconductor device, a heat insulating material that surrounds an outer side of the first member, and a second member that surrounds an outer side of the head insulating material. The heat insulating material has a density and a thermal conductivity lower than those of the first and second members. The first member has a heat capacity larger than that of the second member.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: July 11, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Hiroyasu Kawano, Kazuyuki Ozaki
  • Patent number: 9683278
    Abstract: A method includes providing a first and a second joining partner each having a first main surface, wherein at least a portion of the first main surfaces of the first and joining partners each comprise a metal layer. The method further includes applying a plurality of solder preforms to the metal layer of the first main surface of at least one of the first and second joining partners, positioning the first and second joining partners so that the solder preforms contact the metal layers of the first main surfaces of the first and second joining partners, and melting the plurality of solder preforms under pressure to form a single continuous thin layer area interconnect comprising a diffusion solder bond which bonds together the metal layers of the of the first main surfaces of the first and second joining partners.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: June 20, 2017
    Assignee: Infineon Technologies AG
    Inventors: Alexander Heinrich, Bernd Rakow
  • Patent number: 9666519
    Abstract: A power semiconductor module includes: a plurality of semiconductor element substrates disposed on the same plane, each of which includes an insulating substrate with a front-side electrode formed on one of the surfaces of an insulator plate and a back-side electrode formed on the other surface of the insulator plate and a power semiconductor element fixed on a surface of the front-side electrode; and a wiring member that electrically connects with each other the semiconductor element substrates adjacent to each other; and the semiconductor element substrates and the wiring member are molded with mold resin; wherein the mold resin is provided with a recessed part, between the insulating substrates adjacent to each other, which is not filled with the resin constituting the mold resin to a predetermined depth from the side of the back-side electrode.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: May 30, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventor: Shinnosuke Soda
  • Patent number: 9666395
    Abstract: Provided is a power semiconductor module wherein stress generated at a soldering section of a relay terminal is relaxed. A power semiconductor module (1) is provided with a substrate (2), relay terminals (9, 10), external connecting terminals (13, 14) and a relay terminal holding member (6). The relay terminals (9, 10) are connected to the substrate (2) with a solder (4) therebetween. The external connecting terminals (13, 14) are bonded to the relay terminals (9, 10), respectively. The non-conductive relay terminal holding member (6) holds end portions of the relay terminals (9, 10) said end portions being on the side bonded to the solder (4).
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: May 30, 2017
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Shinjiro Watari, Shuichi Kokubun, Takeshi Yamada, Tsuyoshi Harada
  • Patent number: 9651513
    Abstract: It will be understood by those skilled in the art that there is disclosed in the present application a biometric sensor that may comprise a plurality of a first type of signal traces formed on a first surface of a first layer of a multi-layer laminate package; at least one trace of a second type, formed on a second surface of the first layer or on a first surface of a second layer of the multi-layer laminate package; and connection vias in at least the first layer electrically connecting the signal traces of the first type or the signal traces of the second type to respective circuitry of the respective first or second type contained in an integrated circuit physically and electrically connected to one of the first layer, the second layer or a third layer of the multi-layer laminate package.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: May 16, 2017
    Assignee: Synaptics Incorporated
    Inventors: Brett Dunlap, Paul Wickboldt
  • Patent number: 9607907
    Abstract: A picking-up and placement process for electronic devices comprising: (a) providing a first substrate having a plurality of electronic devices formed thereon, the electronic devices being arranged in an array, and each of the electronic devices comprising a magnetic portion; (b) selectively picking-up parts of the electronic devices from the first substrate via a magnetic force generated from an electric-programmable magnetic module; and (c) bonding the parts of the electronic devices picked-up by the electric-programmable magnetic module with a second substrate.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: March 28, 2017
    Assignees: Industrial Technology Research Institute, PlayNitride Inc.
    Inventors: Ming-Hsien Wu, Yen-Hsiang Fang, Chia-Hsin Chao
  • Patent number: 9570632
    Abstract: A method of manufacturing an optical apparatus is provided. The method includes arranging a photo device above a substrate with an adhesive located between the photo device and the substrate, forming a bonding member that bonds the substrate and the photo device by curing the adhesive, and arranging, above the photo device, a transparent plate and a sealing member. The sealing member covers the photo device and is located between the transparent plate and the substrate. An elastic modulus of the bonding member is 1 GPa or less.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: February 14, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Takashi Miyake
  • Patent number: 9524884
    Abstract: A method of fabricating a semiconductor package includes mounting a plurality of semiconductor devices on a substrate; forming a molding member that covers a top surface of the substrate, top surfaces of the semiconductor devices, and sidewall surfaces of the semiconductor devices; sawing the molding member and the substrate along pre-scribing lines of the substrate; and spraying a metallic epoxy material on the sawn molding members using a sprayer to form an antistatic layer on sidewall surfaces and a top surface of each of the sawn molding members.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: December 20, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Cheol-soo Han
  • Patent number: 9520374
    Abstract: The semiconductor device can prevent damages on a semiconductor chip even when a soldering material is used for bonding the back surface of the semiconductor chip to the junction plane of a chip junction portion such as an island or a die pad. This semiconductor device includes a semiconductor chip and a chip junction portion having a junction plane that is bonded to the back surface of the semiconductor chip with a soldering material. The junction plane is smaller in size than the back surface of the semiconductor chip. This semiconductor device may further include a plurality of extending portions which extend respectively from the periphery of the junction plane to directions parallel with the junction plane.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: December 13, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Yasumasa Kasuya, Motoharu Haga, Hiroaki Matsubara
  • Patent number: 9484331
    Abstract: A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise forming a back end of line layer on a dummy substrate, completing at least a first portion of an assembly, and removing the dummy substrate.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: November 1, 2016
    Inventors: Jong Sik Paek, Doo Hyun Park
  • Patent number: 9472481
    Abstract: A chip includes a semiconductor substrate, an electrical connector over the semiconductor substrate, and a molding compound molding a lower part of the electrical connector therein. A top surface of the molding compound is lower than a top end of the electrical connector. A recess extends from the top surface of the molding compound into the molding compound.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: October 18, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chun-Hung Lin