Encapsulated Patents (Class 257/787)
  • Patent number: 10727125
    Abstract: A bonding structure for a flexible screen and a manufacturing method are provided a flexible screen and a chip mounted on a surface of the flexible screen are arranged on the bonding structure for the flexible screen, and a bonding area for bonding the chip is arranged on the flexible screen, and a flexible protective layer is coated in the bonding area, and the flexible protective layer surrounds around the chip. Compared with the prior art, by forming the flexible protective layer with different hardness around the chip, the stress generated around the chip during the peeling-off are greatly dispersed, a stress gradient is formed, the stress concentration at the position closely adjacent to the periphery of the chip is avoided, the risk of the circuits around the chip being pulled broken can be reduced, and the peeling-off yield of the flexible screen can be finally increased.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: July 28, 2020
    Assignee: Kunshan New Flat Panel Display Technology Center Co., Ltd.
    Inventors: Xiuyu Zhang, Baoyou Wang, Pengle Dang, Liwei Ding, Xiaobao Zhang, Hui Zhu
  • Patent number: 10714404
    Abstract: A technique disclosed in the Description relates to a technique for improving the heat dissipation capability of a semiconductor element and the heat dissipation capability of a lead electrode without increasing the size of a product. A semiconductor device of the technique includes the following: a semiconductor element; a lead electrode having a lower surface connected to an upper surface of the semiconductor element at one end of the lead electrode, the lead electrode being an external terminal; a cooling mechanism disposed on a lower surface side of the semiconductor element; and a heat dissipation mechanism provided to be thermally joined between the lower surface of the lead electrode and the cooling mechanism, the lower surface being more adjacent to an other-end side of the lead electrode than the one end, the heat dissipation mechanism including at least one insulating layer.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: July 14, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ryoji Murai, Mitsunori Aiko, Takaaki Shirasawa
  • Patent number: 10690628
    Abstract: Individual biological micro-objects can be deterministically selected and moved into holding pens in a micro-fluidic device. A flow of a first liquid medium can be provided to the pens. Physical pens can be structured to impede a direct flow of the first medium into a second medium in the pens while allowing diffusive mixing of the first medium and the second medium. Virtual pens can allow a common flow of medium to multiple ones of the pens.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: June 23, 2020
    Assignee: Berkeley Lights, Inc
    Inventors: Kevin T. Chapman, Igor Y. Khandros, Gaetan L. Mathieu, J. Tanner Nevill, Ming C. Wu
  • Patent number: 10692792
    Abstract: An electronic device includes an electronic component, a sealing resin body, and a plurality of conductive members electrically connected to the electronic component in the sealing resin body, including respective portions exposed from the sealing resin body to the outside of the sealing resin body, and having different potentials. The conductive members include a heat sink and a terminal extending from an inside to the outside of the sealing resin body. A surface of the terminal includes, as a part covered with the sealing resin body, a higher adhesion part and a lower adhesion part. The lower adhesion part is provided in an entire portion of a back surface of the terminal, the back surface being opposite to a connection surface of the terminal which is adjacent to a connection part electrically connected to the electronic component. The higher adhesion part is provided in the connection surface.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: June 23, 2020
    Assignee: DENSO CORPORATION
    Inventor: Hirohito Fujita
  • Patent number: 10694633
    Abstract: A method of encapsulating a printed circuit board of a motor controller with a potting material includes inserting the printed circuit board into a recess formed in a base portion of an encapsulation assembly such that a bottom surface of the printed circuit board is spaced from a surface of the recess. The method also includes coupling a cover portion of the encapsulation assembly to the base portion to define a cavity therebetween. The method further includes injecting the potting material into the cavity through at least one injection port defined in at least one of the base portion and the cover portion such that the printed circuit board is at least partially coated in the potting material.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: June 23, 2020
    Assignee: REGAL BELOIT AMERICA, INC.
    Inventors: Maung Eddison, Zachary Joseph Stauffer, Mark A. Swiger, Luis D. Morales
  • Patent number: 10663142
    Abstract: A light-emitting device may include a ceramic substrate having a reflective component, a light-emitting diode on the ceramic substrate, and a light-converting material over the light-emitting diode. A lighting system may include a ceramic substrate having a reflective component, a plurality of light-emitting diodes connected together in series, wherein the plurality of light-emitting diodes are on the ceramic substrate, and a light-converting material over the plurality of light-emitting diodes. The ceramic substrate may provide electrical insulation between the light-emitting diode and the aluminum carrier. The ceramic substrate may provide thermal conductivity between the light-emitting diode and the aluminum carrier. The reflective component may include zirconium oxide. The ceramic substrate may include aluminum oxide and/or aluminum nitride. The light-converting material may include phosphor. The light-emitting diode may have an epitaxial diode structure.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: May 26, 2020
    Assignee: BRIDGELUX INC.
    Inventors: Jesus Del Castillo, Scott West, Vladimir Odnoblyudov
  • Patent number: 10665509
    Abstract: A method for manufacturing chip package includes the steps below. A wafer having an upper surface and a lower surface opposite thereto is provided, in which conductive bumps are disposed on the upper surface. The upper surface of the wafer is diced to form trenches. A first insulation layer exposing the conductive bumps is formed on the upper surface and in the trenches. A surface treatment layer is formed on the conductive bumps, and a top surface of the surface treatment layer is higher than that of the first insulation layer. The wafer is thinned from the lower surface toward the upper surface to expose the first insulation layer in the trenches. A second insulation layer is formed below the lower surface. The first and second insulation layers are diced along a center of each trench to form chip packages.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: May 26, 2020
    Assignee: COMCHIP TECHNOLOGY CO., LTD.
    Inventors: Chien-Chih Lai, Hung-Wen Lin
  • Patent number: 10665816
    Abstract: A protection film for an electronic device includes an adhesive layer including a first surface to which an electronic device is attached, and a film layer which contacts a second surface of the adhesive layer and includes at least one member, where a thickness of the adhesive layer satisfies Inequality 1: z?(5.1x+57.4)·ln(y)?(14.7x+140.5) where z is the thickness of the adhesive layer in terms of micrometers, x is a modulus of a member of the film layer which directly contacts the adhesive layer in terms of gigapascals, and y is a total thickness of the film layer in terms of micrometers.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: May 26, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Young Eun Oh, Jai Ku Shin, Han Sun Ryou, So Dam Ahn, Jang Doo Lee
  • Patent number: 10658256
    Abstract: Mold compound transfer systems and methods for making mold compound transfer systems are disclosed herein. A method configured in accordance with a particular embodiment includes providing a sheet mold compound, and dispensing a granular mold compound directly on the sheet mold compound. The sheet mold compound can have a first density and the overall granular mold compound can have a second density less than the first density. The method further comprises transferring the solid sheet carrying the dispensed granular mold compound to a molding machine without using a release film.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: May 19, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kean Tat Koh, Lien Wah Choong
  • Patent number: 10643939
    Abstract: A semiconductor device has a wiring substrate on which a semiconductor chip is mounted. A wiring layer of the wiring substrate has a wiring. This wiring has a main wiring unit extending in a direction “X” and a plurality of sub-wiring units extending in a direction “Y”, in a cross sectional view, and is supplied with a power source potential. The wiring layer has a wiring. This wiring has a main wiring unit extending in the direction “X” and a plurality of sub-wiring units extending in the direction “Y”, in a cross sectional view, and is supplied with a reference potential. The sub-wiring units and the sub-wiring units have end units and end units on a side opposed to the end units, and are alternately arranged along the direction “X” between the main wiring units. To the end units, via wirings are coupled.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shuuichi Kariyazaki, Keita Tsuchiya, Yoshitaka Okayasu, Wataru Shiroi
  • Patent number: 10644259
    Abstract: A package of electronic device including a substrate, at least one electronic device and an encapsulation layer is provided. The substrate has a device area and a light transmitting area located outside the device area. The at least one electronic device is disposed on the device area of the substrate. The encapsulation layer is disposed on the substrate and covers the at least one electronic device. The encapsulation layer extends continuously from the device area to the light transmitting area, and a nitrogen content of the encapsulation layer on the device area is higher than a nitrogen content of the encapsulation layer on the light transmitting area. A display panel is also provided.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: May 5, 2020
    Assignees: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Hsiao-Fen Wei, Kun-Lin Chuang, Yen-Ching Kuo
  • Patent number: 10629519
    Abstract: A semiconductor device package includes an electronic device, a conductive frame and a first molding layer. The conductive frame is disposed over and electrically connected to the electronic device, and the conductive frame includes a plurality of leads. The first molding layer covers the electronic device and a portion of the conductive frame, and is disposed between at least two adjacent ones of the leads.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: April 21, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tien-Szu Chen, Sheng-Ming Wang, I-Cheng Wang, Wun-Jheng Syu
  • Patent number: 10574025
    Abstract: A hermetic capsule including a semiconductor/metal base with sensitive semiconductor/polymer electrical and optical components formed thereon and a semiconductor/metal lid. The semiconductor/metal lid sealed to the semiconductor/metal base by metallization so as to form a chamber including all of the sensitive semiconductor/polymer electrical and optical components and hermetically sealing the chamber and all sensitive components from the ambient. External access to the sensitive semiconductor/polymer electrical and optical components is provided through a metallization.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: February 25, 2020
    Assignee: Lightwave Logic Inc.
    Inventor: Michael Lebby
  • Patent number: 10573537
    Abstract: An integrated circuit (“IC”) package mold includes an upper mold platen that defines an upper mold cavity for receiving an upper substrate having a die attach side with a plurality of dies mounted thereon and a non-attach side with no dies mounted thereon. The die attach side of the upper substrate faces upwardly. A lower mold platen defines a lower mold cavity for receiving a lower substrate having a die attach side with a plurality dies mounted thereon and a non-attach side with no dies mounted thereon. The die attach side of the lower substrate faces downwardly.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: February 25, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Hiep Xuan Nguyen
  • Patent number: 10553455
    Abstract: A liquid is supplied to a substrate and a chip component is arranged on the liquid. The substrate includes a first surface in which a rectangular mounting region is formed. The chip component includes a second surface having a rectangular shape which substantially coincides with the shape of the mounting region, and has an area substantially equal to that of the mounting region. The mounting region includes first and second regions. Wettability of the first region with respect to the liquid is higher than that of the second region with respect to the liquid. The first region is provided symmetrically with respect to a first central line passing through the middle of a pair of long sides and a second central line passing through the middle of a pair of short sides in the mounting region, and includes rectangular partial regions. The liquid is supplied to the first region.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: February 4, 2020
    Assignees: TOKYO ELECTRON LIMITED, TOHOKU UNIVERSITY
    Inventors: Shinya Kikuta, Satohiko Hoshino, Takafumi Fukushima, Mitsumasa Koyanagi, Kangwook Lee
  • Patent number: 10547119
    Abstract: An antenna module includes a connection member including at least one wiring layer and at least one insulating layer; an integrated circuit (IC) package disposed on a first surface of the connection member; and an antenna package including a plurality of antenna members and a plurality of feed vias, and disposed on a second surface of the connection member, wherein the IC package includes: an IC having an active surface electrically connected to at least one wiring layer and an inactive surface opposing the active surface, and generating the RF signal; a heat sink member disposed on the inactive surface of the IC; and an encapsulant encapsulating at least portions of the IC and the heat sink member.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: January 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo Il Kim, Jung Hyun Cho, Won Wook So, Young Sik Hur, Yong Ho Baek
  • Patent number: 10517176
    Abstract: One semiconductor device includes a wiring substrate, a semiconductor chip, and a sealing body. The wiring substrate includes an insulating base material, a first conductive pattern formed on one surface of the insulating base material, and a second conductive pattern formed on one surface of the insulating base material, connected to the first conductive pattern and having an end face exposed to the side. The semiconductor chip is mounted on the wiring substrate so as to overlap with the first conductive pattern. The sealing body is formed on the wiring substrate so as to cover the semiconductor chip.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: December 24, 2019
    Assignee: LONGITUDE LICENSING LIMITED
    Inventor: Atsushi Tomohiro
  • Patent number: 10510938
    Abstract: A light-emitting diode (LED) package includes a substrate with upper and lower surfaces, including: a metal block; an electrically insulating region surrounding at least a portion of the metal block; an LED chip mounted on the substrate and in electrical communication with the metal block; and an encapsulant covering at least an upper surface of the LED chip. A light-emitting system includes a plurality of light-emitting diode (LED) chips; and a package support for the plurality of LED chips.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: December 17, 2019
    Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jun-Peng Shi, Pei-Song Cai, Hao Huang, Xing-Hua Liang, Zhen-Duan Lin, Chih-Wei Chao, Chen-Ke Hsu
  • Patent number: 10510558
    Abstract: Disclosed are an electronic device and the manufacturing method thereof, a manufacturing method of a thin film transistor, and an array substrate and manufacturing method thereof. The manufacturing method of an electronic device includes: forming a metallic structure on a base substrate; forming an oxygen-free insulating layer on the metallic structure and the base substrate; and forming an insulating protective layer on the oxygen-free insulating layer. The manufacturing method of the electronic device protects a metallic structure by forming an oxygen-free insulating layer, not containing oxygen elements, on the metallic structure, and hence prevents the metallic structure from being oxidized.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: December 17, 2019
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Meili Wang
  • Patent number: 10424541
    Abstract: A component carrier including an electrically insulating core, at least one electronic component embedded in the core, and a coupling structure with at least one electrically conductive through-connection extending at least partially therethrough and having a component contacting end and a wiring contacting end. The electronic component directly contacts the component contacting end. The wiring contacting end is directly electrically contacted to the wiring structure. The exterior surface portion of the coupling structure has homogeneous ablation properties and surface recesses filled with an electrically conductive wiring structure.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: September 24, 2019
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventor: Hannes Stahr
  • Patent number: 10418087
    Abstract: A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die. The first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: September 17, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaehyung Lee, JungSik Kim, Youngdae Lee, Duyeul Kim, Sungmin Yim, Kwangil Park, Chulsung Park
  • Patent number: 10416557
    Abstract: A method for manufacturing a semiconductor apparatus, including preparing a first substrate provided with a pad optionally having a plug and a second substrate or device provided with a plug, forming a solder ball on at least one of the pad or plug of first substrate and the plug of second substrate or device, covering at least one of a pad-forming surface of first substrate and a plug-forming surface of second substrate or device with a photosensitive insulating layer, forming an opening on the pad or plug of the substrate or device that has been covered with photosensitive insulating layer by lithography, pressure-bonding the second substrate or device's plug to the pad or plug of first substrate with the solder ball through the opening, electrically connecting pad or plug of first substrate to second substrate or device's plug by baking, and curing photosensitive insulating layer by baking.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: September 17, 2019
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Kyoko Soga, Satoshi Asai
  • Patent number: 10410774
    Abstract: Provided are a composite material having direct current superposition characteristics, low iron loss, and high strength, a magnetic core for a magnetic component and a reactor, the magnetic core and the reactor including the composite material, a converter including the reactor, and a power conversion device including the converter. A composite material includes a soft magnetic powder, a filler, and a resin portion enclosing the soft magnetic powder and the filler dispersed therein, wherein the filler has rubber and an outer circumferential layer that covers a surface of the rubber and that contains an organic substance, and the resin portion contains a thermoplastic resin.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: September 10, 2019
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Kazushi Kusawake, Atsushi Sato, Shigeki Masuda
  • Patent number: 10410993
    Abstract: A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method for manufacturing a semiconductor device that comprises ordering and performing processing steps in a manner that prevents warpage deformation from occurring to a wafer and/or die due to mismatching thermal coefficients.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: September 10, 2019
    Assignee: Amkor Technology, Inc.
    Inventors: Yeong Beom Ko, Jin Han Kim, Dong Jin Kim, Do Hyung Kim, Glenn Rinne
  • Patent number: 10332965
    Abstract: A semiconductor device includes a plurality of fins. Each of the fins has a multi-layer stack comprising a first nanowire and a second nanowire. A first portion of the first nanowire and second nanowire are doped to form source and drain regions. An epitaxial layer wraps around the first portion of first nanowire and second nanowire over the source and drain region. A gate is disposed over a second portion of the first nanowire and second nanowire. The epitaxial layer is interposed in between the first nanowire and the second nanowire over the source and drain region. The epitaxial layer has a zig-zag contour.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: June 25, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Martin Christopher Holland, Mark Van Dal, Georgios Vellianitis, Blandine Duriez, Gerben Doornbos
  • Patent number: 10325877
    Abstract: In a vertically integrated microelectronic package, a first microelectronic device is coupled to an upper surface of a circuit platform in a wire bond-only surface area thereof. Wire bond wires are coupled to and extends away from an upper surface of the first microelectronic device. A second microelectronic device in a face-down orientation is coupled to upper ends of the wire bond wires in a surface mount-only area. The second microelectronic device is located above and at least partially overlaps the first microelectronic device. A protective layer is disposed over the circuit platform and the first microelectronic device. An upper surface of the protective layer has the surface mount-only area. The upper surface of the protective layer has the second microelectronic device disposed thereon in the face-down orientation in the surface mount-only area for coupling to the upper ends of the first wire bond wires.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: June 18, 2019
    Assignee: Invensas Corporation
    Inventors: Javier A. Delacruz, Abiola Awujoola, Ashok S. Prabhu, Christopher W. Lattin, Zhuowen Sun
  • Patent number: 10316135
    Abstract: Four conjugated copolymers with a donor/acceptor architecture including 4,4-dihexadecyl-4H-cyclopenta[1,2-b:5,4-b?]dithiophene as the donor structural unit and benzo[2,1,3]thiodiazole fragments with varying degrees of fluorination have been synthesized and characterized. It has been shown that the HOMO levels were decreased after the fluorine substitution. The field-effect charge carrier mobility was similar for all polymers with less than an order of magnitude difference between different acceptor units.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: June 11, 2019
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Ming Wang, Guillermo C. Bazan
  • Patent number: 10276463
    Abstract: A semiconductor device includes a substrate with a recess subsiding from a selected surface of the substrate to accommodate a semiconductor element. Connected to the semiconductor element, an electroconductive portion extends from the recess onto the selected surface. A post, formed at the selected surface, has a first surface in contact with the electroconductive portion, a second surface, and a side surface between the first and second surfaces. A sealing resin covers the side surface of the post and the semiconductor element, and has a mounting surface facing in the same direction as the selected surface of the substrate. A pad, on the mounting surface of the sealing resin, is in contact with the second surface of the post. In the thickness direction, the second surface of the post is offset from the mounting surface of the sealing resin toward the selected surface of the substrate.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: April 30, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Hideaki Yanagida
  • Patent number: 10264674
    Abstract: A passive element array includes an element body that includes laminated base material layers, passive elements at different positions in the element body when viewed from a lamination direction of the base material layers, input/output terminals at a first main surface of the element body and connected to one end of each of the passive elements, input/output terminals at a second main surface of the element body and connected to the other end of each of the passive elements, a first ground terminal between the first input/output terminal and the input/output terminal at the first main surface, and a second ground terminal between the input/output terminal and the input/output terminal at the second main surface.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: April 16, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Keito Yonemori, Hirokazu Yazaki
  • Patent number: 10264710
    Abstract: In an embodiment, thermal conductive material within a device having electrical component is described. In an embodiment, a device is disclosed comprising: a printed circuit board comprising electrical components; a housing of the device, wherein the housing substantially encloses the printed circuit board; a thermal conductive material coated on the printed circuit board, wherein the thermal conductive material is configured to coat an interface between an electrical component and the printed circuit board, and wherein the thermal conductive material is located between the printed circuit board and a portion of the housing according to both a three dimensional topography of the printed circuit board and a three dimensional shape of the portion of the housing.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: April 16, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Juha Erkki Antero Penttinen
  • Patent number: 10242924
    Abstract: A base-attached encapsulant for semiconductor encapsulation is used for collectively encapsulating a device-mounted surface of the semiconductor device-mounted substrate having semiconductor devices mounted thereon or a device-formed surface of a semiconductor device-formed wafer having semiconductor devices formed thereon. The base-attached encapsulant has a base and an encapsulating resin layer containing an uncured or semi-cured thermosetting resin component formed onto one of the surfaces of the base, and a linear expansion coefficient ?1 of the semiconductor device to be encapsulated by the base-attached encapsulant, a linear expansion coefficient ?2 of a cured product of the encapsulating resin layer, and a linear expansion coefficient ?3 of the base satisfy both of the following formula (1) and (2); ?1<?3<?2??(1) ?2<?1+?2?2?3<2??(2) wherein the unit of the linear expansion coefficient is ppm/K.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: March 26, 2019
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Tomoaki Nakamura, Hideki Akiba, Toshio Shiobara
  • Patent number: 10230028
    Abstract: A semiconductor light emitting device includes a substrate made of resin, a first wiring and a second wiring formed on the substrate, a light emitting element disposed on the substrate and electrically connected to the first wiring and the second wiring, and a transparent sealing resin configured to seal the light emitting element. The substrate contains an acrylic resin, and the sealing resin contains silicon.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: March 12, 2019
    Assignee: Rohm Co., Ltd.
    Inventors: Hirotaka Obuchi, Junichi Itai
  • Patent number: 10224584
    Abstract: An exemplary battery pack heat exchanger includes a wall of an enclosure, and a heat exchanger lid held against the wall to provide a chamber that receives a fluid to exchange thermal energy with a battery array that is outside of the chamber. An exemplary method of managing battery pack thermal energy includes moving a fluid through a chamber within an enclosure wall of a battery pack to adjust thermal energy levels of the battery pack.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: March 5, 2019
    Assignee: Ford Global Technologies, LLC
    Inventors: Dave Moschet, Rajaram Subramanian, Sai K. Perumalla, Saravanan Paramasivam
  • Patent number: 10199299
    Abstract: Mold compound transfer systems and methods for making mold compound transfer systems are disclosed herein. A method configured in accordance with a particular embodiment includes placing a sheet mold compound in a containment area defined by a tray cover, and dispensing a granular mold compound over the sheet mold compound. The sheet mold compound can have a first density and the overall granular mold compound can have a second density less than the first density. The method further comprises transferring the solid sheet carrying the dispensed grains to a molding machine without using a release film.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: February 5, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kean Tat Koh, Lien Wah Choong
  • Patent number: 10163765
    Abstract: A semiconductor device includes a semiconductor chip having a terminal thereon, a lead frame for connection to an external device, a bonding wire connecting the terminal of the semiconductor chip and the lead frame. A mold resin layer encloses the semiconductor chip and the bonding wire, such that a portion of the lead frame extends out of the mold resin layer. A molecular bonding layer has a portion on a surface of the bonding wire and includes a first molecular portion covalently bonded to a material of the bonding wire and a material of the mold resin layer.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: December 25, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihiko Happoya
  • Patent number: 10162111
    Abstract: An hermetically sealed monolithic photonic integrated circuit (PIC) including optical components and multiple optical and electrical inputs/outputs. The integrated circuit including a semiconductor/metal base with sensitive semiconductor/polymer electrical and optical components formed therein. The electrical and optical components having multiple optical and electrical inputs, multiple optical and electrical outputs, and/or multiple optical and electrical inputs and outputs. A semiconductor/metal basic lid is sealed to the semiconductor/metal base by metallization so as to form a chamber including the sensitive semiconductor/polymer electrical and optical components and hermetically sealing the chamber and the sensitive components from the ambient in a basic hermetic capsule with multiple optical pathways coupling multiple optical fibers to the optical components sealed within the chamber.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: December 25, 2018
    Assignee: Lightwave Logic Inc.
    Inventor: Michael Lebby
  • Patent number: 10128131
    Abstract: A sealing sheet with separators on both surfaces is provided with a sealing sheet, a separator (A) stacked on one surface of the sealing sheet and having a thickness of 50 ?m or more, and a separator (B) stacked on the other surface of the sealing sheet.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: November 13, 2018
    Assignee: NITTO DENKO CORPORATION
    Inventors: Goji Shiga, Tsuyoshi Ishizaka, Kosuke Morita, Chie Iino
  • Patent number: 10104767
    Abstract: A printed circuit board includes: a strip substrate sectioned into unit areas; electronic components respectively installed in each of the unit areas; and a separation space disposed between the unit areas.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: October 16, 2018
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hyung-Gi Ha, Jong-Myeon Lee, Jong-Rip Kim
  • Patent number: 10090237
    Abstract: A semiconductor device includes a die pad, a semiconductor chip with a bonding pad being formed, a lead one end of which is located in the vicinity of the semiconductor chip, a coupling wire that connects an electrode and the lead, and a sealing body that seals the semiconductor chip, the coupling wire, a part of the lead, and a part of the die pad. A lower surface of the die pad is exposed from a lower surface of the sealing body, the die pad and the coupling wire are comprised of copper, and a thickness of the semiconductor chip is larger than the sum of a thickness of the die pad and a thickness from an upper surface of the semiconductor chip to an upper surface of the sealing body.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: October 2, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshihiko Shimanuki
  • Patent number: 10084125
    Abstract: An electronic component includes a substrate a functional section provided on the substrate, and a sealing body which is provided on the substrate and seals the functional section. In a temperature region having a lowest temperature that is at least as high as the glass transition temperature of the sealing body, the coefficient of linear expansion of the sealing body is greater than the coefficient of linear expansion of the substrate. In a temperature region having a highest temperature that is lower than the glass transition temperature of the sealing body, the coefficient of linear expansion of the sealing body is less than the coefficient of linear expansion of the substrate. The electronic component exhibits superior reliability even upon prolonged use.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: September 25, 2018
    Assignee: SKYWORKS FILTER SOLUTIONS JAPAN CO., LTD.
    Inventors: Hidenori Uematsu, Tomohiro Fujita, Ichiro Kameyama, Tetsuya Furihata, Fuyuki Abe, Kazunori Nishimura
  • Patent number: 10056349
    Abstract: A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method for manufacturing a semiconductor device that comprises ordering and performing processing steps in a manner that prevents warpage deformation from occurring to a wafer and/or die due to mismatching thermal coefficients.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: August 21, 2018
    Assignee: Amkor Technology, Inc.
    Inventors: Yeong Beom Ko, Jin Han Kim, Dong Jin Kim, Do Hyung Kim, Glenn Rinne
  • Patent number: 10020206
    Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: July 10, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Thomas Scott Morris, David Jandzinski, Stephen Parker, Jon Chadwick, Julio C. Costa
  • Patent number: 9997376
    Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: June 12, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Thomas Scott Morris, David Jandzinski, Stephen Parker, Jon Chadwick, Julio C. Costa
  • Patent number: 9984992
    Abstract: In a vertically integrated microelectronic package, a first microelectronic device is coupled to an upper surface of a circuit platform in a wire bond-only surface area thereof. Wire bond wires are coupled to and extends away from an upper surface of the first microelectronic device. A second microelectronic device in a face-down orientation is coupled to upper ends of the wire bond wires in a surface mount-only area. The second microelectronic device is located above and at least partially overlaps the first microelectronic device. A protective layer is disposed over the circuit platform and the first microelectronic device. An upper surface of the protective layer has the surface mount-only area. The upper surface of the protective layer has the second microelectronic device disposed thereon in the face-down orientation in the surface mount-only area for coupling to the upper ends of the first wire bond wires.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: May 29, 2018
    Assignee: Invensas Corporation
    Inventors: Javier A. DeLaCruz, Abiola Awujoola, Ashok S. Prabhu, Christopher W. Lattin, Zhuowen Sun
  • Patent number: 9972576
    Abstract: The semiconductor chip package comprises a semiconductor chip, and an encapsulation body encapsulating the semiconductor chip, wherein the encapsulation body comprises a semiconductor chip; an encapsulation body encapsulating the semiconductor chip, wherein the encapsulation body comprises two opposing main faces and side faces which connect the two main faces with each other, wherein the side face have a smaller surface area than the main faces, respectively, and wherein a marking is provided on at least one of the side faces.
    Type: Grant
    Filed: November 24, 2016
    Date of Patent: May 15, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Teck Sim Lee, Amirul Afiq Hud, Fabian Schnoy, Felix Grawert, Uwe Kirchner, Bernd Schmoelzer, Franz Stueckler
  • Patent number: 9960054
    Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: May 1, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Thomas Scott Morris, David Jandzinski, Stephen Parker, Jon Chadwick, Julio C. Costa
  • Patent number: 9947552
    Abstract: Structures and formation methods of a chip package are provided. The method includes forming multiple conductive structures over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes disposing a mold over the carrier substrate. The method further includes forming a protection layer between the mold and the carrier substrate to surround the semiconductor die and the conductive structures. In addition, the method includes removing the mold.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: April 17, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shing-Chao Chen, Chih-Wei Lin, Meng-Tse Chen, Hui-Min Huang, Ming-Da Cheng, Kuo-Lung Pan, Wei-Sen Chang, Tin-Hao Kuo, Hao-Yi Tsai
  • Patent number: 9929078
    Abstract: A semiconductor package structure includes a conductive structure, at least two semiconductor elements and an encapsulant. The conductive structure has a first surface and a second surface opposite the first surface. The semiconductor elements are disposed on and electrically connected to the first surface of the conductive structure. The encapsulant covers the semiconductor elements and the first surface of the conductive structure. The encapsulant has a width ‘L’ and defines at least one notch portion. A minimum distance ‘d’ is between a bottom surface of the notch portion and the second surface of the conductive structure. The encapsulant has a Young's modulus ‘E’ and a rupture strength ‘Sr’, and L/(K×d)>E/Sr, wherein ‘K’ is a stress concentration factor with a value of greater than 1.2.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: March 27, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen-Long Lu, Chi-Chang Lee, Wei-Min Hsiao, Yuan-Feng Chiang
  • Patent number: 9929024
    Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: March 27, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Thomas Scott Morris, David Jandzinski, Stephen Parker, Jon Chadwick, Julio C. Costa
  • Patent number: 9917039
    Abstract: A method of forming a packaged semiconductor device includes providing a conductive frame structure. The conductive frame structure includes a first frame having leadfingers configured for directly attaching to a semiconductor device, such as an integrated power semiconductor device that includes both power devices and logic type devices. The leadfingers are further configured to provide high current capacity and a high thermal dissipation capacity for the power device portion of the semiconductor device. In one embodiment, the conductive frame structure further includes a second frame joined to the first frame. The second frame includes a plurality of leads configured to electrically connect to low power device portions of the semiconductor device. A package body is formed to encapsulate the semiconductor device and at least portions of the leadfingers and leads.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: March 13, 2018
    Assignee: Amkor Technology, Inc.
    Inventors: Marc Alan Mangrum, Thinh Van Pham