Encapsulated Patents (Class 257/787)
  • Patent number: 11076485
    Abstract: A component mounting board includes first and second substrates, a connection substrate, an interposer, and an electronic component. The first substrate has first and second surfaces opposing each other, a first side surface between the first and second surfaces, and a first signal pattern. The second substrate is disposed on the first substrate, has third and fourth surfaces opposing each other and a second side surface between the third and fourth surfaces, and includes a second signal pattern. The connection substrate is bent to connect the first and second side surfaces, and the interposer is disposed between the first and third surfaces and electrically connects the first and second signal patterns. The electronic component is mounted on at least one of the first to fourth surfaces.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: July 27, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Tae Seong Kim, Yun Je Ji, Ho Kwon Yoon, Yong Hoon Kim
  • Patent number: 11069606
    Abstract: A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a solid state diffusion bonding is disclosed. A plurality of traces is formed on a substrate, each respective trace comprising at least four different conductive materials having different melting points and plastic deformation properties, which are optimized for both diffusion bonding of chips and soldering of passives components.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: July 20, 2021
    Assignee: Compass Technology Company Limited
    Inventors: Kelvin Po Leung Pun, Chee Wah Cheung
  • Patent number: 11069588
    Abstract: A semiconductor package includes a package substrate, at least one semiconductor chip mounted on the package substrate, and a molding member that surrounds the at least one semiconductor chip. The molding member includes fillers. Each of the fillers includes a core and a coating layer that surrounds the core. The core includes a non-electromagnetic material and the coating layer includes an electromagnetic material. The molding member includes regions respectively have different distributions of the fillers.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: July 20, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-young Oh, Hyun-ki Kim, Sang-soo Kim, Seung-hwan Kim, Yong-kwan Lee
  • Patent number: 11038279
    Abstract: An antenna module includes a connection member including at least one wiring layer and at least one insulating layer; an integrated circuit (IC) package disposed on a first surface of the connection member; and an antenna package including a plurality of antenna members and a plurality of feed vias, and disposed on a second surface of the connection member, wherein the IC package includes: an IC having an active surface electrically connected to at least one wiring layer and an inactive surface opposing the active surface, and generating the RF signal; a heat sink member disposed on the inactive surface of the IC; and an encapsulant encapsulating at least portions of the IC and the heat sink member.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: June 15, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo Il Kim, Jung Hyun Cho, Won Wook So, Young Sik Hur, Yong Ho Baek
  • Patent number: 11031353
    Abstract: A microelectronic device and/or microelectronic device package having a warpage control structure. The warpage control structure may be positioned over an encapsulating material, wherein the encapsulating material is positioned between the warpage control structure and a die positioned over a substrate. The warpage control structure may have a first thickness over a first portion of the encapsulating material and a second thickness over a second portion of the encapsulating material. Methods of forming the microelectronic device are also disclosed herein.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: June 8, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Christopher Glancey, Shams U. Arifeen
  • Patent number: 10982120
    Abstract: Conventionally, when an adherend is nickel or the like, it has been difficult to realize an electroconductive adhesive that lowers connection resistance in various kinds of thermocurable curing resins. However, it is possible to provide an electroconductive adhesive, in the case where the adherend is nickel or the like, which reduces connection resistance in various kinds of thermocurable curing resins while simultaneously maintaining storage stability to have good handleability. The present description provides a thermocurable electroconductive adhesive including the following components (A) to (D): Component (A): a curable resin, Component (B): a thermal curing agent that cures Component (A), Component (C): an organometallic complex, and Component (D): electroconductive particles.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: April 20, 2021
    Assignee: THREEBOND CO., LTD.
    Inventors: Soichi Ota, Hitoshi Mafune, Makoto Kato, Tomoya Kodama
  • Patent number: 10985147
    Abstract: A stiffener on a semiconductor package substrate includes a plurality of parts that are electrically coupled to the semiconductor package substrate on a die side. Both stiffener parts are electrically contacted through a passive device that is soldered between the two stiffener parts and by an electrically conductive adhesive that bonds a given stiffener part to the semiconductor package substrate. The passive device is embedded between two stiffener parts to create a smaller X-Y footprint as well as a lower Z-direction profile.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: April 20, 2021
    Assignee: Intel Corporation
    Inventors: Jenny Shio Yin Ong, Seok Ling Lim, Bok Eng Cheah, Jackson Chung Peng Kong, Chin Lee Kuan
  • Patent number: 10942110
    Abstract: A system and method for detecting particles in a fluidic medium using a microfluidic sensor is described. The system utilises microfluidic channels though which the fluidic medium is passed. On one section of the microfluidic channel, an array of non-flexible electrodes are coupled with uniform spacing therebetween. On the opposing section of the channel, a flexible electrode is coupled and all electrodes are connected to an electrical analyser which is used to generate an electrical field inside the microfluidic channel with the flexible electrode acting as ground. The flexible electrode is actuated by different means to narrow the width of the microfluidic in the section of interest and to capture the particle between the section, where sectional scans of the particles are obtained and electrical properties of the particle are measured, thereby detecting the particles in the fluidic medium.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: March 9, 2021
    Assignee: UNITED ARAB EMIRATES UNIVERSITY
    Inventor: Mahmoud F. Y. Al Ahmad
  • Patent number: 10943858
    Abstract: A semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a thin fine-pitch redistribution structure.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: March 9, 2021
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Michael Kelly, David Hiner, Ronald Huemoeller, Roger St. Amand
  • Patent number: 10930523
    Abstract: It is an object of the present invention to provide a method for manufacturing a resin-sealed power semiconductor device that facilitates the separation of a suspension lead from a mold resin and a lead frame. A method for manufacturing a resin-sealed power semiconductor device according to the present invention includes the following steps: (a) sealing a semiconductor element and a lead frame, to prepare a sealed body in which a terminal lead and a suspension lead that are included in the lead frame project outward from a side of the mold resin; (b) punching a portion of the suspension lead, the portion projecting from the mold resin, with a first punch in a first direction, to separate the suspension lead from the mold resin; and (c) punching the projecting portion of the suspension lead with a second punch in a second direction.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: February 23, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Keitaro Ichikawa, Ken Sakamoto, Kazuo Funahashi
  • Patent number: 10910588
    Abstract: A display device includes a substrate including an upper surface, a lower surface, and side surfaces; a display element layer on the upper surface overlapping the display area; an encapsulation layer on the upper surface, the encapsulation layer including a main part that overlaps the display element layer and a protruding part that protrudes along a first direction from the main part and overlaps the bezel area; an input sensor on the main part; a first circuit board facing the main part, overlapping the bezel area, and on the upper surface; and a second circuit board on the protruding part, wherein each of the first circuit board and the second circuit board is adjacent to a first side surface among the side surfaces, and in the first direction, the protruding part is more adjacent to the first side surface than the main part.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: February 2, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyoung-Joo Kim, Yunsoo Kim, Jun-Hee Lee, Cheollae Roh, Gyoowan Han
  • Patent number: 10903090
    Abstract: A method of forming a package structure includes the following processes. A die is attached to a polymer layer. An encapsulant is formed over the polymer layer to encapsulate sidewalls of the die. A RDL structure is formed on the encapsulant and the die. A conductive terminal is electrically connected to the die through the RDL structure. A light transmitting film is formed on the polymer layer. An alignment process is performed, and the alignment process uses an optical equipment to see through the light transmitting film to capture the alignment information included in the polymer layer. A singulating process is performed to singulate the package structure according to the alignment information.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: January 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Ting Chen, Ching-Hua Hsieh, Hsiu-Jen Lin, Hao-Jan Pei, Wei-Yu Chen, Chia-Lun Chang, Chia-Shen Cheng, Cheng-Shiuan Wong
  • Patent number: 10886255
    Abstract: A die stack structure may include a base die having base contact pads insulated by a base protection patterns and a flat side surface, a die stack bonded to the base die and having a plurality of component dies on the base die such that each of the component dies includes component contact pads insulated by a corresponding component protection pattern, and a residual mold unevenly arranged on a side surface of the die stack such that the component dies are attached to each other by the residual mold.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: January 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-Seok Hong, Ji-Hoon Kim, Tae-Hun Kim, Hyuek-Jae Lee, Ji-Hwan Hwang
  • Patent number: 10886694
    Abstract: A hermetic capsule including a semiconductor/metal base with sensitive semiconductor/polymer electrical and optical components formed thereon and a semiconductor/metal lid. The semiconductor/metal lid sealed to the semiconductor/metal base by metallization so as to form a chamber including all of the sensitive semiconductor/polymer electrical and optical components and hermetically sealing the chamber and all sensitive components from the ambient. External access to the sensitive semiconductor/polymer electrical and optical components is provided through a metallization.
    Type: Grant
    Filed: December 15, 2019
    Date of Patent: January 5, 2021
    Assignee: Lightwave Logic Inc.
    Inventor: Michael Lebby
  • Patent number: 10872853
    Abstract: A module with high reliability is provided by inhibiting occurrences of air bubbles caused with rise in flow resistance of resin when a sealing resin layer is formed using a die. A module includes a wiring board, components mounted over an upper face of the wiring board, and a sealing resin layer laminated over the upper face. On the upper face, the sealing resin layer includes a high-level region with a long distance from the upper face of the wiring board, a low-level region with a short distance from the upper face, and a level difference region. In a portion included in the wiring board and corresponding to the low-level region and the level difference region, a thin portion is formed so as to be thinner than the remaining portion and overlaps the low-level region at least partially in a plan view.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: December 22, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Issei Yamamoto
  • Patent number: 10872848
    Abstract: An embodiment of a semiconductor package includes a leadframe and a mold compound partly encasing the leadframe so that leads protrude from the mold compound and at least two die pads have a surface at a first side of the leadframe which is not covered by the mold compound. A laser module is attached to the surface of the at least two die pads which is not covered by the mold compound. A driver die is attached to the leadframe at a second side of the leadframe opposite the first side so that the laser module and the driver die are disposed in a stacked arrangement, the driver die configured to control the laser module. The driver die is in direct electrical communication with the laser module only through the leadframe and any interconnects which attach the laser module and driver die to the leadframe.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: December 22, 2020
    Assignee: Infineon Technologies AG
    Inventors: Woon Yik Yong, Andreas Kucher, Chia-Yen Lee, Shao Ping Wan
  • Patent number: 10868251
    Abstract: A method for fabricating an organic light emitting diode (OLED) display is provided. The fabricating method includes: forming a switch array layer on a base substrate; forming an organic light emitting display layer on the switch array layer; forming a thin film package layer on the organic light emitting display layer; and forming a superhydrophobic thin film on the thin film package layer using plasma chemical vapor deposition. The superhydrophobic thin film has a thickness smaller than a predetermined thickness.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: December 15, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Jing Wang, San Zhu
  • Patent number: 10847478
    Abstract: A method of forming an electronic device structure includes providing an electronic component having a first major surface, an opposing second major surface, a first edge surface, and an opposing second edge surface. A substrate having a substrate first major surface and an opposing substrate second major surface is provided. The second major surface of the first electronic component is placed proximate to the substrate first major surface and providing a conductive material adjacent the first edge surface of the first electronic component. The conductive material is exposed to an elevated temperature to reflow the conductive material to raise the first electronic component into an upright position such that the second edge surface is spaced further away from the substrate first major surface than the first edge surface. The method is suitable for providing electronic components, such as antenna, sensors, or optical devices in a vertical or on-edge.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: November 24, 2020
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventor: Shaun Bowers
  • Patent number: 10804196
    Abstract: An electronic component device includes an electronic component embedded in a resin structure and including a portion exposed on a first main surface of the resin structure, first wiring lines extending from the first main surface of the resin structure to the electronic component and electrically connected to the electronic component, second wiring lines on a side of a second main surface of the resin structure and electrically connected to respective connection electrodes that are electrically connected to the first wiring lines, and low-elastic modulus layers at a height position between the first wiring lines and the exposed portion of the electronic component in respective regions in which the first wiring lines straddle boundaries between the resin structure and the electronic component, having elastic moduli lower than those of the first wiring lines, and made of a conductive material.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: October 13, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takashi Iwamoto
  • Patent number: 10790208
    Abstract: Implementations of semiconductor packages may include: a semiconductor wafer, a glass lid fixedly coupled to a first side of the semiconductor die by an adhesive, a redistribution layer coupled to a second side of the semiconductor die, and a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer coupled to the semiconductor die. The adhesive may be located in a trench around a perimeter of the semiconductor die and located in a corresponding trench around a perimeter of the glass lid.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: September 29, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Yu-Te Hsieh
  • Patent number: 10763192
    Abstract: A method of attaching a semiconductor die or chip onto a support member such as a leadframe comprises: applying onto the support member at least one stretch of ribbon electrical bonding material and coupling the ribbon material to the support member, arranging at least one semiconductor die onto the ribbon material with the ribbon material between the support member and the semiconductor die, coupling the semiconductor die to the ribbon material.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: September 1, 2020
    Assignee: STMICROELECTRONICS S.r.l.
    Inventor: Dario Vitello
  • Patent number: 10727125
    Abstract: A bonding structure for a flexible screen and a manufacturing method are provided a flexible screen and a chip mounted on a surface of the flexible screen are arranged on the bonding structure for the flexible screen, and a bonding area for bonding the chip is arranged on the flexible screen, and a flexible protective layer is coated in the bonding area, and the flexible protective layer surrounds around the chip. Compared with the prior art, by forming the flexible protective layer with different hardness around the chip, the stress generated around the chip during the peeling-off are greatly dispersed, a stress gradient is formed, the stress concentration at the position closely adjacent to the periphery of the chip is avoided, the risk of the circuits around the chip being pulled broken can be reduced, and the peeling-off yield of the flexible screen can be finally increased.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: July 28, 2020
    Assignee: Kunshan New Flat Panel Display Technology Center Co., Ltd.
    Inventors: Xiuyu Zhang, Baoyou Wang, Pengle Dang, Liwei Ding, Xiaobao Zhang, Hui Zhu
  • Patent number: 10714404
    Abstract: A technique disclosed in the Description relates to a technique for improving the heat dissipation capability of a semiconductor element and the heat dissipation capability of a lead electrode without increasing the size of a product. A semiconductor device of the technique includes the following: a semiconductor element; a lead electrode having a lower surface connected to an upper surface of the semiconductor element at one end of the lead electrode, the lead electrode being an external terminal; a cooling mechanism disposed on a lower surface side of the semiconductor element; and a heat dissipation mechanism provided to be thermally joined between the lower surface of the lead electrode and the cooling mechanism, the lower surface being more adjacent to an other-end side of the lead electrode than the one end, the heat dissipation mechanism including at least one insulating layer.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: July 14, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ryoji Murai, Mitsunori Aiko, Takaaki Shirasawa
  • Patent number: 10690628
    Abstract: Individual biological micro-objects can be deterministically selected and moved into holding pens in a micro-fluidic device. A flow of a first liquid medium can be provided to the pens. Physical pens can be structured to impede a direct flow of the first medium into a second medium in the pens while allowing diffusive mixing of the first medium and the second medium. Virtual pens can allow a common flow of medium to multiple ones of the pens.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: June 23, 2020
    Assignee: Berkeley Lights, Inc
    Inventors: Kevin T. Chapman, Igor Y. Khandros, Gaetan L. Mathieu, J. Tanner Nevill, Ming C. Wu
  • Patent number: 10694633
    Abstract: A method of encapsulating a printed circuit board of a motor controller with a potting material includes inserting the printed circuit board into a recess formed in a base portion of an encapsulation assembly such that a bottom surface of the printed circuit board is spaced from a surface of the recess. The method also includes coupling a cover portion of the encapsulation assembly to the base portion to define a cavity therebetween. The method further includes injecting the potting material into the cavity through at least one injection port defined in at least one of the base portion and the cover portion such that the printed circuit board is at least partially coated in the potting material.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: June 23, 2020
    Assignee: REGAL BELOIT AMERICA, INC.
    Inventors: Maung Eddison, Zachary Joseph Stauffer, Mark A. Swiger, Luis D. Morales
  • Patent number: 10692792
    Abstract: An electronic device includes an electronic component, a sealing resin body, and a plurality of conductive members electrically connected to the electronic component in the sealing resin body, including respective portions exposed from the sealing resin body to the outside of the sealing resin body, and having different potentials. The conductive members include a heat sink and a terminal extending from an inside to the outside of the sealing resin body. A surface of the terminal includes, as a part covered with the sealing resin body, a higher adhesion part and a lower adhesion part. The lower adhesion part is provided in an entire portion of a back surface of the terminal, the back surface being opposite to a connection surface of the terminal which is adjacent to a connection part electrically connected to the electronic component. The higher adhesion part is provided in the connection surface.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: June 23, 2020
    Assignee: DENSO CORPORATION
    Inventor: Hirohito Fujita
  • Patent number: 10665509
    Abstract: A method for manufacturing chip package includes the steps below. A wafer having an upper surface and a lower surface opposite thereto is provided, in which conductive bumps are disposed on the upper surface. The upper surface of the wafer is diced to form trenches. A first insulation layer exposing the conductive bumps is formed on the upper surface and in the trenches. A surface treatment layer is formed on the conductive bumps, and a top surface of the surface treatment layer is higher than that of the first insulation layer. The wafer is thinned from the lower surface toward the upper surface to expose the first insulation layer in the trenches. A second insulation layer is formed below the lower surface. The first and second insulation layers are diced along a center of each trench to form chip packages.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: May 26, 2020
    Assignee: COMCHIP TECHNOLOGY CO., LTD.
    Inventors: Chien-Chih Lai, Hung-Wen Lin
  • Patent number: 10665816
    Abstract: A protection film for an electronic device includes an adhesive layer including a first surface to which an electronic device is attached, and a film layer which contacts a second surface of the adhesive layer and includes at least one member, where a thickness of the adhesive layer satisfies Inequality 1: z?(5.1x+57.4)·ln(y)?(14.7x+140.5) where z is the thickness of the adhesive layer in terms of micrometers, x is a modulus of a member of the film layer which directly contacts the adhesive layer in terms of gigapascals, and y is a total thickness of the film layer in terms of micrometers.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: May 26, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Young Eun Oh, Jai Ku Shin, Han Sun Ryou, So Dam Ahn, Jang Doo Lee
  • Patent number: 10663142
    Abstract: A light-emitting device may include a ceramic substrate having a reflective component, a light-emitting diode on the ceramic substrate, and a light-converting material over the light-emitting diode. A lighting system may include a ceramic substrate having a reflective component, a plurality of light-emitting diodes connected together in series, wherein the plurality of light-emitting diodes are on the ceramic substrate, and a light-converting material over the plurality of light-emitting diodes. The ceramic substrate may provide electrical insulation between the light-emitting diode and the aluminum carrier. The ceramic substrate may provide thermal conductivity between the light-emitting diode and the aluminum carrier. The reflective component may include zirconium oxide. The ceramic substrate may include aluminum oxide and/or aluminum nitride. The light-converting material may include phosphor. The light-emitting diode may have an epitaxial diode structure.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: May 26, 2020
    Assignee: BRIDGELUX INC.
    Inventors: Jesus Del Castillo, Scott West, Vladimir Odnoblyudov
  • Patent number: 10658256
    Abstract: Mold compound transfer systems and methods for making mold compound transfer systems are disclosed herein. A method configured in accordance with a particular embodiment includes providing a sheet mold compound, and dispensing a granular mold compound directly on the sheet mold compound. The sheet mold compound can have a first density and the overall granular mold compound can have a second density less than the first density. The method further comprises transferring the solid sheet carrying the dispensed granular mold compound to a molding machine without using a release film.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: May 19, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kean Tat Koh, Lien Wah Choong
  • Patent number: 10643939
    Abstract: A semiconductor device has a wiring substrate on which a semiconductor chip is mounted. A wiring layer of the wiring substrate has a wiring. This wiring has a main wiring unit extending in a direction “X” and a plurality of sub-wiring units extending in a direction “Y”, in a cross sectional view, and is supplied with a power source potential. The wiring layer has a wiring. This wiring has a main wiring unit extending in the direction “X” and a plurality of sub-wiring units extending in the direction “Y”, in a cross sectional view, and is supplied with a reference potential. The sub-wiring units and the sub-wiring units have end units and end units on a side opposed to the end units, and are alternately arranged along the direction “X” between the main wiring units. To the end units, via wirings are coupled.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shuuichi Kariyazaki, Keita Tsuchiya, Yoshitaka Okayasu, Wataru Shiroi
  • Patent number: 10644259
    Abstract: A package of electronic device including a substrate, at least one electronic device and an encapsulation layer is provided. The substrate has a device area and a light transmitting area located outside the device area. The at least one electronic device is disposed on the device area of the substrate. The encapsulation layer is disposed on the substrate and covers the at least one electronic device. The encapsulation layer extends continuously from the device area to the light transmitting area, and a nitrogen content of the encapsulation layer on the device area is higher than a nitrogen content of the encapsulation layer on the light transmitting area. A display panel is also provided.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: May 5, 2020
    Assignees: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Hsiao-Fen Wei, Kun-Lin Chuang, Yen-Ching Kuo
  • Patent number: 10629519
    Abstract: A semiconductor device package includes an electronic device, a conductive frame and a first molding layer. The conductive frame is disposed over and electrically connected to the electronic device, and the conductive frame includes a plurality of leads. The first molding layer covers the electronic device and a portion of the conductive frame, and is disposed between at least two adjacent ones of the leads.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: April 21, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tien-Szu Chen, Sheng-Ming Wang, I-Cheng Wang, Wun-Jheng Syu
  • Patent number: 10573537
    Abstract: An integrated circuit (“IC”) package mold includes an upper mold platen that defines an upper mold cavity for receiving an upper substrate having a die attach side with a plurality of dies mounted thereon and a non-attach side with no dies mounted thereon. The die attach side of the upper substrate faces upwardly. A lower mold platen defines a lower mold cavity for receiving a lower substrate having a die attach side with a plurality dies mounted thereon and a non-attach side with no dies mounted thereon. The die attach side of the lower substrate faces downwardly.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: February 25, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Hiep Xuan Nguyen
  • Patent number: 10574025
    Abstract: A hermetic capsule including a semiconductor/metal base with sensitive semiconductor/polymer electrical and optical components formed thereon and a semiconductor/metal lid. The semiconductor/metal lid sealed to the semiconductor/metal base by metallization so as to form a chamber including all of the sensitive semiconductor/polymer electrical and optical components and hermetically sealing the chamber and all sensitive components from the ambient. External access to the sensitive semiconductor/polymer electrical and optical components is provided through a metallization.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: February 25, 2020
    Assignee: Lightwave Logic Inc.
    Inventor: Michael Lebby
  • Patent number: 10553455
    Abstract: A liquid is supplied to a substrate and a chip component is arranged on the liquid. The substrate includes a first surface in which a rectangular mounting region is formed. The chip component includes a second surface having a rectangular shape which substantially coincides with the shape of the mounting region, and has an area substantially equal to that of the mounting region. The mounting region includes first and second regions. Wettability of the first region with respect to the liquid is higher than that of the second region with respect to the liquid. The first region is provided symmetrically with respect to a first central line passing through the middle of a pair of long sides and a second central line passing through the middle of a pair of short sides in the mounting region, and includes rectangular partial regions. The liquid is supplied to the first region.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: February 4, 2020
    Assignees: TOKYO ELECTRON LIMITED, TOHOKU UNIVERSITY
    Inventors: Shinya Kikuta, Satohiko Hoshino, Takafumi Fukushima, Mitsumasa Koyanagi, Kangwook Lee
  • Patent number: 10547119
    Abstract: An antenna module includes a connection member including at least one wiring layer and at least one insulating layer; an integrated circuit (IC) package disposed on a first surface of the connection member; and an antenna package including a plurality of antenna members and a plurality of feed vias, and disposed on a second surface of the connection member, wherein the IC package includes: an IC having an active surface electrically connected to at least one wiring layer and an inactive surface opposing the active surface, and generating the RF signal; a heat sink member disposed on the inactive surface of the IC; and an encapsulant encapsulating at least portions of the IC and the heat sink member.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: January 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo Il Kim, Jung Hyun Cho, Won Wook So, Young Sik Hur, Yong Ho Baek
  • Patent number: 10517176
    Abstract: One semiconductor device includes a wiring substrate, a semiconductor chip, and a sealing body. The wiring substrate includes an insulating base material, a first conductive pattern formed on one surface of the insulating base material, and a second conductive pattern formed on one surface of the insulating base material, connected to the first conductive pattern and having an end face exposed to the side. The semiconductor chip is mounted on the wiring substrate so as to overlap with the first conductive pattern. The sealing body is formed on the wiring substrate so as to cover the semiconductor chip.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: December 24, 2019
    Assignee: LONGITUDE LICENSING LIMITED
    Inventor: Atsushi Tomohiro
  • Patent number: 10510938
    Abstract: A light-emitting diode (LED) package includes a substrate with upper and lower surfaces, including: a metal block; an electrically insulating region surrounding at least a portion of the metal block; an LED chip mounted on the substrate and in electrical communication with the metal block; and an encapsulant covering at least an upper surface of the LED chip. A light-emitting system includes a plurality of light-emitting diode (LED) chips; and a package support for the plurality of LED chips.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: December 17, 2019
    Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jun-Peng Shi, Pei-Song Cai, Hao Huang, Xing-Hua Liang, Zhen-Duan Lin, Chih-Wei Chao, Chen-Ke Hsu
  • Patent number: 10510558
    Abstract: Disclosed are an electronic device and the manufacturing method thereof, a manufacturing method of a thin film transistor, and an array substrate and manufacturing method thereof. The manufacturing method of an electronic device includes: forming a metallic structure on a base substrate; forming an oxygen-free insulating layer on the metallic structure and the base substrate; and forming an insulating protective layer on the oxygen-free insulating layer. The manufacturing method of the electronic device protects a metallic structure by forming an oxygen-free insulating layer, not containing oxygen elements, on the metallic structure, and hence prevents the metallic structure from being oxidized.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: December 17, 2019
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Meili Wang
  • Patent number: 10424541
    Abstract: A component carrier including an electrically insulating core, at least one electronic component embedded in the core, and a coupling structure with at least one electrically conductive through-connection extending at least partially therethrough and having a component contacting end and a wiring contacting end. The electronic component directly contacts the component contacting end. The wiring contacting end is directly electrically contacted to the wiring structure. The exterior surface portion of the coupling structure has homogeneous ablation properties and surface recesses filled with an electrically conductive wiring structure.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: September 24, 2019
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventor: Hannes Stahr
  • Patent number: 10416557
    Abstract: A method for manufacturing a semiconductor apparatus, including preparing a first substrate provided with a pad optionally having a plug and a second substrate or device provided with a plug, forming a solder ball on at least one of the pad or plug of first substrate and the plug of second substrate or device, covering at least one of a pad-forming surface of first substrate and a plug-forming surface of second substrate or device with a photosensitive insulating layer, forming an opening on the pad or plug of the substrate or device that has been covered with photosensitive insulating layer by lithography, pressure-bonding the second substrate or device's plug to the pad or plug of first substrate with the solder ball through the opening, electrically connecting pad or plug of first substrate to second substrate or device's plug by baking, and curing photosensitive insulating layer by baking.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: September 17, 2019
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Kyoko Soga, Satoshi Asai
  • Patent number: 10418087
    Abstract: A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die. The first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: September 17, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaehyung Lee, JungSik Kim, Youngdae Lee, Duyeul Kim, Sungmin Yim, Kwangil Park, Chulsung Park
  • Patent number: 10410993
    Abstract: A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method for manufacturing a semiconductor device that comprises ordering and performing processing steps in a manner that prevents warpage deformation from occurring to a wafer and/or die due to mismatching thermal coefficients.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: September 10, 2019
    Assignee: Amkor Technology, Inc.
    Inventors: Yeong Beom Ko, Jin Han Kim, Dong Jin Kim, Do Hyung Kim, Glenn Rinne
  • Patent number: 10410774
    Abstract: Provided are a composite material having direct current superposition characteristics, low iron loss, and high strength, a magnetic core for a magnetic component and a reactor, the magnetic core and the reactor including the composite material, a converter including the reactor, and a power conversion device including the converter. A composite material includes a soft magnetic powder, a filler, and a resin portion enclosing the soft magnetic powder and the filler dispersed therein, wherein the filler has rubber and an outer circumferential layer that covers a surface of the rubber and that contains an organic substance, and the resin portion contains a thermoplastic resin.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: September 10, 2019
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Kazushi Kusawake, Atsushi Sato, Shigeki Masuda
  • Patent number: 10332965
    Abstract: A semiconductor device includes a plurality of fins. Each of the fins has a multi-layer stack comprising a first nanowire and a second nanowire. A first portion of the first nanowire and second nanowire are doped to form source and drain regions. An epitaxial layer wraps around the first portion of first nanowire and second nanowire over the source and drain region. A gate is disposed over a second portion of the first nanowire and second nanowire. The epitaxial layer is interposed in between the first nanowire and the second nanowire over the source and drain region. The epitaxial layer has a zig-zag contour.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: June 25, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Martin Christopher Holland, Mark Van Dal, Georgios Vellianitis, Blandine Duriez, Gerben Doornbos
  • Patent number: 10325877
    Abstract: In a vertically integrated microelectronic package, a first microelectronic device is coupled to an upper surface of a circuit platform in a wire bond-only surface area thereof. Wire bond wires are coupled to and extends away from an upper surface of the first microelectronic device. A second microelectronic device in a face-down orientation is coupled to upper ends of the wire bond wires in a surface mount-only area. The second microelectronic device is located above and at least partially overlaps the first microelectronic device. A protective layer is disposed over the circuit platform and the first microelectronic device. An upper surface of the protective layer has the surface mount-only area. The upper surface of the protective layer has the second microelectronic device disposed thereon in the face-down orientation in the surface mount-only area for coupling to the upper ends of the first wire bond wires.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: June 18, 2019
    Assignee: Invensas Corporation
    Inventors: Javier A. Delacruz, Abiola Awujoola, Ashok S. Prabhu, Christopher W. Lattin, Zhuowen Sun
  • Patent number: 10316135
    Abstract: Four conjugated copolymers with a donor/acceptor architecture including 4,4-dihexadecyl-4H-cyclopenta[1,2-b:5,4-b?]dithiophene as the donor structural unit and benzo[2,1,3]thiodiazole fragments with varying degrees of fluorination have been synthesized and characterized. It has been shown that the HOMO levels were decreased after the fluorine substitution. The field-effect charge carrier mobility was similar for all polymers with less than an order of magnitude difference between different acceptor units.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: June 11, 2019
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Ming Wang, Guillermo C. Bazan
  • Patent number: 10276463
    Abstract: A semiconductor device includes a substrate with a recess subsiding from a selected surface of the substrate to accommodate a semiconductor element. Connected to the semiconductor element, an electroconductive portion extends from the recess onto the selected surface. A post, formed at the selected surface, has a first surface in contact with the electroconductive portion, a second surface, and a side surface between the first and second surfaces. A sealing resin covers the side surface of the post and the semiconductor element, and has a mounting surface facing in the same direction as the selected surface of the substrate. A pad, on the mounting surface of the sealing resin, is in contact with the second surface of the post. In the thickness direction, the second surface of the post is offset from the mounting surface of the sealing resin toward the selected surface of the substrate.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: April 30, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Hideaki Yanagida
  • Patent number: 10264674
    Abstract: A passive element array includes an element body that includes laminated base material layers, passive elements at different positions in the element body when viewed from a lamination direction of the base material layers, input/output terminals at a first main surface of the element body and connected to one end of each of the passive elements, input/output terminals at a second main surface of the element body and connected to the other end of each of the passive elements, a first ground terminal between the first input/output terminal and the input/output terminal at the first main surface, and a second ground terminal between the input/output terminal and the input/output terminal at the second main surface.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: April 16, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Keito Yonemori, Hirokazu Yazaki