Alignment Marks Patents (Class 257/797)
  • Patent number: 10845714
    Abstract: An exposure method includes exposing a substrate to form a first pattern on a first layer, measuring a first alignment value of the first pattern, generating first correction data by using the first alignment value, storing the first correction data and exposing the substrate to form a second pattern on a second layer disposed on the first layer by using the first correction data.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: November 24, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ik-Han Oh, Seung-Kyu Lee, Hyeon-Min Cho
  • Patent number: 10840140
    Abstract: A wafer dividing method includes a first step of cutting a back side of the wafer by using a cutting blade thereby forming a cut groove on the back side of the wafer along each division line, such that each cut groove has a depth not reaching the front side of the wafer from the back side thereof. A second step includes supplying a water-soluble liquid resin to the back side of the wafer thereby forming a water-soluble protective film on the back side of the wafer. A third step includes positioning a focal point of a laser beam on the bottom surface of each cut groove and next applying the laser beam to the bottom surface of each cut groove thereby fully cutting the wafer along each cut groove.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: November 17, 2020
    Assignee: DISCO CORPORATION
    Inventor: Tsubasa Obata
  • Patent number: 10818606
    Abstract: An alignment mark pattern is provided. The alignment mark pattern includes a first region that includes a first line and a first space having different widths therebetween, a second region that includes a second line and a second space having different widths therebetween, a third region that includes a third line and a third space having different widths therebetween, and a fourth region that includes a fourth line and a fourth space having different widths therebetween. The first and second lines extend in a first direction. The third and fourth lines extend in a second direction perpendicular to the first direction. The first region is diagonal to the second region. The third region is diagonal to the fourth region. The third region is adjacent to the first and second regions. The fourth region is adjacent to the first and second regions.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: October 27, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Jun-Che Wu, Jing-Hua Chiang, Wen-Keir Liang, Ming-Yu Chen
  • Patent number: 10818607
    Abstract: A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: October 27, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
  • Patent number: 10790202
    Abstract: The present invention provides an overlay mark, including a substrate and plural sets of first pattern block and second pattern block. A first direction and a second direction are defined on the substrate, wherein the first direction and the second direction are perpendicular to each other. In each set, the first pattern block is rotational symmetrical to the second pattern block. Each first pattern block includes a big frame and plural small frame. Each second pattern block includes a big frame and plural small frame. The width of the big frame is greater than three times of the width of the small frame. The present invention further provides a method for evaluating the stability of a semiconductor manufacturing process.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: September 29, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 10772216
    Abstract: An electronic component includes a multilayer body including insulating base materials laminated on each other and including first and second main surfaces perpendicular or substantially perpendicular to a lamination direction, and an alignment mark is defined by a conductor on one of the insulating base materials. The multilayer body includes a first layer area at a side of the first main surface and a second layer area at a side of the second main surface with respect to the alignment mark. An insulating base material in the first layer area has higher translucency than an insulating base material in the second layer area. The alignment mark is a trapezoidal cross-sectional shape including a first base at the side of the first main surface and a second base at the side of second main surface, the first base being longer than the second base.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: September 8, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Shingo Ito
  • Patent number: 10756022
    Abstract: Some embodiments include a semiconductor package. The semiconductor package has a semiconductor die with a primary region which includes integrated circuitry, and with an edge region which includes a portion of an alignment mark location. The portion of the alignment mark location includes a segment of an alignment mark. The alignment mark includes a pattern of lines and spaces, with the lines extending along a first direction. The portion of the alignment mark location also includes a texture having a pattern other than lines extending along either the first direction or along a second direction substantially orthogonal to the first direction. Some embodiments include methods for alignment marking semiconductor wafers.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: August 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Richard T. Housley, Jianming Zhou
  • Patent number: 10748910
    Abstract: A semiconductor device includes a substrate that includes a cell region and a peripheral circuit region, a cell insulating pattern disposed in the cell region of the substrate that defines a cell active region, and a peripheral insulating pattern disposed in the peripheral circuit region of the substrate that defines a peripheral active region. The peripheral insulating pattern includes a first peripheral insulating pattern having a first width and a second peripheral insulating pattern having a second width greater than the first width. A topmost surface of at least one of the first peripheral insulating pattern and the second peripheral insulating pattern is positioned higher than a topmost surface of the cell insulating pattern.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan-Sic Yoon, Dongoh Kim, Kiseok Lee, Sunghak Cho, Jemin Park
  • Patent number: 10748861
    Abstract: A package structure includes a chip package and an antenna package. The chip package includes at least one semiconductor die and a first insulating encapsulation encapsulating the at least one semiconductor die. The antenna package is located on and electrically coupled to the chip package. The antenna package includes metallic patterns embedded in a second insulating encapsulation, wherein each of the metallic patterns has a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface, wherein the first surface and the side surface of each of the metallic patterns are covered by the second insulating encapsulation, and the second surface is levelled and coplanar with a third surface of the second insulating encapsulation.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Chiang Wu, Han-Ping Pu, Yen-Ping Wang
  • Patent number: 10715142
    Abstract: An LVDS device wherein driver and receiver functionalities are integrated in the same package, signals are routed from the individual driver and receiver elements inside the package such that all inputs are one side of the package, and all outputs are on the opposite side of the package, allowing for an optimized signal flow through the package. All required capacitors and resistors are integrated inside the package; no external electronic components are required. All of the above novelties also contribute to a 6:1 reduction in size compared to current state-of-the-art, for the same number of communication channels. Embodiments include a packaging topology adaptable to extreme environments, including radiation tolerant to 300 kRad (based on the die technology), so that module operational temperature is in a range of ?55° C. to +100° C. and storage temperature can be as low as ?184° C.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: July 14, 2020
    Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Don J. Hunter, Matthew E. King, Colin McKinney
  • Patent number: 10700016
    Abstract: A protective film material for laser processing comprises a solution of a water-soluble adhesive and a water-soluble laser beam absorbent added to adjust absorbance at a wavelength of 355 nm (absorbance as calculated as a 200-times diluted solution) to 0.3 to 3. The protective film effectively absorbs an irradiated laser beam, reduces generation of debris during laser beam irradiation, and can be removed by washing with water after completion of the laser processing treatment, thereby providing reliable processing. The water-soluble adhesive is preferably a blend of polyvinyl alcohol and poly-N-vinyl acetamide, which are preferably blended at a ratio of 100 to 200:1 in terms of amounts of respective components.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: June 30, 2020
    Assignee: NIKKA SEIKO CO., LTD.
    Inventors: Tsuyoshi Tadano, Masafumi Hirose, Daisuke Tomita
  • Patent number: 10698321
    Abstract: Methods of designing metrology targets are provided, which comprise distinguishing target elements from their background area by segmenting the background area and optionally segmenting the target elements. The provided metrology targets may maintain a required feature size when measured yet be finely segmented to achieve process and design rules compatibility which results in higher accuracy of the metrology measurements. Particularly, all transitions between target features and adjacent background features may be designed to maintain a feature size of the features below a certain threshold.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: June 30, 2020
    Assignee: KLA-Tencor Corporation
    Inventor: Nuriel Amir
  • Patent number: 10643950
    Abstract: A die has a positional location in a wafer defined by first and second coordinates, the first and second coordinates identifying a respective horizontal and vertical location where the die was formed. An index formed on the die has a first comb structure of a first contiguous arrangement of first dots, and a second comb structure of a second contiguous arrangement of second dots. A first marker at a selected one of the first dots indicates a first digit of the first coordinate, and a first additional marker at a selected one of the first dots indicates a second digit of the first coordinate. A second marker at a selected one of the second dots indicates a first digit of the second coordinate, and a second additional marker at a selected one of the second dots indicates a second digit of the second coordinate.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: May 5, 2020
    Assignee: STMicroelectronics S.r.l.
    Inventors: Emanuele Brenna, Antonio Di Franco
  • Patent number: 10636744
    Abstract: A memory device includes an insulation layer, an interconnection structure disposed in the insulation layer, a dielectric layer disposed on the insulation layer and the interconnection structure, a connection hole disposed on the interconnection structure and penetrates the dielectric layer, an alignment mark trench penetrating the dielectric layer on a peripheral region, a first patterned conductive layer, and a patterned memory material layer. The first patterned conductive layer includes a connection structure at least partly disposed in the connection hole and a first pattern disposed in the alignment mark trench. The patterned memory material layer includes a first memory material pattern disposed on the connection structure and a second memory material pattern disposed in the alignment mark trench. Manufacturing yield and alignment condition of forming the memory device may be improved by disposing a part of the first patterned conductive layer in the alignment mark trench.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: April 28, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Meng-Jun Wang, Jiunn-Hsiung Liao, Yu-Tsung Lai
  • Patent number: 10622312
    Abstract: A semiconductor chip includes a substrate including a circuit area having a rectangular shape and a peripheral area surrounding the circuit area, a key area being overlapping a part of the circuit area and a part of the peripheral area, a plurality of drive circuit cells in the circuit area, and a conductive reference line on the peripheral area and extending in a first direction parallel to a first edge among four edges of the rectangular shape of the circuit area.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: April 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myoung-soo Kim, Seong-sik Min
  • Patent number: 10612916
    Abstract: Methods and systems for evaluating the performance of multiple patterning processes are presented. Patterned structures are measured and one or more parameter values characterizing geometric errors induced by the multiple patterning process are determined. In some examples, a single patterned target and a multiple patterned target are measured, the collected data fit to a combined measurement model, and the value of a structural parameter indicative of a geometric error induced by the multiple patterning process is determined based on the fit. In some other examples, light having a diffraction order different from zero is collected and analyzed to determine the value of a structural parameter that is indicative of a geometric error induced by a multiple patterning process. In some embodiments, a single diffraction order different from zero is collected. In some examples, a metrology target is designed to enhance light diffracted at an order different from zero.
    Type: Grant
    Filed: October 15, 2017
    Date of Patent: April 7, 2020
    Assignee: KLA-Tencor Corporation
    Inventors: Andrei V. Shchegrov, Shankar Krishnan, Kevin Peterlinz, Thaddeus Gerard Dziura, Noam Sapiens, Stilian Ivanov Pandev
  • Patent number: 10593689
    Abstract: The inventive concepts provide methods for fabricating a semiconductor device and semiconductor devices fabricated by the same. According to the method, conductive lines having a fine pitch smaller than the minimum pitch realized by an exposure process may be formed using two or three photolithography processes and two spacer formation processes. In addition, node separation regions of the conductive lines may be easily formed without a misalignment problem.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: March 17, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Sung Song, Jae-Hwang Sim, Joon-Sung Lim
  • Patent number: 10573531
    Abstract: A method of manufacturing a semiconductor device includes forming a first photoresist film over a substrate, exposing a first pattern including an alignment pattern in a first region, forming, on the substrate, an alignment mark corresponding to the exposed alignment pattern, forming a second photoresist film over the substrate on which the alignment mark is formed, dividing a second pattern into a plurality of regions and exposing the divided regions separately in a second region while performing positioning with respect to the alignment mark, and developing the second photoresist film and forming the second photoresist film having the second pattern, wherein at least a part of the second region is located outside an effective exposure region of an exposure apparatus in exposure of the first pattern.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: February 25, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Shuji Tobashi, Masayuki Tsuchiya
  • Patent number: 10557982
    Abstract: The present disclosure provides a die core for a light guide plate, a manufacturing method thereof, and the light guide plate. The manufacturing method includes steps of: providing a body, a to-be-processed surface of the body including a dot formation region and a dot-free region; forming dots at the dot formation region, the dots including protrusions and recesses; and forming a coverage layer at least covering the protrusions.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: February 11, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE DISPLAY LIGHTING CO., LTD.
    Inventors: Bo Wu, Zuchuan Shi
  • Patent number: 10551976
    Abstract: A touch-control substrate, a fabrication method of the touch-control substrate, and a display device including the touch-control substrate are presented. The disclosed touch-control substrate includes a plurality of first electrodes and a plurality of second electrodes. The first and second electrodes are crossly configured and electrically insulated from one another. Each of the first and second electrodes includes a plurality of conductive structures. A mark region (8) has an alignment mark (81) and is located within a region containing the first and second electrodes. At least one of the conductive structures in the mark region (8) is at least partially absent in the mark region (8). The mark region (8) includes at least one transparent conductive element (5) complementing the at least partially absent conductive structure and being electrically connected to a corresponding conductive structure outside the mark region (8) and contained in either one first electrode or one second electrode.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: February 4, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Ming Zhang, Guoyong Ma, Zouming Xu, Ming Hu
  • Patent number: 10535573
    Abstract: Disclosed herein is a method for forming a test key system for characterizing wafer processing states, the method comprising forming a plurality of shallow trench isolation structures (STIs) on a substrate of a wafer and in a scribe line of the wafer and forming a test key on the substrate of a wafer and in the scribe line of the wafer. Forming the test key comprises forming at least one test key group having a plurality of test key series, each of the plurality of test key series having a plurality of test pads, each one of the plurality of test key series having a first physical characteristic different from the first physical characteristic of other test key series the at least one first test key group.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Wei-Chun Tsai
  • Patent number: 10529667
    Abstract: A method of forming an overlay mark structure includes the following steps. An insulation layer is formed on a substrate. A first overlay mark is formed in the insulation layer. A metal layer is formed on the substrate. The metal layer covers the insulation layer and the first overlay mark. The metal layer on the first overlay mark is removed. A top surface of the first overlay mark is lower than a top surface of the insulation layer after the step of removing the metal layer on the first overlay mark. A second overlay mark is formed on the metal layer. In the method of forming the overlay mark structure, the first overlay mark may not be covered by the metal layer for avoiding influences on related measurements, and the second overlay mark may be formed on the metal layer for avoiding related defects generated by the height difference.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: January 7, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Zheng-Feng Chen, Sho-Shen Lee, En-Chiuan Liou, Hsiao-Lin Hsu, Yi-Ting Chen, Lu-Wei Kuo
  • Patent number: 10520830
    Abstract: A method is described herein including applying, by a metrology apparatus, an incident radiation beam to a substrate including first features on a first layer and second features on a second layer, a relationship between the first and second features being characterized by a parameter of interest having a first value, wherein the metrology apparatus is operated in accordance with at least one characteristic having a first setting; receiving intensity data representing intensity of a portion of the incident radiation beam scattered by the first and second features; determining, based on the intensity data, a second value of the parameter of interest; and applying one or more adjustments to the at least one characteristic such that the at least one characteristic has a second setting different from the first, the one or more adjustments being determined based on a difference between the first value and the second value.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: December 31, 2019
    Assignee: ASML Netherlands B.V.
    Inventors: Harm Hubertus Joseph Elizabeth Kicken, Martijn Maria Zaal
  • Patent number: 10522474
    Abstract: Embodiments of three-dimensional (3D) memory devices and methods for controlling a photoresist (PR) trimming rate in the formation of the 3D memory devices are disclosed. In an example, a method includes forming a dielectric stack over a substrate, measuring a first distance between the first trimming mark and the PR layer along a first direction, and trimming the PR layer along the first direction. The method also includes etching the dielectric stack using the trimmed PR layer as an etch mask to form a staircase, forming a second trimming mark using the first trimming mark as an etch mask, measuring a second distance between the second trimming mark and the trimmed PR layer, comparing the first distance with the second distance to determine a difference between an actual PR trimming rate and an estimated PR trimming rate, and adjusting PR trimming parameters based on the difference.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: December 31, 2019
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Lidong Song, Yongna Li, Feng Pan, Xiaowang Dai, Dan Liu, Steve Weiyi Yang, Simon Shi-Ning Yang
  • Patent number: 10503069
    Abstract: A method of fabricating a patterned structure includes the following steps. A first pattern transfer layer and a second pattern transfer layer are formed on a material layer. A part of the second pattern transfer layer is patterned to be a first pattern. A first spacer is formed on sidewalls of the first pattern. The first pattern transfer layer is patterned to be a second pattern and a third pattern. A cover layer is formed covering the first pattern, the first spacer, the second pattern, and the third pattern. A part of the cover layer is removed for exposing the first pattern and the first spacer. The first spacer is removed, and a patterning process is performed to the first pattern transfer layer with the first pattern and the cover layer as a mask. The second pattern is patterned to be a fourth pattern by the patterning process.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: December 10, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee
  • Patent number: 10490110
    Abstract: A display apparatus includes, a first pattern included in a first layer, a second pattern included in a second layer, a first test pattern including a plurality of first lines extending in a first direction and having a first width, and being spaced apart from each other, a second test pattern included in the second layer, including a central line and a plurality of second lines connected to the central line, wherein the plurality of second lines extend in the first direction have a second width, and are spaced apart from each other, and wherein at least one of the second lines is electrically connected to the first lines, and a shift tester configured to apply a test voltage to the central line to determine a degree by which the second pattern is shifted with respect to the first pattern by measuring the voltages at the first lines.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: November 26, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jong-Hee Na, Hoisik Moon, Kang-Hyun Kim, Juneyoung Lee, Hyungwoo Yim, Jae-Seob Chung, Min-Yup Chae, Jae-Seok Choi, Hak-Mo Choi, Jung-Suk Han
  • Patent number: 10490590
    Abstract: Disclosed is a method of fabricating a semiconductor image sensor device. The method includes providing a substrate having a pixel region, a periphery region, and a bonding pad region. The substrate further has a first side and a second side opposite the first side. The pixel region contains radiation-sensing regions. The method further includes forming a bonding pad in the bonding pad region; and forming light-blocking structures over the second side of the substrate, at least in the pixel region, after the bonding pad has been formed.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: November 26, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chiu-Jung Chen, Chun-Hao Chou, Hsin-Chi Chen, Kuo-Cheng Lee, Volume Chien, Yung-Lung Hsu, Yun-Wei Cheng
  • Patent number: 10492290
    Abstract: A circuit board pad mounting orientation system includes a board. A signal transmission line is included on the board. A plurality of connector pads are positioned on the board. At least one connector pad receives the signal transmission line adjacent a first end of that connector pad. At least one connector pad includes a second end that provides a reduction in a width of that connector pad to indicate a mounting orientation for coupling to the connector pad that receives the signal transmission line. In a specific example, a first connector pad receives the signal transmission line, includes the first end, and includes the second end that is opposite the first connector pad from the first end and that provides the reduction in the width of the first connector pad to indicate the mounting orientation for coupling to the first connector pad.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: November 26, 2019
    Assignee: Dell Products L.P.
    Inventors: Umesh Chandra, Chun-Lin Liao, Bhyrav M. Mutnury
  • Patent number: 10474040
    Abstract: An overlay metrology system may measure a first-layer pattern placement distance between a pattern of device features and a pattern of reference features on a first layer of an overlay target on a sample. The system may further measure, subsequent to fabricating a second layer including at least the pattern of device features and the pattern of reference features, a second-layer pattern placement distance between the pattern of device features and the pattern of reference features on the second layer. The system may further measure a reference overlay based on relative positions of the pattern of reference features on the first layer and the second layer. The system may further determine a device-relevant overlay for the pattern of device-scale features by adjusting the reference overlay with a difference between the first-layer pattern placement distance and the second-layer pattern placement distance.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: November 12, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Frank Laske, Ulrich Pohlmann, Stefan Eyring, Nadav Gutman
  • Patent number: 10461038
    Abstract: Some embodiments include a semiconductor package. The semiconductor package has a semiconductor die with a primary region which includes integrated circuitry, and with an edge region which includes a portion of an alignment mark location. The portion of the alignment mark location includes a segment of an alignment mark. The alignment mark includes a pattern of lines and spaces, with the lines extending along a first direction. The portion of the alignment mark location also includes a texture having a pattern other than lines extending along either the first direction or along a second direction substantially orthogonal to the first direction. Some embodiments include methods for alignment marking semiconductor wafers.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: October 29, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Richard T. Housley, Jianming Zhou
  • Patent number: 10461247
    Abstract: Device and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first, second and third regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the first and second regions. A MRAM cell which includes a MTJ element sandwiched between top and bottom electrodes is formed in the second region. The bottom electrode is in direct contact with the metal line in the first upper interconnect level of the second region. A dielectric layer which includes a second upper interconnect level with a dual damascene interconnect in the first region and a damascene interconnect in the second region is provided over the first upper dielectric layer. The dual damascene interconnect in the first region is coupled to the metal line in the first region and the damascene interconnect in the second region is coupled to the MTJ element.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: October 29, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Danny Pak-Chum Shum, Juan Boon Tan, Yi Jiang, Wanbing Yi, Francis Yong Wee Poh, Hai Cong
  • Patent number: 10451666
    Abstract: Methods for enabling in-line detection of TS-PC short defects at the TS-CMP processing stage are provided. Embodiments include providing a semiconductor substrate, the substrate having a plurality of partially formed MOSFET devices; performing a first defect inspection on the substrate, the first inspection including ACC; identifying one or more BVC candidates on the substrate based on the first inspection; performing a second defect inspection on the one or more BVC candidates, the second inspection performed without ACC; and detecting one or more BVC defects on the substrate based on the one or more BVC candidates appearing during both the first and second inspections.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: October 22, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Ming Lei
  • Patent number: 10442729
    Abstract: A technical object of the present invention is to devise a glass sheet that facilitates position alignment with a substrate to be processed and is less liable to be broken during conveyance, or processing treatment of the substrate to be processed, to thereby contribute to an increase in density of a semiconductor package. In order to achieve the technical object, the glass sheet of the present invention includes, in a contour thereof: a contour portion; and a position alignment portion, in which all or part of an end edge region of the position alignment portion where a surface thereof and an end surface thereof intersect is chamfered.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: October 15, 2019
    Assignee: NIPPON ELECTRIC GLASS CO., LTD.
    Inventors: Hiroki Katayama, Hiroshi Nakajima
  • Patent number: 10439720
    Abstract: FPC-based optical interconnect modules with glass interposer connecting a VCSEL laser to a fiber ribbon cable is described. Improved optical coupling between VCSEL/PD and polymer waveguides are achieved by monolithically integrating micro-lenses and waveguides on the rear side of glass interposer and active devices on the front side. The waveguide has a vertical portion at one end of a horizontal trench portion joined by a 45 degree sidewall. A method of fabrication includes: providing a glass interposer, an array of micro lenses and an array of polymer waveguides having 45 degree tapered ends as reflectors on one surface, and depositing a metal layer and patterning the metal layer into transmission lines on the second surface of the glass substrate, growing bonding pillars for flip chip mounting and assembling active optical devices on the second surface of the glass to connect with the transmission lines.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: October 8, 2019
    Assignee: ADOLITE INC.
    Inventors: Abraham Jou, Paul Mao-Jen Wu
  • Patent number: 10439313
    Abstract: An integrated circuit (IC) chip socket that can include a non-conductive housing and moveable pogo pins positioned within the non-conductive housing. The moveable pogo pins can include active pogo pins, each active pogo pin being positioned to a corresponding lead of an IC chip insertable into the IC chip socket. Moveable pogo pins can also include an inactive pogo pin positioned to avoid contacting each lead of the IC chip insertable into the IC chip socket.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: October 8, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Dolores Babaran Milo, Michael Flores Milo
  • Patent number: 10431597
    Abstract: An RF electronic circuit comprising at least: a substrate comprising at least one support layer and a semiconducting surface layer located on the support layer; at least one electronic component able to carry out at least one of the RF signal transmission and/or reception and/or processing functions, and made in or on a first region of the surface layer; and a matrix of cavities located in at least one first region of the support layer located under the first region of the surface layer, facing at least the electronic component, and such that the internal volumes of the cavities are separated and isolated from each other by portions of the support layer.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: October 1, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Lucile Arnaud
  • Patent number: 10424543
    Abstract: A method of forming an overlay mark includes disposing a first feature of a plurality of first alignment segments extending along a first direction in a first layer, disposing a second feature of a plurality of second alignment segments extending along a second direction in a second layer over the first layer, and forming a third feature of a plurality of third alignment segments extending along the first direction and a plurality of fourth alignment segments extending along the second direction in a third layer over the second layer. In a plan view, each first alignment segment of the first alignment segments is adjacent to a corresponding third alignment segment of the third alignment segments along the first direction, and each second alignment segment of the second alignment segments is adjacent to a corresponding fourth alignment segment of the fourth alignment segments along the second direction.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: September 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Yu Chen, Ming-Feng Shieh, Ching-Yu Chang
  • Patent number: 10415963
    Abstract: Metrology methods and targets are provided, for estimating inter-cell process variation by deriving, from overlay measurements of at least three target cells having different designed misalignments, a dependency of a measured inaccuracy on the designed misalignments (each designed misalignment is between at least two overlapping periodic structures in the respective target cell). Inaccuracies which are related to the designed misalignments are reduced, process variation sources are detected and targets and measurement algorithms are optimized according to the derived dependency.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: September 17, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Tal Marciano, Eran Amit, Barak Bringoltz, Nuriel Amir, Amit Shaked
  • Patent number: 10388625
    Abstract: A press fitting head comprising an elastic member in a part where the press fitting head contacts a semiconductor device, and an alignment mark recognition area capable of detecting an optically readable marker provided on a surface to be contacted to the semiconductor device is provided. Additionally, a semiconductor manufacturing apparatus in which the press fitting head is applied is provided.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: August 20, 2019
    Assignee: J-Devices Corporation
    Inventor: Minoru Kai
  • Patent number: 10361161
    Abstract: A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: July 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
  • Patent number: 10304680
    Abstract: Methods of fabricating semiconductor devices having patterns with different feature sizes are provided. An example method includes: etching a first film layer below a patterned mask to form first and second features on a second film layer, forming respective first and second spacers adjacent to sidewalls of the first and second features on the second film layer, removing the first and second features to expose respective first and second portion of the second film layer, the second portion having a larger CD than the first portion, controlling an etching process such that the first portion is etched through and the second portion is protected from etching by a protective film formed during the etching process, and patterning a thin film masked by the first spacer, the second spacer, and the second portion to form smaller features and larger features in respective first and second regions of the thin film.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 28, 2019
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih-Hsiung Lee, Tzung-Ting Han
  • Patent number: 10290498
    Abstract: According to an embodiment, a first alignment mark includes a first template-side mark in which a plurality of first portions are arranged with a first period, and a second template-side mark in which a plurality of second portions are arranged with a second period. A second alignment mark includes a first wafer-side mark in which a plurality of third portions are arranged with a third period, and a second wafer-side mark in which a plurality of fourth portions are arranged with a fourth period. The first wafer-side mark and the first template-side mark are configured to be overlaid with each other to constitute a first moire mark. The second wafer-side mark and the second template-side mark are configured to be overlaid with each other to constitute a second moire mark. An average period of the first moire mark and an average period of the second moire mark are different from each other.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: May 14, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Satoshi Mitsugi, Takeshi Suto, Takashi Sato, Yukiyasu Arisawa
  • Patent number: 10283456
    Abstract: In some embodiments, the present disclosure relates a lithographic substrate marking tool. The lithographic substrate marking tool has a first lithographic exposure tool arranged within a shared housing and configured to generate a first type of electromagnetic radiation during a plurality of exposures. A mobile reticle has a plurality of different reticle fields respectively configured to block a portion of the first type of electromagnetic radiation to expose a substrate identification mark within a photosensitive material overlying a semiconductor substrate. A transversal element is configured to move the mobile reticle so that separate ones of the plurality of reticle fields are exposed onto the photosensitive material during separate ones of the plurality of exposures.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: May 7, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hu-Wei Lin, Chih-Hsien Hsu, Yu-Wei Chiu, Hai-Yin Chen, Ying-Hao Wang, Yu-Hen Wu
  • Patent number: 10274837
    Abstract: Metrology targets, design files, and design and production methods thereof are provided. The targets comprise two or more parallel periodic structures at respective layers, wherein a predetermined offset is introduced between the periodic structures, for example, opposite offsets at different parts of a target. Quality metrics are designed to estimate the unintentional overlay from measurements of a same metrology parameter by two or more alternative measurement algorithms. Target parameters are configured to enable both imaging and scatterometry measurements and enhance the metrology measurements by the use of both methods on the same targets. Imaging and scatterometry target parts may share elements or have common element dimensions. Imaging and scatterometry target parts may be combined into a single target area or may be integrated into a hybrid target using a specified geometric arrangement.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: April 30, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Eran Amit, Raviv Yohanan
  • Patent number: 10256436
    Abstract: An organic light-emitting diode (OLED) display and a method of manufacturing the same are disclosed. The OLED display comprises a substrate on which are defined a display area and a non-display area, an inorganic layer formed over the substrate, an encapsulation layer formed over the inorganic layer. A portion of the inorganic layer is formed over the non-display area, a portion of the encapsulation layer is formed over the non-display area, and a plurality of openings are formed in the portion of the encapsulation layer and the portion of the inorganic layer.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: April 9, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Kwang Nyun Kim
  • Patent number: 10163738
    Abstract: A partially fabricated semiconductor device includes a semiconductor overlay structure. The semiconductor overlay structure includes a first gate stack structure over the semiconductor substrate, the first gate stack structure being configured as an overlay mark in an overlay region of the semiconductor substrate. The semiconductor overlay structure further includes a doped region in the semiconductor substrate surrounding the first gate stack structure. The doped region has a first dopant concentration greater than or equal to a second dopant concentration next to a second gate stack structure in a device region of the semiconductor substrate.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Cheng Wang, Ming-Chang Wen, Chun-Kuang Chen, Yao-Ching Ku
  • Patent number: 10163806
    Abstract: A method is provided for fabricating a photolithography alignment mark structure. The method includes providing a substrate; forming a first grating, a second grating, a third grating and a fourth grating in the substrate; forming a photoresist layer on a surface of the substrate; obtaining a first alignment center along a first direction and a second alignment center alone a second direction based on the first grating and the fourth grating, respectively; providing a mask plate having a fifth grating pattern and a sixth grating pattern; aligning the mask plate with the substrate by using the first alignment center as an alignment center along the first direction and the second alignment center as an alignment center along the second direction; reproducing the fifth grating pattern and the sixth grating pattern in the photoresist layer; and forming a fifth grating and a sixth grating on the substrate by removing a portion of photoresist layer.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: December 25, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Boxiu Cai, Yi Huang
  • Patent number: 10115621
    Abstract: Methods for in-die overlay reticle measurement and the resulting devices are disclosed. Embodiments include providing parallel structures in a first layer on a substrate; determining measurement sites, in a second layer above the first layer, void of active integrated circuit elements; forming overlay trenches, in the measurement sites and parallel to the structures, exposing sections of the structures, wherein each overlay trench is aligned over a structure and over spaces between the structure and adjacent structures; determining a trench center-of-gravity of an overlay trench; determining a structure center-of-gravity of a structure exposed in the overlay trench; and determining an overlay parameter based on a difference between the trench center-of-gravity and the structure center-of-gravity.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: October 30, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Peter Moll, Martin Schmidt, Carsten Hartig, Matthias Ruhm, Stefan Thierbach, Stefan Rongen, Daniel Fischer, Andreas Schuring, Guido Überreiter
  • Patent number: 10096554
    Abstract: A mark is formed over the surface of a silicon substrate. The mark includes a silicon oxide film, in which a plurality of rectangular groove patterns are concentrically arranged, and a silicon nitride film formed in the groove patterns. A P-type epitaxial layer is formed over the surface of the silicon substrate. Then, a photoresist pattern is formed. In the photoresist pattern, a rectangular opening pattern is formed in a mark region. Optical superposition inspection is performed for the base of the photoresist pattern.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: October 9, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshikazu Tsunemine
  • Patent number: 10083914
    Abstract: An overlay mark is formed over a substrate. A plurality of first dummy features is formed outside the overlay mark in a top view. A plurality of second dummy features is formed closer to the overlay mark than the first dummy features in a top view. The first dummy features are sufficiently big to be visible to an optical machine used to scan the overlay mark. The second dummy features are sufficiently small to be invisible to the optical machine.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Wei-Chieh Huang