Alignment Marks Patents (Class 257/797)
  • Patent number: 10461038
    Abstract: Some embodiments include a semiconductor package. The semiconductor package has a semiconductor die with a primary region which includes integrated circuitry, and with an edge region which includes a portion of an alignment mark location. The portion of the alignment mark location includes a segment of an alignment mark. The alignment mark includes a pattern of lines and spaces, with the lines extending along a first direction. The portion of the alignment mark location also includes a texture having a pattern other than lines extending along either the first direction or along a second direction substantially orthogonal to the first direction. Some embodiments include methods for alignment marking semiconductor wafers.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: October 29, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Richard T. Housley, Jianming Zhou
  • Patent number: 10461247
    Abstract: Device and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first, second and third regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the first and second regions. A MRAM cell which includes a MTJ element sandwiched between top and bottom electrodes is formed in the second region. The bottom electrode is in direct contact with the metal line in the first upper interconnect level of the second region. A dielectric layer which includes a second upper interconnect level with a dual damascene interconnect in the first region and a damascene interconnect in the second region is provided over the first upper dielectric layer. The dual damascene interconnect in the first region is coupled to the metal line in the first region and the damascene interconnect in the second region is coupled to the MTJ element.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: October 29, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Danny Pak-Chum Shum, Juan Boon Tan, Yi Jiang, Wanbing Yi, Francis Yong Wee Poh, Hai Cong
  • Patent number: 10451666
    Abstract: Methods for enabling in-line detection of TS-PC short defects at the TS-CMP processing stage are provided. Embodiments include providing a semiconductor substrate, the substrate having a plurality of partially formed MOSFET devices; performing a first defect inspection on the substrate, the first inspection including ACC; identifying one or more BVC candidates on the substrate based on the first inspection; performing a second defect inspection on the one or more BVC candidates, the second inspection performed without ACC; and detecting one or more BVC defects on the substrate based on the one or more BVC candidates appearing during both the first and second inspections.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: October 22, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Ming Lei
  • Patent number: 10442729
    Abstract: A technical object of the present invention is to devise a glass sheet that facilitates position alignment with a substrate to be processed and is less liable to be broken during conveyance, or processing treatment of the substrate to be processed, to thereby contribute to an increase in density of a semiconductor package. In order to achieve the technical object, the glass sheet of the present invention includes, in a contour thereof: a contour portion; and a position alignment portion, in which all or part of an end edge region of the position alignment portion where a surface thereof and an end surface thereof intersect is chamfered.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: October 15, 2019
    Assignee: NIPPON ELECTRIC GLASS CO., LTD.
    Inventors: Hiroki Katayama, Hiroshi Nakajima
  • Patent number: 10439313
    Abstract: An integrated circuit (IC) chip socket that can include a non-conductive housing and moveable pogo pins positioned within the non-conductive housing. The moveable pogo pins can include active pogo pins, each active pogo pin being positioned to a corresponding lead of an IC chip insertable into the IC chip socket. Moveable pogo pins can also include an inactive pogo pin positioned to avoid contacting each lead of the IC chip insertable into the IC chip socket.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: October 8, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Dolores Babaran Milo, Michael Flores Milo
  • Patent number: 10439720
    Abstract: FPC-based optical interconnect modules with glass interposer connecting a VCSEL laser to a fiber ribbon cable is described. Improved optical coupling between VCSEL/PD and polymer waveguides are achieved by monolithically integrating micro-lenses and waveguides on the rear side of glass interposer and active devices on the front side. The waveguide has a vertical portion at one end of a horizontal trench portion joined by a 45 degree sidewall. A method of fabrication includes: providing a glass interposer, an array of micro lenses and an array of polymer waveguides having 45 degree tapered ends as reflectors on one surface, and depositing a metal layer and patterning the metal layer into transmission lines on the second surface of the glass substrate, growing bonding pillars for flip chip mounting and assembling active optical devices on the second surface of the glass to connect with the transmission lines.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: October 8, 2019
    Assignee: ADOLITE INC.
    Inventors: Abraham Jou, Paul Mao-Jen Wu
  • Patent number: 10431597
    Abstract: An RF electronic circuit comprising at least: a substrate comprising at least one support layer and a semiconducting surface layer located on the support layer; at least one electronic component able to carry out at least one of the RF signal transmission and/or reception and/or processing functions, and made in or on a first region of the surface layer; and a matrix of cavities located in at least one first region of the support layer located under the first region of the surface layer, facing at least the electronic component, and such that the internal volumes of the cavities are separated and isolated from each other by portions of the support layer.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: October 1, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Lucile Arnaud
  • Patent number: 10424543
    Abstract: A method of forming an overlay mark includes disposing a first feature of a plurality of first alignment segments extending along a first direction in a first layer, disposing a second feature of a plurality of second alignment segments extending along a second direction in a second layer over the first layer, and forming a third feature of a plurality of third alignment segments extending along the first direction and a plurality of fourth alignment segments extending along the second direction in a third layer over the second layer. In a plan view, each first alignment segment of the first alignment segments is adjacent to a corresponding third alignment segment of the third alignment segments along the first direction, and each second alignment segment of the second alignment segments is adjacent to a corresponding fourth alignment segment of the fourth alignment segments along the second direction.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: September 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Yu Chen, Ming-Feng Shieh, Ching-Yu Chang
  • Patent number: 10415963
    Abstract: Metrology methods and targets are provided, for estimating inter-cell process variation by deriving, from overlay measurements of at least three target cells having different designed misalignments, a dependency of a measured inaccuracy on the designed misalignments (each designed misalignment is between at least two overlapping periodic structures in the respective target cell). Inaccuracies which are related to the designed misalignments are reduced, process variation sources are detected and targets and measurement algorithms are optimized according to the derived dependency.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: September 17, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Tal Marciano, Eran Amit, Barak Bringoltz, Nuriel Amir, Amit Shaked
  • Patent number: 10388625
    Abstract: A press fitting head comprising an elastic member in a part where the press fitting head contacts a semiconductor device, and an alignment mark recognition area capable of detecting an optically readable marker provided on a surface to be contacted to the semiconductor device is provided. Additionally, a semiconductor manufacturing apparatus in which the press fitting head is applied is provided.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: August 20, 2019
    Assignee: J-Devices Corporation
    Inventor: Minoru Kai
  • Patent number: 10361161
    Abstract: A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: July 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
  • Patent number: 10304680
    Abstract: Methods of fabricating semiconductor devices having patterns with different feature sizes are provided. An example method includes: etching a first film layer below a patterned mask to form first and second features on a second film layer, forming respective first and second spacers adjacent to sidewalls of the first and second features on the second film layer, removing the first and second features to expose respective first and second portion of the second film layer, the second portion having a larger CD than the first portion, controlling an etching process such that the first portion is etched through and the second portion is protected from etching by a protective film formed during the etching process, and patterning a thin film masked by the first spacer, the second spacer, and the second portion to form smaller features and larger features in respective first and second regions of the thin film.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 28, 2019
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih-Hsiung Lee, Tzung-Ting Han
  • Patent number: 10290498
    Abstract: According to an embodiment, a first alignment mark includes a first template-side mark in which a plurality of first portions are arranged with a first period, and a second template-side mark in which a plurality of second portions are arranged with a second period. A second alignment mark includes a first wafer-side mark in which a plurality of third portions are arranged with a third period, and a second wafer-side mark in which a plurality of fourth portions are arranged with a fourth period. The first wafer-side mark and the first template-side mark are configured to be overlaid with each other to constitute a first moire mark. The second wafer-side mark and the second template-side mark are configured to be overlaid with each other to constitute a second moire mark. An average period of the first moire mark and an average period of the second moire mark are different from each other.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: May 14, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Satoshi Mitsugi, Takeshi Suto, Takashi Sato, Yukiyasu Arisawa
  • Patent number: 10283456
    Abstract: In some embodiments, the present disclosure relates a lithographic substrate marking tool. The lithographic substrate marking tool has a first lithographic exposure tool arranged within a shared housing and configured to generate a first type of electromagnetic radiation during a plurality of exposures. A mobile reticle has a plurality of different reticle fields respectively configured to block a portion of the first type of electromagnetic radiation to expose a substrate identification mark within a photosensitive material overlying a semiconductor substrate. A transversal element is configured to move the mobile reticle so that separate ones of the plurality of reticle fields are exposed onto the photosensitive material during separate ones of the plurality of exposures.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: May 7, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hu-Wei Lin, Chih-Hsien Hsu, Yu-Wei Chiu, Hai-Yin Chen, Ying-Hao Wang, Yu-Hen Wu
  • Patent number: 10274837
    Abstract: Metrology targets, design files, and design and production methods thereof are provided. The targets comprise two or more parallel periodic structures at respective layers, wherein a predetermined offset is introduced between the periodic structures, for example, opposite offsets at different parts of a target. Quality metrics are designed to estimate the unintentional overlay from measurements of a same metrology parameter by two or more alternative measurement algorithms. Target parameters are configured to enable both imaging and scatterometry measurements and enhance the metrology measurements by the use of both methods on the same targets. Imaging and scatterometry target parts may share elements or have common element dimensions. Imaging and scatterometry target parts may be combined into a single target area or may be integrated into a hybrid target using a specified geometric arrangement.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: April 30, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Eran Amit, Raviv Yohanan
  • Patent number: 10256436
    Abstract: An organic light-emitting diode (OLED) display and a method of manufacturing the same are disclosed. The OLED display comprises a substrate on which are defined a display area and a non-display area, an inorganic layer formed over the substrate, an encapsulation layer formed over the inorganic layer. A portion of the inorganic layer is formed over the non-display area, a portion of the encapsulation layer is formed over the non-display area, and a plurality of openings are formed in the portion of the encapsulation layer and the portion of the inorganic layer.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: April 9, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Kwang Nyun Kim
  • Patent number: 10163738
    Abstract: A partially fabricated semiconductor device includes a semiconductor overlay structure. The semiconductor overlay structure includes a first gate stack structure over the semiconductor substrate, the first gate stack structure being configured as an overlay mark in an overlay region of the semiconductor substrate. The semiconductor overlay structure further includes a doped region in the semiconductor substrate surrounding the first gate stack structure. The doped region has a first dopant concentration greater than or equal to a second dopant concentration next to a second gate stack structure in a device region of the semiconductor substrate.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Cheng Wang, Ming-Chang Wen, Chun-Kuang Chen, Yao-Ching Ku
  • Patent number: 10163806
    Abstract: A method is provided for fabricating a photolithography alignment mark structure. The method includes providing a substrate; forming a first grating, a second grating, a third grating and a fourth grating in the substrate; forming a photoresist layer on a surface of the substrate; obtaining a first alignment center along a first direction and a second alignment center alone a second direction based on the first grating and the fourth grating, respectively; providing a mask plate having a fifth grating pattern and a sixth grating pattern; aligning the mask plate with the substrate by using the first alignment center as an alignment center along the first direction and the second alignment center as an alignment center along the second direction; reproducing the fifth grating pattern and the sixth grating pattern in the photoresist layer; and forming a fifth grating and a sixth grating on the substrate by removing a portion of photoresist layer.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: December 25, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Boxiu Cai, Yi Huang
  • Patent number: 10115621
    Abstract: Methods for in-die overlay reticle measurement and the resulting devices are disclosed. Embodiments include providing parallel structures in a first layer on a substrate; determining measurement sites, in a second layer above the first layer, void of active integrated circuit elements; forming overlay trenches, in the measurement sites and parallel to the structures, exposing sections of the structures, wherein each overlay trench is aligned over a structure and over spaces between the structure and adjacent structures; determining a trench center-of-gravity of an overlay trench; determining a structure center-of-gravity of a structure exposed in the overlay trench; and determining an overlay parameter based on a difference between the trench center-of-gravity and the structure center-of-gravity.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: October 30, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Peter Moll, Martin Schmidt, Carsten Hartig, Matthias Ruhm, Stefan Thierbach, Stefan Rongen, Daniel Fischer, Andreas Schuring, Guido Überreiter
  • Patent number: 10096554
    Abstract: A mark is formed over the surface of a silicon substrate. The mark includes a silicon oxide film, in which a plurality of rectangular groove patterns are concentrically arranged, and a silicon nitride film formed in the groove patterns. A P-type epitaxial layer is formed over the surface of the silicon substrate. Then, a photoresist pattern is formed. In the photoresist pattern, a rectangular opening pattern is formed in a mark region. Optical superposition inspection is performed for the base of the photoresist pattern.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: October 9, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshikazu Tsunemine
  • Patent number: 10083914
    Abstract: An overlay mark is formed over a substrate. A plurality of first dummy features is formed outside the overlay mark in a top view. A plurality of second dummy features is formed closer to the overlay mark than the first dummy features in a top view. The first dummy features are sufficiently big to be visible to an optical machine used to scan the overlay mark. The second dummy features are sufficiently small to be invisible to the optical machine.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Wei-Chieh Huang
  • Patent number: 10068881
    Abstract: Provided are a package-on-package type semiconductor package and a method of fabricating the same. The semiconductor package includes upper package stacked on a lower package and a via provided between the lower and upper packages to electrically connect the lower and upper packages to each other. The lower package includes a lower package substrate, a lower semiconductor chip mounted on the lower package substrate, and a lower mold layer encapsulating the lower semiconductor chip and including an alignment mark. The lower mold layer includes a marking region, which is provided between the via and the lower semiconductor chip, and on which the alignment mark is provided.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: September 4, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Heungkyu Kwon
  • Patent number: 10054863
    Abstract: The invention relates to a substrate comprising an optical position mark for being read-out by an optical recording head for emitting light of predetermined wavelength, preferably red or infra-red light, more in particular of 635 nm light, the optical position mark having a mark height, a mark length and a predetermined known position on the substrate, the optical position mark extending along a longitudinal direction and being arranged for varying a reflection coefficient of the position mark along said longitudinal direction, wherein the optical position mark comprises: a first region having a first reflection coefficient and a first width; a second region neighboring the first region and forming a first region pair, the second region having a second reflection coefficient and a second width, and the second reflection coefficient being different from the first reflection coefficient, wherein the first region comprises sub-wavelength structures in comparison with a wavelength of the predetermined waveleng
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: August 21, 2018
    Assignee: MAPPER LITHOGRAPHY IP B.V.
    Inventors: Guido De Boer, Niels Vergeer
  • Patent number: 10043835
    Abstract: A method for producing a display device includes locating a substrate, including a plurality of pixels, on a jig including a magnet; locating a plate formed of a magnetic material on the substrate to secure the substrate; and folding back an end portion of the substrate in a state where the substrate is held between the jig and the plate.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: August 7, 2018
    Assignee: Japan Display Inc.
    Inventor: Takashi Saeki
  • Patent number: 9994042
    Abstract: A novel print engraving substrate is provided that when used with a cutting plotter, is able to improve the functioning of the cutting plotter. In some embodiments, a print engraving substrate may comprise a print engraving material forming a top surface; an adhesive material coupled to the print engraving material opposite to the top surface; a print engraving area disposed on the top surface; and a registration area disposed on the top surface which may receive one or more registration marks. The print engraving area may be configured to receive indicia such as cutting indicia which may be applied by a printer. The registration area may lack one or more colors or textures applied to the print engraving area thereby facilitating or allowing an optical scanner of a cutting plotter to detect registration marks on a substrate comprising a colored and/or textured print engraving area.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: June 12, 2018
    Inventor: Victor Manuel Sud Arce
  • Patent number: 9966437
    Abstract: Included are the steps of: preparing a silicon carbide substrate having an epitaxial layer formed thereon; forming an upper-layer film on the epitaxial layer; and removing at least a portion of the upper-layer film in an outer peripheral portion of the silicon carbide substrate, and patterning the upper-layer film.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: May 8, 2018
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Taku Horii
  • Patent number: 9964855
    Abstract: A method is disclosed that includes forming at least one substrate alignment mark and at least one lithography alignment mark in a substrate; forming a seed layer on the substrate; and forming a guide pattern and at least one guide pattern alignment mark in the seed layer, where the at least one guide pattern alignment mark is formed over the at least one substrate alignment mark. The method further includes determining an alignment error of the at least one guide pattern alignment mark relative to the at least one substrate alignment mark; and patterning features on at least one region of the substrate, where the features are positioned on the substrate based on the at least one lithography alignment mark and the alignment error.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: May 8, 2018
    Assignee: Seagate Technology LLC
    Inventors: HongYing Wang, Kim Y. Lee, Yautzong Hsu, Nobuo Kurataka, Gennady Gauzner, Shuaigang Xiao
  • Patent number: 9960123
    Abstract: The present invention provides a method of forming a semiconductor structure. A wafer with a dicing region is provided, the dicing region comprises a central region, a middle region surrounds the central region, and a peripheral region surrounds the middle region. Next, an aligning mark is formed in the dicing region, wherein the aligning mark is a mirror symmetrical pattern and comprises a plurality of second patterns in the middle region and a plurality of third patterns in the third region, each third pattern has a plurality of lines and the lines comprises a plurality of inner lines which are formed by a sidewall image transfer (SIT) process.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: May 1, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ying-Chiao Wang, Yu-Hsiang Hung, Chao-Hung Lin, Ssu-I Fu, Chih-Kai Hsu, Jyh-Shyang Jenq
  • Patent number: 9941218
    Abstract: A display apparatus is provided including a display panel displaying an image, and a driving chip including a front surface and a rear surface provided with a first marking code, the driving chip being electrically connected with the display panel. The display panel includes an upper substrate, and a lower substrate located facing the upper substrate to include a second marking code, and including a first surface and a second surface facing the first surface. The driving chip is located on the second surface such that a rear surface thereof is closer to the second surface than to the front surface thereof, and wherein the second marking code is provided on the second surface.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: April 10, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jae-kyoung Kim
  • Patent number: 9885961
    Abstract: The present disclosure is directed to overlay metrology with targets including “disappearing” or sacrificial layers that leave no optical trace impacting OVL measurement when processed. In an embodiment, an overlay metrology target may include at least one overlay target structure inducing an optical characteristic and at least one secondary overlay target structure inducing a temporary optical characteristic. The at least one secondary overlay target structure being removable by a lithographic process and/or by etch or clean process, where removal of the at least one secondary overlay target structure removes the temporary optical characteristic. That is, the secondary target structure or “layer” leaves no optical trace impacting OVL measurement when removed, thereby allowing another target structure (e.g., a tertiary target structure or layer) to be printed in a region previously occupied by at least a portion of the secondary target structure.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: February 6, 2018
    Assignee: KLA-Tencor Corporation
    Inventor: Nuriel Amir
  • Patent number: 9876265
    Abstract: The present invention relates to a method of manufacturing a metal foil laminate which may be used for example to produce an antenna for a radio frequency (RFID) tag, electronic circuit, photovoltaic module or the like. A web of material is provided to at least one cutting station in which a first pattern is generated in the web of material. A further cutting may occur to create additional modifications in order to provide additional features for the intended end use of the product. The cutting may be performed by a laser either alone or in combinations with other cutting technologies.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: January 23, 2018
    Assignee: AVERY DENNISON RETAIL INFORMATION SERVICES, LLC
    Inventors: Ian J. Forster, Christian K. Oelsner, Robert Revels, Benjamin Kingston, Peter Cockerell, Moris Amon, Norman Howard
  • Patent number: 9870998
    Abstract: Among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly layer or an inter layer dielectric (ILD) layer, is formed over a substrate. A photoresist mask is formed over the layer. The photoresist mask comprises an open region overlaying a target region of the layer and comprises a protection region overlaying a second region of the layer. An etching process is performed through the open region to reduce a height of the layer in the target region in relation to a height of the layer in the second region because the protection region inhibits the etching process from affecting the layer in the second region. A first structure, having a first height, is formed within the target region. A second structure, having a second height greater than the first height, is formed within the second region.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: January 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Tsung-Yu Chiang, Chen Kuang-Hsin, Bor-Zen Tien, Tzong-Sheng Chang
  • Patent number: 9870525
    Abstract: A semiconductor laser element includes a substrate having a first main surface and a second main surface; a semiconductor layered body including an active layer, the semiconductor layered body being disposed on the first main surface; and a plurality of sub-patterns that, when combined, form an integrated pattern that allows reading of predetermined information, the plurality of sub-patterns being disposed on either one or both a first main surface side and a second main surface side of the substrate.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: January 16, 2018
    Assignee: NICHIA CORPORATION
    Inventors: Atsushi Tanaka, Mitsuhiro Nonaka
  • Patent number: 9865574
    Abstract: A method includes aligning a top package to a bottom package using an alignment mark in the bottom package, and placing the top package over the bottom package, wherein the top package is aligned to the bottom package after the placing the top package over the bottom package. A reflow is then performed to bond the top package to the bottom package.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: January 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Wei Huang, Chih-Wei Lin, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9859223
    Abstract: Dicing structures for semiconductor substrates and methods of fabrication thereof are described. In one embodiment, a semiconductor wafer includes a first chip disposed in a substrate, a second chip disposed adjacent the first chip and disposed in the substrate, and a dicing street disposed between the first and the second chip. A first and a second metal level are disposed over the dicing street, wherein the second metal level is disposed above the first metal level. A first alignment mark is disposed in the first metal level above a first portion of the dicing street, and first metal features disposed in the second metal level above the first portion of the dicing street.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 9841688
    Abstract: A method for detecting an overlay error includes: forming a first overlay key including a plurality of spaced apart first target patterns having a first pitch on a first layer of a substrate; forming a second overlay key including a plurality of spaced apart second target patterns having a second pitch different than the first pitch on a second layer of the substrate below the first layer; irradiating the first layer and the second layer with incident light having a first wavelength; obtaining a phase pattern of light reflected from the first layer and the second layer; calculating a position of a peak point or a valley point of the phase pattern of the reflected light; and detecting an overlay error of the first layer and the second layer using the position of the peak point or the valley point of the phase pattern.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: December 12, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kang-Woong Ko, Hyoung-Jo Jeon, Masahiro Horie, Gil-Woo Song
  • Patent number: 9841686
    Abstract: An exposure method includes exposing a substrate to form a first pattern on a first layer, measuring a first alignment value of the first pattern, generating first correction data by using the first alignment value, storing the first correction data and exposing the substrate to form a second pattern on a second layer disposed on the first layer by using the first correction data.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: December 12, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ik-Han Oh, Seung-Kyu Lee, Hyeon-Min Cho
  • Patent number: 9810917
    Abstract: Passive dampers (e.g., a viscoelastic material such as a silicon gel) may be applied at one or more locations within an actuator module between a moving component (an optics assembly) and a fixed component (e.g., a cover attached to a base). The passive dampers act to passively dampen the motion of the optics assembly on the XY plane within the actuator module during optical image stabilization (OIS) of the optics assembly when subjected to external excitation or disturbance, and may also provide Z (optical) axis damping and impact protection. Process control and automation manufacturing and assembly methods for an OIS voice coil motor (VCM) actuator module including passive dampers are described, as well as design elements that provide for the integrity and reliability of the passive dampers over the life cycle of the actuator module.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: November 7, 2017
    Assignee: Apple Inc.
    Inventors: Aurelien R. Hubert, Douglas S. Brodie
  • Patent number: 9779202
    Abstract: Systems and methods to detect, quantify, and control process-induced asymmetric signatures using patterned wafer geometry measurements are disclosed. The system may include a geometry measurement tool configured to obtain a first set of wafer geometry measurements of the wafer prior to the wafer undergoing a fabrication process and to obtain a second set of wafer geometry measurements of the wafer after the fabrication process. The system may also include a processor in communication with the geometry measurement tool. The processor may be configured to: calculate a geometry-change map based on the first set of wafer geometry measurements and the second set of wafer geometry measurements; analyze the geometry-change map to detect an asymmetric component induced to wafer geometry by the fabrication process; and estimate an asymmetric overlay error induced by the fabrication process based on the asymmetric component detected in wafer geometry.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: October 3, 2017
    Assignee: KLA-Tencor Corporation
    Inventors: Pradeep Vukkadala, Jaydeep Sinha, Jong-Hoon Kim
  • Patent number: 9773739
    Abstract: The present disclosure provides mark structures and fabrication methods thereof. An exemplary fabrication process includes providing a substrate having a device region, a first mark region and a second mark region; sequentially forming a device layer, a dielectric layer and a mask layer on a surface of the substrate; forming a first opening in the dielectric layer in the device region, a first mark in the dielectric layer in the first mark region, and a mark opening in dielectric layer in the second mark region, bottoms of the first opening, the first mark and the mark opening being lower than a surface of the dielectric layer, and higher than a surface of the device layer; and forming a second opening in the dielectric layer on the bottom of the first opening and a second mark in the dielectric layer on the bottom of the mark opening.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: September 26, 2017
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Dao Liang Lu, Hong Wei Zhang, Kui Feng
  • Patent number: 9761603
    Abstract: The inventive concepts provide methods for fabricating a semiconductor device and semiconductor devices fabricated by the same. According to the method, conductive lines having a fine pitch smaller than the minimum pitch realized by an exposure process may be formed using two or three photolithography processes and two spacer formation processes. In addition, node separation regions of the conductive lines may be easily formed without a misalignment problem.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: September 12, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Sung Song, Jae-Hwang Sim, Joon-Sung Lim
  • Patent number: 9746786
    Abstract: An overlay mask includes a plurality of first patterns, a plurality of second patterns and a plurality of third patterns. The first patterns are arranged within a first pitch. The second patterns are arranged within a second pitch. A first portion of the third patterns are arranged alternately with the first patterns, within the first pitch, and a second portion of the third patterns are arranged alternately with the second patterns, within the second pitch, and the first pitch is not equal to the second pitch.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: August 29, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Che-Yi Lin, En-Chiuan Liou, Yi-Jing Wang, Chia-Hsun Tseng
  • Patent number: 9746785
    Abstract: Measurement targets for use on substrates, and overlay targets are presented. The targets include an array of first regions alternating with second regions, wherein the first regions include structures oriented in a first direction and the second regions include structures oriented in a direction different from the first direction. The effective refractive index of the two sets of regions are thereby different when experienced by a polarized beam, which will act as a TM-polarized beam when reflected from the first set of regions, but as a TE-polarized beam when reflected from the second set of regions.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: August 29, 2017
    Assignee: ASML Netherlands B.V.
    Inventors: Maurits Van Der Schaar, Marcus Adrianus Van De Kerkhof, Sami Musa
  • Patent number: 9721901
    Abstract: Disclosed is a thin-film transistor substrate including: a substrate; a thin-film transistor formed on the substrate and including an active layer, a gate electrode, a source electrode, and a drain electrode; an identification (ID) mark formed on the substrate; and a metal layer contacting an upper surface of the ID mark.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: August 1, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jihyeon Ryu
  • Patent number: 9711395
    Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: July 18, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Su Kim, Dong-Woon Park, Tae-Hoi Park, Yong-Kug Bae, Tae-Hwan Oh, Chang-Hoon Lee, Boo-Hyun Ham
  • Patent number: 9685411
    Abstract: Dies having alignment marks and methods of forming the same are provided. A method includes forming a device on a substrate. A plurality of contact pads is formed over the substrate and the device. Simultaneously with forming the plurality of contact pads, one or more alignment marks are formed over the substrate and the device.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: June 20, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 9633925
    Abstract: Structures and methods for improving the visualization of alignment marks on an underfill-covered chip. A feature is formed on a chip, and an underfill material is applied to the chip at a wafer level so that the feature is covered the feature. The feature includes a first structural element comprised of a first material and a second structural element comprised of a second material that is electrochemically dissimilar from the first material to provide a galvanic cell effect. Filler particles in the underfill material are caused by the galvanic cell effect to distribute with a first density in a first region over the first structural element and a second region of a second density over the second structural element. The first density in the first region is less than the second density in the second region such that the first region has a lower opacity than the second region.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: April 25, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Katsuyuki Sakuma, Mukta G. Farooq, Jae-Woong Nah
  • Patent number: 9620380
    Abstract: A method for fabricating an integrated circuit includes providing an semiconductor wafer includes forming in an upper mandrel layer a first upper mandrel having a first critical dimension and a second upper mandrel having a second critical dimension; forming upper sidewall spacers along sidewalls of the first upper mandrel while leaving the second upper mandrel without sidewall spacers; removing the first upper mandrel from between the upper sidewall spacers; transferring a pattern of the upper sidewall spacers and of the second upper mandrel into a lower mandrel layer to form first lower mandrels according to the pattern of the upper sidewall spacers and a second lower mandrel according to the pattern of the second upper mandrel; and forming lower sidewall spacers along sidewalls of the first and second lower mandrels.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: April 11, 2017
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Xintuo Dai, Huang Liu, Jin Ping Liu, Jiong Li
  • Patent number: 9583708
    Abstract: A mask for deposition includes a mask main body extended in a first direction and having a first thickness, and including ends opposite to each other in the first direction and supported by a frame while a tensile force is applied to the mask in the first direction; and a plurality of active patterns separated from each other in the first direction in a center area of the mask main body, and having a second thickness less than the first thickness.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: February 28, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Jung-Woo Ko
  • Patent number: 9583344
    Abstract: Provided are methods of trimming photoresist patterns. The methods involve coating a photoresist trimming composition over a photoresist pattern, wherein the trimming composition includes a matrix polymer, a thermal acid generator and a solvent, the trimming composition being free of cross-linking agents. The coated semiconductor substrate is heated to generate an acid in the trimming composition from the thermal acid generator, thereby causing a change in polarity of the matrix polymer in a surface region of the photoresist pattern. The photoresist pattern is contacted with a developing solution to remove the surface region of the photoresist pattern. The methods find particular applicability in the formation of very fine lithographic features in the manufacture of semiconductor devices.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: February 28, 2017
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventor: Cheng-Bai Xu