Abstract: In some embodiments, the present disclosure relates to a wafer edge trimming apparatus that includes a processing chamber defined by chamber housing. Within the processing chamber is a wafer chuck configured to hold onto a wafer structure. Further, a blade is arranged near an edge of the wafer chuck and configured to remove an edge potion of the wafer structure and to define a new sidewall of the wafer structure. A laser sensor apparatus is configured to direct a laser beam directed toward a top surface of the wafer chuck. The laser sensor apparatus is configured to measure a parameter of an analysis area of the wafer structure. Control circuitry is to the laser sensor apparatus and the blade. The control circuitry is configured to start a damage prevention process when the parameter deviates from a predetermined threshold value by at least a predetermined shift value.

Abstract: A device area includes at least a first layer of photoresist and a second layer of photoresist. First layer metrology targets are positioned at an edge of one of the sides of the first layer of the mat. The first layer metrology targets have a relaxed pitch less than a device pitch. Secondary electron and back-scattered electron images can be simultaneously obtained.

Abstract: The present invention relates to a chip transfer device capable of floatingly positioning a chip and a method for floatingly positioning a chip. When a chip is placed in a chip socket, a control unit controls an air pressure switching valve to allow at least one vent hole to be communicated with a positive air pressure source. An air flow from the positive air pressure source blows a lower surface of the chip through the vent hole, so that the at least one chip is air-floated. Accordingly, when the chip socket is communicated with the positive air pressure source, the air flow blows the lower surface of the chip in the chip socket through the vent hole, so that the chip is air-floated in the chip socket to reduce the error displacement of the chip offset.

Abstract: Herein disclosed are a surface topography measuring system and a method thereof. The method comprises the following steps: dividing a test beam into a first sub-beam, entering a reflecting mirror along a first axis, and a second sub-beam, entering an object surface along a second axis; moving the reflecting mirror for reflecting the first sub-beam at different positions on the first axis to generate N reflected beams; generating an object reflected beam, related to the second sub-beam, reflected from the object surface; generating N images, related to the N reflected beams and the object reflected beam, and each of the N images having a plurality of interference fringes; analyzing the interference fringes in each of the N images to calculate N curve formulas; calculating a surface topography of the object surface from the N curve formulas.

Abstract: The present application provides an overlay measuring apparatus, adapted to determine relative positions of two or more successive patterned layers of a device. The overlay measuring apparatus includes a stage and an imaging assembly. The device is placed on the stage. The imaging assembly includes a plurality of optical heads and a plurality of overlay marks assembled on the optical heads. The relative positions of the two or more successive patterned layers of the device are determined using light reflected from the device and passing through the overlay mark mounted on the respective optical head.

Abstract: Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a first power delivery network (PDN) structure, and a first semiconductor device tier disposed over and electrically connected to the first PDN structure. The multi-tier semiconductor structure can further include a signal wiring tier disposed over and electrically connected to the first semiconductor device tier, a second semiconductor device tier disposed over and electrically connected to the signal wiring tier, and a second PDN structure disposed over and electrically connected to the second semiconductor device tier. The multi-tier semiconductor structure can further include a through-silicon via (TSV) structure electrically connected to the signal wiring tier, wherein the TSV structure penetrates the second PDN structure.

Abstract: A method for aligning a substrate for fabrication of an optical device is disclosed that includes receiving a substrate having a first side and a second side opposite the first side, the first side of the substrate being oriented towards a scanner, the substrate having an alignment mark formed on the first side of the substrate, scanning the alignment mark with the scanner, and fabricating a first pattern for a first optical device on the first side of the substrate. The method includes positioning the substrate such that the second side is oriented toward the scanner, scanning the alignment mark on the first side with the scanner, through the second side, and fabricating a second pattern for a fourth optical device on the second side of the substrate.

Abstract: Embodiments of the present disclosure provide an integrated circuit die having edge interconnect features. The edge interconnect features may be conductive lines extending through sealing rings and exposed on edge surfaces of the integrated circuit die. The edge interconnect features are configured to connect with other integrated circuit dies without going through an interposer. The semiconductor device may include two or more integrated circuit dies with edge interconnect features and connected through one or more inter-chip connectors formed between the two or more integrated circuit dies. In some embodiments, the inter-chip connectors may be formed by a selective bumping process during packaging.

Abstract: Combined electron beam overlay and scatterometry overlay targets include first and second periodic structures with gratings. Gratings in the second periodic structure can be positioned under the gratings of the first periodic structure or can be positioned between the gratings of the first periodic structure. These overlay targets can be used in semiconductor manufacturing.

Abstract: A wiring board includes: a substrate having transparency; a plurality of first wirings which are arranged on an upper surface of the substrate and extend in a first direction and each of which has a back surface in contact with the substrate and a front surface facing an opposite side of the back surface; and has a back surface in contact with the substrate and a front surface facing an opposite side of the back surface. The first wiring has a pair of side surfaces which extend in the first direction and are adjacent to the back surface of the first wiring, and each of the pair of side surfaces of the second wiring is recessed inward. The second wiring has a pair of side surfaces which extend in the second direction and are adjacent to the back surface of the second wiring.

Abstract: A package structure includes a plurality of semiconductor die, an insulating encapsulant and a redistribution layer. Each of the plurality of semiconductor dies includes a semiconductor substrate, conductive pads disposed on the semiconductor substrate, conductive posts disposed on the conductive pads, and at least one alignment mark located on the semiconductor substrate. The insulating encapsulant is encapsulating the plurality of semiconductor dies. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the plurality of semiconductor dies.

Abstract: Apparatus and methods are disclosed, including memory devices and systems. In an example, a memory module can include a first stack of at least eight memory die including four pairs of memory die, each pair of the four pairs of memory die associated with an individual memory rank of four memory ranks of the memory module, a memory controller configured to receive memory access commands and to access memory locations of the first stack, and a substrate configured to route connections between external terminations of the memory module and the memory controller.

Abstract: An imaging optical system includes an imaging device and an optical waveguide. The waveguide includes structures configured to couple light from an external environment into the waveguide. The structures direct the light to propagate in the waveguide via total internal reflection and towards the imaging device.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.

Abstract: A control system for an operable system such as a flow control system or temperature control system. The system operates in a control loop to regularly update a model with respect at least one optimizable input variable based on the detected variables. The model provides prediction of use of the input variables in all possible operation points or paths of the system variables which achieve an output setpoint. In some example embodiments, the control loop is performed during initial setup and subsequent operation of the one or more operable elements in the operable system. The control system is self-learning in that at least some of the initial and subsequent parameters of the system are determined automatically during runtime.

Abstract: A display substrate has a display area and a peripheral area. The display substrate includes a base, a first insulating layer disposed above the base, a first alignment pattern disposed in the peripheral area on a surface of the first insulating layer facing away from the base, and a second alignment pattern disposed in the peripheral area at a side of the first insulating layer away from the base. An orthographic projection of the second alignment pattern on the base and an orthographic projection of the first alignment pattern on the base have a non-overlapping region therebetween, and the second alignment pattern is in contact with the first insulating layer in the non-overlapping region. Adhesion between the second alignment pattern and the first insulating layer is greater than adhesion between the second alignment pattern and the first alignment pattern.

Abstract: The present disclosure provides a semiconductor structure having a first wafer including a first substrate, a first dielectric layer over the first substrate, and a first conductive pad surrounded by the first dielectric layer; a second wafer including a second dielectric layer, a second substrate over the second dielectric layer, and a second conductive pad surrounded by the second dielectric layer; a bonding dielectric disposed between the first dielectric layer and the second dielectric layer to bond the first dielectric layer with the second dielectric layer; and a conductive via extending from the first conductive pad and surrounded by the bonding dielectric, the second conductive pad and the second wafer.

Abstract: A diffraction measurement target that has at least a first sub-target and at least a second sub-target, and wherein (1) the first and second sub-targets each include a pair of periodic structures and the first sub-target has a different design than the second sub-target, the different design including the first sub-target periodic structures having a different pitch, feature width, space width, and/or segmentation than the second sub-target periodic structure or (2) the first and second sub-targets respectively include a first and second periodic structure in a first layer, and a third periodic structure is located at least partly underneath the first periodic structure in a second layer under the first layer and there being no periodic structure underneath the second periodic structure in the second layer, and a fourth periodic structure is located at least partly underneath the second periodic structure in a third layer under the second layer.

Abstract: An apparatus associated with an analysis of a thin film layer comprises two layer structures (100, 102) with a cavity (104) therebetween, and an opening (110) through one of the layer structures (102) to the cavity (104), the cavity (104) being configured to receive, through the opening (110), material used to form a thin film layer (900) inside the cavity (104). At least one of the two layer structures (100, 102) comprises at least one positional indicator (108) for an analysis associated with the thin film layer (900).

Abstract: An electronic device includes a first sensing insulation layer having a first opening defined thereon, a first sensing electrode including a first sensing pattern and a first connection pattern connected to each other, a second sensing electrode including a second sensing pattern spaced apart from the first sensing pattern and a second connection pattern connected to the second sensing pattern and on a different layer from the first connection pattern with the first sensing insulation layer interposed therebetween, sensing lines connected to the first sensing electrode and the second sensing electrode, respectively, a pad unit including sensing pads connected to a corresponding sensing line selected from among the sensing lines, and an input sensing unit including an align key, wherein the align key is exposed through the first sensing insulation layer by the first opening.

Abstract: Various semiconductor chips with solder capped probe test pads are disclosed. In accordance with one aspect of the present invention, a semiconductor chip is provided that includes a substrate, plural input/output (I/O) structures on the substrate and plural test pads on the substrate. Each of the test pads includes a first conductor pad and a first solder cap on the first conductor pad.

Abstract: A semiconductor structure and a method for forming the same are provided.

Abstract: A device may include a wavelength converting layer on an epitaxial layer. The wavelength converting layer may include a first surface having a width that is equal to a width of the epitaxial layer, a second surface having a width that is less than the width of the first surface, and angled sidewalls. A conformal non-emission layer may be formed on the angled sidewalls and sidewalls of the epitaxial layer, such that the second surface of the wavelength converting layer is exposed.

Abstract: A method of measuring misregistration in the manufacture of semiconductor device wafers including providing a multilayered semiconductor device wafer including at least a first layer and a second layer including at least one misregistration measurement target including a first periodic structure formed together with the first layer having a first pitch and a second periodic structure formed together with the second layer having a second pitch, imaging the first layer and the second layer at a depth of focus and using light having at least one first wavelength that causes images of both the first layer and the second layer to appear in at least one plane within the depth of focus and quantifying offset in the at least one plane between the images of the first layer and the second layer, thereby to calculate misregistration of the first layer and the second layer.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body disposed in a first tier, the stacked body including a plurality of conductive layers stacked via an insulating layer; a first pillar that extends in the stacked body in a stacking direction of the stacked body; a first upper structure disposed in a second tier upper than the first tier; and a misalignment mark for inspecting misalignment between the first tier and the second tier, wherein the misalignment mark includes a second pillar that extends the first tier of the misalignment inspection region in the stacking direction, and a second upper structure disposed in the second tier of the misalignment inspection region and superposed on the second pillar in a top view.

Abstract: A method for manufacturing an optical sensor is provided. The method comprises providing an optical sensor arrangement which comprises at least two optical sensor elements on a carrier, where the optical sensor arrangement comprises a light entrance surface at the side of the optical sensor elements facing away from the carrier. The method further comprises forming a trench between two optical sensor elements in a vertical direction which is perpendicular to the main plane of extension of the carrier, where the trench extends from the light entrance surface of the sensor arrangement at least to the carrier. Moreover, the method comprises coating the trench with an opaque material, forming electrical contacts for the at least two optical sensor elements on a back side of the carrier facing away from the optical sensor elements, and forming at least one optical sensor by dicing the optical sensor arrangement along the trench.

Abstract: A method includes placing a first package component and a second package component over a carrier. The first conductive pillars of the first package component and second conductive pillars of the second package component face the carrier. The method further includes encapsulating the first package component and the second package component in an encapsulating material, de-bonding the first package component and the second package component from the carrier, planarizing the first conductive pillars, the second conductive pillars, and the encapsulating material, and forming redistribution lines to electrically couple to the first conductive pillars and the second conductive pillars.

Abstract: A device structure includes a first electronic structure and a plurality of first electric contacts. The first electronic structure has a surface and a center. The first electric contacts are exposed from the surface. The first electric contacts are spaced by a pitch that increases with increasing distance from the center.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a seed layer to cover a first passivation layer over a semiconductor substrate. The method also includes forming a metal layer to partially cover the seed layer by using the seed layer as an electrode layer in a first plating process and forming a metal pillar bump over the metal layer by using the seed layer as an electrode layer in a second plating process. In addition, the method includes forming a second passivation layer over the metal layer, wherein the second passivation layer includes a protrusion portion extending from a top surface of the second passivation layer and surrounding the sidewall of the metal pillar bump.

Abstract: A device includes a molding compound encapsulating a first integrated circuit die and a second integrated circuit die; a dielectric layer over the molding compound, the first integrated circuit die, and the second integrated circuit die; and a metallization pattern over the dielectric layer and electrically connecting the first integrated circuit die to the second integrated circuit die. The metallization pattern comprises a plurality of conductive lines. Each of the plurality of conductive lines extends continuously from a first region of the metallization pattern through a second region of the metallization pattern to a third region of the metallization pattern; and has a same type of manufacturing anomaly in the second region of the metallization pattern.

Abstract: A method and device for the alignment of substrates that are to be bonded. The method includes detecting and storing positions of alignment mark pairs located on surfaces of the substrates, and aligning the substrates with respect to each other in accordance with the detected positions.

Abstract: A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.

Abstract: A target for use in the optical measurement of misregistration in the manufacture of semiconductor devices, the target including a first periodic structure formed on a first layer of a semiconductor device and having a first pitch along an axis and a second periodic structure formed on a second layer of the semiconductor device and having a second pitch along the axis, different from the first pitch, the second periodic structure extending beyond the first periodic structure along the axis.

Abstract: Metrology targets designs, design methods and measurement methods are provided, which reduce noise and enhance measurement accuracy. Disclosed targets comprise an additional periodic structure which is orthogonal to the measurement direction along which given target structures are periodic. For example, in addition to two or more periodic structures along each measurement direction in imaging or scatterometry targets, a third, orthogonal periodic structure may be introduced, which provides additional information in the orthogonal direction, can be used to reduce noise, enhances accuracy and enables the application of machine learning algorithms to further enhance accuracy. Signals may be analyzed slice-wise with respect to the orthogonal periodic structure, which can be integrated in a process compatible manner in both imaging and scatterometry targets.

Abstract: A method of forming an overlay alignment mark in the fabrication of integrated circuitry comprises forming a first series of periodically-horizontally-spaced lower first features on a substrate. A second series of periodically-horizontally-spaced upper second features is formed directly above the first series of the lower first features. Individual of the upper second features are directly above and cover at least a portion of individual of the lower first features in a first horizontal area of the substrate. Individual of the upper second features are not directly above and are not covering any portion of the individual lower first features in a second horizontal area of the substrate that is horizontally adjacent the first horizontal area. Other methods, and structure independent of method, are disclosed.

Abstract: An alignment mark at a position that overlaps an area in which an anisotropic conductive film is pasted, and to accurately perform alignment using an image captured by a camera. An alignment method in which an electronic component is mounted on the obverse surface of a transparent substrate with a conductive adhesive agent interposed therebetween, a substrate-side alignment mark and a component-side alignment mark are adjusted from the captured image, and the position at which the electronic component is mounted on the transparent substrate is aligned, wherein in the conductive adhesive agent, conductive particles are in a regular arrangement as viewed from a planar perspective, and in the captured image, the outside edges of the alignment marks exposed between the conductive particles are intermittently visible as line segments (S) along the imaginary line segments of the outside edges of the alignment mark.

Abstract: A chip package includes a chip, a sidewall structure that has a first light-shielding layer, a second light-shielding layer, and a cover. The chip has a light emitter and a light receiver that are located on a top surface of the chip. The sidewall structure is located on the top surface of the chip and has two aperture areas. The light emitter and the light receiver are respectively located in the two aperture areas. The sidewall structure surrounds the light emitter and the light receiver, and at least one surface of the sidewall structure has the first light-shielding layer. The second light-shielding layer is located between the chip and the sidewall structure. The cover is located on a surface of the sidewall structure facing away from the chip, and at least covers the light receiver and the sidewall structure that surrounds the light receiver.

Abstract: A method comprising contact-free positioning a template mask wafer having a template device pattern relative to a predetermined surface area section of a device pattern wafer. The template mask wafer includes a semitransparent layer. The method includes contact-free aligning one or more mask alignment marks of the template mask wafer with one or more alignment marks of the device pattern wafer and contacting the mask wafer on the device pattern wafer. The method includes transferring a template device pattern of the template mask wafer onto the predetermined surface area section of the device pattern wafer using an electron beam while heat conduction is distributed throughout the mask wafer to maintain a low temperature rise in the mask wafer during the transferring. A system is also provided.

Abstract: An integrated circuit includes at least one antifuse element. The antifuse element is formed from a semiconductor substrate, a trench extending down from a first face of the semiconductor substrate into the semiconductor substrate, a first conductive layer housed in the trench and extending down from the first face of the semiconductor substrate into the semiconductor substrate, a dielectric layer on the first face of the semiconductor substrate, and a second conductive layer on the dielectric layer. A program transistor selectively electrically couples the second conductive layer to a program voltage in response to a program signal. A program/read transistor selectively electrically couples the first conductive layer to a ground voltage in response to the program signal and in response to a read signal. A read transistor selectively electrically couples the second conductive layer to a read amplifier in response to the read signal.

Abstract: A method of manufacturing a mark including the following steps is provided. A substrate including a device area and a mark area is provided. A dielectric layer is formed on the substrate. A dual damascene opening is formed in the dielectric layer of the device area. The dual damascene opening includes a first opening and a second opening connected to each other. The width of the second opening is greater than the width of the first opening. A third opening is formed in the dielectric layer of the mark area. The third opening and the first opening are simultaneously formed by the same process. A barrier material layer is formed on the surfaces of the dual damascene opening and the third opening. The barrier material layer seals the third opening to form a void in the third opening. A metal material layer is formed on the barrier material layer.

Abstract: An exposure method includes exposing a substrate to form a first pattern on a first layer, measuring a first alignment value of the first pattern, generating first correction data by using the first alignment value, storing the first correction data and exposing the substrate to form a second pattern on a second layer disposed on the first layer by using the first correction data.

Abstract: A wafer dividing method includes a first step of cutting a back side of the wafer by using a cutting blade thereby forming a cut groove on the back side of the wafer along each division line, such that each cut groove has a depth not reaching the front side of the wafer from the back side thereof. A second step includes supplying a water-soluble liquid resin to the back side of the wafer thereby forming a water-soluble protective film on the back side of the wafer. A third step includes positioning a focal point of a laser beam on the bottom surface of each cut groove and next applying the laser beam to the bottom surface of each cut groove thereby fully cutting the wafer along each cut groove.

Abstract: A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.

Abstract: An alignment mark pattern is provided. The alignment mark pattern includes a first region that includes a first line and a first space having different widths therebetween, a second region that includes a second line and a second space having different widths therebetween, a third region that includes a third line and a third space having different widths therebetween, and a fourth region that includes a fourth line and a fourth space having different widths therebetween. The first and second lines extend in a first direction. The third and fourth lines extend in a second direction perpendicular to the first direction. The first region is diagonal to the second region. The third region is diagonal to the fourth region. The third region is adjacent to the first and second regions. The fourth region is adjacent to the first and second regions.

Abstract: The present invention provides an overlay mark, including a substrate and plural sets of first pattern block and second pattern block. A first direction and a second direction are defined on the substrate, wherein the first direction and the second direction are perpendicular to each other. In each set, the first pattern block is rotational symmetrical to the second pattern block. Each first pattern block includes a big frame and plural small frame. Each second pattern block includes a big frame and plural small frame. The width of the big frame is greater than three times of the width of the small frame. The present invention further provides a method for evaluating the stability of a semiconductor manufacturing process.

Abstract: An electronic component includes a multilayer body including insulating base materials laminated on each other and including first and second main surfaces perpendicular or substantially perpendicular to a lamination direction, and an alignment mark is defined by a conductor on one of the insulating base materials. The multilayer body includes a first layer area at a side of the first main surface and a second layer area at a side of the second main surface with respect to the alignment mark. An insulating base material in the first layer area has higher translucency than an insulating base material in the second layer area. The alignment mark is a trapezoidal cross-sectional shape including a first base at the side of the first main surface and a second base at the side of second main surface, the first base being longer than the second base.

Abstract: Some embodiments include a semiconductor package. The semiconductor package has a semiconductor die with a primary region which includes integrated circuitry, and with an edge region which includes a portion of an alignment mark location. The portion of the alignment mark location includes a segment of an alignment mark. The alignment mark includes a pattern of lines and spaces, with the lines extending along a first direction. The portion of the alignment mark location also includes a texture having a pattern other than lines extending along either the first direction or along a second direction substantially orthogonal to the first direction. Some embodiments include methods for alignment marking semiconductor wafers.

Abstract: A package structure includes a chip package and an antenna package. The chip package includes at least one semiconductor die and a first insulating encapsulation encapsulating the at least one semiconductor die. The antenna package is located on and electrically coupled to the chip package. The antenna package includes metallic patterns embedded in a second insulating encapsulation, wherein each of the metallic patterns has a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface, wherein the first surface and the side surface of each of the metallic patterns are covered by the second insulating encapsulation, and the second surface is levelled and coplanar with a third surface of the second insulating encapsulation.

Abstract: A semiconductor device includes a substrate that includes a cell region and a peripheral circuit region, a cell insulating pattern disposed in the cell region of the substrate that defines a cell active region, and a peripheral insulating pattern disposed in the peripheral circuit region of the substrate that defines a peripheral active region. The peripheral insulating pattern includes a first peripheral insulating pattern having a first width and a second peripheral insulating pattern having a second width greater than the first width. A topmost surface of at least one of the first peripheral insulating pattern and the second peripheral insulating pattern is positioned higher than a topmost surface of the cell insulating pattern.

Abstract: An LVDS device wherein driver and receiver functionalities are integrated in the same package, signals are routed from the individual driver and receiver elements inside the package such that all inputs are one side of the package, and all outputs are on the opposite side of the package, allowing for an optimized signal flow through the package. All required capacitors and resistors are integrated inside the package; no external electronic components are required. All of the above novelties also contribute to a 6:1 reduction in size compared to current state-of-the-art, for the same number of communication channels. Embodiments include a packaging topology adaptable to extreme environments, including radiation tolerant to 300 kRad (based on the die technology), so that module operational temperature is in a range of ?55° C. to +100° C. and storage temperature can be as low as ?184° C.