Abstract: A six-transistor SRAM of a high-density memory comprises two thin-film n-channel pull-down transistors and four conventional p-channel load and access transistors. As embodied in a semiconductor chip, the cell is simpler than priorly known six-transistor cells and is relatively immune from the deleterious effects of sodium ions and hot-carrier aging.

Abstract: Adjacent memory cells has a two-layer structure formed of first layer and second layer. The first layer is provided with driver transistors of the memory cell, access transistors of the memory cell, and driver transistors formed of the memory cell. The second layer is provided with load transistors of the memory cell, load transistors and of the memory cell, and access transistors of the memory cell. The transistors formed in the first layer are of an NMOS type, and the transistors formed in the second layer are of a PMOS type.

Abstract: In a miniaturized complete CMOS SRAM of a TFT load type, a field effect thin-film transistor (TFT) can achieve stable reading and writing operation of a memory cell and can reduce power consumption thereof. The field effect thin-film transistor formed on an insulator includes an active layer and a gate electrode. The gate electrode is formed on a channel region of the active layer with a gate insulating film therebetween. The active layer is formed of a channel region and source/drain regions. The channel region is formed of a monocrystal silicon layer and does not includes a grain boundary. The source/drain regions is formed of a polysilicon layer. The channel region has a density of crystal defects of less than 10.sup.9 pieces/cm.sup.2. The thin film transistor shows an ON current of 0.25 .mu.A/.mu.m per channel width of 1 .mu.m and an OFF current of 15 fA/.mu.m. The thin-film transistor can be applied to a p-channel MOS transistor serving as a load transistor in a memory cell of a CMOS type SRAM.

Abstract: A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.

Abstract: An SRAM having a TFT load element has a gate electrode of the load TFTs disposed between bit lines and channel regions of the load TFTs. The structure avoids formation of a parasitic transistor in which each of the bit lines would act as a gate electrode for the channel region of the TFT load element. The SRAM has a high soft error immunity even at a low supply voltage.

Abstract: A thin film transistor in which a device active layer is formed on an insulation film, in which an interface state density present at the interface between the active layer and the insulation film is set to less than 1.times.10.sup.11 /cm.sup.2. The characteristics of TFT can be enhanced by decreasing the leak current and SRAM memory cell can be provided with easy design for the process and the structure while avoiding increase in the resistance and additional capacitance and ensuring voltage withstand.

Abstract: A semiconductor device includes a polycrystalline silicon layer formed on a silicon layer with an oxide film therebetween, an interlayer insulating layer formed to cover the surface of the silicon layer and the surface of the polycrystalline silicon layer, and a silicon plug layer formed in an embedded manner in a contact hole in the interlayer insulating layer to be directly connected to the surface of an end portion of the polycrystalline silicon layer and the surface of the silicon layer in the proximity of the end portion of the polycrystalline silicon layer. The polycrystalline silicon layer and the silicon plug layer have the same type of conductivity. By this interconnection structure, the semiconductor device is improved in the patterning accuracy of the contact portion of a multilayer stacked interconnection. Furthermore, an ohmic contact between conductive interconnection layers can be realized with relatively simple manufacturing steps without occurrence of a voltage drop caused by a pn junction.

Abstract: A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronization and permit creation of networks of microcomputers with rapid communication between concurrent processes on the same or different microcomputers.

Abstract: In a static random access memory device where thin film transistors are used memory cell loads, first and second semiconductor layers having source regions, channel regions and drain regions of the thin film transistors partly oppose first and second conductive layers serving as gate electrodes thereof. A third conductive layer for receiving a definite potential opposes at least the channel regions of the first and second semiconductor layers.

Abstract: An SRAM cell includes a pair of cross-coupled inverters where each inverter includes vertical n-channel and p-channel transistors having a gate electrode that is shared between the transistors that make up each inverter. The gate electrodes for the inverters laterally surround the channel regions of the p-channel load transistors to achieve a relatively high beta ratio without occupying a large amount of substrate surface area. Also, the gate electrodes increase the amount of capacitance of the storage nodes and decreases the soft error rate. The active regions of the latch transistors are electrically isolated from the substrate by a buried oxide layer, thereby decreasing the chances of latch-up.

Abstract: An interconnect structure, and method for forming same, is suitable for use in integrated circuits such as SRAM devices. The structure uses masking of a polycrystalline silicon interconnect level to move a P-N junction to a region within a polycrystalline silicon interconnect line, rather than at the substrate. This P-N junction can then be shorted out using a refractory metal silicide formed on the polycrystalline silicon interconnect structure.

Abstract: The present invention includes an integrated circuit having a self-aligned contact that makes contact to both a region within the substrate and a capacitor plate of a capacitor that is adjacent to the doped region. The present invention also includes a static-random-access memory cell with a capacitor having a first plate and a second plate. The first plate includes a first plate section of a gate electrode of a transistor, and the second plate includes a first conductive member that is substantially coincident with the first plate section. The second plate may be formed over a gate electrode of a latch transistor or over a word line. The disclosure includes methods of forming the integrated circuit and the static-random-access memory cell.

Abstract: An MOS transistor for use in an integrated circuit is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from a short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of doped polysilicon covered by titanium silicide encapsulated by a thin film of titanium nitride.

Abstract: A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is provided in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. A wiring line, formed as a separate conductive layer, is provided in the stacking arrangement of the drive and load MISFETs of a memory cell for applying a ground potential to source regions of the drive MISFETs thereof.

Abstract: An interconnect structure, and method for forming same, is suitable for use in integrated circuits such as SRAM devices. The structure uses masking of a polycrystalline silicon interconnect level to move a P-N junction to a region within a polycrystalline silicon interconnect line, rather than at the substrate. This P-N junction can then be shorted out using a refractory metal silicide formed on the polycrystalline silicon interconnect structure.

Abstract: In a gate array with a RAM which is disposed between first and second logic circuit blocks each of which having plural logic gates, by-pass signal lines which interconnect the logic circuit blocks are disposed so as to extend above the RAM. In order to minimize mutual interference, signal lines, such as word lines of the RAM, formed from a layer which is adjacent to the by-pass signal lines are disposed, with respect to a plan view layout arrangement of the main surface of a chip, so as to intersect the latter at right angles. In addition, interconnection pitches of signal lines in different wiring layers which extend parallel with each other are set so that noises are cancelled in differential sense circuits.

Abstract: A silicon layer in a lower layer and an interconnection layer arranged in an upper layer are electrically connected through an opening for contact. A silicon plug layer having the same conductivity type as that of the silicon layer is embedded in the opening. The silicon plug layer is embedded in the opening by an etch back method after deposited using a CVD method. The interconnection layer in the upper layer has conductivity type different from that of the silicon plug layer. A refractory metal silicide layer is formed between the upper interconnection layer and the silicon plug layer.The refractory metal silicide layer prevents pn junction from being formed between the upper interconnection layer and the silicon plug layer.

Abstract: A polysilicon resistor element and a semiconductor device using the same are disclosed. The polysilicon resistor element has a resistive polysilicon film formed on a predetermined interlayer insulating film of a semiconductor chip. The resistive polysilicon film is covered by an insulating film having holes and high melting point metal films are formed in self-alignment to the holes. The high melting metal film constitutes one of lead portions of the polysilicon resistor element. A diffusion of the high melting point metal film due to heat treatment during fabrication, which causes an effective length of the resistor element, becomes negligible and reproducibility is improved.

Abstract: An SRAM cell is formed such that pass channel-stop regions, which are adjacent to the pass transistors, have a higher doping concentration compared to the latch channel-stop regions that are adjacent to the latch transistors. In one embodiment, the pass channel-stop regions are formed using two channel-stop doping steps, whereas the latch channel-stop regions are formed during only one channel-stop doping step. The doping steps may be performed before or after field isolation is formed. The higher doping concentration causes the dopant from the pass channel-stop regions to extend laterally further from the edge of the field isolation compared to the latch channel-stop regions. The process can be adapted for use in almost any type of field isolation process.

Abstract: A pair of load transistors of a flip-flop circuit constituting a memory cell consist of thin film transistors, and channel regions of the pair of load transistors overlap drain regions of the transistors through a gate insulating film. For this reason, a channel length of the load transistor can be sufficiently increased, and a leakage current of the load transistor can be reduced.

Abstract: A self-aligned via between interconnect layers in an integrated circuit allows a less precise masking alignment to be used to fabricate an integrated circuit with increased packing density and improved yield. In one embodiment, self-aligned vias are used to connect first and second interconnect layers in an SRAM memory cell.

Abstract: A semiconductor memory device of the present invention includes a memory cell comprising two transfer transistors and two driver transistors in which a nitride film is covered only on these driver transistor areas. The nitride film is formed over source and drain regions and a gate electrode of the driver transistor.

Abstract: A method of fabricating a transistor on a wafer including: forming a doped transistor body 42 on top of an insulator 34; doping source/drain regions in the transistor body; forming a gate oxide 44 on top of the transistor body; forming sidewall spacers along the transistor body; depositing a metal layer over the transistor body; forming an amorphous silicon layer over the metal layer, the amorphous silicon layer patterned in a gate and a local interconnect configuration; annealing to form silicided regions above the source/drain regions within the transistor body, and where the metal layer reacts with the amorphous silicon layer to create a silicided gate 50 and a silicided local interconnect 50; and etching unsilicided portions of the metal layer to leave silicided source/drain regions, a silicided gate, and a silicided local interconnect.

Abstract: A symmetrical, SRAM silicon device comprises a substrate comprising a semiconductor material with, a set of buried local interconnection lines in the silicon substrate. A word line is located centrally on the surface of the device. Pull down transistors are located symmetrically one either side of the word line. Interconnections are formed in the same layer as a BN+ diffusion. There is only one wordline composed of polysilicon. The pull down transistors are located on opposite sides of the word line. The cell size is small. There is no 45.degree. layout, and the metal rule is loose. Pass transistor source and drain regions are formed in the substrate juxtaposed with the buried local interconnection line. There is a layer of gate oxide above the source region and the drain region, and a gate above the gate oxide juxtaposed with the source region and drain region.

Abstract: A semiconductor memory cell (10) includes first and second cross-coupled driver transistors (13, 19) each having a source-drain region and a channel region formed in a first thin-film layer (36, 36'). First and second parallel opposed wordlines (20, 22) overlie a single-crystal semiconductor substrate (12) and the channel region (46) of each driver transistor overlies a portion of an adjacent wordline. A portion of the thin-film layer (36, 36') makes contact to the single-crystal semiconductor substrate (12) adjacent to the opposite wordline. The channel and source-drain regions of first and second load transistors (15, 21) are formed in a second thin-film layer (64) which overlies the driver transistors (13, 19). The load transistors (15, 21) are cross-coupled to the driver transistors (13, 19) through common nodes (31, 33).

Abstract: Disclosed is a semiconductor integrated circuit device having a plurality of fine memory devices and its fabrication method, and particularly to a semiconductor integrated circuit device capable of suppressing the kink current disturbance of MOS transistors without reducing the junction characteristic of the diffusion layers and its fabrication method. In this device, an angle between the lower surface of each edge of a field oxide formed in an environmental device area, i.e. a peripheral circuit area, and the main surface of a semiconductor substrate is smaller than an angle between the lower surface of each edge of a field oxide formed in a memory cell area and the main surface of the semiconductor substrate.

Abstract: In a semiconductor integrated circuit having a block of static memory cells using CMOS transistors and peripheral components using bipolar transistors, metal interconnections in a layer over the CMOS transistors on the substrate are simplified by using buried layers in the substrate as supply and ground lines for the CMOS transistors. This is accomplished by making buried contacts of a metal such as tungsten in each memory cell to make ohmic connection of the diffused layer of n-MOS transistors and the diffused layer of p-MOS transistors respectively to underlying buried layers of opposite conductivities and applying supply voltage or ground potential to each buried layer from the substrate surface by using additional buried contacts which are made at convenient locations outside the memory block. In the case of n-MOS memory cells using resistors or TFTs as load elements, ground potential is applied to the n-MOS transistors by the same method.

Abstract: An SRAM cell includes an open-base, bipolar transistor serving as a load device and one pull-down transistor having an associated leakage current. The amplification .beta. of the bipolar transistor controls the amount of load current through the bipolar transistor. The bipolar transistor provides the necessary load current to ensure the SRAM cell maintains its logic state.

Abstract: A gate electrode layer constituting a gate of a P-channel type MOS transistor formed on an upper layer is made of P-type polycrystal silicon and is connected to a diffusion region of an N-channel type MOS transistor formed on a lower layer by extending an end of the gate electrode layer into a contact hole above the diffusion region. Therefore, an aspect ratio of the contact hole becomes small and a coverage of a wiring for connecting the gate of the P-channel type MOS transistor and the diffusion region of the N-channel type MOS transistor is improved, so that the wiring is not snapped.

Abstract: A static random access memory of the thin film transistor load type which is enhanced in soft error resistance without involving an increase of the area of a cell is disclosed. A conductor layer is connected to the gate electrode of a first one of a pair of thin film transistors which serve as load means of each cell and is formed as a different layer from the first thin film transistor. The conductor layer is layered on a conductor layer of the other second thin film transistor with an insulating layer interposed therebetween to form a coupling capacity between the conductor layer connected to the gate electrode of the first thin film transistor and the conductor layer of the second thin film transistor. Resistors are interposed between the gates and active layers of the first and second thin film transistors and storage nodes connected to the first and second thin film transistors.

Abstract: An SRAM memory cell structure is provided which has the access transistor gates formed from a different layer than that of the word line. The first access transistor gate of a first memory cell is connected to the first access transistor gate of an adjacent second memory cell, and a second access transistor gate of the first memory cell is connected to a second access transistor gate of an third oppositely adjacent memory cell. Each pair of coupled gates are formed separate from the access transistor gates in adjacent memory cells. The word lines connect the separated access transistor gates. The word lines are formed on an insulating layer above the gates of the access transistors. The word lines are, however, electrically connected to the gates of the access transistors through contact holes formed in the insulating layer. Each memory cell is arranged symmetrically with respect to an adjacent memory cell, and the components of each memory cell are symmetrical.

Abstract: A high capacitance multi-level storage node contact is proposed for high density SRAMs. The proposed contact connects several poly levels to diffusion and to a trench capacitor, in one contact. The high storage node capacitance provided by the trench capacitor substantially reduces the soft error rate probability of the cell. The use of a single contact to connect several levels reduces the area. The contact preferably uses TiN as a barrier layer to reduce dopant diffusion between different poly layers.

Abstract: A thin-film transistor having a thin-film channel region (20) inlaid in a recess (29) along the wall of a multi-layered insulating structure (14), and a gate electrode (12) electrically controlling current conduction in the thin-film channel (20) and separated therefrom by a gate dielectric layer (32). The multi-layered insulating structure (14) includes a spacing layer (28) which is withdrawn from the wall of the multi-layered insulating structure (14) and forms an inner wall of the recess (29). By residing in the recess (29), the thin-film channel region (20) is aligned to the multi-layered insulating structure (14) and the gate dielectric layer (32) separates exposed portions of the thin-film channel region (20) from the gate electrode (12). Thin-film source and drain regions (16, 18) are integral with the thin-film channel region (20) and are self-aligned to the multi-layered insulating structure (14).

Abstract: A new and improved static random access memory (SRAM) cell wherein separate regions of polysilicon are formed over a silicon substrate and are separated by defined openings therein into which oxide filler material is introduced to render the regions of polysilicon and oxide substantially co-planar at their upper surfaces. An access transistor and a thin film load transistor are formed within and adjacent to first and second regions of the polysilicon, respectively, and yet a third, pull down transistor is formed within and adjacent to a third polysilicon region. The thin film transistor includes a thin second layer of polysilicon which is electrically isolated from the second one of the polysilicon regions and is doped to form therein source, drain and channel regions. Advantageously, the thin film transistor is formed on this substantially planar surface, thereby improving process yields and device performance.

Abstract: An SRAM cell comprising a flip-flop consisting of first and second inverters, and two word transistors connected to the flip-flop. In this cell, the gates of the word transistors are composed of a single word line, and the gate of a driver transistor in the first inverter is provided on one side of the word line, while the gate of a driver transistor in the second inverter is provided on the other side of the word line. The gate regions of the driver transistors in the first and second inverters are so formed as to partially overlap the bit-line side diffused layer regions of the word transistors. Also disclosed is a memory cell array comprising a plurality of cell rows each having a plurality of the above SRAM cells. In this array, the memory cells disposed in the even row are so arranged as to have a positional deviation of approximately half the cell length in the same direction respectively from the memory cells disposed in the odd row.

Abstract: A semiconductor device (10) has a thin-film transistor (TFT) formed in and around an opening (24) in a dielectric layer (22). A conductive layer (26) lines the opening sidewalls and serves as a gate electrode of the transistor. A conductive layer (30) is deposited over the gate electrode to form a source region (32), a channel region (36), and a drain region (34). The two conductive layers are separated by a gate dielectric (28). Because both the gate electrode and the channel region conform to the opening sidewalls and bottom, the entire channel region is under direct gate control. Device (10) may also include a conductive region, such as a gate electrode (15) of a bulk transistor, at the bottom of opening (24) and in electrical contact with the TFT gate electrode.

Abstract: A semiconductor transistor device comprises a gate electrode disposed over an insulating surface, a spacer element located at the end of the gate electrode, a gate insulating film covering the gate electrode, a first diffusion region spaced apart from one end of the gate electrode, separated therefrom by the gate insulating film and by the spacer element which reduces the electric field between the gate and first diffusion region, the first diffusion region extending vertically above the gate insulating film, and a second diffusion region disposed above the gate insulating film having one end spaced from the first diffusion vertically extending region.

Abstract: A thin film transistor includes a semiconductor thin film formed with a source region and a drain region at opposite end portions thereof and having an offset region near at the drain region, a gate electrode formed above the region between the source region and the offset region of the semiconductor thin film, with a gate insulating film being interposed, and a conductive layer formed above the gate electrode or under the semiconductor thin film, with an insulating film being interposed, the conductive layer being applied with generally the same potential as the gate electrode, wherein the resistance value of the offset region is controlled by the potential of the conductive layer. The gate electrode may be formed under the semiconductor thin film. In this case, the conductive layer is formed above the semiconductor thin film or under the gate electrode, with an insulating film being interposed. An SRAM is also provided which uses a thin film transistor constructed as above.

Abstract: An improved static random access memory device of the CMOS load memory cell type for storing one-bit information is capable of 4M bit or greater memory capacity. Each memory cell includes two transfer transistors, two driving transistors, and two load transistor elements. Each load transistor element is a PMOS thin film transistor and comprises a source formed of first and second conductive layers and connected to a constant power source line, and a drain also formed of the first and second conductive layers and connected to the drain of a corresponding one of the driving transistors. A channel region of each load transistor element is composed only along the region defined by the second conductive layer and a respective gate is formed of a third conductive layer which is separated from the channel region by a gate insulating layer.

Abstract: A method of fabricating a transistor on a wafer including; forming a doped transistor body 42 on top of an insulator 34; doping source/drain regions in the transistor body; forming a gate oxide 44 on top of the transistor body; forming sidewall spacers along the transistor body; depositing a metal layer over the transistor body; forming an amorphous silicon layer over the metal layer, the amorphous silicon layer patterned in a gate and a local interconnect configuration; annealing to form silicided regions above the source/drain regions within the transistor body, and where the metal layer reacts with the amorphous silicon layer to create a silicided gate 50 and a silicided local interconnect 50; and etching unsilicided portions of the metal layer to leave silicided source/drain regions, a silicided gate, and a silicided local interconnect.

Abstract: A semiconductor memory apparatus comprises a flip-flop circuit formed of a pair of inverters formed of driver transistors formed on a semiconductor substrate and having an input and an output coupled to each other in a crossing fashion, and transistors formed on a semiconductor thin film formed on the semiconductor substrate, and a pair of access transistors coupled to drain electrodes of the inverters constructing the flip-flop circuit. In this semiconductor memory apparatus, a coupling capacitance is formed on an overlapping portion in which active layers of the semiconductor thin film transistors and gate electrodes of the semiconductor thin film transistors are overlapped to each other and a part of the overlapping portion in which the coupling capacitance is formed is formed within a contact hole, thereby forming a coupling capacitance between the gate electrode and the drain electrode of the inverters. A soft error, caused by an .alpha.

Abstract: A resistor is connected to the source/drain of a transistor and used as a load element of a memory cell. A trench is formed which extends from a top of the wafer through an isolation region of the wafer to a silicon base of the wafer. The silicon base of the wafer is located below the isolation region of the wafer. A resistive layer of material is formed in the trench. The resistive layer extends from the top of the wafer through the isolation region of the wafer and is electrically connected to the silicon base of the wafer. The resistor is connected to other circuitry on the wafer, for example, by implanting into the wafer atoms of a first conductivity type into a region immediately adjacent to the resistive layer of material in the trench. In the preferred embodiment, the resistive layer of material is deposited polysilicon.

Abstract: Herein disclosed is a semiconductor integrated circuit device which has a memory array or a memory mat formed of memory cells arranged regularly in a matrix shape. At the end portion or inside of the memory array or memory cell in the region of the device where the patterning of the memory cells is discontinued or interrupted, the shape of an element isolating insulating film, which is formed for regulating the memory cells having pattern interruptions, is made substantially identical to the shape of the element isolating insulating film for regulating the memory cells in the region of the device where the patternings of the memory cells are of an uninterrupted regular form. In the location on the chip front face where the regular patterns associated with the memory area are discontinued, there is formed a dummy pattern having a shape made substantially identical to that of a gate electrode arranged at the end portion of the location where the regular patterns are interrupted.

Abstract: A memory cell includes gated diodes as load elements. For example, the memory cell includes a word line, a bit line, an inverted bit line, a ground line, a power line, a first transistor, a second transistor, a third transistor, a fourth transistor, a first gated diode and a second gated diode. The first transistor has a first end connected to the inverted bit line, a second end, and a gate connected to the word line. The second transistor has a first end, a second end connected to the bit line, and a gate connected to the word line. The third transistor has a first end connected to the second end of the first transistor, a second end connected to the ground line, and a gate connected to the first end of the second transistor. The fourth transistor has a first end connected to the first end of the second transistor, a second end connected to the ground line, and a gate connected to the second end of the first transistor.

Abstract: A lower gate type semiconductor device, in which, for increasing an on-current of a lower gate type thin film transistor and restricting an off-current, there is provided a gate-controlled offset region different from a channel region in one or both conductivity types. This region increases the on-current of the transistor, provides a reduction of a leakage current, and restriction of a subthreshold coefficient. A two-dimensional size can also be reduced by altering the gate height. The on-current is increased, and the leakage current is reduced in the device. The offset region is composed of a semiconductor material and is formed at the end of a drain region of the device.

Abstract: A CMOS SRAM cell includes "true" and "false" NMOS word-line access transistors, "true" and "false" NMOS pull-down transistors, and "true" and "false" PMOS pull-down transistors arranged in a classical six-transistor SRAM electrical configuration. "True" and "false" inter-level interconnects of silicidable material provide for respective five-way connections among the transistors. The "true" inter-level interconnect connects: the drain of the "true" pull-up transistor, a gate level polysilicon conductor defining and connecting the gates of the "false" pull-up transistor and the "false" pull-down transistor, and a diffusion region defining and connecting the source of the "true" access transistor and the drain of the "true" pull-down transistor.

Abstract: A semiconductor memory device includes a semiconductor substrate, a memory cell formed on the semiconductor substrate and including first and second transfer transistors, first and second driver transistors and first and second thin film transistor loads, and first and second word lines extending generally parallel to each other along a predetermined direction and respectively coupled to gate electrodes of the first and second transfer transistors. Each of the first and second thin film transistor loads include first and second impurity regions which sandwich a channel region formed by a semiconductor layer provided on the semiconductor substrate, and a gate electrode formed by confronting conductor layers and isolated from the channel region.

Abstract: A structure of a thin film transistor capable of reducing the power consumption in the waiting state and stabilizing the data holding characteristic in application of the thin film transistor as a load transistor in a memory cell in a CMOS-type SRAM is provided. A gate electrode is formed of a polycrystalline silicon film on a substrate having an insulating property. A gate insulating film is formed on the gate electrode. A polycrystalline silicon film is formed on the gate electrode with the gate insulating film interposed therebetween. Source/drain regions including a region of low concentration and a region of high concentration are formed in one and another regions of the polycrystalline silicon film separated by the gate electrode. Thus, the thin film transistor is formed. The thin film transistor is applied to p-channel MOS transistors serving as load transistors in a memory cell of a CMOS-type SRAM.

Abstract: An SRAM memory cell structure, wherein a word line is disposed near the center of a cell, each one of driver transistors is disposed on both sides thereof substantially in parallel with each other, a contact portion for a gate electrode of said driver transistor is formed being laminated on a word transistor formed together with said word line, and a semiconductor, wherein an upper transistor and a lower transistor are disposed, an overlapped portion in which at least three layers each having a diffusion region for forming each of said transistors are overlapped is formed, and a contact is taken at said overlapped portion.

Abstract: A semiconductor memory device includes a plurality of memory cells each specified by selecting one of rows and one of columns, a plurality of word lines to each of which the memory cells associated with selected one of the rows are connected in a branch form, for selecting the rows, and a plurality of bit lines to each of which the memory cells associated with selected one of the columns are connected in a branch form, for selecting the columns and providing data transmission paths for the memory cells, wherein at least one wiring of the word lines and bit lines constitutes part of at least one closed circuit. Thus, even if breaking of wire occurs in part of the wiring in the manufacturing process or in use, the memory device can be prevented from becoming a defective product due to the breaking of wire. As a result, high manufacturing yield and high reliability in use can be obtained.