Abstract: A FET device comprising a semiconductor substrate; diffusion regions in the substrate separated by a channel region; a gate overlapping the channel region and a portion of the diffusion regions and separated from the substrate by a gate dielectric; and a sidewall dielectric on a sidewall of the gate; and a sidewall spacer conductor on the sidewall dielectric contacting one of the diffusion regions but not both of the diffusion regions of one device is provided along with a method for its fabrication. The conductive spacer connects diffusions of adjacent devices that share a common gate electrode.

Abstract: A pair of directly coupled Field Effect transistors (FETs), a latch of directly coupled FETS, a Static Random Access Memory (SRAM) cell including a latch of directly coupled FETs and the process of forming the directly coupled FET structure, latch and SRAM cell. The vertical FETs, which may be both PFETs, NFETs or one of each, are epi-grown NPN or PNP stacks separated by a gate oxide, SiO.sub.2. Each device's gate is the source or drain of the other device of the pair. The preferred embodiment latch includes two such pairs of directly coupled vertical FETs connected together to form cross coupled invertors. A pass gate layer is bonded to one surface of a layer of preferred embodiment latches to form an array of preferred embodiment SRAM cells. The SRAM cell may include one or two pass gates. The preferred embodiment SRAM process has three major steps. First, preferred embodiment latches are formed in an oxide layer on a silicon wafer.

Abstract: There is provided a semiconductor memory device including a semiconductor substrate, a pair of transfer transistors formed on the substrate, a pair of driver transistors formed on the substrate, first and second thin film load transistors formed above the transfer transistors and the driver transistors with an interlayer insulative film sandwiched therebetween, a drain region of the first thin film load transistor having at least one portion over which a gate electrode of the second thin film load transistor partially lies. The portion is heavily doped with impurities. The above mentioned semiconductor memory device prevents reduction in ON-state current in thin film transistors, and hence improves stability in operation of SRAM cell having a top gate type thin film transistor.

Abstract: A novel vertical poly load device in 4T SRAM and a method for fabricating the same are disclosed. The poly load structure is a vertical device formed on a buried contact. The poly load vertical device is constructed by forming a hollow in a planarized dielectric layer with a high temperature oxide layer on the walls of the hollow and with lightly doped n-type polysilicon in the hollow. The poly load is connected to the respective drain of the driver transistor through the buried contact and to the gate of the respective gate of the other driver transistor through a connecting line. The resistance of the poly load will increase, as the voltage of the buried contact becomes low thereby reducing the standby current.

Abstract: A static random access memory (SRAM) cell having increased cell capacitance at the storage nodes utilizes a capacitive structure disposed in a trench. The capacitive structure includes an oxide liner disposed underneath two polysilicon plates. The polysilicon plates are each connected to drains of lateral transistors associated with the SRAM cell. The capacitive plates are deposited as a conformal layer polysilicon and then anisotropically etched to form plates on the side walls of the trench. A dielectric material such as silicon dioxide may be deposited between the polysilicon plates in the trench. The capacitor structures are provided between first and second N-channel pull down transistors associated with the SRAM cell.

Abstract: Static random access memory (SRAM) cell is disclosed, which is suitable for high packing density and cell stabilization, including a substrate, a wordline formed over the substrate, including two parallel legs having gates of first and second access transistors, respectively, gates of first and second drive transistors formed between the two parallel legs, and an active area defined in a surface of the substrate under the gates of the first and second access transistors and gates of the first and second drive transistors.

Abstract: An N-type buried diffusion layer as a portion of the collector region of a bipolar transistor and an N-type buried diffusion layer of a memory cell region are simultaneously formed, and the buried diffusion layer of the memory cell region serves as a potential groove for electrons. The threshold voltage of a MOS transistor in the memory cell region is higher than the threshold voltage of a MOS transistor in a peripheral circuit region, preventing an increase in the standby current in the memory cell region. This increases the soft error resistance of the memory cell and prevents a decrease in the operating speed and an increase in the consumption power.

Abstract: A static random access memory (SRAM) device having an improved degree of integration. The SRAM device has a cell array region in which a unit cell is arranged in a matrix. The unit cell includes a first NMOS inverter including a first NMOS driver transistor and a first NMOS access transistor, a second NMOS inverter including a second NMOS driver transistor and a second NMOS access transistor, a first CMOS inverter including the first NMOS driver transistor and a first PMOS load transistor, and a second CMOS inverter including the second NMOS driver transistor and a second PMOS load transistor, wherein the first and second NMOS inverters, and the first and second CMOS inverters are respectively connected by a flip-flop, and a pick-up region for applying a predetermined bias voltage to the memory cell array region formed in a semiconductor substrate is included in the memory cell array region.

Abstract: Area efficient static memory cells and arrays containing p-n-p-n or n-p-n-p transistors which can be latched-up in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch-up the cell. Also provided are linked memory cells in which the transistors share common regions.

Abstract: An improved circuit and method for gate-body transistors is provided. The improved circuit and method can accord a faster switching speed and low power consumption. The present invention capitalizes on opposing sidewalls and adjacent conductive sidewall members to conserve available surface space on the semiconductor chips. The gate and body of the transistors are biased to modify the threshold voltage of the transistor (V.sub.t). Additionally, the conductive sidewall members and a gate are biased from a single source. The structure offers performance advantages from both metal-oxide semiconductor (MOS) and bipolar junction transistor (BJT) designs. The device can be used in a variety of applications, digital and analog, wherever a more compact structure with low power consumption and fast response time is needed.

Abstract: A semiconductor device including a substrate (220) having a primary surface, a memory cell (202) provided on the substrate, the memory cell (202) including a P-channel transistor, the P-channel transistor having an N-type gate (72), and peripheral portion (204) provided on the substrate, the peripheral portion including a P-channel transistor , the P-channel transistor having a P-type gate (99). A method for forming the semiconductor device is also disclosed.

Abstract: A semiconductor memory device which can reduce the size of a memory cell and increase the packing density is disclosed. Each memory cell comprises a p-type active region, an n-type active region, two word lines, a common gate line and a common gate line. Two memory cells are deviated by, for example, an amount of a half bit in the direction which perpendicularly crosses the word line direction. The memory cells are arranged with one of their parts overlapped with one another in the word line direction. Thus, the size of the memory cell can be reduced in the word line direction.

Abstract: P.sup.+ -type source/drain regions for load transistors and N.sup.+ -type source/drain regions for driver transistors are connected by means of P.sup.+ -type source/drain region outgoing lead and N.sup.+ -type source/drain region outgoing lead via direct contact holes. The drain region outgoing lead for the load transistors and ground lead are formed in a three-dimensionally overlapping manner, and the drain region outgoing lead for the driver transistors connected to memory nodes on one side and the drain region outgoing lead for the load transistors connected to memory nodes on the other side are also formed in a three-dimensionally overlapping manner, whereby memory node charge accumulators are constituted.

Abstract: An object is to provide a structure of a semiconductor device which allows higher degree of integration both in vertical and horizontal directions, and to provide manufacturing method therefor. The semiconductor device includes source.drain electrodes connected to n.sup.- and n.sup.+ source.drain regions of an MISFET and has a function as a part of a bit line, and a gate electrode connected to a first interconnection as a word line. Electrodes are insulated from each other by a sidewall insulating film, silicon oxide film or a silicon nitride film provided inbetween. Since the word line and the bit line do not cross in the same plane, the difference in level in the vertical direction can be reduced.

Abstract: A static random access memory (SRAM) cell includes a substrate having first and second semiconductor layers, the second semiconductor layer being on the first semiconductor layer, active regions of first and second access transistors in the second semiconductor layer, gate electrodes of the first and second access transistors on the active regions, gate electrodes of first and second drive transistors in first terminals of the first and second access transistors, respectively, the gate electrodes penetrating the second semiconductor layer, first and second load resistors electrically contacting the first terminals of the first and second access transistors, respectively, and first and second bit lines electrically contacting second terminals of the first and second access transistors, respectively.

Abstract: A contact between a conductor and a substrate region in a MOSFET SRAM device is formed by a dielectric layer on the surface of a partially completed SRAM device with pass transistors and latch transistors with the dielectric layer being formed above those pass and latch transistors. A thin film transistor gate electrode and an interconnection line are formed on the upper surface of the dielectric layer. A gate oxide layer covers the gate electrode and the interconnection line. A polysilicon conductive layer which covers the gate oxide layer includes a channel region between a source region and a drain region which are formed on opposite sides of the channel region. There is a channel mask formed self-aligned with the channel region formed above the channel region as well as being above the gate electrode. The polysilicon conductive layer is doped aside from the channel mask thereby providing a source region and a drain region on opposite sides of the channel region.

Abstract: A memory cell is provided. The memory cell includes a field-effect transistor having a source region, a drain region and a gate coupled to a wordline. The memory cell also includes a vertical bipolar junction transistor that is biased for use of the reverse base current effect to store data. The bipolar junction transistor has an emitter region formed within a source/drain region of the field-effect transistor. The emitter region is self-aligned with a minimum dimension isolation region adjacent to the memory cell and is coupled to a ground line. A portion of the source/drain region acts as the base of the bipolar junction transistor.

Abstract: A first driver MOS transistor and a second driver MOS transistor are formed at the surface of a semiconductor substrate. A first load element is connected to the drain region of the first driver MOS transistor and the gate electrode of the second driver MOS transistor. A second load element is connected to the drain region of the second driver MOS transistor and the gate electrode of the first driver MOS transistor. A first transfer MOS transistor is formed at the surface, one of the source and drain regions of which is connected to the drain region of the first driver MOS transistor. Further, a second transfer MOS transistor is formed at the surface, one of the source and drain regions of which is connected to the drain region of the second driver MOS transistor. An inter-layer insulation film is formed on the first driver MOS transistor, the second driver MOS transistor, the first transfer MOS transistor and the second transfer MOS transistor.

Abstract: It is an object of the present invention to provide a data storing device capable of responding in high speed without providing a power supply just for maintaining the stored data. A memory cell MC11 is made so as to replace only a memory transistor MT1 out of a pair of memory transistors MT1 and MT2 used for the prior art SRAM with a transistor with "MFMIS structure" having a ferroelectric layer 32. The ferroelectric layer 32 keep storing a polarization state in response to ON state stored in the memory transistor MT1 even when a power supply of the device is turned off. The memory transistor MT1 is turned into ON state in accordance with the polarization state stored in the ferroelectric layer 32 when the power supply is turned on again. In response to the change in state at the memory transistor MT1, the memory transistor MT2 is turned into OFF state. That is, the memory cell MC11 is defined as a ferroelectric memory.

Abstract: On a semiconductor substrate, there are formed a first macro cell having wiring layers of three layers each formed of a metal wiring layer (for example, an aluminum wiring) and a second macro cell having wiring layers of three layers each formed of a metal wiring layer similar to the first macro cell. The first macro cell is formed to have a wiring structure of three wiring layers though the originally necessary number of metal wiring layers is two. The metal wiring layer of each layer on the first macro cell is formed of the same material as the metal wiring layer of the corresponding each layer on the second macro cell. Moreover, the metal wiring layer of each layer is formed to have the same film thickness. In order to connect the first and second macro cells to each other, a macro interconnection wiring is formed to be included in the third wiring layer (uppermost wiring layer).

Abstract: A complementary device consisting of a PMOS TFT transistor and an NMOS FET transistor uses a conducting layer to shunt drain regions of the transistors to eliminate any detrimental diode or p-n junction effects. The use of the conducting layer significantly improves the current drive capabilities of the PMOS TFT when the complementary device is used to design SRAM cells with NMOS pull-down transistors.

Abstract: A pair of thin film transistors formed in adjacent layers of polysilicon. The gate of the first TFT and the source, drain and channel regions of the second TFT are formed in the first polysilicon layer. The source, drain and channel regions of the first TFT and the gate of the second TFT are formed in the second polysilicon layer. A dielectric layer is interposed between the first and second polysilicon layers. The first TFT gate overlaps the second TFT drain region in the first polysilicon layer and the second TFT gate overlaps the first TFT drain region in the second polysilicon layer. In another aspect of the invention, two TFTs are incorporated into a SRAM memory cell.

Abstract: A 4-T SRAM cell includes access transistors of a first type and cell (pull-up or pull-down) transistors of a second type. For example, the cell includes PMOS access transistors and NMOS pull-down transistors. The cell may also include leaky-junction or Schottky loads.

Abstract: An SRAM of the present invention has a first load resistor connected between a first power source terminal and a first node, a second load resistor connected between the first power source terminal and a second node, a first drive transistor having a source-drain path connected between the first node and a second power source terminal, and a gate connected to the second node, a second drive transistor having a source-drain path connected between the second node and the second power source terminal, and a gate connected to the first node, a first switching transistor having a source-drain path connected between the first node and a first bit line, and a gate connected to a word line, and a second switching transistor having a source-drain path connected between the first node and a second bit line, and a gate connected to the word line.

Abstract: A layout pattern of a memory cell circuit has a plurality of basic cells. Each basic cell has a small aspect ratio. Each basic cell has a NMOS transistor and a PMOS transistor. In the layout pattern, one basic cell is arranged in each row direction and the sixteen basic cells are arranged in each column direction.

Abstract: The gates 31, 32, 33 and 34 of a pair of driver transistors Q1, Q2 and a pair of address-selecting transistors Q3, Q4 are arranged so as to be perpendicular to bit lines BL, /BL. The drain regions of the driver transistors Q1, Q2 forming a flip-flop are arranged point-symmetrically around an element isolating region. The source regions of the driver transistors Q1, Q2 are arranged point-symmetrically. Similarly, the address-selecting transistors Q3, Q4 are arranged point-symmetrically. An upper wiring layer connected to two gates of the transistors are arranged so as to be perpendicular to the bit lines BL, /BL. Two Vss lines are formed in the same layer as that for the bit lines BL, /BL and arranged on both sides of the bit lines BL, /BL in parallel thereto. The Vss lines are connected to the source regions of the driver transistors.

Abstract: A method for fabricating polycrystalline silicon resistor structures includes steps directed to the provision of a polycrystalline silicon structure having a decreased width. In one embodiment, sidewall spacers are used to narrow a region in which the polycrystalline silicon resistors are formed. In an alternative embodiment, polycrystalline silicon resistors are formed as sidewall structures in a resistor region. Use of either technique provides a reduced cross-section for the resistor structures, allowing shorter resistors to be used, or providing increased resistance for longer resistors.

Abstract: A metallic layer (10), a thin-film first polycrystalline silicon layer (14), a first contact hole for connecting the metallic layer and first polycrystalline silicon layer, a second polycrystalline silicon layer (18) which becomes an etching stopper layer for the prevention of penetration in the first contact hole area, and a second contact hole which connects the second polycrystalline silicon layer and the first polycrystalline silicon layer are included. P-type impurities are introduced into the first polycrystalline silicon layer, and the second polycrystalline silicon layer is non-doped in the first contact hole area. By a heating step, the P-type impurities in the first polycrystalline silicon layer are diffused to the second polycrystalline silicon layer. The second polycrystalline silicon layer is N-type in a memory cell area.

Abstract: A static random access memory (SRAM) cell includes first and second load devices, first and second access transistors, first and second drive transistors, and two bit lines. The SRAM includes a substrate; an active region in the substrate, the active region being formed in a direction; gate electrodes of the first and second access transistors crossing the active region, the gate electrodes of the first and second access transistors are parallel with each other; gate electrodes of the first and second drive transistors crossing the active region, the gate electrodes of the first and second drive transistors are parallel with each other, and first and second load devices on the gate electrodes of the first and second access transistors, the first and second load devices are parallel with each other.

Abstract: A power distribution system for a semiconductor die includes bonding pads located adjacent to and connected to power busses with connections between the bonding pads providing a parallel path for current. Connections may be provided by stitch bonds, by conductors within a substrate or by other means.

Abstract: The present invention is a method for preventing backside polysilicon peeling in 4T+2R SRAM process. This invention utilizes forming oxide cap layer on the backside of the wafer to protect the backside polysilicon. Thus, the backside polysilicon is free from peeling and damage.

Abstract: A static RAM which is a CMOS static RAM having first and second load transistors, first and second driver transistors, and first and second switching transistors in one memory cell includes: a laminated structure of a first polysilicon layer, a silicide layer and a second polysilicon layer, forming the gate regions of the second load and driver transistors in a body; an interconnection layer comprising a laminated structure of the silicide layer and the second polysilicon layer to form a p-n junction between the drain regions of the first load and driver transistors; and one contact for making the gate regions and the interconnection layer in a body by the second polysilicon layer.

Abstract: A thin film transistor includes a substrate with a trench having first and second sides and a bottom, and a gate electrode at one of the first and second sides of the trench. The thin film transistor further includes a gate insulating layer on the entire surface of the substrate including the gate electrode, and an active layer on the gate insulating layer along the trench, the active layer having source and drain regions substantially outside the trench.

Abstract: A layout is provided for an SRAM structure. The layout includes a first storage transistor cross-coupled to a second storage transistor to form an SRAM cell. The source regions of the first and second storage transistors are formed in a common region in the substrate to provide a more compact and dense array. The memory cell also includes a first access transistor and a second access transistor appropriately coupled to the appropriate data storage notes. The gate electrodes for the storage transistors and the access transistors are substantially parallel to each other thus providing advantages in operational characteristics and layout efficiencies. The channel regions are also exactly perpendicular to the gate electrodes and are parallel to each other for each of their respective transistors, thereby obtaining similar benefits. The memory cell is designed having a low aspect ratio, preferably lower than 1.2.

Abstract: In a CMOS SRAM cell formed on an SOI substrate and including a flip-flop having first and second NMOS and PMOS transistors, transfer gates having first and seconf MOS transistors, and a word line section, characterized in that:the word line section extends along a predetermined direction; that source and drain diffusion layer regions of the first and second NMOS and PMOS transistors are arranged along the predetermined direction, and gates of these NMOS and PMOS transistors are arranged on channel regions thereof in a direction perpendicular to the predetermined direction; that the gates of the first and second NMOS transistors are electrically connected to the gates of the first and second PMOS transistors, respectively; and that in regions between the gates of the first and second NMOS transistors on the channel regions and the gates of the first and second PMOS transistors on the channel regions, each of the drain diffusion layer regions of the fisrt and second NMOS and PMOS transistors, and each one of th

Abstract: A process of fabricating a mask type ROM is described wherein second type impurity ions are implanted into a semiconductor substrate having a first opposite type background impurity to form a depletion region adjacent the surface. A plurality of parallel nitride lines are formed on the surface, and a first gate oxide formed on the spaces between the nitride lines. Subsequently, a first layer of doped polycrystalline silicon is deposited over the nitride lines, and the layer etched back to expose the top surfaces of the nitride lines. After the nitride lines are removed, a thin gate oxide layer is formed on the exposed surface of the substrate, and on the surfaces of the resultant first polycrystalline gate electrode lines. A second layer of doped polycrystalline silicon is deposited over the polycrystalline silicon lines, and it is etched back. The etch back of the first, and also the second polycrystalline silicon layers, produces an elongated central depression in each of the resultant lines.

Abstract: The present invention provides an improved static random access memory which can be manufactured into values as designed by photolithography. Second direct contract for connecting active region and ground line for first and second memory cells is provided at a boundary between the first memory cell and second memory cell. Second direct contact is divided into a plurality of portions.

Abstract: An method for the fabrication of an improved polysilicon buried contact is described. The contact is formed within a trench etched into the silicon substrate. The effective area of the contact is thereby increased over the conventional planar buried contact by an amount equal to the area of the trench walls. For sub-micron sized buried contacts and trenches 1000 to 3000 Angstroms deep this area can be twice that of the conventional planar buried contact. Contacts formed in this fashion are particularly beneficial in the manufacture of static-random-access memory, devices (SRAMs) through their application with local-interconnects. They afford a lower contact resistance, manifested by the greater effective contact area, as well as a much reduced risk of open or high resistive contacts due to photomask mis-alignment. The presence of the trench also results in a higher junction capacitance which affords a reduction in soft-error-rates, a notable concern for memory devices.

Abstract: A static random access memory (SRAM) cell has a decreased cell size and utilizes transistors disposed in a number of trenches. Four trenches generally contain six transistors associated with the memory cell. The transistors are provided as sidewall transistors which are coupled to buried bit lines, VSS nodes, and VDD nodes at the bottom of the trenches. A first trench includes a driver transistor and a load transistor which have gates coupled together by a bridge over the trench. Another bridge is provided over the bridge over the trench to couple the source of the load transistor to the drain of the driver transistor. The drain of the driver transistor is coupled to another drain of the access gate transistor. The access gate transistor is located in a trench with a access gate transistor from another cell. The buried bit line is located in the trench with the access gate transistors.

Abstract: In a memory cell of an SRAM, a load transistor has a pair of source/drain regions formed to define a channel region, and a gate electrode layer being opposite to the channel region with an insulating layer therebetween. A VVP layer is formed to sandwich the channel region with the gate electrode layer to be opposite to channel region with an insulating layer therebetween. This VVP layer is provided such that GND potential is applied when active and Vcc potential is applied during standby. Thus, a large ON current can be implemented while maintaining a small OFF current of a TFT, even when the power supply voltage is made lower due to reduction in voltage.

Abstract: This invention discloses a memory cell that has a first polysilicon, which functions as a gate. The memory cell further includes a first TEOS oxide layer overlying the first polysilicon and a plurality of via-1 openings exposing the first polysilicon therein. The memory cell further includes a patterned second polysilicon layer overlying the first TEOS oxide layer and filling the via-1 openings thus contacting the gate wherein the patterned second polysilicon containing dopant ions for functioning as a connector for the memory cell. The memory cell further includes a second TEOS oxide layer overlying the connector includes a plurality of via-2 openings for exposing the connector therein. The memory cell further includes a silicide barrier layer disposed in the via-2 openings.

Abstract: A layout structure of an SRAM for reductions in the number of interconnect layers and in the number of connection holes with conventional advantages maintained is disclosed. Contact holes and fields which have been shared between cells vertically adjacent to each other in plan view are divided between the cells. The cells are then positioned in translated relation also in a bit line direction (D1). In a resultant region, first-level polysilicon interconnect layers (1G(G)) for a GND line and first-level polysilicon interconnect layers (1G(W)) for a word line are formed in parallel in a word line direction (D2). Connection holes (GK2, GK1) for connecting gate electrodes of driver transistors (DTr1, DTr2) and fields (FL) are also used for connection holes (GK3) for connecting the fields (FL) and the GND interconnect layers (1G(G)). Further, interconnect layers having a high power supply potential is formed on the interconnect layers (1G(G)).

Abstract: A memory cell for a semiconductor device includes two pairs of a transfer transistor and a drive transistor at a first level and a pair of load transistors above the two pairs of transfer and drive transistors at a second level. Each of the load transistors includes a gate, a source/drain, and a channel. The cell further includes a pair of contacts extending between the first and second levels and that connect one of the gates to a respective one of the two pairs of transfer and drive transistors. Each load transistor gate includes a portion that overlies its respective channel and a lateral extension therefrom that contacts a respective one of the contacts. The extension of one load transistor gate overlaps the source/drain of the other load transistor adjacent the respective one of the contacts.

Abstract: A TFT with a drain-offset structure is provided, which realizes a high ON current while keeping an OFF current at a low level. This TFT includes a substrate and a patterned semiconductor film formed on a main surface of the substrate. At least the main surface of the substrate has an insulating property. The patterned semiconductor film is made of a silicon-system semiconductor material and is not monocrystalline. The patterned semiconductor film includes a source region of a first conductivity type, a channel region of a second conductivity type opposite to the first conductivity type, a first drain region of the first conductivity type, and a second drain region of the second conductivity type. The first drain region serves as an offset region. A gate electrode is formed to be opposite to the channel region through a gate insulating film. The source region is formed on one end of the semiconductor film. The second drain region is formed on an opposite end of the semiconductor film to the source region.

Abstract: A semiconductor structure that includes a silicon substrate which has a top surface, a diffusion region formed in the substrate adjacent to the top surface, a polysilicon gate formed on the top surface of the substrate adjacent to but not contacting the diffusion region, an insulator layer substantially covers the polysilicon gate and the diffusion region, the layer contains a via opening therein, and an electrically conducting plug filling at least partially the via opening providing electrical communication between the polysilicon gate and the diffusion region.

Abstract: The disclosed semiconductor memory cell can be formed in accordance with the standard process for the logic LSI, so that the manufacturing cost can be reduced and an increased node capacitance can be secured.

Abstract: A bipolar transistor is formed by forming a base region continuing from a source/drain region of an MOS transistor, as a link base region, and forming an emitter region at a bit line contact hole by impurity implantation. Alternatively, the bipolar transistor is formed by forming an intrinsic base region and an emitter region at a bit line contact hole by impurity implantation. The intrinsic base region is made deeper than the source/drain region. Further, the impurity of the intrinsic base region is made different from that of the link base region.

Abstract: A method of forming a contact between a conductor and a substrate region in a MOSFET device is provided starting with forming a semiconductor substrate with a silicon oxide layer formed on the surface thereof. Then form a stack of a conductor material upon the surface of the silicon oxide layer and form a first dielectric layer upon the conductor material. Pattern the conductor stack into conductors. Form a butted contact pattern in the first dielectric layer by removal of the dielectric layer in at least one butted contact region. Form doped regions in the substrate self-aligned with the conductors. Form an etch stop layer over the device. Form a second dielectric layer over the device and pattern the second dielectric layer with contact openings therethrough down to the substrate and to the butted contact region. Employ the etch stop layer when patterning the second dielectric layer. Remove exposed portions of the etch stop layer subsequent to patterning the second dielectric layer.

Abstract: A ROM memory array comprises a doped silicon substrate having a surface with a first array of parallel bitlines formed in the substrate at the surface with an array of channel regions between the bitlines. A dielectric layer is formed on the substrate with a wordline array composed of transversely disposed parallel conductors formed on the dielectric layer, with the bitlines and the channel regions and the wordline array forming an array of field effect transistors. A gate oxide layer is formed over the wordlines. A thin film polysilicon storage plane is formed over the gate oxide layer with a second array of alternating parallel bitlines and channel regions formed in the thin film polysilicon storage plane. The second array of bitlines and channel regions is orthogonally disposed relative to the wordline array and the second array of bitlines is formed in a storage plane over an interpolysilicon oxide dielectric isolation layer.

Abstract: SRAM memory cells is provided with high resistance to soft error and no parasitic capacitance due to PN junction. SRAM memory cells comprises the load resister is a thin film transistor having a same conductive type as that of the driver transistor.